1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (c) 2018 Intel Corporation */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _IGC_BASE_H_ 5*4882a593Smuzhiyun #define _IGC_BASE_H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* forward declaration */ 8*4882a593Smuzhiyun void igc_rx_fifo_flush_base(struct igc_hw *hw); 9*4882a593Smuzhiyun void igc_power_down_phy_copper_base(struct igc_hw *hw); 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* Transmit Descriptor - Advanced */ 12*4882a593Smuzhiyun union igc_adv_tx_desc { 13*4882a593Smuzhiyun struct { 14*4882a593Smuzhiyun __le64 buffer_addr; /* Address of descriptor's data buf */ 15*4882a593Smuzhiyun __le32 cmd_type_len; 16*4882a593Smuzhiyun __le32 olinfo_status; 17*4882a593Smuzhiyun } read; 18*4882a593Smuzhiyun struct { 19*4882a593Smuzhiyun __le64 rsvd; /* Reserved */ 20*4882a593Smuzhiyun __le32 nxtseq_seed; 21*4882a593Smuzhiyun __le32 status; 22*4882a593Smuzhiyun } wb; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Context descriptors */ 26*4882a593Smuzhiyun struct igc_adv_tx_context_desc { 27*4882a593Smuzhiyun __le32 vlan_macip_lens; 28*4882a593Smuzhiyun __le32 launch_time; 29*4882a593Smuzhiyun __le32 type_tucmd_mlhl; 30*4882a593Smuzhiyun __le32 mss_l4len_idx; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Adv Transmit Descriptor Config Masks */ 34*4882a593Smuzhiyun #define IGC_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */ 35*4882a593Smuzhiyun #define IGC_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ 36*4882a593Smuzhiyun #define IGC_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 37*4882a593Smuzhiyun #define IGC_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ 38*4882a593Smuzhiyun #define IGC_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 39*4882a593Smuzhiyun #define IGC_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ 40*4882a593Smuzhiyun #define IGC_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ 41*4882a593Smuzhiyun #define IGC_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ 42*4882a593Smuzhiyun #define IGC_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 43*4882a593Smuzhiyun #define IGC_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define IGC_RAR_ENTRIES 16 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* Receive Descriptor - Advanced */ 48*4882a593Smuzhiyun union igc_adv_rx_desc { 49*4882a593Smuzhiyun struct { 50*4882a593Smuzhiyun __le64 pkt_addr; /* Packet buffer address */ 51*4882a593Smuzhiyun __le64 hdr_addr; /* Header buffer address */ 52*4882a593Smuzhiyun } read; 53*4882a593Smuzhiyun struct { 54*4882a593Smuzhiyun struct { 55*4882a593Smuzhiyun union { 56*4882a593Smuzhiyun __le32 data; 57*4882a593Smuzhiyun struct { 58*4882a593Smuzhiyun __le16 pkt_info; /*RSS type, Pkt type*/ 59*4882a593Smuzhiyun /* Split Header, header buffer len */ 60*4882a593Smuzhiyun __le16 hdr_info; 61*4882a593Smuzhiyun } hs_rss; 62*4882a593Smuzhiyun } lo_dword; 63*4882a593Smuzhiyun union { 64*4882a593Smuzhiyun __le32 rss; /* RSS Hash */ 65*4882a593Smuzhiyun struct { 66*4882a593Smuzhiyun __le16 ip_id; /* IP id */ 67*4882a593Smuzhiyun __le16 csum; /* Packet Checksum */ 68*4882a593Smuzhiyun } csum_ip; 69*4882a593Smuzhiyun } hi_dword; 70*4882a593Smuzhiyun } lower; 71*4882a593Smuzhiyun struct { 72*4882a593Smuzhiyun __le32 status_error; /* ext status/error */ 73*4882a593Smuzhiyun __le16 length; /* Packet length */ 74*4882a593Smuzhiyun __le16 vlan; /* VLAN tag */ 75*4882a593Smuzhiyun } upper; 76*4882a593Smuzhiyun } wb; /* writeback */ 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* Additional Transmit Descriptor Control definitions */ 80*4882a593Smuzhiyun #define IGC_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */ 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* Additional Receive Descriptor Control definitions */ 83*4882a593Smuzhiyun #define IGC_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */ 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* SRRCTL bit definitions */ 86*4882a593Smuzhiyun #define IGC_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 87*4882a593Smuzhiyun #define IGC_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 88*4882a593Smuzhiyun #define IGC_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #endif /* _IGC_BASE_H */ 91