1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _E1000_MBX_H_ 5*4882a593Smuzhiyun #define _E1000_MBX_H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include "vf.h" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define E1000_V2PMAILBOX_REQ 0x00000001 /* Request for PF Ready bit */ 10*4882a593Smuzhiyun #define E1000_V2PMAILBOX_ACK 0x00000002 /* Ack PF message received */ 11*4882a593Smuzhiyun #define E1000_V2PMAILBOX_VFU 0x00000004 /* VF owns the mailbox buffer */ 12*4882a593Smuzhiyun #define E1000_V2PMAILBOX_PFU 0x00000008 /* PF owns the mailbox buffer */ 13*4882a593Smuzhiyun #define E1000_V2PMAILBOX_PFSTS 0x00000010 /* PF wrote a message in the MB */ 14*4882a593Smuzhiyun #define E1000_V2PMAILBOX_PFACK 0x00000020 /* PF ack the previous VF msg */ 15*4882a593Smuzhiyun #define E1000_V2PMAILBOX_RSTI 0x00000040 /* PF has reset indication */ 16*4882a593Smuzhiyun #define E1000_V2PMAILBOX_RSTD 0x00000080 /* PF has indicated reset done */ 17*4882a593Smuzhiyun #define E1000_V2PMAILBOX_R2C_BITS 0x000000B0 /* All read to clear bits */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define E1000_VFMAILBOX_SIZE 16 /* 16 32 bit words - 64 bytes */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* If it's a E1000_VF_* msg then it originates in the VF and is sent to the 22*4882a593Smuzhiyun * PF. The reverse is true if it is E1000_PF_*. 23*4882a593Smuzhiyun * Message ACK's are the value or'd with 0xF0000000 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun /* Messages below or'd with this are the ACK */ 26*4882a593Smuzhiyun #define E1000_VT_MSGTYPE_ACK 0x80000000 27*4882a593Smuzhiyun /* Messages below or'd with this are the NACK */ 28*4882a593Smuzhiyun #define E1000_VT_MSGTYPE_NACK 0x40000000 29*4882a593Smuzhiyun /* Indicates that VF is still clear to send requests */ 30*4882a593Smuzhiyun #define E1000_VT_MSGTYPE_CTS 0x20000000 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* We have a total wait time of 1s for vf mailbox posted messages */ 33*4882a593Smuzhiyun #define E1000_VF_MBX_INIT_TIMEOUT 2000 /* retry count for mbx timeout */ 34*4882a593Smuzhiyun #define E1000_VF_MBX_INIT_DELAY 500 /* usec delay between retries */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define E1000_VT_MSGINFO_SHIFT 16 37*4882a593Smuzhiyun /* bits 23:16 are used for exra info for certain messages */ 38*4882a593Smuzhiyun #define E1000_VT_MSGINFO_MASK (0xFF << E1000_VT_MSGINFO_SHIFT) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define E1000_VF_RESET 0x01 /* VF requests reset */ 41*4882a593Smuzhiyun #define E1000_VF_SET_MAC_ADDR 0x02 /* VF requests PF to set MAC addr */ 42*4882a593Smuzhiyun /* VF requests PF to clear all unicast MAC filters */ 43*4882a593Smuzhiyun #define E1000_VF_MAC_FILTER_CLR (0x01 << E1000_VT_MSGINFO_SHIFT) 44*4882a593Smuzhiyun /* VF requests PF to add unicast MAC filter */ 45*4882a593Smuzhiyun #define E1000_VF_MAC_FILTER_ADD (0x02 << E1000_VT_MSGINFO_SHIFT) 46*4882a593Smuzhiyun #define E1000_VF_SET_MULTICAST 0x03 /* VF requests PF to set MC addr */ 47*4882a593Smuzhiyun #define E1000_VF_SET_VLAN 0x04 /* VF requests PF to set VLAN */ 48*4882a593Smuzhiyun #define E1000_VF_SET_LPE 0x05 /* VF requests PF to set VMOLR.LPE */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define E1000_PF_CONTROL_MSG 0x0100 /* PF control message */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun void e1000_init_mbx_ops_generic(struct e1000_hw *hw); 53*4882a593Smuzhiyun s32 e1000_init_mbx_params_vf(struct e1000_hw *); 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #endif /* _E1000_MBX_H_ */ 56