1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
3
4 /* ethtool support for igb */
5
6 #include <linux/vmalloc.h>
7 #include <linux/netdevice.h>
8 #include <linux/pci.h>
9 #include <linux/delay.h>
10 #include <linux/interrupt.h>
11 #include <linux/if_ether.h>
12 #include <linux/ethtool.h>
13 #include <linux/sched.h>
14 #include <linux/slab.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/highmem.h>
17 #include <linux/mdio.h>
18
19 #include "igb.h"
20
21 struct igb_stats {
22 char stat_string[ETH_GSTRING_LEN];
23 int sizeof_stat;
24 int stat_offset;
25 };
26
27 #define IGB_STAT(_name, _stat) { \
28 .stat_string = _name, \
29 .sizeof_stat = sizeof_field(struct igb_adapter, _stat), \
30 .stat_offset = offsetof(struct igb_adapter, _stat) \
31 }
32 static const struct igb_stats igb_gstrings_stats[] = {
33 IGB_STAT("rx_packets", stats.gprc),
34 IGB_STAT("tx_packets", stats.gptc),
35 IGB_STAT("rx_bytes", stats.gorc),
36 IGB_STAT("tx_bytes", stats.gotc),
37 IGB_STAT("rx_broadcast", stats.bprc),
38 IGB_STAT("tx_broadcast", stats.bptc),
39 IGB_STAT("rx_multicast", stats.mprc),
40 IGB_STAT("tx_multicast", stats.mptc),
41 IGB_STAT("multicast", stats.mprc),
42 IGB_STAT("collisions", stats.colc),
43 IGB_STAT("rx_crc_errors", stats.crcerrs),
44 IGB_STAT("rx_no_buffer_count", stats.rnbc),
45 IGB_STAT("rx_missed_errors", stats.mpc),
46 IGB_STAT("tx_aborted_errors", stats.ecol),
47 IGB_STAT("tx_carrier_errors", stats.tncrs),
48 IGB_STAT("tx_window_errors", stats.latecol),
49 IGB_STAT("tx_abort_late_coll", stats.latecol),
50 IGB_STAT("tx_deferred_ok", stats.dc),
51 IGB_STAT("tx_single_coll_ok", stats.scc),
52 IGB_STAT("tx_multi_coll_ok", stats.mcc),
53 IGB_STAT("tx_timeout_count", tx_timeout_count),
54 IGB_STAT("rx_long_length_errors", stats.roc),
55 IGB_STAT("rx_short_length_errors", stats.ruc),
56 IGB_STAT("rx_align_errors", stats.algnerrc),
57 IGB_STAT("tx_tcp_seg_good", stats.tsctc),
58 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
59 IGB_STAT("rx_flow_control_xon", stats.xonrxc),
60 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
61 IGB_STAT("tx_flow_control_xon", stats.xontxc),
62 IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
63 IGB_STAT("rx_long_byte_count", stats.gorc),
64 IGB_STAT("tx_dma_out_of_sync", stats.doosync),
65 IGB_STAT("tx_smbus", stats.mgptc),
66 IGB_STAT("rx_smbus", stats.mgprc),
67 IGB_STAT("dropped_smbus", stats.mgpdc),
68 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc),
69 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc),
70 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc),
71 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc),
72 IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts),
73 IGB_STAT("tx_hwtstamp_skipped", tx_hwtstamp_skipped),
74 IGB_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared),
75 };
76
77 #define IGB_NETDEV_STAT(_net_stat) { \
78 .stat_string = __stringify(_net_stat), \
79 .sizeof_stat = sizeof_field(struct rtnl_link_stats64, _net_stat), \
80 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \
81 }
82 static const struct igb_stats igb_gstrings_net_stats[] = {
83 IGB_NETDEV_STAT(rx_errors),
84 IGB_NETDEV_STAT(tx_errors),
85 IGB_NETDEV_STAT(tx_dropped),
86 IGB_NETDEV_STAT(rx_length_errors),
87 IGB_NETDEV_STAT(rx_over_errors),
88 IGB_NETDEV_STAT(rx_frame_errors),
89 IGB_NETDEV_STAT(rx_fifo_errors),
90 IGB_NETDEV_STAT(tx_fifo_errors),
91 IGB_NETDEV_STAT(tx_heartbeat_errors)
92 };
93
94 #define IGB_GLOBAL_STATS_LEN \
95 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
96 #define IGB_NETDEV_STATS_LEN \
97 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
98 #define IGB_RX_QUEUE_STATS_LEN \
99 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
100
101 #define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */
102
103 #define IGB_QUEUE_STATS_LEN \
104 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
105 IGB_RX_QUEUE_STATS_LEN) + \
106 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
107 IGB_TX_QUEUE_STATS_LEN))
108 #define IGB_STATS_LEN \
109 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
110
111 enum igb_diagnostics_results {
112 TEST_REG = 0,
113 TEST_EEP,
114 TEST_IRQ,
115 TEST_LOOP,
116 TEST_LINK
117 };
118
119 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
120 [TEST_REG] = "Register test (offline)",
121 [TEST_EEP] = "Eeprom test (offline)",
122 [TEST_IRQ] = "Interrupt test (offline)",
123 [TEST_LOOP] = "Loopback test (offline)",
124 [TEST_LINK] = "Link test (on/offline)"
125 };
126 #define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
127
128 static const char igb_priv_flags_strings[][ETH_GSTRING_LEN] = {
129 #define IGB_PRIV_FLAGS_LEGACY_RX BIT(0)
130 "legacy-rx",
131 };
132
133 #define IGB_PRIV_FLAGS_STR_LEN ARRAY_SIZE(igb_priv_flags_strings)
134
igb_get_link_ksettings(struct net_device * netdev,struct ethtool_link_ksettings * cmd)135 static int igb_get_link_ksettings(struct net_device *netdev,
136 struct ethtool_link_ksettings *cmd)
137 {
138 struct igb_adapter *adapter = netdev_priv(netdev);
139 struct e1000_hw *hw = &adapter->hw;
140 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
141 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
142 u32 status;
143 u32 speed;
144 u32 supported, advertising;
145
146 status = pm_runtime_suspended(&adapter->pdev->dev) ?
147 0 : rd32(E1000_STATUS);
148 if (hw->phy.media_type == e1000_media_type_copper) {
149
150 supported = (SUPPORTED_10baseT_Half |
151 SUPPORTED_10baseT_Full |
152 SUPPORTED_100baseT_Half |
153 SUPPORTED_100baseT_Full |
154 SUPPORTED_1000baseT_Full|
155 SUPPORTED_Autoneg |
156 SUPPORTED_TP |
157 SUPPORTED_Pause);
158 advertising = ADVERTISED_TP;
159
160 if (hw->mac.autoneg == 1) {
161 advertising |= ADVERTISED_Autoneg;
162 /* the e1000 autoneg seems to match ethtool nicely */
163 advertising |= hw->phy.autoneg_advertised;
164 }
165
166 cmd->base.port = PORT_TP;
167 cmd->base.phy_address = hw->phy.addr;
168 } else {
169 supported = (SUPPORTED_FIBRE |
170 SUPPORTED_1000baseKX_Full |
171 SUPPORTED_Autoneg |
172 SUPPORTED_Pause);
173 advertising = (ADVERTISED_FIBRE |
174 ADVERTISED_1000baseKX_Full);
175 if (hw->mac.type == e1000_i354) {
176 if ((hw->device_id ==
177 E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) &&
178 !(status & E1000_STATUS_2P5_SKU_OVER)) {
179 supported |= SUPPORTED_2500baseX_Full;
180 supported &= ~SUPPORTED_1000baseKX_Full;
181 advertising |= ADVERTISED_2500baseX_Full;
182 advertising &= ~ADVERTISED_1000baseKX_Full;
183 }
184 }
185 if (eth_flags->e100_base_fx || eth_flags->e100_base_lx) {
186 supported |= SUPPORTED_100baseT_Full;
187 advertising |= ADVERTISED_100baseT_Full;
188 }
189 if (hw->mac.autoneg == 1)
190 advertising |= ADVERTISED_Autoneg;
191
192 cmd->base.port = PORT_FIBRE;
193 }
194 if (hw->mac.autoneg != 1)
195 advertising &= ~(ADVERTISED_Pause |
196 ADVERTISED_Asym_Pause);
197
198 switch (hw->fc.requested_mode) {
199 case e1000_fc_full:
200 advertising |= ADVERTISED_Pause;
201 break;
202 case e1000_fc_rx_pause:
203 advertising |= (ADVERTISED_Pause |
204 ADVERTISED_Asym_Pause);
205 break;
206 case e1000_fc_tx_pause:
207 advertising |= ADVERTISED_Asym_Pause;
208 break;
209 default:
210 advertising &= ~(ADVERTISED_Pause |
211 ADVERTISED_Asym_Pause);
212 }
213 if (status & E1000_STATUS_LU) {
214 if ((status & E1000_STATUS_2P5_SKU) &&
215 !(status & E1000_STATUS_2P5_SKU_OVER)) {
216 speed = SPEED_2500;
217 } else if (status & E1000_STATUS_SPEED_1000) {
218 speed = SPEED_1000;
219 } else if (status & E1000_STATUS_SPEED_100) {
220 speed = SPEED_100;
221 } else {
222 speed = SPEED_10;
223 }
224 if ((status & E1000_STATUS_FD) ||
225 hw->phy.media_type != e1000_media_type_copper)
226 cmd->base.duplex = DUPLEX_FULL;
227 else
228 cmd->base.duplex = DUPLEX_HALF;
229 } else {
230 speed = SPEED_UNKNOWN;
231 cmd->base.duplex = DUPLEX_UNKNOWN;
232 }
233 cmd->base.speed = speed;
234 if ((hw->phy.media_type == e1000_media_type_fiber) ||
235 hw->mac.autoneg)
236 cmd->base.autoneg = AUTONEG_ENABLE;
237 else
238 cmd->base.autoneg = AUTONEG_DISABLE;
239
240 /* MDI-X => 2; MDI =>1; Invalid =>0 */
241 if (hw->phy.media_type == e1000_media_type_copper)
242 cmd->base.eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X :
243 ETH_TP_MDI;
244 else
245 cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID;
246
247 if (hw->phy.mdix == AUTO_ALL_MODES)
248 cmd->base.eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
249 else
250 cmd->base.eth_tp_mdix_ctrl = hw->phy.mdix;
251
252 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
253 supported);
254 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
255 advertising);
256
257 return 0;
258 }
259
igb_set_link_ksettings(struct net_device * netdev,const struct ethtool_link_ksettings * cmd)260 static int igb_set_link_ksettings(struct net_device *netdev,
261 const struct ethtool_link_ksettings *cmd)
262 {
263 struct igb_adapter *adapter = netdev_priv(netdev);
264 struct e1000_hw *hw = &adapter->hw;
265 u32 advertising;
266
267 /* When SoL/IDER sessions are active, autoneg/speed/duplex
268 * cannot be changed
269 */
270 if (igb_check_reset_block(hw)) {
271 dev_err(&adapter->pdev->dev,
272 "Cannot change link characteristics when SoL/IDER is active.\n");
273 return -EINVAL;
274 }
275
276 /* MDI setting is only allowed when autoneg enabled because
277 * some hardware doesn't allow MDI setting when speed or
278 * duplex is forced.
279 */
280 if (cmd->base.eth_tp_mdix_ctrl) {
281 if (hw->phy.media_type != e1000_media_type_copper)
282 return -EOPNOTSUPP;
283
284 if ((cmd->base.eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) &&
285 (cmd->base.autoneg != AUTONEG_ENABLE)) {
286 dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n");
287 return -EINVAL;
288 }
289 }
290
291 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
292 usleep_range(1000, 2000);
293
294 ethtool_convert_link_mode_to_legacy_u32(&advertising,
295 cmd->link_modes.advertising);
296
297 if (cmd->base.autoneg == AUTONEG_ENABLE) {
298 hw->mac.autoneg = 1;
299 if (hw->phy.media_type == e1000_media_type_fiber) {
300 hw->phy.autoneg_advertised = advertising |
301 ADVERTISED_FIBRE |
302 ADVERTISED_Autoneg;
303 switch (adapter->link_speed) {
304 case SPEED_2500:
305 hw->phy.autoneg_advertised =
306 ADVERTISED_2500baseX_Full;
307 break;
308 case SPEED_1000:
309 hw->phy.autoneg_advertised =
310 ADVERTISED_1000baseT_Full;
311 break;
312 case SPEED_100:
313 hw->phy.autoneg_advertised =
314 ADVERTISED_100baseT_Full;
315 break;
316 default:
317 break;
318 }
319 } else {
320 hw->phy.autoneg_advertised = advertising |
321 ADVERTISED_TP |
322 ADVERTISED_Autoneg;
323 }
324 advertising = hw->phy.autoneg_advertised;
325 if (adapter->fc_autoneg)
326 hw->fc.requested_mode = e1000_fc_default;
327 } else {
328 u32 speed = cmd->base.speed;
329 /* calling this overrides forced MDI setting */
330 if (igb_set_spd_dplx(adapter, speed, cmd->base.duplex)) {
331 clear_bit(__IGB_RESETTING, &adapter->state);
332 return -EINVAL;
333 }
334 }
335
336 /* MDI-X => 2; MDI => 1; Auto => 3 */
337 if (cmd->base.eth_tp_mdix_ctrl) {
338 /* fix up the value for auto (3 => 0) as zero is mapped
339 * internally to auto
340 */
341 if (cmd->base.eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO)
342 hw->phy.mdix = AUTO_ALL_MODES;
343 else
344 hw->phy.mdix = cmd->base.eth_tp_mdix_ctrl;
345 }
346
347 /* reset the link */
348 if (netif_running(adapter->netdev)) {
349 igb_down(adapter);
350 igb_up(adapter);
351 } else
352 igb_reset(adapter);
353
354 clear_bit(__IGB_RESETTING, &adapter->state);
355 return 0;
356 }
357
igb_get_link(struct net_device * netdev)358 static u32 igb_get_link(struct net_device *netdev)
359 {
360 struct igb_adapter *adapter = netdev_priv(netdev);
361 struct e1000_mac_info *mac = &adapter->hw.mac;
362
363 /* If the link is not reported up to netdev, interrupts are disabled,
364 * and so the physical link state may have changed since we last
365 * looked. Set get_link_status to make sure that the true link
366 * state is interrogated, rather than pulling a cached and possibly
367 * stale link state from the driver.
368 */
369 if (!netif_carrier_ok(netdev))
370 mac->get_link_status = 1;
371
372 return igb_has_link(adapter);
373 }
374
igb_get_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pause)375 static void igb_get_pauseparam(struct net_device *netdev,
376 struct ethtool_pauseparam *pause)
377 {
378 struct igb_adapter *adapter = netdev_priv(netdev);
379 struct e1000_hw *hw = &adapter->hw;
380
381 pause->autoneg =
382 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
383
384 if (hw->fc.current_mode == e1000_fc_rx_pause)
385 pause->rx_pause = 1;
386 else if (hw->fc.current_mode == e1000_fc_tx_pause)
387 pause->tx_pause = 1;
388 else if (hw->fc.current_mode == e1000_fc_full) {
389 pause->rx_pause = 1;
390 pause->tx_pause = 1;
391 }
392 }
393
igb_set_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pause)394 static int igb_set_pauseparam(struct net_device *netdev,
395 struct ethtool_pauseparam *pause)
396 {
397 struct igb_adapter *adapter = netdev_priv(netdev);
398 struct e1000_hw *hw = &adapter->hw;
399 int retval = 0;
400 int i;
401
402 /* 100basefx does not support setting link flow control */
403 if (hw->dev_spec._82575.eth_flags.e100_base_fx)
404 return -EINVAL;
405
406 adapter->fc_autoneg = pause->autoneg;
407
408 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
409 usleep_range(1000, 2000);
410
411 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
412 hw->fc.requested_mode = e1000_fc_default;
413 if (netif_running(adapter->netdev)) {
414 igb_down(adapter);
415 igb_up(adapter);
416 } else {
417 igb_reset(adapter);
418 }
419 } else {
420 if (pause->rx_pause && pause->tx_pause)
421 hw->fc.requested_mode = e1000_fc_full;
422 else if (pause->rx_pause && !pause->tx_pause)
423 hw->fc.requested_mode = e1000_fc_rx_pause;
424 else if (!pause->rx_pause && pause->tx_pause)
425 hw->fc.requested_mode = e1000_fc_tx_pause;
426 else if (!pause->rx_pause && !pause->tx_pause)
427 hw->fc.requested_mode = e1000_fc_none;
428
429 hw->fc.current_mode = hw->fc.requested_mode;
430
431 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
432 igb_force_mac_fc(hw) : igb_setup_link(hw));
433
434 /* Make sure SRRCTL considers new fc settings for each ring */
435 for (i = 0; i < adapter->num_rx_queues; i++) {
436 struct igb_ring *ring = adapter->rx_ring[i];
437
438 igb_setup_srrctl(adapter, ring);
439 }
440 }
441
442 clear_bit(__IGB_RESETTING, &adapter->state);
443 return retval;
444 }
445
igb_get_msglevel(struct net_device * netdev)446 static u32 igb_get_msglevel(struct net_device *netdev)
447 {
448 struct igb_adapter *adapter = netdev_priv(netdev);
449 return adapter->msg_enable;
450 }
451
igb_set_msglevel(struct net_device * netdev,u32 data)452 static void igb_set_msglevel(struct net_device *netdev, u32 data)
453 {
454 struct igb_adapter *adapter = netdev_priv(netdev);
455 adapter->msg_enable = data;
456 }
457
igb_get_regs_len(struct net_device * netdev)458 static int igb_get_regs_len(struct net_device *netdev)
459 {
460 #define IGB_REGS_LEN 740
461 return IGB_REGS_LEN * sizeof(u32);
462 }
463
igb_get_regs(struct net_device * netdev,struct ethtool_regs * regs,void * p)464 static void igb_get_regs(struct net_device *netdev,
465 struct ethtool_regs *regs, void *p)
466 {
467 struct igb_adapter *adapter = netdev_priv(netdev);
468 struct e1000_hw *hw = &adapter->hw;
469 u32 *regs_buff = p;
470 u8 i;
471
472 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
473
474 regs->version = (1u << 24) | (hw->revision_id << 16) | hw->device_id;
475
476 /* General Registers */
477 regs_buff[0] = rd32(E1000_CTRL);
478 regs_buff[1] = rd32(E1000_STATUS);
479 regs_buff[2] = rd32(E1000_CTRL_EXT);
480 regs_buff[3] = rd32(E1000_MDIC);
481 regs_buff[4] = rd32(E1000_SCTL);
482 regs_buff[5] = rd32(E1000_CONNSW);
483 regs_buff[6] = rd32(E1000_VET);
484 regs_buff[7] = rd32(E1000_LEDCTL);
485 regs_buff[8] = rd32(E1000_PBA);
486 regs_buff[9] = rd32(E1000_PBS);
487 regs_buff[10] = rd32(E1000_FRTIMER);
488 regs_buff[11] = rd32(E1000_TCPTIMER);
489
490 /* NVM Register */
491 regs_buff[12] = rd32(E1000_EECD);
492
493 /* Interrupt */
494 /* Reading EICS for EICR because they read the
495 * same but EICS does not clear on read
496 */
497 regs_buff[13] = rd32(E1000_EICS);
498 regs_buff[14] = rd32(E1000_EICS);
499 regs_buff[15] = rd32(E1000_EIMS);
500 regs_buff[16] = rd32(E1000_EIMC);
501 regs_buff[17] = rd32(E1000_EIAC);
502 regs_buff[18] = rd32(E1000_EIAM);
503 /* Reading ICS for ICR because they read the
504 * same but ICS does not clear on read
505 */
506 regs_buff[19] = rd32(E1000_ICS);
507 regs_buff[20] = rd32(E1000_ICS);
508 regs_buff[21] = rd32(E1000_IMS);
509 regs_buff[22] = rd32(E1000_IMC);
510 regs_buff[23] = rd32(E1000_IAC);
511 regs_buff[24] = rd32(E1000_IAM);
512 regs_buff[25] = rd32(E1000_IMIRVP);
513
514 /* Flow Control */
515 regs_buff[26] = rd32(E1000_FCAL);
516 regs_buff[27] = rd32(E1000_FCAH);
517 regs_buff[28] = rd32(E1000_FCTTV);
518 regs_buff[29] = rd32(E1000_FCRTL);
519 regs_buff[30] = rd32(E1000_FCRTH);
520 regs_buff[31] = rd32(E1000_FCRTV);
521
522 /* Receive */
523 regs_buff[32] = rd32(E1000_RCTL);
524 regs_buff[33] = rd32(E1000_RXCSUM);
525 regs_buff[34] = rd32(E1000_RLPML);
526 regs_buff[35] = rd32(E1000_RFCTL);
527 regs_buff[36] = rd32(E1000_MRQC);
528 regs_buff[37] = rd32(E1000_VT_CTL);
529
530 /* Transmit */
531 regs_buff[38] = rd32(E1000_TCTL);
532 regs_buff[39] = rd32(E1000_TCTL_EXT);
533 regs_buff[40] = rd32(E1000_TIPG);
534 regs_buff[41] = rd32(E1000_DTXCTL);
535
536 /* Wake Up */
537 regs_buff[42] = rd32(E1000_WUC);
538 regs_buff[43] = rd32(E1000_WUFC);
539 regs_buff[44] = rd32(E1000_WUS);
540 regs_buff[45] = rd32(E1000_IPAV);
541 regs_buff[46] = rd32(E1000_WUPL);
542
543 /* MAC */
544 regs_buff[47] = rd32(E1000_PCS_CFG0);
545 regs_buff[48] = rd32(E1000_PCS_LCTL);
546 regs_buff[49] = rd32(E1000_PCS_LSTAT);
547 regs_buff[50] = rd32(E1000_PCS_ANADV);
548 regs_buff[51] = rd32(E1000_PCS_LPAB);
549 regs_buff[52] = rd32(E1000_PCS_NPTX);
550 regs_buff[53] = rd32(E1000_PCS_LPABNP);
551
552 /* Statistics */
553 regs_buff[54] = adapter->stats.crcerrs;
554 regs_buff[55] = adapter->stats.algnerrc;
555 regs_buff[56] = adapter->stats.symerrs;
556 regs_buff[57] = adapter->stats.rxerrc;
557 regs_buff[58] = adapter->stats.mpc;
558 regs_buff[59] = adapter->stats.scc;
559 regs_buff[60] = adapter->stats.ecol;
560 regs_buff[61] = adapter->stats.mcc;
561 regs_buff[62] = adapter->stats.latecol;
562 regs_buff[63] = adapter->stats.colc;
563 regs_buff[64] = adapter->stats.dc;
564 regs_buff[65] = adapter->stats.tncrs;
565 regs_buff[66] = adapter->stats.sec;
566 regs_buff[67] = adapter->stats.htdpmc;
567 regs_buff[68] = adapter->stats.rlec;
568 regs_buff[69] = adapter->stats.xonrxc;
569 regs_buff[70] = adapter->stats.xontxc;
570 regs_buff[71] = adapter->stats.xoffrxc;
571 regs_buff[72] = adapter->stats.xofftxc;
572 regs_buff[73] = adapter->stats.fcruc;
573 regs_buff[74] = adapter->stats.prc64;
574 regs_buff[75] = adapter->stats.prc127;
575 regs_buff[76] = adapter->stats.prc255;
576 regs_buff[77] = adapter->stats.prc511;
577 regs_buff[78] = adapter->stats.prc1023;
578 regs_buff[79] = adapter->stats.prc1522;
579 regs_buff[80] = adapter->stats.gprc;
580 regs_buff[81] = adapter->stats.bprc;
581 regs_buff[82] = adapter->stats.mprc;
582 regs_buff[83] = adapter->stats.gptc;
583 regs_buff[84] = adapter->stats.gorc;
584 regs_buff[86] = adapter->stats.gotc;
585 regs_buff[88] = adapter->stats.rnbc;
586 regs_buff[89] = adapter->stats.ruc;
587 regs_buff[90] = adapter->stats.rfc;
588 regs_buff[91] = adapter->stats.roc;
589 regs_buff[92] = adapter->stats.rjc;
590 regs_buff[93] = adapter->stats.mgprc;
591 regs_buff[94] = adapter->stats.mgpdc;
592 regs_buff[95] = adapter->stats.mgptc;
593 regs_buff[96] = adapter->stats.tor;
594 regs_buff[98] = adapter->stats.tot;
595 regs_buff[100] = adapter->stats.tpr;
596 regs_buff[101] = adapter->stats.tpt;
597 regs_buff[102] = adapter->stats.ptc64;
598 regs_buff[103] = adapter->stats.ptc127;
599 regs_buff[104] = adapter->stats.ptc255;
600 regs_buff[105] = adapter->stats.ptc511;
601 regs_buff[106] = adapter->stats.ptc1023;
602 regs_buff[107] = adapter->stats.ptc1522;
603 regs_buff[108] = adapter->stats.mptc;
604 regs_buff[109] = adapter->stats.bptc;
605 regs_buff[110] = adapter->stats.tsctc;
606 regs_buff[111] = adapter->stats.iac;
607 regs_buff[112] = adapter->stats.rpthc;
608 regs_buff[113] = adapter->stats.hgptc;
609 regs_buff[114] = adapter->stats.hgorc;
610 regs_buff[116] = adapter->stats.hgotc;
611 regs_buff[118] = adapter->stats.lenerrs;
612 regs_buff[119] = adapter->stats.scvpc;
613 regs_buff[120] = adapter->stats.hrmpc;
614
615 for (i = 0; i < 4; i++)
616 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
617 for (i = 0; i < 4; i++)
618 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
619 for (i = 0; i < 4; i++)
620 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
621 for (i = 0; i < 4; i++)
622 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
623 for (i = 0; i < 4; i++)
624 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
625 for (i = 0; i < 4; i++)
626 regs_buff[141 + i] = rd32(E1000_RDH(i));
627 for (i = 0; i < 4; i++)
628 regs_buff[145 + i] = rd32(E1000_RDT(i));
629 for (i = 0; i < 4; i++)
630 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
631
632 for (i = 0; i < 10; i++)
633 regs_buff[153 + i] = rd32(E1000_EITR(i));
634 for (i = 0; i < 8; i++)
635 regs_buff[163 + i] = rd32(E1000_IMIR(i));
636 for (i = 0; i < 8; i++)
637 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
638 for (i = 0; i < 16; i++)
639 regs_buff[179 + i] = rd32(E1000_RAL(i));
640 for (i = 0; i < 16; i++)
641 regs_buff[195 + i] = rd32(E1000_RAH(i));
642
643 for (i = 0; i < 4; i++)
644 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
645 for (i = 0; i < 4; i++)
646 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
647 for (i = 0; i < 4; i++)
648 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
649 for (i = 0; i < 4; i++)
650 regs_buff[223 + i] = rd32(E1000_TDH(i));
651 for (i = 0; i < 4; i++)
652 regs_buff[227 + i] = rd32(E1000_TDT(i));
653 for (i = 0; i < 4; i++)
654 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
655 for (i = 0; i < 4; i++)
656 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
657 for (i = 0; i < 4; i++)
658 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
659 for (i = 0; i < 4; i++)
660 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
661
662 for (i = 0; i < 4; i++)
663 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
664 for (i = 0; i < 4; i++)
665 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
666 for (i = 0; i < 32; i++)
667 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
668 for (i = 0; i < 128; i++)
669 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
670 for (i = 0; i < 128; i++)
671 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
672 for (i = 0; i < 4; i++)
673 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
674
675 regs_buff[547] = rd32(E1000_TDFH);
676 regs_buff[548] = rd32(E1000_TDFT);
677 regs_buff[549] = rd32(E1000_TDFHS);
678 regs_buff[550] = rd32(E1000_TDFPC);
679
680 if (hw->mac.type > e1000_82580) {
681 regs_buff[551] = adapter->stats.o2bgptc;
682 regs_buff[552] = adapter->stats.b2ospc;
683 regs_buff[553] = adapter->stats.o2bspc;
684 regs_buff[554] = adapter->stats.b2ogprc;
685 }
686
687 if (hw->mac.type == e1000_82576) {
688 for (i = 0; i < 12; i++)
689 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4));
690 for (i = 0; i < 4; i++)
691 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4));
692 for (i = 0; i < 12; i++)
693 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4));
694 for (i = 0; i < 12; i++)
695 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4));
696 for (i = 0; i < 12; i++)
697 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4));
698 for (i = 0; i < 12; i++)
699 regs_buff[607 + i] = rd32(E1000_RDH(i + 4));
700 for (i = 0; i < 12; i++)
701 regs_buff[619 + i] = rd32(E1000_RDT(i + 4));
702 for (i = 0; i < 12; i++)
703 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4));
704
705 for (i = 0; i < 12; i++)
706 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4));
707 for (i = 0; i < 12; i++)
708 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4));
709 for (i = 0; i < 12; i++)
710 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4));
711 for (i = 0; i < 12; i++)
712 regs_buff[679 + i] = rd32(E1000_TDH(i + 4));
713 for (i = 0; i < 12; i++)
714 regs_buff[691 + i] = rd32(E1000_TDT(i + 4));
715 for (i = 0; i < 12; i++)
716 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4));
717 for (i = 0; i < 12; i++)
718 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4));
719 for (i = 0; i < 12; i++)
720 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4));
721 }
722
723 if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211)
724 regs_buff[739] = rd32(E1000_I210_RR2DCDELAY);
725 }
726
igb_get_eeprom_len(struct net_device * netdev)727 static int igb_get_eeprom_len(struct net_device *netdev)
728 {
729 struct igb_adapter *adapter = netdev_priv(netdev);
730 return adapter->hw.nvm.word_size * 2;
731 }
732
igb_get_eeprom(struct net_device * netdev,struct ethtool_eeprom * eeprom,u8 * bytes)733 static int igb_get_eeprom(struct net_device *netdev,
734 struct ethtool_eeprom *eeprom, u8 *bytes)
735 {
736 struct igb_adapter *adapter = netdev_priv(netdev);
737 struct e1000_hw *hw = &adapter->hw;
738 u16 *eeprom_buff;
739 int first_word, last_word;
740 int ret_val = 0;
741 u16 i;
742
743 if (eeprom->len == 0)
744 return -EINVAL;
745
746 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
747
748 first_word = eeprom->offset >> 1;
749 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
750
751 eeprom_buff = kmalloc_array(last_word - first_word + 1, sizeof(u16),
752 GFP_KERNEL);
753 if (!eeprom_buff)
754 return -ENOMEM;
755
756 if (hw->nvm.type == e1000_nvm_eeprom_spi)
757 ret_val = hw->nvm.ops.read(hw, first_word,
758 last_word - first_word + 1,
759 eeprom_buff);
760 else {
761 for (i = 0; i < last_word - first_word + 1; i++) {
762 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
763 &eeprom_buff[i]);
764 if (ret_val)
765 break;
766 }
767 }
768
769 /* Device's eeprom is always little-endian, word addressable */
770 for (i = 0; i < last_word - first_word + 1; i++)
771 le16_to_cpus(&eeprom_buff[i]);
772
773 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
774 eeprom->len);
775 kfree(eeprom_buff);
776
777 return ret_val;
778 }
779
igb_set_eeprom(struct net_device * netdev,struct ethtool_eeprom * eeprom,u8 * bytes)780 static int igb_set_eeprom(struct net_device *netdev,
781 struct ethtool_eeprom *eeprom, u8 *bytes)
782 {
783 struct igb_adapter *adapter = netdev_priv(netdev);
784 struct e1000_hw *hw = &adapter->hw;
785 u16 *eeprom_buff;
786 void *ptr;
787 int max_len, first_word, last_word, ret_val = 0;
788 u16 i;
789
790 if (eeprom->len == 0)
791 return -EOPNOTSUPP;
792
793 if ((hw->mac.type >= e1000_i210) &&
794 !igb_get_flash_presence_i210(hw)) {
795 return -EOPNOTSUPP;
796 }
797
798 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
799 return -EFAULT;
800
801 max_len = hw->nvm.word_size * 2;
802
803 first_word = eeprom->offset >> 1;
804 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
805 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
806 if (!eeprom_buff)
807 return -ENOMEM;
808
809 ptr = (void *)eeprom_buff;
810
811 if (eeprom->offset & 1) {
812 /* need read/modify/write of first changed EEPROM word
813 * only the second byte of the word is being modified
814 */
815 ret_val = hw->nvm.ops.read(hw, first_word, 1,
816 &eeprom_buff[0]);
817 ptr++;
818 }
819 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
820 /* need read/modify/write of last changed EEPROM word
821 * only the first byte of the word is being modified
822 */
823 ret_val = hw->nvm.ops.read(hw, last_word, 1,
824 &eeprom_buff[last_word - first_word]);
825 }
826
827 /* Device's eeprom is always little-endian, word addressable */
828 for (i = 0; i < last_word - first_word + 1; i++)
829 le16_to_cpus(&eeprom_buff[i]);
830
831 memcpy(ptr, bytes, eeprom->len);
832
833 for (i = 0; i < last_word - first_word + 1; i++)
834 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
835
836 ret_val = hw->nvm.ops.write(hw, first_word,
837 last_word - first_word + 1, eeprom_buff);
838
839 /* Update the checksum if nvm write succeeded */
840 if (ret_val == 0)
841 hw->nvm.ops.update(hw);
842
843 igb_set_fw_version(adapter);
844 kfree(eeprom_buff);
845 return ret_val;
846 }
847
igb_get_drvinfo(struct net_device * netdev,struct ethtool_drvinfo * drvinfo)848 static void igb_get_drvinfo(struct net_device *netdev,
849 struct ethtool_drvinfo *drvinfo)
850 {
851 struct igb_adapter *adapter = netdev_priv(netdev);
852
853 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver));
854
855 /* EEPROM image version # is reported as firmware version # for
856 * 82575 controllers
857 */
858 strlcpy(drvinfo->fw_version, adapter->fw_version,
859 sizeof(drvinfo->fw_version));
860 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
861 sizeof(drvinfo->bus_info));
862
863 drvinfo->n_priv_flags = IGB_PRIV_FLAGS_STR_LEN;
864 }
865
igb_get_ringparam(struct net_device * netdev,struct ethtool_ringparam * ring)866 static void igb_get_ringparam(struct net_device *netdev,
867 struct ethtool_ringparam *ring)
868 {
869 struct igb_adapter *adapter = netdev_priv(netdev);
870
871 ring->rx_max_pending = IGB_MAX_RXD;
872 ring->tx_max_pending = IGB_MAX_TXD;
873 ring->rx_pending = adapter->rx_ring_count;
874 ring->tx_pending = adapter->tx_ring_count;
875 }
876
igb_set_ringparam(struct net_device * netdev,struct ethtool_ringparam * ring)877 static int igb_set_ringparam(struct net_device *netdev,
878 struct ethtool_ringparam *ring)
879 {
880 struct igb_adapter *adapter = netdev_priv(netdev);
881 struct igb_ring *temp_ring;
882 int i, err = 0;
883 u16 new_rx_count, new_tx_count;
884
885 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
886 return -EINVAL;
887
888 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
889 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
890 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
891
892 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
893 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
894 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
895
896 if ((new_tx_count == adapter->tx_ring_count) &&
897 (new_rx_count == adapter->rx_ring_count)) {
898 /* nothing to do */
899 return 0;
900 }
901
902 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
903 usleep_range(1000, 2000);
904
905 if (!netif_running(adapter->netdev)) {
906 for (i = 0; i < adapter->num_tx_queues; i++)
907 adapter->tx_ring[i]->count = new_tx_count;
908 for (i = 0; i < adapter->num_rx_queues; i++)
909 adapter->rx_ring[i]->count = new_rx_count;
910 adapter->tx_ring_count = new_tx_count;
911 adapter->rx_ring_count = new_rx_count;
912 goto clear_reset;
913 }
914
915 if (adapter->num_tx_queues > adapter->num_rx_queues)
916 temp_ring = vmalloc(array_size(sizeof(struct igb_ring),
917 adapter->num_tx_queues));
918 else
919 temp_ring = vmalloc(array_size(sizeof(struct igb_ring),
920 adapter->num_rx_queues));
921
922 if (!temp_ring) {
923 err = -ENOMEM;
924 goto clear_reset;
925 }
926
927 igb_down(adapter);
928
929 /* We can't just free everything and then setup again,
930 * because the ISRs in MSI-X mode get passed pointers
931 * to the Tx and Rx ring structs.
932 */
933 if (new_tx_count != adapter->tx_ring_count) {
934 for (i = 0; i < adapter->num_tx_queues; i++) {
935 memcpy(&temp_ring[i], adapter->tx_ring[i],
936 sizeof(struct igb_ring));
937
938 temp_ring[i].count = new_tx_count;
939 err = igb_setup_tx_resources(&temp_ring[i]);
940 if (err) {
941 while (i) {
942 i--;
943 igb_free_tx_resources(&temp_ring[i]);
944 }
945 goto err_setup;
946 }
947 }
948
949 for (i = 0; i < adapter->num_tx_queues; i++) {
950 igb_free_tx_resources(adapter->tx_ring[i]);
951
952 memcpy(adapter->tx_ring[i], &temp_ring[i],
953 sizeof(struct igb_ring));
954 }
955
956 adapter->tx_ring_count = new_tx_count;
957 }
958
959 if (new_rx_count != adapter->rx_ring_count) {
960 for (i = 0; i < adapter->num_rx_queues; i++) {
961 memcpy(&temp_ring[i], adapter->rx_ring[i],
962 sizeof(struct igb_ring));
963
964 /* Clear copied XDP RX-queue info */
965 memset(&temp_ring[i].xdp_rxq, 0,
966 sizeof(temp_ring[i].xdp_rxq));
967
968 temp_ring[i].count = new_rx_count;
969 err = igb_setup_rx_resources(&temp_ring[i]);
970 if (err) {
971 while (i) {
972 i--;
973 igb_free_rx_resources(&temp_ring[i]);
974 }
975 goto err_setup;
976 }
977
978 }
979
980 for (i = 0; i < adapter->num_rx_queues; i++) {
981 igb_free_rx_resources(adapter->rx_ring[i]);
982
983 memcpy(adapter->rx_ring[i], &temp_ring[i],
984 sizeof(struct igb_ring));
985 }
986
987 adapter->rx_ring_count = new_rx_count;
988 }
989 err_setup:
990 igb_up(adapter);
991 vfree(temp_ring);
992 clear_reset:
993 clear_bit(__IGB_RESETTING, &adapter->state);
994 return err;
995 }
996
997 /* ethtool register test data */
998 struct igb_reg_test {
999 u16 reg;
1000 u16 reg_offset;
1001 u16 array_len;
1002 u16 test_type;
1003 u32 mask;
1004 u32 write;
1005 };
1006
1007 /* In the hardware, registers are laid out either singly, in arrays
1008 * spaced 0x100 bytes apart, or in contiguous tables. We assume
1009 * most tests take place on arrays or single registers (handled
1010 * as a single-element array) and special-case the tables.
1011 * Table tests are always pattern tests.
1012 *
1013 * We also make provision for some required setup steps by specifying
1014 * registers to be written without any read-back testing.
1015 */
1016
1017 #define PATTERN_TEST 1
1018 #define SET_READ_TEST 2
1019 #define WRITE_NO_TEST 3
1020 #define TABLE32_TEST 4
1021 #define TABLE64_TEST_LO 5
1022 #define TABLE64_TEST_HI 6
1023
1024 /* i210 reg test */
1025 static struct igb_reg_test reg_test_i210[] = {
1026 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1027 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1028 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1029 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1030 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1031 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1032 /* RDH is read-only for i210, only test RDT. */
1033 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1034 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1035 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1036 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1037 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1038 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1039 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1040 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1041 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1042 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1043 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1044 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1045 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1046 0xFFFFFFFF, 0xFFFFFFFF },
1047 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1048 0x900FFFFF, 0xFFFFFFFF },
1049 { E1000_MTA, 0, 128, TABLE32_TEST,
1050 0xFFFFFFFF, 0xFFFFFFFF },
1051 { 0, 0, 0, 0, 0 }
1052 };
1053
1054 /* i350 reg test */
1055 static struct igb_reg_test reg_test_i350[] = {
1056 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1057 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1058 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1059 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 },
1060 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1061 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1062 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1063 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1064 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1065 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1066 /* RDH is read-only for i350, only test RDT. */
1067 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1068 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1069 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1070 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1071 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1072 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1073 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1074 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1075 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1076 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1077 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1078 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1079 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1080 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1081 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1082 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1083 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1084 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1085 0xFFFFFFFF, 0xFFFFFFFF },
1086 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1087 0xC3FFFFFF, 0xFFFFFFFF },
1088 { E1000_RA2, 0, 16, TABLE64_TEST_LO,
1089 0xFFFFFFFF, 0xFFFFFFFF },
1090 { E1000_RA2, 0, 16, TABLE64_TEST_HI,
1091 0xC3FFFFFF, 0xFFFFFFFF },
1092 { E1000_MTA, 0, 128, TABLE32_TEST,
1093 0xFFFFFFFF, 0xFFFFFFFF },
1094 { 0, 0, 0, 0 }
1095 };
1096
1097 /* 82580 reg test */
1098 static struct igb_reg_test reg_test_82580[] = {
1099 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1100 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1101 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1102 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1103 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1104 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1105 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1106 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1107 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1108 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1109 /* RDH is read-only for 82580, only test RDT. */
1110 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1111 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1112 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1113 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1114 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1115 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1116 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1117 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1118 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1119 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1120 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1121 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1122 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1123 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1124 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1125 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1126 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1127 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1128 0xFFFFFFFF, 0xFFFFFFFF },
1129 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1130 0x83FFFFFF, 0xFFFFFFFF },
1131 { E1000_RA2, 0, 8, TABLE64_TEST_LO,
1132 0xFFFFFFFF, 0xFFFFFFFF },
1133 { E1000_RA2, 0, 8, TABLE64_TEST_HI,
1134 0x83FFFFFF, 0xFFFFFFFF },
1135 { E1000_MTA, 0, 128, TABLE32_TEST,
1136 0xFFFFFFFF, 0xFFFFFFFF },
1137 { 0, 0, 0, 0 }
1138 };
1139
1140 /* 82576 reg test */
1141 static struct igb_reg_test reg_test_82576[] = {
1142 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1143 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1144 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1145 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1146 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1147 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1148 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1149 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1150 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1151 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1152 /* Enable all RX queues before testing. */
1153 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0,
1154 E1000_RXDCTL_QUEUE_ENABLE },
1155 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0,
1156 E1000_RXDCTL_QUEUE_ENABLE },
1157 /* RDH is read-only for 82576, only test RDT. */
1158 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1159 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1160 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1161 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
1162 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1163 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1164 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1165 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1166 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1167 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1168 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1169 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1170 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1171 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1172 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1173 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1174 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1175 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1176 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1177 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1178 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1179 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1180 { 0, 0, 0, 0 }
1181 };
1182
1183 /* 82575 register test */
1184 static struct igb_reg_test reg_test_82575[] = {
1185 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1186 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1187 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1188 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1189 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1190 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1191 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1192 /* Enable all four RX queues before testing. */
1193 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0,
1194 E1000_RXDCTL_QUEUE_ENABLE },
1195 /* RDH is read-only for 82575, only test RDT. */
1196 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1197 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1198 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1199 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1200 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1201 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1202 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1203 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1204 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1205 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1206 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1207 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1208 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1209 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1210 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1211 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1212 { 0, 0, 0, 0 }
1213 };
1214
reg_pattern_test(struct igb_adapter * adapter,u64 * data,int reg,u32 mask,u32 write)1215 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1216 int reg, u32 mask, u32 write)
1217 {
1218 struct e1000_hw *hw = &adapter->hw;
1219 u32 pat, val;
1220 static const u32 _test[] = {
1221 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1222 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
1223 wr32(reg, (_test[pat] & write));
1224 val = rd32(reg) & mask;
1225 if (val != (_test[pat] & write & mask)) {
1226 dev_err(&adapter->pdev->dev,
1227 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
1228 reg, val, (_test[pat] & write & mask));
1229 *data = reg;
1230 return true;
1231 }
1232 }
1233
1234 return false;
1235 }
1236
reg_set_and_check(struct igb_adapter * adapter,u64 * data,int reg,u32 mask,u32 write)1237 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1238 int reg, u32 mask, u32 write)
1239 {
1240 struct e1000_hw *hw = &adapter->hw;
1241 u32 val;
1242
1243 wr32(reg, write & mask);
1244 val = rd32(reg);
1245 if ((write & mask) != (val & mask)) {
1246 dev_err(&adapter->pdev->dev,
1247 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n",
1248 reg, (val & mask), (write & mask));
1249 *data = reg;
1250 return true;
1251 }
1252
1253 return false;
1254 }
1255
1256 #define REG_PATTERN_TEST(reg, mask, write) \
1257 do { \
1258 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1259 return 1; \
1260 } while (0)
1261
1262 #define REG_SET_AND_CHECK(reg, mask, write) \
1263 do { \
1264 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1265 return 1; \
1266 } while (0)
1267
igb_reg_test(struct igb_adapter * adapter,u64 * data)1268 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1269 {
1270 struct e1000_hw *hw = &adapter->hw;
1271 struct igb_reg_test *test;
1272 u32 value, before, after;
1273 u32 i, toggle;
1274
1275 switch (adapter->hw.mac.type) {
1276 case e1000_i350:
1277 case e1000_i354:
1278 test = reg_test_i350;
1279 toggle = 0x7FEFF3FF;
1280 break;
1281 case e1000_i210:
1282 case e1000_i211:
1283 test = reg_test_i210;
1284 toggle = 0x7FEFF3FF;
1285 break;
1286 case e1000_82580:
1287 test = reg_test_82580;
1288 toggle = 0x7FEFF3FF;
1289 break;
1290 case e1000_82576:
1291 test = reg_test_82576;
1292 toggle = 0x7FFFF3FF;
1293 break;
1294 default:
1295 test = reg_test_82575;
1296 toggle = 0x7FFFF3FF;
1297 break;
1298 }
1299
1300 /* Because the status register is such a special case,
1301 * we handle it separately from the rest of the register
1302 * tests. Some bits are read-only, some toggle, and some
1303 * are writable on newer MACs.
1304 */
1305 before = rd32(E1000_STATUS);
1306 value = (rd32(E1000_STATUS) & toggle);
1307 wr32(E1000_STATUS, toggle);
1308 after = rd32(E1000_STATUS) & toggle;
1309 if (value != after) {
1310 dev_err(&adapter->pdev->dev,
1311 "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1312 after, value);
1313 *data = 1;
1314 return 1;
1315 }
1316 /* restore previous status */
1317 wr32(E1000_STATUS, before);
1318
1319 /* Perform the remainder of the register test, looping through
1320 * the test table until we either fail or reach the null entry.
1321 */
1322 while (test->reg) {
1323 for (i = 0; i < test->array_len; i++) {
1324 switch (test->test_type) {
1325 case PATTERN_TEST:
1326 REG_PATTERN_TEST(test->reg +
1327 (i * test->reg_offset),
1328 test->mask,
1329 test->write);
1330 break;
1331 case SET_READ_TEST:
1332 REG_SET_AND_CHECK(test->reg +
1333 (i * test->reg_offset),
1334 test->mask,
1335 test->write);
1336 break;
1337 case WRITE_NO_TEST:
1338 writel(test->write,
1339 (adapter->hw.hw_addr + test->reg)
1340 + (i * test->reg_offset));
1341 break;
1342 case TABLE32_TEST:
1343 REG_PATTERN_TEST(test->reg + (i * 4),
1344 test->mask,
1345 test->write);
1346 break;
1347 case TABLE64_TEST_LO:
1348 REG_PATTERN_TEST(test->reg + (i * 8),
1349 test->mask,
1350 test->write);
1351 break;
1352 case TABLE64_TEST_HI:
1353 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1354 test->mask,
1355 test->write);
1356 break;
1357 }
1358 }
1359 test++;
1360 }
1361
1362 *data = 0;
1363 return 0;
1364 }
1365
igb_eeprom_test(struct igb_adapter * adapter,u64 * data)1366 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1367 {
1368 struct e1000_hw *hw = &adapter->hw;
1369
1370 *data = 0;
1371
1372 /* Validate eeprom on all parts but flashless */
1373 switch (hw->mac.type) {
1374 case e1000_i210:
1375 case e1000_i211:
1376 if (igb_get_flash_presence_i210(hw)) {
1377 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1378 *data = 2;
1379 }
1380 break;
1381 default:
1382 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1383 *data = 2;
1384 break;
1385 }
1386
1387 return *data;
1388 }
1389
igb_test_intr(int irq,void * data)1390 static irqreturn_t igb_test_intr(int irq, void *data)
1391 {
1392 struct igb_adapter *adapter = (struct igb_adapter *) data;
1393 struct e1000_hw *hw = &adapter->hw;
1394
1395 adapter->test_icr |= rd32(E1000_ICR);
1396
1397 return IRQ_HANDLED;
1398 }
1399
igb_intr_test(struct igb_adapter * adapter,u64 * data)1400 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1401 {
1402 struct e1000_hw *hw = &adapter->hw;
1403 struct net_device *netdev = adapter->netdev;
1404 u32 mask, ics_mask, i = 0, shared_int = true;
1405 u32 irq = adapter->pdev->irq;
1406
1407 *data = 0;
1408
1409 /* Hook up test interrupt handler just for this test */
1410 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1411 if (request_irq(adapter->msix_entries[0].vector,
1412 igb_test_intr, 0, netdev->name, adapter)) {
1413 *data = 1;
1414 return -1;
1415 }
1416 wr32(E1000_IVAR_MISC, E1000_IVAR_VALID << 8);
1417 wr32(E1000_EIMS, BIT(0));
1418 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
1419 shared_int = false;
1420 if (request_irq(irq,
1421 igb_test_intr, 0, netdev->name, adapter)) {
1422 *data = 1;
1423 return -1;
1424 }
1425 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
1426 netdev->name, adapter)) {
1427 shared_int = false;
1428 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
1429 netdev->name, adapter)) {
1430 *data = 1;
1431 return -1;
1432 }
1433 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1434 (shared_int ? "shared" : "unshared"));
1435
1436 /* Disable all the interrupts */
1437 wr32(E1000_IMC, ~0);
1438 wrfl();
1439 usleep_range(10000, 11000);
1440
1441 /* Define all writable bits for ICS */
1442 switch (hw->mac.type) {
1443 case e1000_82575:
1444 ics_mask = 0x37F47EDD;
1445 break;
1446 case e1000_82576:
1447 ics_mask = 0x77D4FBFD;
1448 break;
1449 case e1000_82580:
1450 ics_mask = 0x77DCFED5;
1451 break;
1452 case e1000_i350:
1453 case e1000_i354:
1454 case e1000_i210:
1455 case e1000_i211:
1456 ics_mask = 0x77DCFED5;
1457 break;
1458 default:
1459 ics_mask = 0x7FFFFFFF;
1460 break;
1461 }
1462
1463 /* Test each interrupt */
1464 for (; i < 31; i++) {
1465 /* Interrupt to test */
1466 mask = BIT(i);
1467
1468 if (!(mask & ics_mask))
1469 continue;
1470
1471 if (!shared_int) {
1472 /* Disable the interrupt to be reported in
1473 * the cause register and then force the same
1474 * interrupt and see if one gets posted. If
1475 * an interrupt was posted to the bus, the
1476 * test failed.
1477 */
1478 adapter->test_icr = 0;
1479
1480 /* Flush any pending interrupts */
1481 wr32(E1000_ICR, ~0);
1482
1483 wr32(E1000_IMC, mask);
1484 wr32(E1000_ICS, mask);
1485 wrfl();
1486 usleep_range(10000, 11000);
1487
1488 if (adapter->test_icr & mask) {
1489 *data = 3;
1490 break;
1491 }
1492 }
1493
1494 /* Enable the interrupt to be reported in
1495 * the cause register and then force the same
1496 * interrupt and see if one gets posted. If
1497 * an interrupt was not posted to the bus, the
1498 * test failed.
1499 */
1500 adapter->test_icr = 0;
1501
1502 /* Flush any pending interrupts */
1503 wr32(E1000_ICR, ~0);
1504
1505 wr32(E1000_IMS, mask);
1506 wr32(E1000_ICS, mask);
1507 wrfl();
1508 usleep_range(10000, 11000);
1509
1510 if (!(adapter->test_icr & mask)) {
1511 *data = 4;
1512 break;
1513 }
1514
1515 if (!shared_int) {
1516 /* Disable the other interrupts to be reported in
1517 * the cause register and then force the other
1518 * interrupts and see if any get posted. If
1519 * an interrupt was posted to the bus, the
1520 * test failed.
1521 */
1522 adapter->test_icr = 0;
1523
1524 /* Flush any pending interrupts */
1525 wr32(E1000_ICR, ~0);
1526
1527 wr32(E1000_IMC, ~mask);
1528 wr32(E1000_ICS, ~mask);
1529 wrfl();
1530 usleep_range(10000, 11000);
1531
1532 if (adapter->test_icr & mask) {
1533 *data = 5;
1534 break;
1535 }
1536 }
1537 }
1538
1539 /* Disable all the interrupts */
1540 wr32(E1000_IMC, ~0);
1541 wrfl();
1542 usleep_range(10000, 11000);
1543
1544 /* Unhook test interrupt handler */
1545 if (adapter->flags & IGB_FLAG_HAS_MSIX)
1546 free_irq(adapter->msix_entries[0].vector, adapter);
1547 else
1548 free_irq(irq, adapter);
1549
1550 return *data;
1551 }
1552
igb_free_desc_rings(struct igb_adapter * adapter)1553 static void igb_free_desc_rings(struct igb_adapter *adapter)
1554 {
1555 igb_free_tx_resources(&adapter->test_tx_ring);
1556 igb_free_rx_resources(&adapter->test_rx_ring);
1557 }
1558
igb_setup_desc_rings(struct igb_adapter * adapter)1559 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1560 {
1561 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1562 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1563 struct e1000_hw *hw = &adapter->hw;
1564 int ret_val;
1565
1566 /* Setup Tx descriptor ring and Tx buffers */
1567 tx_ring->count = IGB_DEFAULT_TXD;
1568 tx_ring->dev = &adapter->pdev->dev;
1569 tx_ring->netdev = adapter->netdev;
1570 tx_ring->reg_idx = adapter->vfs_allocated_count;
1571
1572 if (igb_setup_tx_resources(tx_ring)) {
1573 ret_val = 1;
1574 goto err_nomem;
1575 }
1576
1577 igb_setup_tctl(adapter);
1578 igb_configure_tx_ring(adapter, tx_ring);
1579
1580 /* Setup Rx descriptor ring and Rx buffers */
1581 rx_ring->count = IGB_DEFAULT_RXD;
1582 rx_ring->dev = &adapter->pdev->dev;
1583 rx_ring->netdev = adapter->netdev;
1584 rx_ring->reg_idx = adapter->vfs_allocated_count;
1585
1586 if (igb_setup_rx_resources(rx_ring)) {
1587 ret_val = 3;
1588 goto err_nomem;
1589 }
1590
1591 /* set the default queue to queue 0 of PF */
1592 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
1593
1594 /* enable receive ring */
1595 igb_setup_rctl(adapter);
1596 igb_configure_rx_ring(adapter, rx_ring);
1597
1598 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring));
1599
1600 return 0;
1601
1602 err_nomem:
1603 igb_free_desc_rings(adapter);
1604 return ret_val;
1605 }
1606
igb_phy_disable_receiver(struct igb_adapter * adapter)1607 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1608 {
1609 struct e1000_hw *hw = &adapter->hw;
1610
1611 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1612 igb_write_phy_reg(hw, 29, 0x001F);
1613 igb_write_phy_reg(hw, 30, 0x8FFC);
1614 igb_write_phy_reg(hw, 29, 0x001A);
1615 igb_write_phy_reg(hw, 30, 0x8FF0);
1616 }
1617
igb_integrated_phy_loopback(struct igb_adapter * adapter)1618 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1619 {
1620 struct e1000_hw *hw = &adapter->hw;
1621 u32 ctrl_reg = 0;
1622
1623 hw->mac.autoneg = false;
1624
1625 if (hw->phy.type == e1000_phy_m88) {
1626 if (hw->phy.id != I210_I_PHY_ID) {
1627 /* Auto-MDI/MDIX Off */
1628 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1629 /* reset to update Auto-MDI/MDIX */
1630 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1631 /* autoneg off */
1632 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1633 } else {
1634 /* force 1000, set loopback */
1635 igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0);
1636 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1637 }
1638 } else if (hw->phy.type == e1000_phy_82580) {
1639 /* enable MII loopback */
1640 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041);
1641 }
1642
1643 /* add small delay to avoid loopback test failure */
1644 msleep(50);
1645
1646 /* force 1000, set loopback */
1647 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1648
1649 /* Now set up the MAC to the same speed/duplex as the PHY. */
1650 ctrl_reg = rd32(E1000_CTRL);
1651 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1652 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1653 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1654 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1655 E1000_CTRL_FD | /* Force Duplex to FULL */
1656 E1000_CTRL_SLU); /* Set link up enable bit */
1657
1658 if (hw->phy.type == e1000_phy_m88)
1659 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1660
1661 wr32(E1000_CTRL, ctrl_reg);
1662
1663 /* Disable the receiver on the PHY so when a cable is plugged in, the
1664 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1665 */
1666 if (hw->phy.type == e1000_phy_m88)
1667 igb_phy_disable_receiver(adapter);
1668
1669 msleep(500);
1670 return 0;
1671 }
1672
igb_set_phy_loopback(struct igb_adapter * adapter)1673 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1674 {
1675 return igb_integrated_phy_loopback(adapter);
1676 }
1677
igb_setup_loopback_test(struct igb_adapter * adapter)1678 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1679 {
1680 struct e1000_hw *hw = &adapter->hw;
1681 u32 reg;
1682
1683 reg = rd32(E1000_CTRL_EXT);
1684
1685 /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1686 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
1687 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1688 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1689 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1690 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||
1691 (hw->device_id == E1000_DEV_ID_I354_SGMII) ||
1692 (hw->device_id == E1000_DEV_ID_I354_BACKPLANE_2_5GBPS)) {
1693 /* Enable DH89xxCC MPHY for near end loopback */
1694 reg = rd32(E1000_MPHY_ADDR_CTL);
1695 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1696 E1000_MPHY_PCS_CLK_REG_OFFSET;
1697 wr32(E1000_MPHY_ADDR_CTL, reg);
1698
1699 reg = rd32(E1000_MPHY_DATA);
1700 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1701 wr32(E1000_MPHY_DATA, reg);
1702 }
1703
1704 reg = rd32(E1000_RCTL);
1705 reg |= E1000_RCTL_LBM_TCVR;
1706 wr32(E1000_RCTL, reg);
1707
1708 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1709
1710 reg = rd32(E1000_CTRL);
1711 reg &= ~(E1000_CTRL_RFCE |
1712 E1000_CTRL_TFCE |
1713 E1000_CTRL_LRST);
1714 reg |= E1000_CTRL_SLU |
1715 E1000_CTRL_FD;
1716 wr32(E1000_CTRL, reg);
1717
1718 /* Unset switch control to serdes energy detect */
1719 reg = rd32(E1000_CONNSW);
1720 reg &= ~E1000_CONNSW_ENRGSRC;
1721 wr32(E1000_CONNSW, reg);
1722
1723 /* Unset sigdetect for SERDES loopback on
1724 * 82580 and newer devices.
1725 */
1726 if (hw->mac.type >= e1000_82580) {
1727 reg = rd32(E1000_PCS_CFG0);
1728 reg |= E1000_PCS_CFG_IGN_SD;
1729 wr32(E1000_PCS_CFG0, reg);
1730 }
1731
1732 /* Set PCS register for forced speed */
1733 reg = rd32(E1000_PCS_LCTL);
1734 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1735 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1736 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1737 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1738 E1000_PCS_LCTL_FSD | /* Force Speed */
1739 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1740 wr32(E1000_PCS_LCTL, reg);
1741
1742 return 0;
1743 }
1744
1745 return igb_set_phy_loopback(adapter);
1746 }
1747
igb_loopback_cleanup(struct igb_adapter * adapter)1748 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1749 {
1750 struct e1000_hw *hw = &adapter->hw;
1751 u32 rctl;
1752 u16 phy_reg;
1753
1754 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1755 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1756 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1757 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP) ||
1758 (hw->device_id == E1000_DEV_ID_I354_SGMII)) {
1759 u32 reg;
1760
1761 /* Disable near end loopback on DH89xxCC */
1762 reg = rd32(E1000_MPHY_ADDR_CTL);
1763 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1764 E1000_MPHY_PCS_CLK_REG_OFFSET;
1765 wr32(E1000_MPHY_ADDR_CTL, reg);
1766
1767 reg = rd32(E1000_MPHY_DATA);
1768 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1769 wr32(E1000_MPHY_DATA, reg);
1770 }
1771
1772 rctl = rd32(E1000_RCTL);
1773 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1774 wr32(E1000_RCTL, rctl);
1775
1776 hw->mac.autoneg = true;
1777 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1778 if (phy_reg & MII_CR_LOOPBACK) {
1779 phy_reg &= ~MII_CR_LOOPBACK;
1780 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1781 igb_phy_sw_reset(hw);
1782 }
1783 }
1784
igb_create_lbtest_frame(struct sk_buff * skb,unsigned int frame_size)1785 static void igb_create_lbtest_frame(struct sk_buff *skb,
1786 unsigned int frame_size)
1787 {
1788 memset(skb->data, 0xFF, frame_size);
1789 frame_size /= 2;
1790 memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1791 skb->data[frame_size + 10] = 0xBE;
1792 skb->data[frame_size + 12] = 0xAF;
1793 }
1794
igb_check_lbtest_frame(struct igb_rx_buffer * rx_buffer,unsigned int frame_size)1795 static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer,
1796 unsigned int frame_size)
1797 {
1798 unsigned char *data;
1799 bool match = true;
1800
1801 frame_size >>= 1;
1802
1803 data = kmap(rx_buffer->page);
1804
1805 if (data[3] != 0xFF ||
1806 data[frame_size + 10] != 0xBE ||
1807 data[frame_size + 12] != 0xAF)
1808 match = false;
1809
1810 kunmap(rx_buffer->page);
1811
1812 return match;
1813 }
1814
igb_clean_test_rings(struct igb_ring * rx_ring,struct igb_ring * tx_ring,unsigned int size)1815 static int igb_clean_test_rings(struct igb_ring *rx_ring,
1816 struct igb_ring *tx_ring,
1817 unsigned int size)
1818 {
1819 union e1000_adv_rx_desc *rx_desc;
1820 struct igb_rx_buffer *rx_buffer_info;
1821 struct igb_tx_buffer *tx_buffer_info;
1822 u16 rx_ntc, tx_ntc, count = 0;
1823
1824 /* initialize next to clean and descriptor values */
1825 rx_ntc = rx_ring->next_to_clean;
1826 tx_ntc = tx_ring->next_to_clean;
1827 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1828
1829 while (rx_desc->wb.upper.length) {
1830 /* check Rx buffer */
1831 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
1832
1833 /* sync Rx buffer for CPU read */
1834 dma_sync_single_for_cpu(rx_ring->dev,
1835 rx_buffer_info->dma,
1836 size,
1837 DMA_FROM_DEVICE);
1838
1839 /* verify contents of skb */
1840 if (igb_check_lbtest_frame(rx_buffer_info, size))
1841 count++;
1842
1843 /* sync Rx buffer for device write */
1844 dma_sync_single_for_device(rx_ring->dev,
1845 rx_buffer_info->dma,
1846 size,
1847 DMA_FROM_DEVICE);
1848
1849 /* unmap buffer on Tx side */
1850 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
1851
1852 /* Free all the Tx ring sk_buffs */
1853 dev_kfree_skb_any(tx_buffer_info->skb);
1854
1855 /* unmap skb header data */
1856 dma_unmap_single(tx_ring->dev,
1857 dma_unmap_addr(tx_buffer_info, dma),
1858 dma_unmap_len(tx_buffer_info, len),
1859 DMA_TO_DEVICE);
1860 dma_unmap_len_set(tx_buffer_info, len, 0);
1861
1862 /* increment Rx/Tx next to clean counters */
1863 rx_ntc++;
1864 if (rx_ntc == rx_ring->count)
1865 rx_ntc = 0;
1866 tx_ntc++;
1867 if (tx_ntc == tx_ring->count)
1868 tx_ntc = 0;
1869
1870 /* fetch next descriptor */
1871 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1872 }
1873
1874 netdev_tx_reset_queue(txring_txq(tx_ring));
1875
1876 /* re-map buffers to ring, store next to clean values */
1877 igb_alloc_rx_buffers(rx_ring, count);
1878 rx_ring->next_to_clean = rx_ntc;
1879 tx_ring->next_to_clean = tx_ntc;
1880
1881 return count;
1882 }
1883
igb_run_loopback_test(struct igb_adapter * adapter)1884 static int igb_run_loopback_test(struct igb_adapter *adapter)
1885 {
1886 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1887 struct igb_ring *rx_ring = &adapter->test_rx_ring;
1888 u16 i, j, lc, good_cnt;
1889 int ret_val = 0;
1890 unsigned int size = IGB_RX_HDR_LEN;
1891 netdev_tx_t tx_ret_val;
1892 struct sk_buff *skb;
1893
1894 /* allocate test skb */
1895 skb = alloc_skb(size, GFP_KERNEL);
1896 if (!skb)
1897 return 11;
1898
1899 /* place data into test skb */
1900 igb_create_lbtest_frame(skb, size);
1901 skb_put(skb, size);
1902
1903 /* Calculate the loop count based on the largest descriptor ring
1904 * The idea is to wrap the largest ring a number of times using 64
1905 * send/receive pairs during each loop
1906 */
1907
1908 if (rx_ring->count <= tx_ring->count)
1909 lc = ((tx_ring->count / 64) * 2) + 1;
1910 else
1911 lc = ((rx_ring->count / 64) * 2) + 1;
1912
1913 for (j = 0; j <= lc; j++) { /* loop count loop */
1914 /* reset count of good packets */
1915 good_cnt = 0;
1916
1917 /* place 64 packets on the transmit queue*/
1918 for (i = 0; i < 64; i++) {
1919 skb_get(skb);
1920 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring);
1921 if (tx_ret_val == NETDEV_TX_OK)
1922 good_cnt++;
1923 }
1924
1925 if (good_cnt != 64) {
1926 ret_val = 12;
1927 break;
1928 }
1929
1930 /* allow 200 milliseconds for packets to go from Tx to Rx */
1931 msleep(200);
1932
1933 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1934 if (good_cnt != 64) {
1935 ret_val = 13;
1936 break;
1937 }
1938 } /* end loop count loop */
1939
1940 /* free the original skb */
1941 kfree_skb(skb);
1942
1943 return ret_val;
1944 }
1945
igb_loopback_test(struct igb_adapter * adapter,u64 * data)1946 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1947 {
1948 /* PHY loopback cannot be performed if SoL/IDER
1949 * sessions are active
1950 */
1951 if (igb_check_reset_block(&adapter->hw)) {
1952 dev_err(&adapter->pdev->dev,
1953 "Cannot do PHY loopback test when SoL/IDER is active.\n");
1954 *data = 0;
1955 goto out;
1956 }
1957
1958 if (adapter->hw.mac.type == e1000_i354) {
1959 dev_info(&adapter->pdev->dev,
1960 "Loopback test not supported on i354.\n");
1961 *data = 0;
1962 goto out;
1963 }
1964 *data = igb_setup_desc_rings(adapter);
1965 if (*data)
1966 goto out;
1967 *data = igb_setup_loopback_test(adapter);
1968 if (*data)
1969 goto err_loopback;
1970 *data = igb_run_loopback_test(adapter);
1971 igb_loopback_cleanup(adapter);
1972
1973 err_loopback:
1974 igb_free_desc_rings(adapter);
1975 out:
1976 return *data;
1977 }
1978
igb_link_test(struct igb_adapter * adapter,u64 * data)1979 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1980 {
1981 struct e1000_hw *hw = &adapter->hw;
1982 *data = 0;
1983 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1984 int i = 0;
1985
1986 hw->mac.serdes_has_link = false;
1987
1988 /* On some blade server designs, link establishment
1989 * could take as long as 2-3 minutes
1990 */
1991 do {
1992 hw->mac.ops.check_for_link(&adapter->hw);
1993 if (hw->mac.serdes_has_link)
1994 return *data;
1995 msleep(20);
1996 } while (i++ < 3750);
1997
1998 *data = 1;
1999 } else {
2000 hw->mac.ops.check_for_link(&adapter->hw);
2001 if (hw->mac.autoneg)
2002 msleep(5000);
2003
2004 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
2005 *data = 1;
2006 }
2007 return *data;
2008 }
2009
igb_diag_test(struct net_device * netdev,struct ethtool_test * eth_test,u64 * data)2010 static void igb_diag_test(struct net_device *netdev,
2011 struct ethtool_test *eth_test, u64 *data)
2012 {
2013 struct igb_adapter *adapter = netdev_priv(netdev);
2014 u16 autoneg_advertised;
2015 u8 forced_speed_duplex, autoneg;
2016 bool if_running = netif_running(netdev);
2017
2018 set_bit(__IGB_TESTING, &adapter->state);
2019
2020 /* can't do offline tests on media switching devices */
2021 if (adapter->hw.dev_spec._82575.mas_capable)
2022 eth_test->flags &= ~ETH_TEST_FL_OFFLINE;
2023 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
2024 /* Offline tests */
2025
2026 /* save speed, duplex, autoneg settings */
2027 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
2028 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
2029 autoneg = adapter->hw.mac.autoneg;
2030
2031 dev_info(&adapter->pdev->dev, "offline testing starting\n");
2032
2033 /* power up link for link test */
2034 igb_power_up_link(adapter);
2035
2036 /* Link test performed before hardware reset so autoneg doesn't
2037 * interfere with test result
2038 */
2039 if (igb_link_test(adapter, &data[TEST_LINK]))
2040 eth_test->flags |= ETH_TEST_FL_FAILED;
2041
2042 if (if_running)
2043 /* indicate we're in test mode */
2044 igb_close(netdev);
2045 else
2046 igb_reset(adapter);
2047
2048 if (igb_reg_test(adapter, &data[TEST_REG]))
2049 eth_test->flags |= ETH_TEST_FL_FAILED;
2050
2051 igb_reset(adapter);
2052 if (igb_eeprom_test(adapter, &data[TEST_EEP]))
2053 eth_test->flags |= ETH_TEST_FL_FAILED;
2054
2055 igb_reset(adapter);
2056 if (igb_intr_test(adapter, &data[TEST_IRQ]))
2057 eth_test->flags |= ETH_TEST_FL_FAILED;
2058
2059 igb_reset(adapter);
2060 /* power up link for loopback test */
2061 igb_power_up_link(adapter);
2062 if (igb_loopback_test(adapter, &data[TEST_LOOP]))
2063 eth_test->flags |= ETH_TEST_FL_FAILED;
2064
2065 /* restore speed, duplex, autoneg settings */
2066 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
2067 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
2068 adapter->hw.mac.autoneg = autoneg;
2069
2070 /* force this routine to wait until autoneg complete/timeout */
2071 adapter->hw.phy.autoneg_wait_to_complete = true;
2072 igb_reset(adapter);
2073 adapter->hw.phy.autoneg_wait_to_complete = false;
2074
2075 clear_bit(__IGB_TESTING, &adapter->state);
2076 if (if_running)
2077 igb_open(netdev);
2078 } else {
2079 dev_info(&adapter->pdev->dev, "online testing starting\n");
2080
2081 /* PHY is powered down when interface is down */
2082 if (if_running && igb_link_test(adapter, &data[TEST_LINK]))
2083 eth_test->flags |= ETH_TEST_FL_FAILED;
2084 else
2085 data[TEST_LINK] = 0;
2086
2087 /* Online tests aren't run; pass by default */
2088 data[TEST_REG] = 0;
2089 data[TEST_EEP] = 0;
2090 data[TEST_IRQ] = 0;
2091 data[TEST_LOOP] = 0;
2092
2093 clear_bit(__IGB_TESTING, &adapter->state);
2094 }
2095 msleep_interruptible(4 * 1000);
2096 }
2097
igb_get_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)2098 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2099 {
2100 struct igb_adapter *adapter = netdev_priv(netdev);
2101
2102 wol->wolopts = 0;
2103
2104 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
2105 return;
2106
2107 wol->supported = WAKE_UCAST | WAKE_MCAST |
2108 WAKE_BCAST | WAKE_MAGIC |
2109 WAKE_PHY;
2110
2111 /* apply any specific unsupported masks here */
2112 switch (adapter->hw.device_id) {
2113 default:
2114 break;
2115 }
2116
2117 if (adapter->wol & E1000_WUFC_EX)
2118 wol->wolopts |= WAKE_UCAST;
2119 if (adapter->wol & E1000_WUFC_MC)
2120 wol->wolopts |= WAKE_MCAST;
2121 if (adapter->wol & E1000_WUFC_BC)
2122 wol->wolopts |= WAKE_BCAST;
2123 if (adapter->wol & E1000_WUFC_MAG)
2124 wol->wolopts |= WAKE_MAGIC;
2125 if (adapter->wol & E1000_WUFC_LNKC)
2126 wol->wolopts |= WAKE_PHY;
2127 }
2128
igb_set_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)2129 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2130 {
2131 struct igb_adapter *adapter = netdev_priv(netdev);
2132
2133 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE | WAKE_FILTER))
2134 return -EOPNOTSUPP;
2135
2136 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
2137 return wol->wolopts ? -EOPNOTSUPP : 0;
2138
2139 /* these settings will always override what we currently have */
2140 adapter->wol = 0;
2141
2142 if (wol->wolopts & WAKE_UCAST)
2143 adapter->wol |= E1000_WUFC_EX;
2144 if (wol->wolopts & WAKE_MCAST)
2145 adapter->wol |= E1000_WUFC_MC;
2146 if (wol->wolopts & WAKE_BCAST)
2147 adapter->wol |= E1000_WUFC_BC;
2148 if (wol->wolopts & WAKE_MAGIC)
2149 adapter->wol |= E1000_WUFC_MAG;
2150 if (wol->wolopts & WAKE_PHY)
2151 adapter->wol |= E1000_WUFC_LNKC;
2152 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2153
2154 return 0;
2155 }
2156
2157 /* bit defines for adapter->led_status */
2158 #define IGB_LED_ON 0
2159
igb_set_phys_id(struct net_device * netdev,enum ethtool_phys_id_state state)2160 static int igb_set_phys_id(struct net_device *netdev,
2161 enum ethtool_phys_id_state state)
2162 {
2163 struct igb_adapter *adapter = netdev_priv(netdev);
2164 struct e1000_hw *hw = &adapter->hw;
2165
2166 switch (state) {
2167 case ETHTOOL_ID_ACTIVE:
2168 igb_blink_led(hw);
2169 return 2;
2170 case ETHTOOL_ID_ON:
2171 igb_blink_led(hw);
2172 break;
2173 case ETHTOOL_ID_OFF:
2174 igb_led_off(hw);
2175 break;
2176 case ETHTOOL_ID_INACTIVE:
2177 igb_led_off(hw);
2178 clear_bit(IGB_LED_ON, &adapter->led_status);
2179 igb_cleanup_led(hw);
2180 break;
2181 }
2182
2183 return 0;
2184 }
2185
igb_set_coalesce(struct net_device * netdev,struct ethtool_coalesce * ec)2186 static int igb_set_coalesce(struct net_device *netdev,
2187 struct ethtool_coalesce *ec)
2188 {
2189 struct igb_adapter *adapter = netdev_priv(netdev);
2190 int i;
2191
2192 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2193 ((ec->rx_coalesce_usecs > 3) &&
2194 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2195 (ec->rx_coalesce_usecs == 2))
2196 return -EINVAL;
2197
2198 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2199 ((ec->tx_coalesce_usecs > 3) &&
2200 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2201 (ec->tx_coalesce_usecs == 2))
2202 return -EINVAL;
2203
2204 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
2205 return -EINVAL;
2206
2207 /* If ITR is disabled, disable DMAC */
2208 if (ec->rx_coalesce_usecs == 0) {
2209 if (adapter->flags & IGB_FLAG_DMAC)
2210 adapter->flags &= ~IGB_FLAG_DMAC;
2211 }
2212
2213 /* convert to rate of irq's per second */
2214 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
2215 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2216 else
2217 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2218
2219 /* convert to rate of irq's per second */
2220 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
2221 adapter->tx_itr_setting = adapter->rx_itr_setting;
2222 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
2223 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2224 else
2225 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2226
2227 for (i = 0; i < adapter->num_q_vectors; i++) {
2228 struct igb_q_vector *q_vector = adapter->q_vector[i];
2229 q_vector->tx.work_limit = adapter->tx_work_limit;
2230 if (q_vector->rx.ring)
2231 q_vector->itr_val = adapter->rx_itr_setting;
2232 else
2233 q_vector->itr_val = adapter->tx_itr_setting;
2234 if (q_vector->itr_val && q_vector->itr_val <= 3)
2235 q_vector->itr_val = IGB_START_ITR;
2236 q_vector->set_itr = 1;
2237 }
2238
2239 return 0;
2240 }
2241
igb_get_coalesce(struct net_device * netdev,struct ethtool_coalesce * ec)2242 static int igb_get_coalesce(struct net_device *netdev,
2243 struct ethtool_coalesce *ec)
2244 {
2245 struct igb_adapter *adapter = netdev_priv(netdev);
2246
2247 if (adapter->rx_itr_setting <= 3)
2248 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2249 else
2250 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2251
2252 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
2253 if (adapter->tx_itr_setting <= 3)
2254 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2255 else
2256 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2257 }
2258
2259 return 0;
2260 }
2261
igb_nway_reset(struct net_device * netdev)2262 static int igb_nway_reset(struct net_device *netdev)
2263 {
2264 struct igb_adapter *adapter = netdev_priv(netdev);
2265 if (netif_running(netdev))
2266 igb_reinit_locked(adapter);
2267 return 0;
2268 }
2269
igb_get_sset_count(struct net_device * netdev,int sset)2270 static int igb_get_sset_count(struct net_device *netdev, int sset)
2271 {
2272 switch (sset) {
2273 case ETH_SS_STATS:
2274 return IGB_STATS_LEN;
2275 case ETH_SS_TEST:
2276 return IGB_TEST_LEN;
2277 case ETH_SS_PRIV_FLAGS:
2278 return IGB_PRIV_FLAGS_STR_LEN;
2279 default:
2280 return -ENOTSUPP;
2281 }
2282 }
2283
igb_get_ethtool_stats(struct net_device * netdev,struct ethtool_stats * stats,u64 * data)2284 static void igb_get_ethtool_stats(struct net_device *netdev,
2285 struct ethtool_stats *stats, u64 *data)
2286 {
2287 struct igb_adapter *adapter = netdev_priv(netdev);
2288 struct rtnl_link_stats64 *net_stats = &adapter->stats64;
2289 unsigned int start;
2290 struct igb_ring *ring;
2291 int i, j;
2292 char *p;
2293
2294 spin_lock(&adapter->stats64_lock);
2295 igb_update_stats(adapter);
2296
2297 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2298 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
2299 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2300 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2301 }
2302 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2303 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2304 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2305 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2306 }
2307 for (j = 0; j < adapter->num_tx_queues; j++) {
2308 u64 restart2;
2309
2310 ring = adapter->tx_ring[j];
2311 do {
2312 start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
2313 data[i] = ring->tx_stats.packets;
2314 data[i+1] = ring->tx_stats.bytes;
2315 data[i+2] = ring->tx_stats.restart_queue;
2316 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
2317 do {
2318 start = u64_stats_fetch_begin_irq(&ring->tx_syncp2);
2319 restart2 = ring->tx_stats.restart_queue2;
2320 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp2, start));
2321 data[i+2] += restart2;
2322
2323 i += IGB_TX_QUEUE_STATS_LEN;
2324 }
2325 for (j = 0; j < adapter->num_rx_queues; j++) {
2326 ring = adapter->rx_ring[j];
2327 do {
2328 start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
2329 data[i] = ring->rx_stats.packets;
2330 data[i+1] = ring->rx_stats.bytes;
2331 data[i+2] = ring->rx_stats.drops;
2332 data[i+3] = ring->rx_stats.csum_err;
2333 data[i+4] = ring->rx_stats.alloc_failed;
2334 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
2335 i += IGB_RX_QUEUE_STATS_LEN;
2336 }
2337 spin_unlock(&adapter->stats64_lock);
2338 }
2339
igb_get_strings(struct net_device * netdev,u32 stringset,u8 * data)2340 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2341 {
2342 struct igb_adapter *adapter = netdev_priv(netdev);
2343 u8 *p = data;
2344 int i;
2345
2346 switch (stringset) {
2347 case ETH_SS_TEST:
2348 memcpy(data, *igb_gstrings_test,
2349 IGB_TEST_LEN*ETH_GSTRING_LEN);
2350 break;
2351 case ETH_SS_STATS:
2352 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2353 memcpy(p, igb_gstrings_stats[i].stat_string,
2354 ETH_GSTRING_LEN);
2355 p += ETH_GSTRING_LEN;
2356 }
2357 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
2358 memcpy(p, igb_gstrings_net_stats[i].stat_string,
2359 ETH_GSTRING_LEN);
2360 p += ETH_GSTRING_LEN;
2361 }
2362 for (i = 0; i < adapter->num_tx_queues; i++) {
2363 sprintf(p, "tx_queue_%u_packets", i);
2364 p += ETH_GSTRING_LEN;
2365 sprintf(p, "tx_queue_%u_bytes", i);
2366 p += ETH_GSTRING_LEN;
2367 sprintf(p, "tx_queue_%u_restart", i);
2368 p += ETH_GSTRING_LEN;
2369 }
2370 for (i = 0; i < adapter->num_rx_queues; i++) {
2371 sprintf(p, "rx_queue_%u_packets", i);
2372 p += ETH_GSTRING_LEN;
2373 sprintf(p, "rx_queue_%u_bytes", i);
2374 p += ETH_GSTRING_LEN;
2375 sprintf(p, "rx_queue_%u_drops", i);
2376 p += ETH_GSTRING_LEN;
2377 sprintf(p, "rx_queue_%u_csum_err", i);
2378 p += ETH_GSTRING_LEN;
2379 sprintf(p, "rx_queue_%u_alloc_failed", i);
2380 p += ETH_GSTRING_LEN;
2381 }
2382 /* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2383 break;
2384 case ETH_SS_PRIV_FLAGS:
2385 memcpy(data, igb_priv_flags_strings,
2386 IGB_PRIV_FLAGS_STR_LEN * ETH_GSTRING_LEN);
2387 break;
2388 }
2389 }
2390
igb_get_ts_info(struct net_device * dev,struct ethtool_ts_info * info)2391 static int igb_get_ts_info(struct net_device *dev,
2392 struct ethtool_ts_info *info)
2393 {
2394 struct igb_adapter *adapter = netdev_priv(dev);
2395
2396 if (adapter->ptp_clock)
2397 info->phc_index = ptp_clock_index(adapter->ptp_clock);
2398 else
2399 info->phc_index = -1;
2400
2401 switch (adapter->hw.mac.type) {
2402 case e1000_82575:
2403 info->so_timestamping =
2404 SOF_TIMESTAMPING_TX_SOFTWARE |
2405 SOF_TIMESTAMPING_RX_SOFTWARE |
2406 SOF_TIMESTAMPING_SOFTWARE;
2407 return 0;
2408 case e1000_82576:
2409 case e1000_82580:
2410 case e1000_i350:
2411 case e1000_i354:
2412 case e1000_i210:
2413 case e1000_i211:
2414 info->so_timestamping =
2415 SOF_TIMESTAMPING_TX_SOFTWARE |
2416 SOF_TIMESTAMPING_RX_SOFTWARE |
2417 SOF_TIMESTAMPING_SOFTWARE |
2418 SOF_TIMESTAMPING_TX_HARDWARE |
2419 SOF_TIMESTAMPING_RX_HARDWARE |
2420 SOF_TIMESTAMPING_RAW_HARDWARE;
2421
2422 info->tx_types =
2423 BIT(HWTSTAMP_TX_OFF) |
2424 BIT(HWTSTAMP_TX_ON);
2425
2426 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE);
2427
2428 /* 82576 does not support timestamping all packets. */
2429 if (adapter->hw.mac.type >= e1000_82580)
2430 info->rx_filters |= BIT(HWTSTAMP_FILTER_ALL);
2431 else
2432 info->rx_filters |=
2433 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2434 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2435 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT);
2436
2437 return 0;
2438 default:
2439 return -EOPNOTSUPP;
2440 }
2441 }
2442
2443 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0)
igb_get_ethtool_nfc_entry(struct igb_adapter * adapter,struct ethtool_rxnfc * cmd)2444 static int igb_get_ethtool_nfc_entry(struct igb_adapter *adapter,
2445 struct ethtool_rxnfc *cmd)
2446 {
2447 struct ethtool_rx_flow_spec *fsp = &cmd->fs;
2448 struct igb_nfc_filter *rule = NULL;
2449
2450 /* report total rule count */
2451 cmd->data = IGB_MAX_RXNFC_FILTERS;
2452
2453 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {
2454 if (fsp->location <= rule->sw_idx)
2455 break;
2456 }
2457
2458 if (!rule || fsp->location != rule->sw_idx)
2459 return -EINVAL;
2460
2461 if (rule->filter.match_flags) {
2462 fsp->flow_type = ETHER_FLOW;
2463 fsp->ring_cookie = rule->action;
2464 if (rule->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) {
2465 fsp->h_u.ether_spec.h_proto = rule->filter.etype;
2466 fsp->m_u.ether_spec.h_proto = ETHER_TYPE_FULL_MASK;
2467 }
2468 if (rule->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI) {
2469 fsp->flow_type |= FLOW_EXT;
2470 fsp->h_ext.vlan_tci = rule->filter.vlan_tci;
2471 fsp->m_ext.vlan_tci = htons(VLAN_PRIO_MASK);
2472 }
2473 if (rule->filter.match_flags & IGB_FILTER_FLAG_DST_MAC_ADDR) {
2474 ether_addr_copy(fsp->h_u.ether_spec.h_dest,
2475 rule->filter.dst_addr);
2476 /* As we only support matching by the full
2477 * mask, return the mask to userspace
2478 */
2479 eth_broadcast_addr(fsp->m_u.ether_spec.h_dest);
2480 }
2481 if (rule->filter.match_flags & IGB_FILTER_FLAG_SRC_MAC_ADDR) {
2482 ether_addr_copy(fsp->h_u.ether_spec.h_source,
2483 rule->filter.src_addr);
2484 /* As we only support matching by the full
2485 * mask, return the mask to userspace
2486 */
2487 eth_broadcast_addr(fsp->m_u.ether_spec.h_source);
2488 }
2489
2490 return 0;
2491 }
2492 return -EINVAL;
2493 }
2494
igb_get_ethtool_nfc_all(struct igb_adapter * adapter,struct ethtool_rxnfc * cmd,u32 * rule_locs)2495 static int igb_get_ethtool_nfc_all(struct igb_adapter *adapter,
2496 struct ethtool_rxnfc *cmd,
2497 u32 *rule_locs)
2498 {
2499 struct igb_nfc_filter *rule;
2500 int cnt = 0;
2501
2502 /* report total rule count */
2503 cmd->data = IGB_MAX_RXNFC_FILTERS;
2504
2505 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {
2506 if (cnt == cmd->rule_cnt)
2507 return -EMSGSIZE;
2508 rule_locs[cnt] = rule->sw_idx;
2509 cnt++;
2510 }
2511
2512 cmd->rule_cnt = cnt;
2513
2514 return 0;
2515 }
2516
igb_get_rss_hash_opts(struct igb_adapter * adapter,struct ethtool_rxnfc * cmd)2517 static int igb_get_rss_hash_opts(struct igb_adapter *adapter,
2518 struct ethtool_rxnfc *cmd)
2519 {
2520 cmd->data = 0;
2521
2522 /* Report default options for RSS on igb */
2523 switch (cmd->flow_type) {
2524 case TCP_V4_FLOW:
2525 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2526 fallthrough;
2527 case UDP_V4_FLOW:
2528 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2529 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2530 fallthrough;
2531 case SCTP_V4_FLOW:
2532 case AH_ESP_V4_FLOW:
2533 case AH_V4_FLOW:
2534 case ESP_V4_FLOW:
2535 case IPV4_FLOW:
2536 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2537 break;
2538 case TCP_V6_FLOW:
2539 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2540 fallthrough;
2541 case UDP_V6_FLOW:
2542 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2543 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2544 fallthrough;
2545 case SCTP_V6_FLOW:
2546 case AH_ESP_V6_FLOW:
2547 case AH_V6_FLOW:
2548 case ESP_V6_FLOW:
2549 case IPV6_FLOW:
2550 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2551 break;
2552 default:
2553 return -EINVAL;
2554 }
2555
2556 return 0;
2557 }
2558
igb_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd,u32 * rule_locs)2559 static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2560 u32 *rule_locs)
2561 {
2562 struct igb_adapter *adapter = netdev_priv(dev);
2563 int ret = -EOPNOTSUPP;
2564
2565 switch (cmd->cmd) {
2566 case ETHTOOL_GRXRINGS:
2567 cmd->data = adapter->num_rx_queues;
2568 ret = 0;
2569 break;
2570 case ETHTOOL_GRXCLSRLCNT:
2571 cmd->rule_cnt = adapter->nfc_filter_count;
2572 ret = 0;
2573 break;
2574 case ETHTOOL_GRXCLSRULE:
2575 ret = igb_get_ethtool_nfc_entry(adapter, cmd);
2576 break;
2577 case ETHTOOL_GRXCLSRLALL:
2578 ret = igb_get_ethtool_nfc_all(adapter, cmd, rule_locs);
2579 break;
2580 case ETHTOOL_GRXFH:
2581 ret = igb_get_rss_hash_opts(adapter, cmd);
2582 break;
2583 default:
2584 break;
2585 }
2586
2587 return ret;
2588 }
2589
2590 #define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \
2591 IGB_FLAG_RSS_FIELD_IPV6_UDP)
igb_set_rss_hash_opt(struct igb_adapter * adapter,struct ethtool_rxnfc * nfc)2592 static int igb_set_rss_hash_opt(struct igb_adapter *adapter,
2593 struct ethtool_rxnfc *nfc)
2594 {
2595 u32 flags = adapter->flags;
2596
2597 /* RSS does not support anything other than hashing
2598 * to queues on src and dst IPs and ports
2599 */
2600 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2601 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2602 return -EINVAL;
2603
2604 switch (nfc->flow_type) {
2605 case TCP_V4_FLOW:
2606 case TCP_V6_FLOW:
2607 if (!(nfc->data & RXH_IP_SRC) ||
2608 !(nfc->data & RXH_IP_DST) ||
2609 !(nfc->data & RXH_L4_B_0_1) ||
2610 !(nfc->data & RXH_L4_B_2_3))
2611 return -EINVAL;
2612 break;
2613 case UDP_V4_FLOW:
2614 if (!(nfc->data & RXH_IP_SRC) ||
2615 !(nfc->data & RXH_IP_DST))
2616 return -EINVAL;
2617 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2618 case 0:
2619 flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP;
2620 break;
2621 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2622 flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP;
2623 break;
2624 default:
2625 return -EINVAL;
2626 }
2627 break;
2628 case UDP_V6_FLOW:
2629 if (!(nfc->data & RXH_IP_SRC) ||
2630 !(nfc->data & RXH_IP_DST))
2631 return -EINVAL;
2632 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2633 case 0:
2634 flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP;
2635 break;
2636 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2637 flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP;
2638 break;
2639 default:
2640 return -EINVAL;
2641 }
2642 break;
2643 case AH_ESP_V4_FLOW:
2644 case AH_V4_FLOW:
2645 case ESP_V4_FLOW:
2646 case SCTP_V4_FLOW:
2647 case AH_ESP_V6_FLOW:
2648 case AH_V6_FLOW:
2649 case ESP_V6_FLOW:
2650 case SCTP_V6_FLOW:
2651 if (!(nfc->data & RXH_IP_SRC) ||
2652 !(nfc->data & RXH_IP_DST) ||
2653 (nfc->data & RXH_L4_B_0_1) ||
2654 (nfc->data & RXH_L4_B_2_3))
2655 return -EINVAL;
2656 break;
2657 default:
2658 return -EINVAL;
2659 }
2660
2661 /* if we changed something we need to update flags */
2662 if (flags != adapter->flags) {
2663 struct e1000_hw *hw = &adapter->hw;
2664 u32 mrqc = rd32(E1000_MRQC);
2665
2666 if ((flags & UDP_RSS_FLAGS) &&
2667 !(adapter->flags & UDP_RSS_FLAGS))
2668 dev_err(&adapter->pdev->dev,
2669 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
2670
2671 adapter->flags = flags;
2672
2673 /* Perform hash on these packet types */
2674 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |
2675 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2676 E1000_MRQC_RSS_FIELD_IPV6 |
2677 E1000_MRQC_RSS_FIELD_IPV6_TCP;
2678
2679 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP |
2680 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2681
2682 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2683 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
2684
2685 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2686 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
2687
2688 wr32(E1000_MRQC, mrqc);
2689 }
2690
2691 return 0;
2692 }
2693
igb_rxnfc_write_etype_filter(struct igb_adapter * adapter,struct igb_nfc_filter * input)2694 static int igb_rxnfc_write_etype_filter(struct igb_adapter *adapter,
2695 struct igb_nfc_filter *input)
2696 {
2697 struct e1000_hw *hw = &adapter->hw;
2698 u8 i;
2699 u32 etqf;
2700 u16 etype;
2701
2702 /* find an empty etype filter register */
2703 for (i = 0; i < MAX_ETYPE_FILTER; ++i) {
2704 if (!adapter->etype_bitmap[i])
2705 break;
2706 }
2707 if (i == MAX_ETYPE_FILTER) {
2708 dev_err(&adapter->pdev->dev, "ethtool -N: etype filters are all used.\n");
2709 return -EINVAL;
2710 }
2711
2712 adapter->etype_bitmap[i] = true;
2713
2714 etqf = rd32(E1000_ETQF(i));
2715 etype = ntohs(input->filter.etype & ETHER_TYPE_FULL_MASK);
2716
2717 etqf |= E1000_ETQF_FILTER_ENABLE;
2718 etqf &= ~E1000_ETQF_ETYPE_MASK;
2719 etqf |= (etype & E1000_ETQF_ETYPE_MASK);
2720
2721 etqf &= ~E1000_ETQF_QUEUE_MASK;
2722 etqf |= ((input->action << E1000_ETQF_QUEUE_SHIFT)
2723 & E1000_ETQF_QUEUE_MASK);
2724 etqf |= E1000_ETQF_QUEUE_ENABLE;
2725
2726 wr32(E1000_ETQF(i), etqf);
2727
2728 input->etype_reg_index = i;
2729
2730 return 0;
2731 }
2732
igb_rxnfc_write_vlan_prio_filter(struct igb_adapter * adapter,struct igb_nfc_filter * input)2733 static int igb_rxnfc_write_vlan_prio_filter(struct igb_adapter *adapter,
2734 struct igb_nfc_filter *input)
2735 {
2736 struct e1000_hw *hw = &adapter->hw;
2737 u8 vlan_priority;
2738 u16 queue_index;
2739 u32 vlapqf;
2740
2741 vlapqf = rd32(E1000_VLAPQF);
2742 vlan_priority = (ntohs(input->filter.vlan_tci) & VLAN_PRIO_MASK)
2743 >> VLAN_PRIO_SHIFT;
2744 queue_index = (vlapqf >> (vlan_priority * 4)) & E1000_VLAPQF_QUEUE_MASK;
2745
2746 /* check whether this vlan prio is already set */
2747 if ((vlapqf & E1000_VLAPQF_P_VALID(vlan_priority)) &&
2748 (queue_index != input->action)) {
2749 dev_err(&adapter->pdev->dev, "ethtool rxnfc set vlan prio filter failed.\n");
2750 return -EEXIST;
2751 }
2752
2753 vlapqf |= E1000_VLAPQF_P_VALID(vlan_priority);
2754 vlapqf |= E1000_VLAPQF_QUEUE_SEL(vlan_priority, input->action);
2755
2756 wr32(E1000_VLAPQF, vlapqf);
2757
2758 return 0;
2759 }
2760
igb_add_filter(struct igb_adapter * adapter,struct igb_nfc_filter * input)2761 int igb_add_filter(struct igb_adapter *adapter, struct igb_nfc_filter *input)
2762 {
2763 struct e1000_hw *hw = &adapter->hw;
2764 int err = -EINVAL;
2765
2766 if (hw->mac.type == e1000_i210 &&
2767 !(input->filter.match_flags & ~IGB_FILTER_FLAG_SRC_MAC_ADDR)) {
2768 dev_err(&adapter->pdev->dev,
2769 "i210 doesn't support flow classification rules specifying only source addresses.\n");
2770 return -EOPNOTSUPP;
2771 }
2772
2773 if (input->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE) {
2774 err = igb_rxnfc_write_etype_filter(adapter, input);
2775 if (err)
2776 return err;
2777 }
2778
2779 if (input->filter.match_flags & IGB_FILTER_FLAG_DST_MAC_ADDR) {
2780 err = igb_add_mac_steering_filter(adapter,
2781 input->filter.dst_addr,
2782 input->action, 0);
2783 err = min_t(int, err, 0);
2784 if (err)
2785 return err;
2786 }
2787
2788 if (input->filter.match_flags & IGB_FILTER_FLAG_SRC_MAC_ADDR) {
2789 err = igb_add_mac_steering_filter(adapter,
2790 input->filter.src_addr,
2791 input->action,
2792 IGB_MAC_STATE_SRC_ADDR);
2793 err = min_t(int, err, 0);
2794 if (err)
2795 return err;
2796 }
2797
2798 if (input->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI)
2799 err = igb_rxnfc_write_vlan_prio_filter(adapter, input);
2800
2801 return err;
2802 }
2803
igb_clear_etype_filter_regs(struct igb_adapter * adapter,u16 reg_index)2804 static void igb_clear_etype_filter_regs(struct igb_adapter *adapter,
2805 u16 reg_index)
2806 {
2807 struct e1000_hw *hw = &adapter->hw;
2808 u32 etqf = rd32(E1000_ETQF(reg_index));
2809
2810 etqf &= ~E1000_ETQF_QUEUE_ENABLE;
2811 etqf &= ~E1000_ETQF_QUEUE_MASK;
2812 etqf &= ~E1000_ETQF_FILTER_ENABLE;
2813
2814 wr32(E1000_ETQF(reg_index), etqf);
2815
2816 adapter->etype_bitmap[reg_index] = false;
2817 }
2818
igb_clear_vlan_prio_filter(struct igb_adapter * adapter,u16 vlan_tci)2819 static void igb_clear_vlan_prio_filter(struct igb_adapter *adapter,
2820 u16 vlan_tci)
2821 {
2822 struct e1000_hw *hw = &adapter->hw;
2823 u8 vlan_priority;
2824 u32 vlapqf;
2825
2826 vlan_priority = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
2827
2828 vlapqf = rd32(E1000_VLAPQF);
2829 vlapqf &= ~E1000_VLAPQF_P_VALID(vlan_priority);
2830 vlapqf &= ~E1000_VLAPQF_QUEUE_SEL(vlan_priority,
2831 E1000_VLAPQF_QUEUE_MASK);
2832
2833 wr32(E1000_VLAPQF, vlapqf);
2834 }
2835
igb_erase_filter(struct igb_adapter * adapter,struct igb_nfc_filter * input)2836 int igb_erase_filter(struct igb_adapter *adapter, struct igb_nfc_filter *input)
2837 {
2838 if (input->filter.match_flags & IGB_FILTER_FLAG_ETHER_TYPE)
2839 igb_clear_etype_filter_regs(adapter,
2840 input->etype_reg_index);
2841
2842 if (input->filter.match_flags & IGB_FILTER_FLAG_VLAN_TCI)
2843 igb_clear_vlan_prio_filter(adapter,
2844 ntohs(input->filter.vlan_tci));
2845
2846 if (input->filter.match_flags & IGB_FILTER_FLAG_SRC_MAC_ADDR)
2847 igb_del_mac_steering_filter(adapter, input->filter.src_addr,
2848 input->action,
2849 IGB_MAC_STATE_SRC_ADDR);
2850
2851 if (input->filter.match_flags & IGB_FILTER_FLAG_DST_MAC_ADDR)
2852 igb_del_mac_steering_filter(adapter, input->filter.dst_addr,
2853 input->action, 0);
2854
2855 return 0;
2856 }
2857
igb_update_ethtool_nfc_entry(struct igb_adapter * adapter,struct igb_nfc_filter * input,u16 sw_idx)2858 static int igb_update_ethtool_nfc_entry(struct igb_adapter *adapter,
2859 struct igb_nfc_filter *input,
2860 u16 sw_idx)
2861 {
2862 struct igb_nfc_filter *rule, *parent;
2863 int err = -EINVAL;
2864
2865 parent = NULL;
2866 rule = NULL;
2867
2868 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {
2869 /* hash found, or no matching entry */
2870 if (rule->sw_idx >= sw_idx)
2871 break;
2872 parent = rule;
2873 }
2874
2875 /* if there is an old rule occupying our place remove it */
2876 if (rule && (rule->sw_idx == sw_idx)) {
2877 if (!input)
2878 err = igb_erase_filter(adapter, rule);
2879
2880 hlist_del(&rule->nfc_node);
2881 kfree(rule);
2882 adapter->nfc_filter_count--;
2883 }
2884
2885 /* If no input this was a delete, err should be 0 if a rule was
2886 * successfully found and removed from the list else -EINVAL
2887 */
2888 if (!input)
2889 return err;
2890
2891 /* initialize node */
2892 INIT_HLIST_NODE(&input->nfc_node);
2893
2894 /* add filter to the list */
2895 if (parent)
2896 hlist_add_behind(&input->nfc_node, &parent->nfc_node);
2897 else
2898 hlist_add_head(&input->nfc_node, &adapter->nfc_filter_list);
2899
2900 /* update counts */
2901 adapter->nfc_filter_count++;
2902
2903 return 0;
2904 }
2905
igb_add_ethtool_nfc_entry(struct igb_adapter * adapter,struct ethtool_rxnfc * cmd)2906 static int igb_add_ethtool_nfc_entry(struct igb_adapter *adapter,
2907 struct ethtool_rxnfc *cmd)
2908 {
2909 struct net_device *netdev = adapter->netdev;
2910 struct ethtool_rx_flow_spec *fsp =
2911 (struct ethtool_rx_flow_spec *)&cmd->fs;
2912 struct igb_nfc_filter *input, *rule;
2913 int err = 0;
2914
2915 if (!(netdev->hw_features & NETIF_F_NTUPLE))
2916 return -EOPNOTSUPP;
2917
2918 /* Don't allow programming if the action is a queue greater than
2919 * the number of online Rx queues.
2920 */
2921 if ((fsp->ring_cookie == RX_CLS_FLOW_DISC) ||
2922 (fsp->ring_cookie >= adapter->num_rx_queues)) {
2923 dev_err(&adapter->pdev->dev, "ethtool -N: The specified action is invalid\n");
2924 return -EINVAL;
2925 }
2926
2927 /* Don't allow indexes to exist outside of available space */
2928 if (fsp->location >= IGB_MAX_RXNFC_FILTERS) {
2929 dev_err(&adapter->pdev->dev, "Location out of range\n");
2930 return -EINVAL;
2931 }
2932
2933 if ((fsp->flow_type & ~FLOW_EXT) != ETHER_FLOW)
2934 return -EINVAL;
2935
2936 input = kzalloc(sizeof(*input), GFP_KERNEL);
2937 if (!input)
2938 return -ENOMEM;
2939
2940 if (fsp->m_u.ether_spec.h_proto == ETHER_TYPE_FULL_MASK) {
2941 input->filter.etype = fsp->h_u.ether_spec.h_proto;
2942 input->filter.match_flags = IGB_FILTER_FLAG_ETHER_TYPE;
2943 }
2944
2945 /* Only support matching addresses by the full mask */
2946 if (is_broadcast_ether_addr(fsp->m_u.ether_spec.h_source)) {
2947 input->filter.match_flags |= IGB_FILTER_FLAG_SRC_MAC_ADDR;
2948 ether_addr_copy(input->filter.src_addr,
2949 fsp->h_u.ether_spec.h_source);
2950 }
2951
2952 /* Only support matching addresses by the full mask */
2953 if (is_broadcast_ether_addr(fsp->m_u.ether_spec.h_dest)) {
2954 input->filter.match_flags |= IGB_FILTER_FLAG_DST_MAC_ADDR;
2955 ether_addr_copy(input->filter.dst_addr,
2956 fsp->h_u.ether_spec.h_dest);
2957 }
2958
2959 if ((fsp->flow_type & FLOW_EXT) && fsp->m_ext.vlan_tci) {
2960 if (fsp->m_ext.vlan_tci != htons(VLAN_PRIO_MASK)) {
2961 err = -EINVAL;
2962 goto err_out;
2963 }
2964 input->filter.vlan_tci = fsp->h_ext.vlan_tci;
2965 input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI;
2966 }
2967
2968 input->action = fsp->ring_cookie;
2969 input->sw_idx = fsp->location;
2970
2971 spin_lock(&adapter->nfc_lock);
2972
2973 hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node) {
2974 if (!memcmp(&input->filter, &rule->filter,
2975 sizeof(input->filter))) {
2976 err = -EEXIST;
2977 dev_err(&adapter->pdev->dev,
2978 "ethtool: this filter is already set\n");
2979 goto err_out_w_lock;
2980 }
2981 }
2982
2983 err = igb_add_filter(adapter, input);
2984 if (err)
2985 goto err_out_w_lock;
2986
2987 igb_update_ethtool_nfc_entry(adapter, input, input->sw_idx);
2988
2989 spin_unlock(&adapter->nfc_lock);
2990 return 0;
2991
2992 err_out_w_lock:
2993 spin_unlock(&adapter->nfc_lock);
2994 err_out:
2995 kfree(input);
2996 return err;
2997 }
2998
igb_del_ethtool_nfc_entry(struct igb_adapter * adapter,struct ethtool_rxnfc * cmd)2999 static int igb_del_ethtool_nfc_entry(struct igb_adapter *adapter,
3000 struct ethtool_rxnfc *cmd)
3001 {
3002 struct ethtool_rx_flow_spec *fsp =
3003 (struct ethtool_rx_flow_spec *)&cmd->fs;
3004 int err;
3005
3006 spin_lock(&adapter->nfc_lock);
3007 err = igb_update_ethtool_nfc_entry(adapter, NULL, fsp->location);
3008 spin_unlock(&adapter->nfc_lock);
3009
3010 return err;
3011 }
3012
igb_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)3013 static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
3014 {
3015 struct igb_adapter *adapter = netdev_priv(dev);
3016 int ret = -EOPNOTSUPP;
3017
3018 switch (cmd->cmd) {
3019 case ETHTOOL_SRXFH:
3020 ret = igb_set_rss_hash_opt(adapter, cmd);
3021 break;
3022 case ETHTOOL_SRXCLSRLINS:
3023 ret = igb_add_ethtool_nfc_entry(adapter, cmd);
3024 break;
3025 case ETHTOOL_SRXCLSRLDEL:
3026 ret = igb_del_ethtool_nfc_entry(adapter, cmd);
3027 default:
3028 break;
3029 }
3030
3031 return ret;
3032 }
3033
igb_get_eee(struct net_device * netdev,struct ethtool_eee * edata)3034 static int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
3035 {
3036 struct igb_adapter *adapter = netdev_priv(netdev);
3037 struct e1000_hw *hw = &adapter->hw;
3038 u32 ret_val;
3039 u16 phy_data;
3040
3041 if ((hw->mac.type < e1000_i350) ||
3042 (hw->phy.media_type != e1000_media_type_copper))
3043 return -EOPNOTSUPP;
3044
3045 edata->supported = (SUPPORTED_1000baseT_Full |
3046 SUPPORTED_100baseT_Full);
3047 if (!hw->dev_spec._82575.eee_disable)
3048 edata->advertised =
3049 mmd_eee_adv_to_ethtool_adv_t(adapter->eee_advert);
3050
3051 /* The IPCNFG and EEER registers are not supported on I354. */
3052 if (hw->mac.type == e1000_i354) {
3053 igb_get_eee_status_i354(hw, (bool *)&edata->eee_active);
3054 } else {
3055 u32 eeer;
3056
3057 eeer = rd32(E1000_EEER);
3058
3059 /* EEE status on negotiated link */
3060 if (eeer & E1000_EEER_EEE_NEG)
3061 edata->eee_active = true;
3062
3063 if (eeer & E1000_EEER_TX_LPI_EN)
3064 edata->tx_lpi_enabled = true;
3065 }
3066
3067 /* EEE Link Partner Advertised */
3068 switch (hw->mac.type) {
3069 case e1000_i350:
3070 ret_val = igb_read_emi_reg(hw, E1000_EEE_LP_ADV_ADDR_I350,
3071 &phy_data);
3072 if (ret_val)
3073 return -ENODATA;
3074
3075 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);
3076 break;
3077 case e1000_i354:
3078 case e1000_i210:
3079 case e1000_i211:
3080 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_LP_ADV_ADDR_I210,
3081 E1000_EEE_LP_ADV_DEV_I210,
3082 &phy_data);
3083 if (ret_val)
3084 return -ENODATA;
3085
3086 edata->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(phy_data);
3087
3088 break;
3089 default:
3090 break;
3091 }
3092
3093 edata->eee_enabled = !hw->dev_spec._82575.eee_disable;
3094
3095 if ((hw->mac.type == e1000_i354) &&
3096 (edata->eee_enabled))
3097 edata->tx_lpi_enabled = true;
3098
3099 /* Report correct negotiated EEE status for devices that
3100 * wrongly report EEE at half-duplex
3101 */
3102 if (adapter->link_duplex == HALF_DUPLEX) {
3103 edata->eee_enabled = false;
3104 edata->eee_active = false;
3105 edata->tx_lpi_enabled = false;
3106 edata->advertised &= ~edata->advertised;
3107 }
3108
3109 return 0;
3110 }
3111
igb_set_eee(struct net_device * netdev,struct ethtool_eee * edata)3112 static int igb_set_eee(struct net_device *netdev,
3113 struct ethtool_eee *edata)
3114 {
3115 struct igb_adapter *adapter = netdev_priv(netdev);
3116 struct e1000_hw *hw = &adapter->hw;
3117 struct ethtool_eee eee_curr;
3118 bool adv1g_eee = true, adv100m_eee = true;
3119 s32 ret_val;
3120
3121 if ((hw->mac.type < e1000_i350) ||
3122 (hw->phy.media_type != e1000_media_type_copper))
3123 return -EOPNOTSUPP;
3124
3125 memset(&eee_curr, 0, sizeof(struct ethtool_eee));
3126
3127 ret_val = igb_get_eee(netdev, &eee_curr);
3128 if (ret_val)
3129 return ret_val;
3130
3131 if (eee_curr.eee_enabled) {
3132 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) {
3133 dev_err(&adapter->pdev->dev,
3134 "Setting EEE tx-lpi is not supported\n");
3135 return -EINVAL;
3136 }
3137
3138 /* Tx LPI timer is not implemented currently */
3139 if (edata->tx_lpi_timer) {
3140 dev_err(&adapter->pdev->dev,
3141 "Setting EEE Tx LPI timer is not supported\n");
3142 return -EINVAL;
3143 }
3144
3145 if (!edata->advertised || (edata->advertised &
3146 ~(ADVERTISE_100_FULL | ADVERTISE_1000_FULL))) {
3147 dev_err(&adapter->pdev->dev,
3148 "EEE Advertisement supports only 100Tx and/or 100T full duplex\n");
3149 return -EINVAL;
3150 }
3151 adv100m_eee = !!(edata->advertised & ADVERTISE_100_FULL);
3152 adv1g_eee = !!(edata->advertised & ADVERTISE_1000_FULL);
3153
3154 } else if (!edata->eee_enabled) {
3155 dev_err(&adapter->pdev->dev,
3156 "Setting EEE options are not supported with EEE disabled\n");
3157 return -EINVAL;
3158 }
3159
3160 adapter->eee_advert = ethtool_adv_to_mmd_eee_adv_t(edata->advertised);
3161 if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) {
3162 hw->dev_spec._82575.eee_disable = !edata->eee_enabled;
3163 adapter->flags |= IGB_FLAG_EEE;
3164
3165 /* reset link */
3166 if (netif_running(netdev))
3167 igb_reinit_locked(adapter);
3168 else
3169 igb_reset(adapter);
3170 }
3171
3172 if (hw->mac.type == e1000_i354)
3173 ret_val = igb_set_eee_i354(hw, adv1g_eee, adv100m_eee);
3174 else
3175 ret_val = igb_set_eee_i350(hw, adv1g_eee, adv100m_eee);
3176
3177 if (ret_val) {
3178 dev_err(&adapter->pdev->dev,
3179 "Problem setting EEE advertisement options\n");
3180 return -EINVAL;
3181 }
3182
3183 return 0;
3184 }
3185
igb_get_module_info(struct net_device * netdev,struct ethtool_modinfo * modinfo)3186 static int igb_get_module_info(struct net_device *netdev,
3187 struct ethtool_modinfo *modinfo)
3188 {
3189 struct igb_adapter *adapter = netdev_priv(netdev);
3190 struct e1000_hw *hw = &adapter->hw;
3191 u32 status = 0;
3192 u16 sff8472_rev, addr_mode;
3193 bool page_swap = false;
3194
3195 if ((hw->phy.media_type == e1000_media_type_copper) ||
3196 (hw->phy.media_type == e1000_media_type_unknown))
3197 return -EOPNOTSUPP;
3198
3199 /* Check whether we support SFF-8472 or not */
3200 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
3201 if (status)
3202 return -EIO;
3203
3204 /* addressing mode is not supported */
3205 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
3206 if (status)
3207 return -EIO;
3208
3209 /* addressing mode is not supported */
3210 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
3211 hw_dbg("Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
3212 page_swap = true;
3213 }
3214
3215 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
3216 /* We have an SFP, but it does not support SFF-8472 */
3217 modinfo->type = ETH_MODULE_SFF_8079;
3218 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
3219 } else {
3220 /* We have an SFP which supports a revision of SFF-8472 */
3221 modinfo->type = ETH_MODULE_SFF_8472;
3222 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
3223 }
3224
3225 return 0;
3226 }
3227
igb_get_module_eeprom(struct net_device * netdev,struct ethtool_eeprom * ee,u8 * data)3228 static int igb_get_module_eeprom(struct net_device *netdev,
3229 struct ethtool_eeprom *ee, u8 *data)
3230 {
3231 struct igb_adapter *adapter = netdev_priv(netdev);
3232 struct e1000_hw *hw = &adapter->hw;
3233 u32 status = 0;
3234 u16 *dataword;
3235 u16 first_word, last_word;
3236 int i = 0;
3237
3238 if (ee->len == 0)
3239 return -EINVAL;
3240
3241 first_word = ee->offset >> 1;
3242 last_word = (ee->offset + ee->len - 1) >> 1;
3243
3244 dataword = kmalloc_array(last_word - first_word + 1, sizeof(u16),
3245 GFP_KERNEL);
3246 if (!dataword)
3247 return -ENOMEM;
3248
3249 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
3250 for (i = 0; i < last_word - first_word + 1; i++) {
3251 status = igb_read_phy_reg_i2c(hw, (first_word + i) * 2,
3252 &dataword[i]);
3253 if (status) {
3254 /* Error occurred while reading module */
3255 kfree(dataword);
3256 return -EIO;
3257 }
3258
3259 be16_to_cpus(&dataword[i]);
3260 }
3261
3262 memcpy(data, (u8 *)dataword + (ee->offset & 1), ee->len);
3263 kfree(dataword);
3264
3265 return 0;
3266 }
3267
igb_ethtool_begin(struct net_device * netdev)3268 static int igb_ethtool_begin(struct net_device *netdev)
3269 {
3270 struct igb_adapter *adapter = netdev_priv(netdev);
3271 pm_runtime_get_sync(&adapter->pdev->dev);
3272 return 0;
3273 }
3274
igb_ethtool_complete(struct net_device * netdev)3275 static void igb_ethtool_complete(struct net_device *netdev)
3276 {
3277 struct igb_adapter *adapter = netdev_priv(netdev);
3278 pm_runtime_put(&adapter->pdev->dev);
3279 }
3280
igb_get_rxfh_indir_size(struct net_device * netdev)3281 static u32 igb_get_rxfh_indir_size(struct net_device *netdev)
3282 {
3283 return IGB_RETA_SIZE;
3284 }
3285
igb_get_rxfh(struct net_device * netdev,u32 * indir,u8 * key,u8 * hfunc)3286 static int igb_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
3287 u8 *hfunc)
3288 {
3289 struct igb_adapter *adapter = netdev_priv(netdev);
3290 int i;
3291
3292 if (hfunc)
3293 *hfunc = ETH_RSS_HASH_TOP;
3294 if (!indir)
3295 return 0;
3296 for (i = 0; i < IGB_RETA_SIZE; i++)
3297 indir[i] = adapter->rss_indir_tbl[i];
3298
3299 return 0;
3300 }
3301
igb_write_rss_indir_tbl(struct igb_adapter * adapter)3302 void igb_write_rss_indir_tbl(struct igb_adapter *adapter)
3303 {
3304 struct e1000_hw *hw = &adapter->hw;
3305 u32 reg = E1000_RETA(0);
3306 u32 shift = 0;
3307 int i = 0;
3308
3309 switch (hw->mac.type) {
3310 case e1000_82575:
3311 shift = 6;
3312 break;
3313 case e1000_82576:
3314 /* 82576 supports 2 RSS queues for SR-IOV */
3315 if (adapter->vfs_allocated_count)
3316 shift = 3;
3317 break;
3318 default:
3319 break;
3320 }
3321
3322 while (i < IGB_RETA_SIZE) {
3323 u32 val = 0;
3324 int j;
3325
3326 for (j = 3; j >= 0; j--) {
3327 val <<= 8;
3328 val |= adapter->rss_indir_tbl[i + j];
3329 }
3330
3331 wr32(reg, val << shift);
3332 reg += 4;
3333 i += 4;
3334 }
3335 }
3336
igb_set_rxfh(struct net_device * netdev,const u32 * indir,const u8 * key,const u8 hfunc)3337 static int igb_set_rxfh(struct net_device *netdev, const u32 *indir,
3338 const u8 *key, const u8 hfunc)
3339 {
3340 struct igb_adapter *adapter = netdev_priv(netdev);
3341 struct e1000_hw *hw = &adapter->hw;
3342 int i;
3343 u32 num_queues;
3344
3345 /* We do not allow change in unsupported parameters */
3346 if (key ||
3347 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3348 return -EOPNOTSUPP;
3349 if (!indir)
3350 return 0;
3351
3352 num_queues = adapter->rss_queues;
3353
3354 switch (hw->mac.type) {
3355 case e1000_82576:
3356 /* 82576 supports 2 RSS queues for SR-IOV */
3357 if (adapter->vfs_allocated_count)
3358 num_queues = 2;
3359 break;
3360 default:
3361 break;
3362 }
3363
3364 /* Verify user input. */
3365 for (i = 0; i < IGB_RETA_SIZE; i++)
3366 if (indir[i] >= num_queues)
3367 return -EINVAL;
3368
3369
3370 for (i = 0; i < IGB_RETA_SIZE; i++)
3371 adapter->rss_indir_tbl[i] = indir[i];
3372
3373 igb_write_rss_indir_tbl(adapter);
3374
3375 return 0;
3376 }
3377
igb_max_channels(struct igb_adapter * adapter)3378 static unsigned int igb_max_channels(struct igb_adapter *adapter)
3379 {
3380 return igb_get_max_rss_queues(adapter);
3381 }
3382
igb_get_channels(struct net_device * netdev,struct ethtool_channels * ch)3383 static void igb_get_channels(struct net_device *netdev,
3384 struct ethtool_channels *ch)
3385 {
3386 struct igb_adapter *adapter = netdev_priv(netdev);
3387
3388 /* Report maximum channels */
3389 ch->max_combined = igb_max_channels(adapter);
3390
3391 /* Report info for other vector */
3392 if (adapter->flags & IGB_FLAG_HAS_MSIX) {
3393 ch->max_other = NON_Q_VECTORS;
3394 ch->other_count = NON_Q_VECTORS;
3395 }
3396
3397 ch->combined_count = adapter->rss_queues;
3398 }
3399
igb_set_channels(struct net_device * netdev,struct ethtool_channels * ch)3400 static int igb_set_channels(struct net_device *netdev,
3401 struct ethtool_channels *ch)
3402 {
3403 struct igb_adapter *adapter = netdev_priv(netdev);
3404 unsigned int count = ch->combined_count;
3405 unsigned int max_combined = 0;
3406
3407 /* Verify they are not requesting separate vectors */
3408 if (!count || ch->rx_count || ch->tx_count)
3409 return -EINVAL;
3410
3411 /* Verify other_count is valid and has not been changed */
3412 if (ch->other_count != NON_Q_VECTORS)
3413 return -EINVAL;
3414
3415 /* Verify the number of channels doesn't exceed hw limits */
3416 max_combined = igb_max_channels(adapter);
3417 if (count > max_combined)
3418 return -EINVAL;
3419
3420 if (count != adapter->rss_queues) {
3421 adapter->rss_queues = count;
3422 igb_set_flag_queue_pairs(adapter, max_combined);
3423
3424 /* Hardware has to reinitialize queues and interrupts to
3425 * match the new configuration.
3426 */
3427 return igb_reinit_queues(adapter);
3428 }
3429
3430 return 0;
3431 }
3432
igb_get_priv_flags(struct net_device * netdev)3433 static u32 igb_get_priv_flags(struct net_device *netdev)
3434 {
3435 struct igb_adapter *adapter = netdev_priv(netdev);
3436 u32 priv_flags = 0;
3437
3438 if (adapter->flags & IGB_FLAG_RX_LEGACY)
3439 priv_flags |= IGB_PRIV_FLAGS_LEGACY_RX;
3440
3441 return priv_flags;
3442 }
3443
igb_set_priv_flags(struct net_device * netdev,u32 priv_flags)3444 static int igb_set_priv_flags(struct net_device *netdev, u32 priv_flags)
3445 {
3446 struct igb_adapter *adapter = netdev_priv(netdev);
3447 unsigned int flags = adapter->flags;
3448
3449 flags &= ~IGB_FLAG_RX_LEGACY;
3450 if (priv_flags & IGB_PRIV_FLAGS_LEGACY_RX)
3451 flags |= IGB_FLAG_RX_LEGACY;
3452
3453 if (flags != adapter->flags) {
3454 adapter->flags = flags;
3455
3456 /* reset interface to repopulate queues */
3457 if (netif_running(netdev))
3458 igb_reinit_locked(adapter);
3459 }
3460
3461 return 0;
3462 }
3463
3464 static const struct ethtool_ops igb_ethtool_ops = {
3465 .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
3466 .get_drvinfo = igb_get_drvinfo,
3467 .get_regs_len = igb_get_regs_len,
3468 .get_regs = igb_get_regs,
3469 .get_wol = igb_get_wol,
3470 .set_wol = igb_set_wol,
3471 .get_msglevel = igb_get_msglevel,
3472 .set_msglevel = igb_set_msglevel,
3473 .nway_reset = igb_nway_reset,
3474 .get_link = igb_get_link,
3475 .get_eeprom_len = igb_get_eeprom_len,
3476 .get_eeprom = igb_get_eeprom,
3477 .set_eeprom = igb_set_eeprom,
3478 .get_ringparam = igb_get_ringparam,
3479 .set_ringparam = igb_set_ringparam,
3480 .get_pauseparam = igb_get_pauseparam,
3481 .set_pauseparam = igb_set_pauseparam,
3482 .self_test = igb_diag_test,
3483 .get_strings = igb_get_strings,
3484 .set_phys_id = igb_set_phys_id,
3485 .get_sset_count = igb_get_sset_count,
3486 .get_ethtool_stats = igb_get_ethtool_stats,
3487 .get_coalesce = igb_get_coalesce,
3488 .set_coalesce = igb_set_coalesce,
3489 .get_ts_info = igb_get_ts_info,
3490 .get_rxnfc = igb_get_rxnfc,
3491 .set_rxnfc = igb_set_rxnfc,
3492 .get_eee = igb_get_eee,
3493 .set_eee = igb_set_eee,
3494 .get_module_info = igb_get_module_info,
3495 .get_module_eeprom = igb_get_module_eeprom,
3496 .get_rxfh_indir_size = igb_get_rxfh_indir_size,
3497 .get_rxfh = igb_get_rxfh,
3498 .set_rxfh = igb_set_rxfh,
3499 .get_channels = igb_get_channels,
3500 .set_channels = igb_set_channels,
3501 .get_priv_flags = igb_get_priv_flags,
3502 .set_priv_flags = igb_set_priv_flags,
3503 .begin = igb_ethtool_begin,
3504 .complete = igb_ethtool_complete,
3505 .get_link_ksettings = igb_get_link_ksettings,
3506 .set_link_ksettings = igb_set_link_ksettings,
3507 };
3508
igb_set_ethtool_ops(struct net_device * netdev)3509 void igb_set_ethtool_ops(struct net_device *netdev)
3510 {
3511 netdev->ethtool_ops = &igb_ethtool_ops;
3512 }
3513