1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _E1000_NVM_H_ 5*4882a593Smuzhiyun #define _E1000_NVM_H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun s32 igb_acquire_nvm(struct e1000_hw *hw); 8*4882a593Smuzhiyun void igb_release_nvm(struct e1000_hw *hw); 9*4882a593Smuzhiyun s32 igb_read_mac_addr(struct e1000_hw *hw); 10*4882a593Smuzhiyun s32 igb_read_part_num(struct e1000_hw *hw, u32 *part_num); 11*4882a593Smuzhiyun s32 igb_read_part_string(struct e1000_hw *hw, u8 *part_num, 12*4882a593Smuzhiyun u32 part_num_size); 13*4882a593Smuzhiyun s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); 14*4882a593Smuzhiyun s32 igb_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); 15*4882a593Smuzhiyun s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data); 16*4882a593Smuzhiyun s32 igb_validate_nvm_checksum(struct e1000_hw *hw); 17*4882a593Smuzhiyun s32 igb_update_nvm_checksum(struct e1000_hw *hw); 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun struct e1000_fw_version { 20*4882a593Smuzhiyun u32 etrack_id; 21*4882a593Smuzhiyun u16 eep_major; 22*4882a593Smuzhiyun u16 eep_minor; 23*4882a593Smuzhiyun u16 eep_build; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun u8 invm_major; 26*4882a593Smuzhiyun u8 invm_minor; 27*4882a593Smuzhiyun u8 invm_img_type; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun bool or_valid; 30*4882a593Smuzhiyun u16 or_major; 31*4882a593Smuzhiyun u16 or_build; 32*4882a593Smuzhiyun u16 or_patch; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun void igb_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers); 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #endif 37