1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _E1000_MAC_H_ 5*4882a593Smuzhiyun #define _E1000_MAC_H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include "e1000_hw.h" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include "e1000_phy.h" 10*4882a593Smuzhiyun #include "e1000_nvm.h" 11*4882a593Smuzhiyun #include "e1000_defines.h" 12*4882a593Smuzhiyun #include "e1000_i210.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Functions that should not be called directly from drivers but can be used 15*4882a593Smuzhiyun * by other files in this 'shared code' 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun s32 igb_blink_led(struct e1000_hw *hw); 18*4882a593Smuzhiyun s32 igb_check_for_copper_link(struct e1000_hw *hw); 19*4882a593Smuzhiyun s32 igb_cleanup_led(struct e1000_hw *hw); 20*4882a593Smuzhiyun s32 igb_config_fc_after_link_up(struct e1000_hw *hw); 21*4882a593Smuzhiyun s32 igb_disable_pcie_master(struct e1000_hw *hw); 22*4882a593Smuzhiyun s32 igb_force_mac_fc(struct e1000_hw *hw); 23*4882a593Smuzhiyun s32 igb_get_auto_rd_done(struct e1000_hw *hw); 24*4882a593Smuzhiyun s32 igb_get_bus_info_pcie(struct e1000_hw *hw); 25*4882a593Smuzhiyun s32 igb_get_hw_semaphore(struct e1000_hw *hw); 26*4882a593Smuzhiyun s32 igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, 27*4882a593Smuzhiyun u16 *duplex); 28*4882a593Smuzhiyun s32 igb_id_led_init(struct e1000_hw *hw); 29*4882a593Smuzhiyun s32 igb_led_off(struct e1000_hw *hw); 30*4882a593Smuzhiyun void igb_update_mc_addr_list(struct e1000_hw *hw, 31*4882a593Smuzhiyun u8 *mc_addr_list, u32 mc_addr_count); 32*4882a593Smuzhiyun s32 igb_setup_link(struct e1000_hw *hw); 33*4882a593Smuzhiyun s32 igb_validate_mdi_setting(struct e1000_hw *hw); 34*4882a593Smuzhiyun s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg, 35*4882a593Smuzhiyun u32 offset, u8 data); 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun void igb_clear_hw_cntrs_base(struct e1000_hw *hw); 38*4882a593Smuzhiyun void igb_clear_vfta(struct e1000_hw *hw); 39*4882a593Smuzhiyun void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value); 40*4882a593Smuzhiyun s32 igb_vfta_set(struct e1000_hw *hw, u32 vid, u32 vind, 41*4882a593Smuzhiyun bool vlan_on, bool vlvf_bypass); 42*4882a593Smuzhiyun void igb_config_collision_dist(struct e1000_hw *hw); 43*4882a593Smuzhiyun void igb_init_rx_addrs(struct e1000_hw *hw, u16 rar_count); 44*4882a593Smuzhiyun void igb_mta_set(struct e1000_hw *hw, u32 hash_value); 45*4882a593Smuzhiyun void igb_put_hw_semaphore(struct e1000_hw *hw); 46*4882a593Smuzhiyun void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index); 47*4882a593Smuzhiyun s32 igb_check_alt_mac_addr(struct e1000_hw *hw); 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun bool igb_enable_mng_pass_thru(struct e1000_hw *hw); 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun enum e1000_mng_mode { 52*4882a593Smuzhiyun e1000_mng_mode_none = 0, 53*4882a593Smuzhiyun e1000_mng_mode_asf, 54*4882a593Smuzhiyun e1000_mng_mode_pt, 55*4882a593Smuzhiyun e1000_mng_mode_ipmi, 56*4882a593Smuzhiyun e1000_mng_mode_host_if_only 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define E1000_FACTPS_MNGCG 0x20000000 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define E1000_FWSM_MODE_MASK 0xE 62*4882a593Smuzhiyun #define E1000_FWSM_MODE_SHIFT 1 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun void e1000_init_function_pointers_82575(struct e1000_hw *hw); 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #endif 69