1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (c) 2018, Intel Corporation. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _ICE_SCHED_H_ 5*4882a593Smuzhiyun #define _ICE_SCHED_H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include "ice_common.h" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define ICE_QGRP_LAYER_OFFSET 2 10*4882a593Smuzhiyun #define ICE_VSI_LAYER_OFFSET 4 11*4882a593Smuzhiyun #define ICE_SCHED_INVAL_LAYER_NUM 0xFF 12*4882a593Smuzhiyun /* Burst size is a 12 bits register that is configured while creating the RL 13*4882a593Smuzhiyun * profile(s). MSB is a granularity bit and tells the granularity type 14*4882a593Smuzhiyun * 0 - LSB bits are in 64 bytes granularity 15*4882a593Smuzhiyun * 1 - LSB bits are in 1K bytes granularity 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun #define ICE_64_BYTE_GRANULARITY 0 18*4882a593Smuzhiyun #define ICE_KBYTE_GRANULARITY BIT(11) 19*4882a593Smuzhiyun #define ICE_MIN_BURST_SIZE_ALLOWED 64 /* In Bytes */ 20*4882a593Smuzhiyun #define ICE_MAX_BURST_SIZE_ALLOWED \ 21*4882a593Smuzhiyun ((BIT(11) - 1) * 1024) /* In Bytes */ 22*4882a593Smuzhiyun #define ICE_MAX_BURST_SIZE_64_BYTE_GRANULARITY \ 23*4882a593Smuzhiyun ((BIT(11) - 1) * 64) /* In Bytes */ 24*4882a593Smuzhiyun #define ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY ICE_MAX_BURST_SIZE_ALLOWED 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define ICE_RL_PROF_FREQUENCY 446000000 27*4882a593Smuzhiyun #define ICE_RL_PROF_ACCURACY_BYTES 128 28*4882a593Smuzhiyun #define ICE_RL_PROF_MULTIPLIER 10000 29*4882a593Smuzhiyun #define ICE_RL_PROF_TS_MULTIPLIER 32 30*4882a593Smuzhiyun #define ICE_RL_PROF_FRACTION 512 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* BW rate limit profile parameters list entry along 33*4882a593Smuzhiyun * with bandwidth maintained per layer in port info 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun struct ice_aqc_rl_profile_info { 36*4882a593Smuzhiyun struct ice_aqc_rl_profile_elem profile; 37*4882a593Smuzhiyun struct list_head list_entry; 38*4882a593Smuzhiyun u32 bw; /* requested */ 39*4882a593Smuzhiyun u16 prof_id_ref; /* profile ID to node association ref count */ 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun struct ice_sched_agg_vsi_info { 43*4882a593Smuzhiyun struct list_head list_entry; 44*4882a593Smuzhiyun DECLARE_BITMAP(tc_bitmap, ICE_MAX_TRAFFIC_CLASS); 45*4882a593Smuzhiyun u16 vsi_handle; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun struct ice_sched_agg_info { 49*4882a593Smuzhiyun struct list_head agg_vsi_list; 50*4882a593Smuzhiyun struct list_head list_entry; 51*4882a593Smuzhiyun DECLARE_BITMAP(tc_bitmap, ICE_MAX_TRAFFIC_CLASS); 52*4882a593Smuzhiyun u32 agg_id; 53*4882a593Smuzhiyun enum ice_agg_type agg_type; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* FW AQ command calls */ 57*4882a593Smuzhiyun enum ice_status 58*4882a593Smuzhiyun ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req, 59*4882a593Smuzhiyun struct ice_aqc_txsched_elem_data *buf, u16 buf_size, 60*4882a593Smuzhiyun u16 *elems_ret, struct ice_sq_cd *cd); 61*4882a593Smuzhiyun enum ice_status ice_sched_init_port(struct ice_port_info *pi); 62*4882a593Smuzhiyun enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw); 63*4882a593Smuzhiyun void ice_sched_clear_port(struct ice_port_info *pi); 64*4882a593Smuzhiyun void ice_sched_cleanup_all(struct ice_hw *hw); 65*4882a593Smuzhiyun void ice_sched_clear_agg(struct ice_hw *hw); 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun struct ice_sched_node * 68*4882a593Smuzhiyun ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid); 69*4882a593Smuzhiyun enum ice_status 70*4882a593Smuzhiyun ice_sched_add_node(struct ice_port_info *pi, u8 layer, 71*4882a593Smuzhiyun struct ice_aqc_txsched_elem_data *info); 72*4882a593Smuzhiyun void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node); 73*4882a593Smuzhiyun struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc); 74*4882a593Smuzhiyun struct ice_sched_node * 75*4882a593Smuzhiyun ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 76*4882a593Smuzhiyun u8 owner); 77*4882a593Smuzhiyun enum ice_status 78*4882a593Smuzhiyun ice_sched_cfg_vsi(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 maxqs, 79*4882a593Smuzhiyun u8 owner, bool enable); 80*4882a593Smuzhiyun enum ice_status ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle); 81*4882a593Smuzhiyun enum ice_status 82*4882a593Smuzhiyun ice_cfg_q_bw_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 83*4882a593Smuzhiyun u16 q_handle, enum ice_rl_type rl_type, u32 bw); 84*4882a593Smuzhiyun enum ice_status 85*4882a593Smuzhiyun ice_cfg_q_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 86*4882a593Smuzhiyun u16 q_handle, enum ice_rl_type rl_type); 87*4882a593Smuzhiyun enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes); 88*4882a593Smuzhiyun enum ice_status 89*4882a593Smuzhiyun ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx); 90*4882a593Smuzhiyun #endif /* _ICE_SCHED_H_ */ 91