1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (c) 2019, Intel Corporation. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _ICE_BASE_H_ 5*4882a593Smuzhiyun #define _ICE_BASE_H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include "ice.h" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun int ice_setup_rx_ctx(struct ice_ring *ring); 10*4882a593Smuzhiyun int __ice_vsi_get_qs(struct ice_qs_cfg *qs_cfg); 11*4882a593Smuzhiyun int 12*4882a593Smuzhiyun ice_vsi_ctrl_one_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx, bool wait); 13*4882a593Smuzhiyun int ice_vsi_wait_one_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx); 14*4882a593Smuzhiyun int ice_vsi_alloc_q_vectors(struct ice_vsi *vsi); 15*4882a593Smuzhiyun void ice_vsi_map_rings_to_vectors(struct ice_vsi *vsi); 16*4882a593Smuzhiyun void ice_vsi_free_q_vectors(struct ice_vsi *vsi); 17*4882a593Smuzhiyun int 18*4882a593Smuzhiyun ice_vsi_cfg_txq(struct ice_vsi *vsi, struct ice_ring *ring, 19*4882a593Smuzhiyun struct ice_aqc_add_tx_qgrp *qg_buf); 20*4882a593Smuzhiyun void ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector); 21*4882a593Smuzhiyun void 22*4882a593Smuzhiyun ice_cfg_txq_interrupt(struct ice_vsi *vsi, u16 txq, u16 msix_idx, u16 itr_idx); 23*4882a593Smuzhiyun void 24*4882a593Smuzhiyun ice_cfg_rxq_interrupt(struct ice_vsi *vsi, u16 rxq, u16 msix_idx, u16 itr_idx); 25*4882a593Smuzhiyun void ice_trigger_sw_intr(struct ice_hw *hw, struct ice_q_vector *q_vector); 26*4882a593Smuzhiyun int 27*4882a593Smuzhiyun ice_vsi_stop_tx_ring(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src, 28*4882a593Smuzhiyun u16 rel_vmvf_num, struct ice_ring *ring, 29*4882a593Smuzhiyun struct ice_txq_meta *txq_meta); 30*4882a593Smuzhiyun void 31*4882a593Smuzhiyun ice_fill_txq_meta(struct ice_vsi *vsi, struct ice_ring *ring, 32*4882a593Smuzhiyun struct ice_txq_meta *txq_meta); 33*4882a593Smuzhiyun #endif /* _ICE_BASE_H_ */ 34