1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /* Copyright (c) 2018, Intel Corporation. */
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #ifndef _ICE_H_
5*4882a593Smuzhiyun #define _ICE_H_
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/types.h>
8*4882a593Smuzhiyun #include <linux/errno.h>
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/firmware.h>
12*4882a593Smuzhiyun #include <linux/netdevice.h>
13*4882a593Smuzhiyun #include <linux/compiler.h>
14*4882a593Smuzhiyun #include <linux/etherdevice.h>
15*4882a593Smuzhiyun #include <linux/skbuff.h>
16*4882a593Smuzhiyun #include <linux/cpumask.h>
17*4882a593Smuzhiyun #include <linux/rtnetlink.h>
18*4882a593Smuzhiyun #include <linux/if_vlan.h>
19*4882a593Smuzhiyun #include <linux/dma-mapping.h>
20*4882a593Smuzhiyun #include <linux/pci.h>
21*4882a593Smuzhiyun #include <linux/workqueue.h>
22*4882a593Smuzhiyun #include <linux/wait.h>
23*4882a593Smuzhiyun #include <linux/aer.h>
24*4882a593Smuzhiyun #include <linux/interrupt.h>
25*4882a593Smuzhiyun #include <linux/ethtool.h>
26*4882a593Smuzhiyun #include <linux/timer.h>
27*4882a593Smuzhiyun #include <linux/delay.h>
28*4882a593Smuzhiyun #include <linux/bitmap.h>
29*4882a593Smuzhiyun #include <linux/log2.h>
30*4882a593Smuzhiyun #include <linux/ip.h>
31*4882a593Smuzhiyun #include <linux/sctp.h>
32*4882a593Smuzhiyun #include <linux/ipv6.h>
33*4882a593Smuzhiyun #include <linux/pkt_sched.h>
34*4882a593Smuzhiyun #include <linux/if_bridge.h>
35*4882a593Smuzhiyun #include <linux/ctype.h>
36*4882a593Smuzhiyun #include <linux/bpf.h>
37*4882a593Smuzhiyun #include <linux/avf/virtchnl.h>
38*4882a593Smuzhiyun #include <linux/cpu_rmap.h>
39*4882a593Smuzhiyun #include <net/devlink.h>
40*4882a593Smuzhiyun #include <net/ipv6.h>
41*4882a593Smuzhiyun #include <net/xdp_sock.h>
42*4882a593Smuzhiyun #include <net/geneve.h>
43*4882a593Smuzhiyun #include <net/gre.h>
44*4882a593Smuzhiyun #include <net/udp_tunnel.h>
45*4882a593Smuzhiyun #include <net/vxlan.h>
46*4882a593Smuzhiyun #include "ice_devids.h"
47*4882a593Smuzhiyun #include "ice_type.h"
48*4882a593Smuzhiyun #include "ice_txrx.h"
49*4882a593Smuzhiyun #include "ice_dcb.h"
50*4882a593Smuzhiyun #include "ice_switch.h"
51*4882a593Smuzhiyun #include "ice_common.h"
52*4882a593Smuzhiyun #include "ice_sched.h"
53*4882a593Smuzhiyun #include "ice_virtchnl_pf.h"
54*4882a593Smuzhiyun #include "ice_sriov.h"
55*4882a593Smuzhiyun #include "ice_fdir.h"
56*4882a593Smuzhiyun #include "ice_xsk.h"
57*4882a593Smuzhiyun #include "ice_arfs.h"
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun #define ICE_BAR0 0
60*4882a593Smuzhiyun #define ICE_REQ_DESC_MULTIPLE 32
61*4882a593Smuzhiyun #define ICE_MIN_NUM_DESC 64
62*4882a593Smuzhiyun #define ICE_MAX_NUM_DESC 8160
63*4882a593Smuzhiyun #define ICE_DFLT_MIN_RX_DESC 512
64*4882a593Smuzhiyun #define ICE_DFLT_NUM_TX_DESC 256
65*4882a593Smuzhiyun #define ICE_DFLT_NUM_RX_DESC 2048
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #define ICE_DFLT_TRAFFIC_CLASS BIT(0)
68*4882a593Smuzhiyun #define ICE_INT_NAME_STR_LEN (IFNAMSIZ + 16)
69*4882a593Smuzhiyun #define ICE_AQ_LEN 64
70*4882a593Smuzhiyun #define ICE_MBXSQ_LEN 64
71*4882a593Smuzhiyun #define ICE_MIN_LAN_TXRX_MSIX 1
72*4882a593Smuzhiyun #define ICE_MIN_LAN_OICR_MSIX 1
73*4882a593Smuzhiyun #define ICE_MIN_MSIX (ICE_MIN_LAN_TXRX_MSIX + ICE_MIN_LAN_OICR_MSIX)
74*4882a593Smuzhiyun #define ICE_FDIR_MSIX 1
75*4882a593Smuzhiyun #define ICE_NO_VSI 0xffff
76*4882a593Smuzhiyun #define ICE_VSI_MAP_CONTIG 0
77*4882a593Smuzhiyun #define ICE_VSI_MAP_SCATTER 1
78*4882a593Smuzhiyun #define ICE_MAX_SCATTER_TXQS 16
79*4882a593Smuzhiyun #define ICE_MAX_SCATTER_RXQS 16
80*4882a593Smuzhiyun #define ICE_Q_WAIT_RETRY_LIMIT 10
81*4882a593Smuzhiyun #define ICE_Q_WAIT_MAX_RETRY (5 * ICE_Q_WAIT_RETRY_LIMIT)
82*4882a593Smuzhiyun #define ICE_MAX_LG_RSS_QS 256
83*4882a593Smuzhiyun #define ICE_RES_VALID_BIT 0x8000
84*4882a593Smuzhiyun #define ICE_RES_MISC_VEC_ID (ICE_RES_VALID_BIT - 1)
85*4882a593Smuzhiyun #define ICE_INVAL_Q_INDEX 0xffff
86*4882a593Smuzhiyun #define ICE_INVAL_VFID 256
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun #define ICE_MAX_RESET_WAIT 20
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun #define ICE_VSIQF_HKEY_ARRAY_SIZE ((VSIQF_HKEY_MAX_INDEX + 1) * 4)
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun #define ICE_DFLT_NETIF_M (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun #define ICE_MAX_MTU (ICE_AQ_SET_MAC_FRAME_SIZE_MAX - ICE_ETH_PKT_HDR_PAD)
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun #define ICE_UP_TABLE_TRANSLATE(val, i) \
97*4882a593Smuzhiyun (((val) << ICE_AQ_VSI_UP_TABLE_UP##i##_S) & \
98*4882a593Smuzhiyun ICE_AQ_VSI_UP_TABLE_UP##i##_M)
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun #define ICE_TX_DESC(R, i) (&(((struct ice_tx_desc *)((R)->desc))[i]))
101*4882a593Smuzhiyun #define ICE_RX_DESC(R, i) (&(((union ice_32b_rx_flex_desc *)((R)->desc))[i]))
102*4882a593Smuzhiyun #define ICE_TX_CTX_DESC(R, i) (&(((struct ice_tx_ctx_desc *)((R)->desc))[i]))
103*4882a593Smuzhiyun #define ICE_TX_FDIRDESC(R, i) (&(((struct ice_fltr_desc *)((R)->desc))[i]))
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /* Macro for each VSI in a PF */
106*4882a593Smuzhiyun #define ice_for_each_vsi(pf, i) \
107*4882a593Smuzhiyun for ((i) = 0; (i) < (pf)->num_alloc_vsi; (i)++)
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* Macros for each Tx/Rx ring in a VSI */
110*4882a593Smuzhiyun #define ice_for_each_txq(vsi, i) \
111*4882a593Smuzhiyun for ((i) = 0; (i) < (vsi)->num_txq; (i)++)
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun #define ice_for_each_rxq(vsi, i) \
114*4882a593Smuzhiyun for ((i) = 0; (i) < (vsi)->num_rxq; (i)++)
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun /* Macros for each allocated Tx/Rx ring whether used or not in a VSI */
117*4882a593Smuzhiyun #define ice_for_each_alloc_txq(vsi, i) \
118*4882a593Smuzhiyun for ((i) = 0; (i) < (vsi)->alloc_txq; (i)++)
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun #define ice_for_each_alloc_rxq(vsi, i) \
121*4882a593Smuzhiyun for ((i) = 0; (i) < (vsi)->alloc_rxq; (i)++)
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun #define ice_for_each_q_vector(vsi, i) \
124*4882a593Smuzhiyun for ((i) = 0; (i) < (vsi)->num_q_vectors; (i)++)
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun #define ICE_UCAST_PROMISC_BITS (ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX | \
127*4882a593Smuzhiyun ICE_PROMISC_UCAST_RX | ICE_PROMISC_MCAST_RX)
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun #define ICE_UCAST_VLAN_PROMISC_BITS (ICE_PROMISC_UCAST_TX | \
130*4882a593Smuzhiyun ICE_PROMISC_MCAST_TX | \
131*4882a593Smuzhiyun ICE_PROMISC_UCAST_RX | \
132*4882a593Smuzhiyun ICE_PROMISC_MCAST_RX | \
133*4882a593Smuzhiyun ICE_PROMISC_VLAN_TX | \
134*4882a593Smuzhiyun ICE_PROMISC_VLAN_RX)
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun #define ICE_MCAST_PROMISC_BITS (ICE_PROMISC_MCAST_TX | ICE_PROMISC_MCAST_RX)
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun #define ICE_MCAST_VLAN_PROMISC_BITS (ICE_PROMISC_MCAST_TX | \
139*4882a593Smuzhiyun ICE_PROMISC_MCAST_RX | \
140*4882a593Smuzhiyun ICE_PROMISC_VLAN_TX | \
141*4882a593Smuzhiyun ICE_PROMISC_VLAN_RX)
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun #define ice_pf_to_dev(pf) (&((pf)->pdev->dev))
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun struct ice_txq_meta {
146*4882a593Smuzhiyun u32 q_teid; /* Tx-scheduler element identifier */
147*4882a593Smuzhiyun u16 q_id; /* Entry in VSI's txq_map bitmap */
148*4882a593Smuzhiyun u16 q_handle; /* Relative index of Tx queue within TC */
149*4882a593Smuzhiyun u16 vsi_idx; /* VSI index that Tx queue belongs to */
150*4882a593Smuzhiyun u8 tc; /* TC number that Tx queue belongs to */
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun struct ice_tc_info {
154*4882a593Smuzhiyun u16 qoffset;
155*4882a593Smuzhiyun u16 qcount_tx;
156*4882a593Smuzhiyun u16 qcount_rx;
157*4882a593Smuzhiyun u8 netdev_tc;
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun struct ice_tc_cfg {
161*4882a593Smuzhiyun u8 numtc; /* Total number of enabled TCs */
162*4882a593Smuzhiyun u8 ena_tc; /* Tx map */
163*4882a593Smuzhiyun struct ice_tc_info tc_info[ICE_MAX_TRAFFIC_CLASS];
164*4882a593Smuzhiyun };
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun struct ice_res_tracker {
167*4882a593Smuzhiyun u16 num_entries;
168*4882a593Smuzhiyun u16 end;
169*4882a593Smuzhiyun u16 list[1];
170*4882a593Smuzhiyun };
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun struct ice_qs_cfg {
173*4882a593Smuzhiyun struct mutex *qs_mutex; /* will be assigned to &pf->avail_q_mutex */
174*4882a593Smuzhiyun unsigned long *pf_map;
175*4882a593Smuzhiyun unsigned long pf_map_size;
176*4882a593Smuzhiyun unsigned int q_count;
177*4882a593Smuzhiyun unsigned int scatter_count;
178*4882a593Smuzhiyun u16 *vsi_map;
179*4882a593Smuzhiyun u16 vsi_map_offset;
180*4882a593Smuzhiyun u8 mapping_mode;
181*4882a593Smuzhiyun };
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun struct ice_sw {
184*4882a593Smuzhiyun struct ice_pf *pf;
185*4882a593Smuzhiyun u16 sw_id; /* switch ID for this switch */
186*4882a593Smuzhiyun u16 bridge_mode; /* VEB/VEPA/Port Virtualizer */
187*4882a593Smuzhiyun struct ice_vsi *dflt_vsi; /* default VSI for this switch */
188*4882a593Smuzhiyun u8 dflt_vsi_ena:1; /* true if above dflt_vsi is enabled */
189*4882a593Smuzhiyun };
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun enum ice_state {
192*4882a593Smuzhiyun __ICE_TESTING,
193*4882a593Smuzhiyun __ICE_DOWN,
194*4882a593Smuzhiyun __ICE_NEEDS_RESTART,
195*4882a593Smuzhiyun __ICE_PREPARED_FOR_RESET, /* set by driver when prepared */
196*4882a593Smuzhiyun __ICE_RESET_OICR_RECV, /* set by driver after rcv reset OICR */
197*4882a593Smuzhiyun __ICE_PFR_REQ, /* set by driver and peers */
198*4882a593Smuzhiyun __ICE_CORER_REQ, /* set by driver and peers */
199*4882a593Smuzhiyun __ICE_GLOBR_REQ, /* set by driver and peers */
200*4882a593Smuzhiyun __ICE_CORER_RECV, /* set by OICR handler */
201*4882a593Smuzhiyun __ICE_GLOBR_RECV, /* set by OICR handler */
202*4882a593Smuzhiyun __ICE_EMPR_RECV, /* set by OICR handler */
203*4882a593Smuzhiyun __ICE_SUSPENDED, /* set on module remove path */
204*4882a593Smuzhiyun __ICE_RESET_FAILED, /* set by reset/rebuild */
205*4882a593Smuzhiyun /* When checking for the PF to be in a nominal operating state, the
206*4882a593Smuzhiyun * bits that are grouped at the beginning of the list need to be
207*4882a593Smuzhiyun * checked. Bits occurring before __ICE_STATE_NOMINAL_CHECK_BITS will
208*4882a593Smuzhiyun * be checked. If you need to add a bit into consideration for nominal
209*4882a593Smuzhiyun * operating state, it must be added before
210*4882a593Smuzhiyun * __ICE_STATE_NOMINAL_CHECK_BITS. Do not move this entry's position
211*4882a593Smuzhiyun * without appropriate consideration.
212*4882a593Smuzhiyun */
213*4882a593Smuzhiyun __ICE_STATE_NOMINAL_CHECK_BITS,
214*4882a593Smuzhiyun __ICE_ADMINQ_EVENT_PENDING,
215*4882a593Smuzhiyun __ICE_MAILBOXQ_EVENT_PENDING,
216*4882a593Smuzhiyun __ICE_MDD_EVENT_PENDING,
217*4882a593Smuzhiyun __ICE_VFLR_EVENT_PENDING,
218*4882a593Smuzhiyun __ICE_FLTR_OVERFLOW_PROMISC,
219*4882a593Smuzhiyun __ICE_VF_DIS,
220*4882a593Smuzhiyun __ICE_CFG_BUSY,
221*4882a593Smuzhiyun __ICE_SERVICE_SCHED,
222*4882a593Smuzhiyun __ICE_SERVICE_DIS,
223*4882a593Smuzhiyun __ICE_FD_FLUSH_REQ,
224*4882a593Smuzhiyun __ICE_OICR_INTR_DIS, /* Global OICR interrupt disabled */
225*4882a593Smuzhiyun __ICE_MDD_VF_PRINT_PENDING, /* set when MDD event handle */
226*4882a593Smuzhiyun __ICE_VF_RESETS_DISABLED, /* disable resets during ice_remove */
227*4882a593Smuzhiyun __ICE_LINK_DEFAULT_OVERRIDE_PENDING,
228*4882a593Smuzhiyun __ICE_PHY_INIT_COMPLETE,
229*4882a593Smuzhiyun __ICE_STATE_NBITS /* must be last */
230*4882a593Smuzhiyun };
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun enum ice_vsi_flags {
233*4882a593Smuzhiyun ICE_VSI_FLAG_UMAC_FLTR_CHANGED,
234*4882a593Smuzhiyun ICE_VSI_FLAG_MMAC_FLTR_CHANGED,
235*4882a593Smuzhiyun ICE_VSI_FLAG_VLAN_FLTR_CHANGED,
236*4882a593Smuzhiyun ICE_VSI_FLAG_PROMISC_CHANGED,
237*4882a593Smuzhiyun ICE_VSI_FLAG_NBITS /* must be last */
238*4882a593Smuzhiyun };
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun /* struct that defines a VSI, associated with a dev */
241*4882a593Smuzhiyun struct ice_vsi {
242*4882a593Smuzhiyun struct net_device *netdev;
243*4882a593Smuzhiyun struct ice_sw *vsw; /* switch this VSI is on */
244*4882a593Smuzhiyun struct ice_pf *back; /* back pointer to PF */
245*4882a593Smuzhiyun struct ice_port_info *port_info; /* back pointer to port_info */
246*4882a593Smuzhiyun struct ice_ring **rx_rings; /* Rx ring array */
247*4882a593Smuzhiyun struct ice_ring **tx_rings; /* Tx ring array */
248*4882a593Smuzhiyun struct ice_q_vector **q_vectors; /* q_vector array */
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun irqreturn_t (*irq_handler)(int irq, void *data);
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun u64 tx_linearize;
253*4882a593Smuzhiyun DECLARE_BITMAP(state, __ICE_STATE_NBITS);
254*4882a593Smuzhiyun DECLARE_BITMAP(flags, ICE_VSI_FLAG_NBITS);
255*4882a593Smuzhiyun unsigned int current_netdev_flags;
256*4882a593Smuzhiyun u32 tx_restart;
257*4882a593Smuzhiyun u32 tx_busy;
258*4882a593Smuzhiyun u32 rx_buf_failed;
259*4882a593Smuzhiyun u32 rx_page_failed;
260*4882a593Smuzhiyun u32 rx_gro_dropped;
261*4882a593Smuzhiyun u16 num_q_vectors;
262*4882a593Smuzhiyun u16 base_vector; /* IRQ base for OS reserved vectors */
263*4882a593Smuzhiyun enum ice_vsi_type type;
264*4882a593Smuzhiyun u16 vsi_num; /* HW (absolute) index of this VSI */
265*4882a593Smuzhiyun u16 idx; /* software index in pf->vsi[] */
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun s16 vf_id; /* VF ID for SR-IOV VSIs */
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun u16 ethtype; /* Ethernet protocol for pause frame */
270*4882a593Smuzhiyun u16 num_gfltr;
271*4882a593Smuzhiyun u16 num_bfltr;
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun /* RSS config */
274*4882a593Smuzhiyun u16 rss_table_size; /* HW RSS table size */
275*4882a593Smuzhiyun u16 rss_size; /* Allocated RSS queues */
276*4882a593Smuzhiyun u8 *rss_hkey_user; /* User configured hash keys */
277*4882a593Smuzhiyun u8 *rss_lut_user; /* User configured lookup table entries */
278*4882a593Smuzhiyun u8 rss_lut_type; /* used to configure Get/Set RSS LUT AQ call */
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun /* aRFS members only allocated for the PF VSI */
281*4882a593Smuzhiyun #define ICE_MAX_ARFS_LIST 1024
282*4882a593Smuzhiyun #define ICE_ARFS_LST_MASK (ICE_MAX_ARFS_LIST - 1)
283*4882a593Smuzhiyun struct hlist_head *arfs_fltr_list;
284*4882a593Smuzhiyun struct ice_arfs_active_fltr_cntrs *arfs_fltr_cntrs;
285*4882a593Smuzhiyun spinlock_t arfs_lock; /* protects aRFS hash table and filter state */
286*4882a593Smuzhiyun atomic_t *arfs_last_fltr_id;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun /* devlink port data */
289*4882a593Smuzhiyun struct devlink_port devlink_port;
290*4882a593Smuzhiyun bool devlink_port_registered;
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun u16 max_frame;
293*4882a593Smuzhiyun u16 rx_buf_len;
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun struct ice_aqc_vsi_props info; /* VSI properties */
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun /* VSI stats */
298*4882a593Smuzhiyun struct rtnl_link_stats64 net_stats;
299*4882a593Smuzhiyun struct ice_eth_stats eth_stats;
300*4882a593Smuzhiyun struct ice_eth_stats eth_stats_prev;
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun struct list_head tmp_sync_list; /* MAC filters to be synced */
303*4882a593Smuzhiyun struct list_head tmp_unsync_list; /* MAC filters to be unsynced */
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun u8 irqs_ready:1;
306*4882a593Smuzhiyun u8 current_isup:1; /* Sync 'link up' logging */
307*4882a593Smuzhiyun u8 stat_offsets_loaded:1;
308*4882a593Smuzhiyun u8 vlan_ena:1;
309*4882a593Smuzhiyun u16 num_vlan;
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun /* queue information */
312*4882a593Smuzhiyun u8 tx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */
313*4882a593Smuzhiyun u8 rx_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */
314*4882a593Smuzhiyun u16 *txq_map; /* index in pf->avail_txqs */
315*4882a593Smuzhiyun u16 *rxq_map; /* index in pf->avail_rxqs */
316*4882a593Smuzhiyun u16 alloc_txq; /* Allocated Tx queues */
317*4882a593Smuzhiyun u16 num_txq; /* Used Tx queues */
318*4882a593Smuzhiyun u16 alloc_rxq; /* Allocated Rx queues */
319*4882a593Smuzhiyun u16 num_rxq; /* Used Rx queues */
320*4882a593Smuzhiyun u16 req_txq; /* User requested Tx queues */
321*4882a593Smuzhiyun u16 req_rxq; /* User requested Rx queues */
322*4882a593Smuzhiyun u16 num_rx_desc;
323*4882a593Smuzhiyun u16 num_tx_desc;
324*4882a593Smuzhiyun struct ice_tc_cfg tc_cfg;
325*4882a593Smuzhiyun struct bpf_prog *xdp_prog;
326*4882a593Smuzhiyun struct ice_ring **xdp_rings; /* XDP ring array */
327*4882a593Smuzhiyun u16 num_xdp_txq; /* Used XDP queues */
328*4882a593Smuzhiyun u8 xdp_mapping_mode; /* ICE_MAP_MODE_[CONTIG|SCATTER] */
329*4882a593Smuzhiyun struct xsk_buff_pool **xsk_pools;
330*4882a593Smuzhiyun u16 num_xsk_pools_used;
331*4882a593Smuzhiyun u16 num_xsk_pools;
332*4882a593Smuzhiyun } ____cacheline_internodealigned_in_smp;
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun /* struct that defines an interrupt vector */
335*4882a593Smuzhiyun struct ice_q_vector {
336*4882a593Smuzhiyun struct ice_vsi *vsi;
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun u16 v_idx; /* index in the vsi->q_vector array. */
339*4882a593Smuzhiyun u16 reg_idx;
340*4882a593Smuzhiyun u8 num_ring_rx; /* total number of Rx rings in vector */
341*4882a593Smuzhiyun u8 num_ring_tx; /* total number of Tx rings in vector */
342*4882a593Smuzhiyun u8 itr_countdown; /* when 0 should adjust adaptive ITR */
343*4882a593Smuzhiyun /* in usecs, need to use ice_intrl_to_usecs_reg() before writing this
344*4882a593Smuzhiyun * value to the device
345*4882a593Smuzhiyun */
346*4882a593Smuzhiyun u8 intrl;
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun struct napi_struct napi;
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun struct ice_ring_container rx;
351*4882a593Smuzhiyun struct ice_ring_container tx;
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun cpumask_t affinity_mask;
354*4882a593Smuzhiyun struct irq_affinity_notify affinity_notify;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun char name[ICE_INT_NAME_STR_LEN];
357*4882a593Smuzhiyun } ____cacheline_internodealigned_in_smp;
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun enum ice_pf_flags {
360*4882a593Smuzhiyun ICE_FLAG_FLTR_SYNC,
361*4882a593Smuzhiyun ICE_FLAG_RSS_ENA,
362*4882a593Smuzhiyun ICE_FLAG_SRIOV_ENA,
363*4882a593Smuzhiyun ICE_FLAG_SRIOV_CAPABLE,
364*4882a593Smuzhiyun ICE_FLAG_DCB_CAPABLE,
365*4882a593Smuzhiyun ICE_FLAG_DCB_ENA,
366*4882a593Smuzhiyun ICE_FLAG_FD_ENA,
367*4882a593Smuzhiyun ICE_FLAG_ADV_FEATURES,
368*4882a593Smuzhiyun ICE_FLAG_LINK_DOWN_ON_CLOSE_ENA,
369*4882a593Smuzhiyun ICE_FLAG_TOTAL_PORT_SHUTDOWN_ENA,
370*4882a593Smuzhiyun ICE_FLAG_NO_MEDIA,
371*4882a593Smuzhiyun ICE_FLAG_FW_LLDP_AGENT,
372*4882a593Smuzhiyun ICE_FLAG_ETHTOOL_CTXT, /* set when ethtool holds RTNL lock */
373*4882a593Smuzhiyun ICE_FLAG_LEGACY_RX,
374*4882a593Smuzhiyun ICE_FLAG_VF_TRUE_PROMISC_ENA,
375*4882a593Smuzhiyun ICE_FLAG_MDD_AUTO_RESET_VF,
376*4882a593Smuzhiyun ICE_FLAG_LINK_LENIENT_MODE_ENA,
377*4882a593Smuzhiyun ICE_PF_FLAGS_NBITS /* must be last */
378*4882a593Smuzhiyun };
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun struct ice_pf {
381*4882a593Smuzhiyun struct pci_dev *pdev;
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun struct devlink_region *nvm_region;
384*4882a593Smuzhiyun struct devlink_region *devcaps_region;
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun /* OS reserved IRQ details */
387*4882a593Smuzhiyun struct msix_entry *msix_entries;
388*4882a593Smuzhiyun struct ice_res_tracker *irq_tracker;
389*4882a593Smuzhiyun /* First MSIX vector used by SR-IOV VFs. Calculated by subtracting the
390*4882a593Smuzhiyun * number of MSIX vectors needed for all SR-IOV VFs from the number of
391*4882a593Smuzhiyun * MSIX vectors allowed on this PF.
392*4882a593Smuzhiyun */
393*4882a593Smuzhiyun u16 sriov_base_vector;
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun u16 ctrl_vsi_idx; /* control VSI index in pf->vsi array */
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun struct ice_vsi **vsi; /* VSIs created by the driver */
398*4882a593Smuzhiyun struct ice_sw *first_sw; /* first switch created by firmware */
399*4882a593Smuzhiyun /* Virtchnl/SR-IOV config info */
400*4882a593Smuzhiyun struct ice_vf *vf;
401*4882a593Smuzhiyun u16 num_alloc_vfs; /* actual number of VFs allocated */
402*4882a593Smuzhiyun u16 num_vfs_supported; /* num VFs supported for this PF */
403*4882a593Smuzhiyun u16 num_qps_per_vf;
404*4882a593Smuzhiyun u16 num_msix_per_vf;
405*4882a593Smuzhiyun /* used to ratelimit the MDD event logging */
406*4882a593Smuzhiyun unsigned long last_printed_mdd_jiffies;
407*4882a593Smuzhiyun DECLARE_BITMAP(state, __ICE_STATE_NBITS);
408*4882a593Smuzhiyun DECLARE_BITMAP(flags, ICE_PF_FLAGS_NBITS);
409*4882a593Smuzhiyun unsigned long *avail_txqs; /* bitmap to track PF Tx queue usage */
410*4882a593Smuzhiyun unsigned long *avail_rxqs; /* bitmap to track PF Rx queue usage */
411*4882a593Smuzhiyun unsigned long serv_tmr_period;
412*4882a593Smuzhiyun unsigned long serv_tmr_prev;
413*4882a593Smuzhiyun struct timer_list serv_tmr;
414*4882a593Smuzhiyun struct work_struct serv_task;
415*4882a593Smuzhiyun struct mutex avail_q_mutex; /* protects access to avail_[rx|tx]qs */
416*4882a593Smuzhiyun struct mutex sw_mutex; /* lock for protecting VSI alloc flow */
417*4882a593Smuzhiyun struct mutex tc_mutex; /* lock to protect TC changes */
418*4882a593Smuzhiyun u32 msg_enable;
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun /* spinlock to protect the AdminQ wait list */
421*4882a593Smuzhiyun spinlock_t aq_wait_lock;
422*4882a593Smuzhiyun struct hlist_head aq_wait_list;
423*4882a593Smuzhiyun wait_queue_head_t aq_wait_queue;
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun u32 hw_csum_rx_error;
426*4882a593Smuzhiyun u16 oicr_idx; /* Other interrupt cause MSIX vector index */
427*4882a593Smuzhiyun u16 num_avail_sw_msix; /* remaining MSIX SW vectors left unclaimed */
428*4882a593Smuzhiyun u16 max_pf_txqs; /* Total Tx queues PF wide */
429*4882a593Smuzhiyun u16 max_pf_rxqs; /* Total Rx queues PF wide */
430*4882a593Smuzhiyun u16 num_lan_msix; /* Total MSIX vectors for base driver */
431*4882a593Smuzhiyun u16 num_lan_tx; /* num LAN Tx queues setup */
432*4882a593Smuzhiyun u16 num_lan_rx; /* num LAN Rx queues setup */
433*4882a593Smuzhiyun u16 next_vsi; /* Next free slot in pf->vsi[] - 0-based! */
434*4882a593Smuzhiyun u16 num_alloc_vsi;
435*4882a593Smuzhiyun u16 corer_count; /* Core reset count */
436*4882a593Smuzhiyun u16 globr_count; /* Global reset count */
437*4882a593Smuzhiyun u16 empr_count; /* EMP reset count */
438*4882a593Smuzhiyun u16 pfr_count; /* PF reset count */
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun u8 wol_ena : 1; /* software state of WoL */
441*4882a593Smuzhiyun u32 wakeup_reason; /* last wakeup reason */
442*4882a593Smuzhiyun struct ice_hw_port_stats stats;
443*4882a593Smuzhiyun struct ice_hw_port_stats stats_prev;
444*4882a593Smuzhiyun struct ice_hw hw;
445*4882a593Smuzhiyun u8 stat_prev_loaded:1; /* has previous stats been loaded */
446*4882a593Smuzhiyun u16 dcbx_cap;
447*4882a593Smuzhiyun u32 tx_timeout_count;
448*4882a593Smuzhiyun unsigned long tx_timeout_last_recovery;
449*4882a593Smuzhiyun u32 tx_timeout_recovery_level;
450*4882a593Smuzhiyun char int_name[ICE_INT_NAME_STR_LEN];
451*4882a593Smuzhiyun u32 sw_int_count;
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun __le64 nvm_phy_type_lo; /* NVM PHY type low */
454*4882a593Smuzhiyun __le64 nvm_phy_type_hi; /* NVM PHY type high */
455*4882a593Smuzhiyun struct ice_link_default_override_tlv link_dflt_override;
456*4882a593Smuzhiyun };
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun struct ice_netdev_priv {
459*4882a593Smuzhiyun struct ice_vsi *vsi;
460*4882a593Smuzhiyun };
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun /**
463*4882a593Smuzhiyun * ice_irq_dynamic_ena - Enable default interrupt generation settings
464*4882a593Smuzhiyun * @hw: pointer to HW struct
465*4882a593Smuzhiyun * @vsi: pointer to VSI struct, can be NULL
466*4882a593Smuzhiyun * @q_vector: pointer to q_vector, can be NULL
467*4882a593Smuzhiyun */
468*4882a593Smuzhiyun static inline void
ice_irq_dynamic_ena(struct ice_hw * hw,struct ice_vsi * vsi,struct ice_q_vector * q_vector)469*4882a593Smuzhiyun ice_irq_dynamic_ena(struct ice_hw *hw, struct ice_vsi *vsi,
470*4882a593Smuzhiyun struct ice_q_vector *q_vector)
471*4882a593Smuzhiyun {
472*4882a593Smuzhiyun u32 vector = (vsi && q_vector) ? q_vector->reg_idx :
473*4882a593Smuzhiyun ((struct ice_pf *)hw->back)->oicr_idx;
474*4882a593Smuzhiyun int itr = ICE_ITR_NONE;
475*4882a593Smuzhiyun u32 val;
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun /* clear the PBA here, as this function is meant to clean out all
478*4882a593Smuzhiyun * previous interrupts and enable the interrupt
479*4882a593Smuzhiyun */
480*4882a593Smuzhiyun val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
481*4882a593Smuzhiyun (itr << GLINT_DYN_CTL_ITR_INDX_S);
482*4882a593Smuzhiyun if (vsi)
483*4882a593Smuzhiyun if (test_bit(__ICE_DOWN, vsi->state))
484*4882a593Smuzhiyun return;
485*4882a593Smuzhiyun wr32(hw, GLINT_DYN_CTL(vector), val);
486*4882a593Smuzhiyun }
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun /**
489*4882a593Smuzhiyun * ice_netdev_to_pf - Retrieve the PF struct associated with a netdev
490*4882a593Smuzhiyun * @netdev: pointer to the netdev struct
491*4882a593Smuzhiyun */
ice_netdev_to_pf(struct net_device * netdev)492*4882a593Smuzhiyun static inline struct ice_pf *ice_netdev_to_pf(struct net_device *netdev)
493*4882a593Smuzhiyun {
494*4882a593Smuzhiyun struct ice_netdev_priv *np = netdev_priv(netdev);
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun return np->vsi->back;
497*4882a593Smuzhiyun }
498*4882a593Smuzhiyun
ice_is_xdp_ena_vsi(struct ice_vsi * vsi)499*4882a593Smuzhiyun static inline bool ice_is_xdp_ena_vsi(struct ice_vsi *vsi)
500*4882a593Smuzhiyun {
501*4882a593Smuzhiyun return !!READ_ONCE(vsi->xdp_prog);
502*4882a593Smuzhiyun }
503*4882a593Smuzhiyun
ice_set_ring_xdp(struct ice_ring * ring)504*4882a593Smuzhiyun static inline void ice_set_ring_xdp(struct ice_ring *ring)
505*4882a593Smuzhiyun {
506*4882a593Smuzhiyun ring->flags |= ICE_TX_FLAGS_RING_XDP;
507*4882a593Smuzhiyun }
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun /**
510*4882a593Smuzhiyun * ice_xsk_pool - get XSK buffer pool bound to a ring
511*4882a593Smuzhiyun * @ring: ring to use
512*4882a593Smuzhiyun *
513*4882a593Smuzhiyun * Returns a pointer to xdp_umem structure if there is a buffer pool present,
514*4882a593Smuzhiyun * NULL otherwise.
515*4882a593Smuzhiyun */
ice_xsk_pool(struct ice_ring * ring)516*4882a593Smuzhiyun static inline struct xsk_buff_pool *ice_xsk_pool(struct ice_ring *ring)
517*4882a593Smuzhiyun {
518*4882a593Smuzhiyun struct xsk_buff_pool **pools = ring->vsi->xsk_pools;
519*4882a593Smuzhiyun u16 qid = ring->q_index;
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun if (ice_ring_is_xdp(ring))
522*4882a593Smuzhiyun qid -= ring->vsi->num_xdp_txq;
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun if (qid >= ring->vsi->num_xsk_pools || !pools || !pools[qid] ||
525*4882a593Smuzhiyun !ice_is_xdp_ena_vsi(ring->vsi))
526*4882a593Smuzhiyun return NULL;
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun return pools[qid];
529*4882a593Smuzhiyun }
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun /**
532*4882a593Smuzhiyun * ice_get_main_vsi - Get the PF VSI
533*4882a593Smuzhiyun * @pf: PF instance
534*4882a593Smuzhiyun *
535*4882a593Smuzhiyun * returns pf->vsi[0], which by definition is the PF VSI
536*4882a593Smuzhiyun */
ice_get_main_vsi(struct ice_pf * pf)537*4882a593Smuzhiyun static inline struct ice_vsi *ice_get_main_vsi(struct ice_pf *pf)
538*4882a593Smuzhiyun {
539*4882a593Smuzhiyun if (pf->vsi)
540*4882a593Smuzhiyun return pf->vsi[0];
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun return NULL;
543*4882a593Smuzhiyun }
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun /**
546*4882a593Smuzhiyun * ice_get_ctrl_vsi - Get the control VSI
547*4882a593Smuzhiyun * @pf: PF instance
548*4882a593Smuzhiyun */
ice_get_ctrl_vsi(struct ice_pf * pf)549*4882a593Smuzhiyun static inline struct ice_vsi *ice_get_ctrl_vsi(struct ice_pf *pf)
550*4882a593Smuzhiyun {
551*4882a593Smuzhiyun /* if pf->ctrl_vsi_idx is ICE_NO_VSI, control VSI was not set up */
552*4882a593Smuzhiyun if (!pf->vsi || pf->ctrl_vsi_idx == ICE_NO_VSI)
553*4882a593Smuzhiyun return NULL;
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun return pf->vsi[pf->ctrl_vsi_idx];
556*4882a593Smuzhiyun }
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun #define ICE_FD_STAT_CTR_BLOCK_COUNT 256
559*4882a593Smuzhiyun #define ICE_FD_STAT_PF_IDX(base_idx) \
560*4882a593Smuzhiyun ((base_idx) * ICE_FD_STAT_CTR_BLOCK_COUNT)
561*4882a593Smuzhiyun #define ICE_FD_SB_STAT_IDX(base_idx) ICE_FD_STAT_PF_IDX(base_idx)
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun int ice_vsi_setup_tx_rings(struct ice_vsi *vsi);
564*4882a593Smuzhiyun int ice_vsi_setup_rx_rings(struct ice_vsi *vsi);
565*4882a593Smuzhiyun int ice_vsi_open_ctrl(struct ice_vsi *vsi);
566*4882a593Smuzhiyun void ice_set_ethtool_ops(struct net_device *netdev);
567*4882a593Smuzhiyun void ice_set_ethtool_safe_mode_ops(struct net_device *netdev);
568*4882a593Smuzhiyun u16 ice_get_avail_txq_count(struct ice_pf *pf);
569*4882a593Smuzhiyun u16 ice_get_avail_rxq_count(struct ice_pf *pf);
570*4882a593Smuzhiyun int ice_vsi_recfg_qs(struct ice_vsi *vsi, int new_rx, int new_tx);
571*4882a593Smuzhiyun void ice_update_vsi_stats(struct ice_vsi *vsi);
572*4882a593Smuzhiyun void ice_update_pf_stats(struct ice_pf *pf);
573*4882a593Smuzhiyun int ice_up(struct ice_vsi *vsi);
574*4882a593Smuzhiyun int ice_down(struct ice_vsi *vsi);
575*4882a593Smuzhiyun int ice_vsi_cfg(struct ice_vsi *vsi);
576*4882a593Smuzhiyun struct ice_vsi *ice_lb_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi);
577*4882a593Smuzhiyun int ice_prepare_xdp_rings(struct ice_vsi *vsi, struct bpf_prog *prog);
578*4882a593Smuzhiyun int ice_destroy_xdp_rings(struct ice_vsi *vsi);
579*4882a593Smuzhiyun int
580*4882a593Smuzhiyun ice_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames,
581*4882a593Smuzhiyun u32 flags);
582*4882a593Smuzhiyun int ice_set_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
583*4882a593Smuzhiyun int ice_get_rss(struct ice_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
584*4882a593Smuzhiyun void ice_fill_rss_lut(u8 *lut, u16 rss_table_size, u16 rss_size);
585*4882a593Smuzhiyun int ice_schedule_reset(struct ice_pf *pf, enum ice_reset_req reset);
586*4882a593Smuzhiyun void ice_print_link_msg(struct ice_vsi *vsi, bool isup);
587*4882a593Smuzhiyun const char *ice_stat_str(enum ice_status stat_err);
588*4882a593Smuzhiyun const char *ice_aq_str(enum ice_aq_err aq_err);
589*4882a593Smuzhiyun bool ice_is_wol_supported(struct ice_hw *hw);
590*4882a593Smuzhiyun int
591*4882a593Smuzhiyun ice_fdir_write_fltr(struct ice_pf *pf, struct ice_fdir_fltr *input, bool add,
592*4882a593Smuzhiyun bool is_tun);
593*4882a593Smuzhiyun void ice_vsi_manage_fdir(struct ice_vsi *vsi, bool ena);
594*4882a593Smuzhiyun int ice_add_fdir_ethtool(struct ice_vsi *vsi, struct ethtool_rxnfc *cmd);
595*4882a593Smuzhiyun int ice_del_fdir_ethtool(struct ice_vsi *vsi, struct ethtool_rxnfc *cmd);
596*4882a593Smuzhiyun int ice_get_ethtool_fdir_entry(struct ice_hw *hw, struct ethtool_rxnfc *cmd);
597*4882a593Smuzhiyun int
598*4882a593Smuzhiyun ice_get_fdir_fltr_ids(struct ice_hw *hw, struct ethtool_rxnfc *cmd,
599*4882a593Smuzhiyun u32 *rule_locs);
600*4882a593Smuzhiyun void ice_fdir_release_flows(struct ice_hw *hw);
601*4882a593Smuzhiyun void ice_fdir_replay_flows(struct ice_hw *hw);
602*4882a593Smuzhiyun void ice_fdir_replay_fltrs(struct ice_pf *pf);
603*4882a593Smuzhiyun int ice_fdir_create_dflt_rules(struct ice_pf *pf);
604*4882a593Smuzhiyun int ice_aq_wait_for_event(struct ice_pf *pf, u16 opcode, unsigned long timeout,
605*4882a593Smuzhiyun struct ice_rq_event_info *event);
606*4882a593Smuzhiyun int ice_open(struct net_device *netdev);
607*4882a593Smuzhiyun int ice_open_internal(struct net_device *netdev);
608*4882a593Smuzhiyun int ice_stop(struct net_device *netdev);
609*4882a593Smuzhiyun void ice_service_task_schedule(struct ice_pf *pf);
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun #endif /* _ICE_H_ */
612