1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _I40E_REGISTER_H_ 5*4882a593Smuzhiyun #define _I40E_REGISTER_H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define I40E_GL_ATQLEN_ATQCRIT_SHIFT 30 8*4882a593Smuzhiyun #define I40E_GL_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQCRIT_SHIFT) 9*4882a593Smuzhiyun #define I40E_PF_ARQBAH 0x00080180 /* Reset: EMPR */ 10*4882a593Smuzhiyun #define I40E_PF_ARQBAL 0x00080080 /* Reset: EMPR */ 11*4882a593Smuzhiyun #define I40E_PF_ARQH 0x00080380 /* Reset: EMPR */ 12*4882a593Smuzhiyun #define I40E_PF_ARQH_ARQH_SHIFT 0 13*4882a593Smuzhiyun #define I40E_PF_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_PF_ARQH_ARQH_SHIFT) 14*4882a593Smuzhiyun #define I40E_PF_ARQLEN 0x00080280 /* Reset: EMPR */ 15*4882a593Smuzhiyun #define I40E_PF_ARQLEN_ARQVFE_SHIFT 28 16*4882a593Smuzhiyun #define I40E_PF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQVFE_SHIFT) 17*4882a593Smuzhiyun #define I40E_PF_ARQLEN_ARQOVFL_SHIFT 29 18*4882a593Smuzhiyun #define I40E_PF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQOVFL_SHIFT) 19*4882a593Smuzhiyun #define I40E_PF_ARQLEN_ARQCRIT_SHIFT 30 20*4882a593Smuzhiyun #define I40E_PF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQCRIT_SHIFT) 21*4882a593Smuzhiyun #define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31 22*4882a593Smuzhiyun #define I40E_PF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ARQLEN_ARQENABLE_SHIFT) 23*4882a593Smuzhiyun #define I40E_PF_ARQT 0x00080480 /* Reset: EMPR */ 24*4882a593Smuzhiyun #define I40E_PF_ATQBAH 0x00080100 /* Reset: EMPR */ 25*4882a593Smuzhiyun #define I40E_PF_ATQBAL 0x00080000 /* Reset: EMPR */ 26*4882a593Smuzhiyun #define I40E_PF_ATQH 0x00080300 /* Reset: EMPR */ 27*4882a593Smuzhiyun #define I40E_PF_ATQLEN 0x00080200 /* Reset: EMPR */ 28*4882a593Smuzhiyun #define I40E_PF_ATQLEN_ATQVFE_SHIFT 28 29*4882a593Smuzhiyun #define I40E_PF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQVFE_SHIFT) 30*4882a593Smuzhiyun #define I40E_PF_ATQLEN_ATQOVFL_SHIFT 29 31*4882a593Smuzhiyun #define I40E_PF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQOVFL_SHIFT) 32*4882a593Smuzhiyun #define I40E_PF_ATQLEN_ATQCRIT_SHIFT 30 33*4882a593Smuzhiyun #define I40E_PF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQCRIT_SHIFT) 34*4882a593Smuzhiyun #define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31 35*4882a593Smuzhiyun #define I40E_PF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ATQLEN_ATQENABLE_SHIFT) 36*4882a593Smuzhiyun #define I40E_PF_ATQT 0x00080400 /* Reset: EMPR */ 37*4882a593Smuzhiyun #define I40E_PRTDCB_GENC 0x00083000 /* Reset: CORER */ 38*4882a593Smuzhiyun #define I40E_PRTDCB_GENC_PFCLDA_SHIFT 16 39*4882a593Smuzhiyun #define I40E_PRTDCB_GENC_PFCLDA_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_GENC_PFCLDA_SHIFT) 40*4882a593Smuzhiyun #define I40E_PRTDCB_GENS 0x00083020 /* Reset: CORER */ 41*4882a593Smuzhiyun #define I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT 0 42*4882a593Smuzhiyun #define I40E_PRTDCB_GENS_DCBX_STATUS_MASK I40E_MASK(0x7, I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT) 43*4882a593Smuzhiyun #define I40E_GL_FWSTS 0x00083048 /* Reset: POR */ 44*4882a593Smuzhiyun #define I40E_GL_FWSTS_FWS1B_SHIFT 16 45*4882a593Smuzhiyun #define I40E_GL_FWSTS_FWS1B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS1B_SHIFT) 46*4882a593Smuzhiyun #define I40E_GL_FWSTS_FWS1B_EMPR_0 I40E_MASK(0x20, I40E_GL_FWSTS_FWS1B_SHIFT) 47*4882a593Smuzhiyun #define I40E_GL_FWSTS_FWS1B_EMPR_10 I40E_MASK(0x2A, I40E_GL_FWSTS_FWS1B_SHIFT) 48*4882a593Smuzhiyun #define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK I40E_MASK(0x30, I40E_GL_FWSTS_FWS1B_SHIFT) 49*4882a593Smuzhiyun #define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK I40E_MASK(0x31, I40E_GL_FWSTS_FWS1B_SHIFT) 50*4882a593Smuzhiyun #define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_TRANSITION_MASK I40E_MASK(0x32, I40E_GL_FWSTS_FWS1B_SHIFT) 51*4882a593Smuzhiyun #define I40E_XL710_GL_FWSTS_FWS1B_REC_MOD_NVM_MASK I40E_MASK(0x33, I40E_GL_FWSTS_FWS1B_SHIFT) 52*4882a593Smuzhiyun #define I40E_X722_GL_FWSTS_FWS1B_REC_MOD_CORER_MASK I40E_MASK(0xB, I40E_GL_FWSTS_FWS1B_SHIFT) 53*4882a593Smuzhiyun #define I40E_X722_GL_FWSTS_FWS1B_REC_MOD_GLOBR_MASK I40E_MASK(0xC, I40E_GL_FWSTS_FWS1B_SHIFT) 54*4882a593Smuzhiyun #define I40E_GLGEN_GPIO_CTL(_i) (0x00088100 + ((_i) * 4)) /* _i=0...29 */ /* Reset: POR */ 55*4882a593Smuzhiyun #define I40E_GLGEN_GPIO_CTL_MAX_INDEX 29 56*4882a593Smuzhiyun #define I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT 0 57*4882a593Smuzhiyun #define I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT) 58*4882a593Smuzhiyun #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT 3 59*4882a593Smuzhiyun #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT) 60*4882a593Smuzhiyun #define I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT 7 61*4882a593Smuzhiyun #define I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK I40E_MASK(0x7, I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) 62*4882a593Smuzhiyun #define I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT 11 63*4882a593Smuzhiyun #define I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT 12 64*4882a593Smuzhiyun #define I40E_GLGEN_GPIO_CTL_LED_MODE_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) 65*4882a593Smuzhiyun #define I40E_GLGEN_MDIO_I2C_SEL(_i) (0x000881C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 66*4882a593Smuzhiyun #define I40E_GLGEN_MSCA(_i) (0x0008818C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 67*4882a593Smuzhiyun #define I40E_GLGEN_MSCA_MDIADD_SHIFT 0 68*4882a593Smuzhiyun #define I40E_GLGEN_MSCA_DEVADD_SHIFT 16 69*4882a593Smuzhiyun #define I40E_GLGEN_MSCA_PHYADD_SHIFT 21 70*4882a593Smuzhiyun #define I40E_GLGEN_MSCA_OPCODE_SHIFT 26 71*4882a593Smuzhiyun #define I40E_GLGEN_MSCA_STCODE_SHIFT 28 72*4882a593Smuzhiyun #define I40E_GLGEN_MSCA_MDICMD_SHIFT 30 73*4882a593Smuzhiyun #define I40E_GLGEN_MSCA_MDICMD_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDICMD_SHIFT) 74*4882a593Smuzhiyun #define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31 75*4882a593Smuzhiyun #define I40E_GLGEN_MSCA_MDIINPROGEN_MASK I40E_MASK(0x1u, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT) 76*4882a593Smuzhiyun #define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 77*4882a593Smuzhiyun #define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0 78*4882a593Smuzhiyun #define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16 79*4882a593Smuzhiyun #define I40E_GLGEN_MSRWD_MDIRDDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT) 80*4882a593Smuzhiyun #define I40E_GLGEN_PCIFCNCNT 0x001C0AB4 /* Reset: PCIR */ 81*4882a593Smuzhiyun #define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0 82*4882a593Smuzhiyun #define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK I40E_MASK(0x1F, I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT) 83*4882a593Smuzhiyun #define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT 16 84*4882a593Smuzhiyun #define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_MASK I40E_MASK(0xFF, I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT) 85*4882a593Smuzhiyun #define I40E_GLGEN_RSTAT 0x000B8188 /* Reset: POR */ 86*4882a593Smuzhiyun #define I40E_GLGEN_RSTAT_DEVSTATE_SHIFT 0 87*4882a593Smuzhiyun #define I40E_GLGEN_RSTAT_DEVSTATE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_DEVSTATE_SHIFT) 88*4882a593Smuzhiyun #define I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT 2 89*4882a593Smuzhiyun #define I40E_GLGEN_RSTAT_RESET_TYPE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT) 90*4882a593Smuzhiyun #define I40E_GLGEN_RSTCTL 0x000B8180 /* Reset: POR */ 91*4882a593Smuzhiyun #define I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT 0 92*4882a593Smuzhiyun #define I40E_GLGEN_RSTCTL_GRSTDEL_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT) 93*4882a593Smuzhiyun #define I40E_GLGEN_RTRIG 0x000B8190 /* Reset: CORER */ 94*4882a593Smuzhiyun #define I40E_GLGEN_RTRIG_CORER_SHIFT 0 95*4882a593Smuzhiyun #define I40E_GLGEN_RTRIG_CORER_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_CORER_SHIFT) 96*4882a593Smuzhiyun #define I40E_GLGEN_RTRIG_GLOBR_SHIFT 1 97*4882a593Smuzhiyun #define I40E_GLGEN_RTRIG_GLOBR_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_GLOBR_SHIFT) 98*4882a593Smuzhiyun #define I40E_GLGEN_STAT 0x000B612C /* Reset: POR */ 99*4882a593Smuzhiyun #define I40E_GLGEN_VFLRSTAT(_i) (0x00092600 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */ 100*4882a593Smuzhiyun #define I40E_GLVFGEN_TIMER 0x000881BC /* Reset: CORER */ 101*4882a593Smuzhiyun #define I40E_PFGEN_CTRL 0x00092400 /* Reset: PFR */ 102*4882a593Smuzhiyun #define I40E_PFGEN_CTRL_PFSWR_SHIFT 0 103*4882a593Smuzhiyun #define I40E_PFGEN_CTRL_PFSWR_MASK I40E_MASK(0x1, I40E_PFGEN_CTRL_PFSWR_SHIFT) 104*4882a593Smuzhiyun #define I40E_PFGEN_PORTNUM 0x001C0480 /* Reset: CORER */ 105*4882a593Smuzhiyun #define I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT 0 106*4882a593Smuzhiyun #define I40E_PFGEN_PORTNUM_PORT_NUM_MASK I40E_MASK(0x3, I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT) 107*4882a593Smuzhiyun #define I40E_PRTGEN_CNF 0x000B8120 /* Reset: POR */ 108*4882a593Smuzhiyun #define I40E_PRTGEN_CNF_PORT_DIS_SHIFT 0 109*4882a593Smuzhiyun #define I40E_PRTGEN_CNF_PORT_DIS_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF_PORT_DIS_SHIFT) 110*4882a593Smuzhiyun #define I40E_PRTGEN_STATUS 0x000B8100 /* Reset: POR */ 111*4882a593Smuzhiyun #define I40E_VFGEN_RSTAT1(_VF) (0x00074400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 112*4882a593Smuzhiyun #define I40E_VPGEN_VFRSTAT(_VF) (0x00091C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 113*4882a593Smuzhiyun #define I40E_VPGEN_VFRSTAT_VFRD_SHIFT 0 114*4882a593Smuzhiyun #define I40E_VPGEN_VFRSTAT_VFRD_MASK I40E_MASK(0x1, I40E_VPGEN_VFRSTAT_VFRD_SHIFT) 115*4882a593Smuzhiyun #define I40E_VPGEN_VFRTRIG(_VF) (0x00091800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 116*4882a593Smuzhiyun #define I40E_VPGEN_VFRTRIG_VFSWR_SHIFT 0 117*4882a593Smuzhiyun #define I40E_VPGEN_VFRTRIG_VFSWR_MASK I40E_MASK(0x1, I40E_VPGEN_VFRTRIG_VFSWR_SHIFT) 118*4882a593Smuzhiyun #define I40E_GLHMC_FCOEDDPBASE(_i) (0x000C6600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 119*4882a593Smuzhiyun #define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT 0 120*4882a593Smuzhiyun #define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT) 121*4882a593Smuzhiyun #define I40E_GLHMC_FCOEDDPCNT(_i) (0x000C6700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 122*4882a593Smuzhiyun #define I40E_GLHMC_FCOEDDPOBJSZ 0x000C2010 /* Reset: CORER */ 123*4882a593Smuzhiyun #define I40E_GLHMC_FCOEFBASE(_i) (0x000C6800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 124*4882a593Smuzhiyun #define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT 0 125*4882a593Smuzhiyun #define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT) 126*4882a593Smuzhiyun #define I40E_GLHMC_FCOEFCNT(_i) (0x000C6900 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 127*4882a593Smuzhiyun #define I40E_GLHMC_FCOEFMAX 0x000C20D0 /* Reset: CORER */ 128*4882a593Smuzhiyun #define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT 0 129*4882a593Smuzhiyun #define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK I40E_MASK(0xFFFF, I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT) 130*4882a593Smuzhiyun #define I40E_GLHMC_FCOEFOBJSZ 0x000C2018 /* Reset: CORER */ 131*4882a593Smuzhiyun #define I40E_GLHMC_FCOEMAX 0x000C2014 /* Reset: CORER */ 132*4882a593Smuzhiyun #define I40E_GLHMC_LANQMAX 0x000C2008 /* Reset: CORER */ 133*4882a593Smuzhiyun #define I40E_GLHMC_LANRXBASE(_i) (0x000C6400 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 134*4882a593Smuzhiyun #define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT 0 135*4882a593Smuzhiyun #define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT) 136*4882a593Smuzhiyun #define I40E_GLHMC_LANRXCNT(_i) (0x000C6500 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 137*4882a593Smuzhiyun #define I40E_GLHMC_LANRXOBJSZ 0x000C200c /* Reset: CORER */ 138*4882a593Smuzhiyun #define I40E_GLHMC_LANTXBASE(_i) (0x000C6200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 139*4882a593Smuzhiyun #define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT 0 140*4882a593Smuzhiyun #define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT) 141*4882a593Smuzhiyun #define I40E_GLHMC_LANTXCNT(_i) (0x000C6300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 142*4882a593Smuzhiyun #define I40E_GLHMC_LANTXOBJSZ 0x000C2004 /* Reset: CORER */ 143*4882a593Smuzhiyun #define I40E_PFHMC_ERRORDATA 0x000C0500 /* Reset: PFR */ 144*4882a593Smuzhiyun #define I40E_PFHMC_ERRORINFO 0x000C0400 /* Reset: PFR */ 145*4882a593Smuzhiyun #define I40E_PFHMC_PDINV 0x000C0300 /* Reset: PFR */ 146*4882a593Smuzhiyun #define I40E_PFHMC_PDINV_PMSDIDX_SHIFT 0 147*4882a593Smuzhiyun #define I40E_PFHMC_PDINV_PMPDIDX_SHIFT 16 148*4882a593Smuzhiyun #define I40E_PFHMC_SDCMD 0x000C0000 /* Reset: PFR */ 149*4882a593Smuzhiyun #define I40E_PFHMC_SDCMD_PMSDWR_SHIFT 31 150*4882a593Smuzhiyun #define I40E_PFHMC_SDDATAHIGH 0x000C0200 /* Reset: PFR */ 151*4882a593Smuzhiyun #define I40E_PFHMC_SDDATALOW 0x000C0100 /* Reset: PFR */ 152*4882a593Smuzhiyun #define I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT 0 153*4882a593Smuzhiyun #define I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT 1 154*4882a593Smuzhiyun #define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT 2 155*4882a593Smuzhiyun #define I40E_PFGEN_PORTMDIO_NUM 0x0003F100 /* Reset: CORER */ 156*4882a593Smuzhiyun #define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT 4 157*4882a593Smuzhiyun #define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK I40E_MASK(0x1, I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT) 158*4882a593Smuzhiyun #define I40E_PFINT_AEQCTL 0x00038700 /* Reset: CORER */ 159*4882a593Smuzhiyun #define I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT 0 160*4882a593Smuzhiyun #define I40E_PFINT_AEQCTL_ITR_INDX_SHIFT 11 161*4882a593Smuzhiyun #define I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT 30 162*4882a593Smuzhiyun #define I40E_PFINT_AEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT) 163*4882a593Smuzhiyun #define I40E_PFINT_CEQCTL(_INTPF) (0x00036800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: CORER */ 164*4882a593Smuzhiyun #define I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT 0 165*4882a593Smuzhiyun #define I40E_PFINT_CEQCTL_ITR_INDX_SHIFT 11 166*4882a593Smuzhiyun #define I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT 16 167*4882a593Smuzhiyun #define I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT 30 168*4882a593Smuzhiyun #define I40E_PFINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT) 169*4882a593Smuzhiyun #define I40E_GLINT_CTL 0x0003F800 /* Reset: CORER */ 170*4882a593Smuzhiyun #define I40E_GLINT_CTL_DIS_AUTOMASK_VF0_SHIFT 1 171*4882a593Smuzhiyun #define I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK I40E_MASK(0x1, I40E_GLINT_CTL_DIS_AUTOMASK_VF0_SHIFT) 172*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTL0 0x00038480 /* Reset: PFR */ 173*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTL0_INTENA_SHIFT 0 174*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTL0_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_SHIFT) 175*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT 1 176*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTL0_CLEARPBA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT) 177*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT 2 178*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT) 179*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT 3 180*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTL0_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) 181*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24 182*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT) 183*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT 25 184*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT) 185*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT 31 186*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT) 187*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTLN(_INTPF) (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ 188*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTLN_INTENA_SHIFT 0 189*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTLN_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_INTENA_SHIFT) 190*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT 1 191*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTLN_CLEARPBA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT) 192*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT 2 193*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT) 194*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT 3 195*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTLN_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) 196*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT 5 197*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24 198*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT) 199*4882a593Smuzhiyun #define I40E_PFINT_ICR0 0x00038780 /* Reset: CORER */ 200*4882a593Smuzhiyun #define I40E_PFINT_ICR0_INTEVENT_SHIFT 0 201*4882a593Smuzhiyun #define I40E_PFINT_ICR0_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_INTEVENT_SHIFT) 202*4882a593Smuzhiyun #define I40E_PFINT_ICR0_QUEUE_0_SHIFT 1 203*4882a593Smuzhiyun #define I40E_PFINT_ICR0_QUEUE_0_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_0_SHIFT) 204*4882a593Smuzhiyun #define I40E_PFINT_ICR0_ECC_ERR_SHIFT 16 205*4882a593Smuzhiyun #define I40E_PFINT_ICR0_ECC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ECC_ERR_SHIFT) 206*4882a593Smuzhiyun #define I40E_PFINT_ICR0_MAL_DETECT_SHIFT 19 207*4882a593Smuzhiyun #define I40E_PFINT_ICR0_MAL_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_MAL_DETECT_SHIFT) 208*4882a593Smuzhiyun #define I40E_PFINT_ICR0_GRST_SHIFT 20 209*4882a593Smuzhiyun #define I40E_PFINT_ICR0_GRST_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_GRST_SHIFT) 210*4882a593Smuzhiyun #define I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT 21 211*4882a593Smuzhiyun #define I40E_PFINT_ICR0_PCI_EXCEPTION_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT) 212*4882a593Smuzhiyun #define I40E_PFINT_ICR0_TIMESYNC_SHIFT 23 213*4882a593Smuzhiyun #define I40E_PFINT_ICR0_TIMESYNC_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_TIMESYNC_SHIFT) 214*4882a593Smuzhiyun #define I40E_PFINT_ICR0_HMC_ERR_SHIFT 26 215*4882a593Smuzhiyun #define I40E_PFINT_ICR0_HMC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_HMC_ERR_SHIFT) 216*4882a593Smuzhiyun #define I40E_PFINT_ICR0_PE_CRITERR_SHIFT 28 217*4882a593Smuzhiyun #define I40E_PFINT_ICR0_PE_CRITERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_PE_CRITERR_SHIFT) 218*4882a593Smuzhiyun #define I40E_PFINT_ICR0_VFLR_SHIFT 29 219*4882a593Smuzhiyun #define I40E_PFINT_ICR0_VFLR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_VFLR_SHIFT) 220*4882a593Smuzhiyun #define I40E_PFINT_ICR0_ADMINQ_SHIFT 30 221*4882a593Smuzhiyun #define I40E_PFINT_ICR0_ADMINQ_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ADMINQ_SHIFT) 222*4882a593Smuzhiyun #define I40E_PFINT_ICR0_SWINT_SHIFT 31 223*4882a593Smuzhiyun #define I40E_PFINT_ICR0_SWINT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_SWINT_SHIFT) 224*4882a593Smuzhiyun #define I40E_PFINT_ICR0_ENA 0x00038800 /* Reset: CORER */ 225*4882a593Smuzhiyun #define I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT 16 226*4882a593Smuzhiyun #define I40E_PFINT_ICR0_ENA_ECC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT) 227*4882a593Smuzhiyun #define I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT 19 228*4882a593Smuzhiyun #define I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT) 229*4882a593Smuzhiyun #define I40E_PFINT_ICR0_ENA_GRST_SHIFT 20 230*4882a593Smuzhiyun #define I40E_PFINT_ICR0_ENA_GRST_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_GRST_SHIFT) 231*4882a593Smuzhiyun #define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT 21 232*4882a593Smuzhiyun #define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT) 233*4882a593Smuzhiyun #define I40E_PFINT_ICR0_ENA_GPIO_SHIFT 22 234*4882a593Smuzhiyun #define I40E_PFINT_ICR0_ENA_GPIO_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_GPIO_SHIFT) 235*4882a593Smuzhiyun #define I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT 23 236*4882a593Smuzhiyun #define I40E_PFINT_ICR0_ENA_TIMESYNC_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT) 237*4882a593Smuzhiyun #define I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT 26 238*4882a593Smuzhiyun #define I40E_PFINT_ICR0_ENA_HMC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT) 239*4882a593Smuzhiyun #define I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT 28 240*4882a593Smuzhiyun #define I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT) 241*4882a593Smuzhiyun #define I40E_PFINT_ICR0_ENA_VFLR_SHIFT 29 242*4882a593Smuzhiyun #define I40E_PFINT_ICR0_ENA_VFLR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_VFLR_SHIFT) 243*4882a593Smuzhiyun #define I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT 30 244*4882a593Smuzhiyun #define I40E_PFINT_ICR0_ENA_ADMINQ_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT) 245*4882a593Smuzhiyun #define I40E_PFINT_ITR0(_i) (0x00038000 + ((_i) * 128)) /* _i=0...2 */ /* Reset: PFR */ 246*4882a593Smuzhiyun #define I40E_PFINT_ITRN(_i, _INTPF) (0x00030000 + ((_i) * 2048 + (_INTPF) * 4)) /* _i=0...2, _INTPF=0...511 */ /* Reset: PFR */ 247*4882a593Smuzhiyun #define I40E_PFINT_LNKLST0 0x00038500 /* Reset: PFR */ 248*4882a593Smuzhiyun #define I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT 0 249*4882a593Smuzhiyun #define I40E_PFINT_LNKLSTN(_INTPF) (0x00035000 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ 250*4882a593Smuzhiyun #define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0 251*4882a593Smuzhiyun #define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) 252*4882a593Smuzhiyun #define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11 253*4882a593Smuzhiyun #define I40E_PFINT_RATEN(_INTPF) (0x00035800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ 254*4882a593Smuzhiyun #define I40E_PFINT_STAT_CTL0 0x00038400 /* Reset: CORER */ 255*4882a593Smuzhiyun #define I40E_QINT_RQCTL(_Q) (0x0003A000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 256*4882a593Smuzhiyun #define I40E_QINT_RQCTL_MSIX_INDX_SHIFT 0 257*4882a593Smuzhiyun #define I40E_QINT_RQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_RQCTL_MSIX_INDX_SHIFT) 258*4882a593Smuzhiyun #define I40E_QINT_RQCTL_ITR_INDX_SHIFT 11 259*4882a593Smuzhiyun #define I40E_QINT_RQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_QINT_RQCTL_ITR_INDX_SHIFT) 260*4882a593Smuzhiyun #define I40E_QINT_RQCTL_MSIX0_INDX_SHIFT 13 261*4882a593Smuzhiyun #define I40E_QINT_RQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_QINT_RQCTL_MSIX0_INDX_SHIFT) 262*4882a593Smuzhiyun #define I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT 16 263*4882a593Smuzhiyun #define I40E_QINT_RQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) 264*4882a593Smuzhiyun #define I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT 27 265*4882a593Smuzhiyun #define I40E_QINT_RQCTL_CAUSE_ENA_SHIFT 30 266*4882a593Smuzhiyun #define I40E_QINT_RQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) 267*4882a593Smuzhiyun #define I40E_QINT_RQCTL_INTEVENT_SHIFT 31 268*4882a593Smuzhiyun #define I40E_QINT_RQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_QINT_RQCTL_INTEVENT_SHIFT) 269*4882a593Smuzhiyun #define I40E_QINT_TQCTL(_Q) (0x0003C000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 270*4882a593Smuzhiyun #define I40E_QINT_TQCTL_MSIX_INDX_SHIFT 0 271*4882a593Smuzhiyun #define I40E_QINT_TQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_TQCTL_MSIX_INDX_SHIFT) 272*4882a593Smuzhiyun #define I40E_QINT_TQCTL_ITR_INDX_SHIFT 11 273*4882a593Smuzhiyun #define I40E_QINT_TQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_QINT_TQCTL_ITR_INDX_SHIFT) 274*4882a593Smuzhiyun #define I40E_QINT_TQCTL_MSIX0_INDX_SHIFT 13 275*4882a593Smuzhiyun #define I40E_QINT_TQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_QINT_TQCTL_MSIX0_INDX_SHIFT) 276*4882a593Smuzhiyun #define I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT 16 277*4882a593Smuzhiyun #define I40E_QINT_TQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) 278*4882a593Smuzhiyun #define I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT 27 279*4882a593Smuzhiyun #define I40E_QINT_TQCTL_CAUSE_ENA_SHIFT 30 280*4882a593Smuzhiyun #define I40E_QINT_TQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_QINT_TQCTL_CAUSE_ENA_SHIFT) 281*4882a593Smuzhiyun #define I40E_QINT_TQCTL_INTEVENT_SHIFT 31 282*4882a593Smuzhiyun #define I40E_QINT_TQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_QINT_TQCTL_INTEVENT_SHIFT) 283*4882a593Smuzhiyun #define I40E_VFINT_DYN_CTL0(_VF) (0x0002A400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 284*4882a593Smuzhiyun #define I40E_VFINT_DYN_CTLN(_INTVF) (0x00024800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */ 285*4882a593Smuzhiyun #define I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT 1 286*4882a593Smuzhiyun #define I40E_VFINT_DYN_CTLN_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT) 287*4882a593Smuzhiyun #define I40E_VFINT_ICR0_ADMINQ_SHIFT 30 288*4882a593Smuzhiyun #define I40E_VFINT_ICR0_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ADMINQ_SHIFT) 289*4882a593Smuzhiyun #define I40E_VFINT_ICR0_ENA(_VF) (0x0002C000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 290*4882a593Smuzhiyun #define I40E_VPINT_AEQCTL(_VF) (0x0002B800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 291*4882a593Smuzhiyun #define I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT 0 292*4882a593Smuzhiyun #define I40E_VPINT_AEQCTL_ITR_INDX_SHIFT 11 293*4882a593Smuzhiyun #define I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT 30 294*4882a593Smuzhiyun #define I40E_VPINT_AEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT) 295*4882a593Smuzhiyun #define I40E_VPINT_CEQCTL(_INTVF) (0x00026800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: CORER */ 296*4882a593Smuzhiyun #define I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT 0 297*4882a593Smuzhiyun #define I40E_VPINT_CEQCTL_ITR_INDX_SHIFT 11 298*4882a593Smuzhiyun #define I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT 16 299*4882a593Smuzhiyun #define I40E_VPINT_CEQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT) 300*4882a593Smuzhiyun #define I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT 27 301*4882a593Smuzhiyun #define I40E_VPINT_CEQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT) 302*4882a593Smuzhiyun #define I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT 30 303*4882a593Smuzhiyun #define I40E_VPINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT) 304*4882a593Smuzhiyun #define I40E_VPINT_LNKLST0(_VF) (0x0002A800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 305*4882a593Smuzhiyun #define I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT 0 306*4882a593Smuzhiyun #define I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) 307*4882a593Smuzhiyun #define I40E_VPINT_LNKLSTN(_INTVF) (0x00025000 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */ 308*4882a593Smuzhiyun #define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0 309*4882a593Smuzhiyun #define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) 310*4882a593Smuzhiyun #define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11 311*4882a593Smuzhiyun #define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT) 312*4882a593Smuzhiyun #define I40E_GLLAN_RCTL_0 0x0012A500 /* Reset: CORER */ 313*4882a593Smuzhiyun #define I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT 0 314*4882a593Smuzhiyun #define I40E_GLLAN_RCTL_0_PXE_MODE_MASK I40E_MASK(0x1, I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT) 315*4882a593Smuzhiyun #define I40E_GLLAN_TSOMSK_F 0x000442D8 /* Reset: CORER */ 316*4882a593Smuzhiyun #define I40E_GLLAN_TSOMSK_L 0x000442E0 /* Reset: CORER */ 317*4882a593Smuzhiyun #define I40E_GLLAN_TSOMSK_M 0x000442DC /* Reset: CORER */ 318*4882a593Smuzhiyun #define I40E_GLLAN_TXPRE_QDIS(_i) (0x000e6500 + ((_i) * 4)) /* _i=0...11 */ /* Reset: CORER */ 319*4882a593Smuzhiyun #define I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT 0 320*4882a593Smuzhiyun #define I40E_GLLAN_TXPRE_QDIS_QINDX_MASK I40E_MASK(0x7FF, I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT) 321*4882a593Smuzhiyun #define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT 30 322*4882a593Smuzhiyun #define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT) 323*4882a593Smuzhiyun #define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31 324*4882a593Smuzhiyun #define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK I40E_MASK(0x1u, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT) 325*4882a593Smuzhiyun #define I40E_PFLAN_QALLOC 0x001C0400 /* Reset: CORER */ 326*4882a593Smuzhiyun #define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0 327*4882a593Smuzhiyun #define I40E_PFLAN_QALLOC_FIRSTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_FIRSTQ_SHIFT) 328*4882a593Smuzhiyun #define I40E_PFLAN_QALLOC_LASTQ_SHIFT 16 329*4882a593Smuzhiyun #define I40E_PFLAN_QALLOC_LASTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_LASTQ_SHIFT) 330*4882a593Smuzhiyun #define I40E_PFLAN_QALLOC_VALID_SHIFT 31 331*4882a593Smuzhiyun #define I40E_PFLAN_QALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PFLAN_QALLOC_VALID_SHIFT) 332*4882a593Smuzhiyun #define I40E_QRX_ENA(_Q) (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */ 333*4882a593Smuzhiyun #define I40E_QRX_ENA_QENA_REQ_SHIFT 0 334*4882a593Smuzhiyun #define I40E_QRX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_REQ_SHIFT) 335*4882a593Smuzhiyun #define I40E_QRX_ENA_QENA_STAT_SHIFT 2 336*4882a593Smuzhiyun #define I40E_QRX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_STAT_SHIFT) 337*4882a593Smuzhiyun #define I40E_QRX_TAIL(_Q) (0x00128000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 338*4882a593Smuzhiyun #define I40E_QTX_CTL(_Q) (0x00104000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 339*4882a593Smuzhiyun #define I40E_QTX_CTL_PFVF_Q_SHIFT 0 340*4882a593Smuzhiyun #define I40E_QTX_CTL_PFVF_Q_MASK I40E_MASK(0x3, I40E_QTX_CTL_PFVF_Q_SHIFT) 341*4882a593Smuzhiyun #define I40E_QTX_CTL_PF_INDX_SHIFT 2 342*4882a593Smuzhiyun #define I40E_QTX_CTL_PF_INDX_MASK I40E_MASK(0xF, I40E_QTX_CTL_PF_INDX_SHIFT) 343*4882a593Smuzhiyun #define I40E_QTX_CTL_VFVM_INDX_SHIFT 7 344*4882a593Smuzhiyun #define I40E_QTX_CTL_VFVM_INDX_MASK I40E_MASK(0x1FF, I40E_QTX_CTL_VFVM_INDX_SHIFT) 345*4882a593Smuzhiyun #define I40E_QTX_ENA(_Q) (0x00100000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */ 346*4882a593Smuzhiyun #define I40E_QTX_ENA_QENA_REQ_SHIFT 0 347*4882a593Smuzhiyun #define I40E_QTX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QTX_ENA_QENA_REQ_SHIFT) 348*4882a593Smuzhiyun #define I40E_QTX_ENA_QENA_STAT_SHIFT 2 349*4882a593Smuzhiyun #define I40E_QTX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QTX_ENA_QENA_STAT_SHIFT) 350*4882a593Smuzhiyun #define I40E_QTX_HEAD(_Q) (0x000E4000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 351*4882a593Smuzhiyun #define I40E_QTX_TAIL(_Q) (0x00108000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */ 352*4882a593Smuzhiyun #define I40E_VPLAN_MAPENA(_VF) (0x00074000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 353*4882a593Smuzhiyun #define I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT 0 354*4882a593Smuzhiyun #define I40E_VPLAN_MAPENA_TXRX_ENA_MASK I40E_MASK(0x1, I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT) 355*4882a593Smuzhiyun #define I40E_VPLAN_QTABLE(_i, _VF) (0x00070000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: VFR */ 356*4882a593Smuzhiyun #define I40E_VPLAN_QTABLE_QINDEX_SHIFT 0 357*4882a593Smuzhiyun #define I40E_VPLAN_QTABLE_QINDEX_MASK I40E_MASK(0x7FF, I40E_VPLAN_QTABLE_QINDEX_SHIFT) 358*4882a593Smuzhiyun #define I40E_VSILAN_QBASE(_VSI) (0x0020C800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */ 359*4882a593Smuzhiyun #define I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT 11 360*4882a593Smuzhiyun #define I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK I40E_MASK(0x1, I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT) 361*4882a593Smuzhiyun #define I40E_VSILAN_QTABLE(_i, _VSI) (0x00200000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...7, _VSI=0...383 */ /* Reset: PFR */ 362*4882a593Smuzhiyun #define I40E_PRTGL_SAH 0x001E2140 /* Reset: GLOBR */ 363*4882a593Smuzhiyun #define I40E_PRTGL_SAH_FC_SAH_SHIFT 0 364*4882a593Smuzhiyun #define I40E_PRTGL_SAH_FC_SAH_MASK I40E_MASK(0xFFFF, I40E_PRTGL_SAH_FC_SAH_SHIFT) 365*4882a593Smuzhiyun #define I40E_PRTGL_SAH_MFS_SHIFT 16 366*4882a593Smuzhiyun #define I40E_PRTGL_SAH_MFS_MASK I40E_MASK(0xFFFF, I40E_PRTGL_SAH_MFS_SHIFT) 367*4882a593Smuzhiyun #define I40E_PRTGL_SAL 0x001E2120 /* Reset: GLOBR */ 368*4882a593Smuzhiyun #define I40E_PRTGL_SAL_FC_SAL_SHIFT 0 369*4882a593Smuzhiyun #define I40E_PRTGL_SAL_FC_SAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTGL_SAL_FC_SAL_SHIFT) 370*4882a593Smuzhiyun #define I40E_GLNVM_FLA 0x000B6108 /* Reset: POR */ 371*4882a593Smuzhiyun #define I40E_GLNVM_FLA_LOCKED_SHIFT 6 372*4882a593Smuzhiyun #define I40E_GLNVM_FLA_LOCKED_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_LOCKED_SHIFT) 373*4882a593Smuzhiyun #define I40E_GLNVM_GENS 0x000B6100 /* Reset: POR */ 374*4882a593Smuzhiyun #define I40E_GLNVM_GENS_SR_SIZE_SHIFT 5 375*4882a593Smuzhiyun #define I40E_GLNVM_GENS_SR_SIZE_MASK I40E_MASK(0x7, I40E_GLNVM_GENS_SR_SIZE_SHIFT) 376*4882a593Smuzhiyun #define I40E_GLNVM_SRCTL 0x000B6110 /* Reset: POR */ 377*4882a593Smuzhiyun #define I40E_GLNVM_SRCTL_ADDR_SHIFT 14 378*4882a593Smuzhiyun #define I40E_GLNVM_SRCTL_START_SHIFT 30 379*4882a593Smuzhiyun #define I40E_GLNVM_SRCTL_DONE_SHIFT 31 380*4882a593Smuzhiyun #define I40E_GLNVM_SRCTL_DONE_MASK I40E_MASK(0x1u, I40E_GLNVM_SRCTL_DONE_SHIFT) 381*4882a593Smuzhiyun #define I40E_GLNVM_SRDATA 0x000B6114 /* Reset: POR */ 382*4882a593Smuzhiyun #define I40E_GLNVM_SRDATA_RDDATA_SHIFT 16 383*4882a593Smuzhiyun #define I40E_GLNVM_SRDATA_RDDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_RDDATA_SHIFT) 384*4882a593Smuzhiyun #define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */ 385*4882a593Smuzhiyun #define I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT 3 386*4882a593Smuzhiyun #define I40E_GLNVM_ULD_CONF_CORE_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT) 387*4882a593Smuzhiyun #define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT 4 388*4882a593Smuzhiyun #define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT) 389*4882a593Smuzhiyun #define I40E_GLPCI_CAPSUP 0x000BE4A8 /* Reset: PCIR */ 390*4882a593Smuzhiyun #define I40E_GLPCI_CAPSUP_ARI_EN_SHIFT 4 391*4882a593Smuzhiyun #define I40E_GLPCI_CAPSUP_ARI_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ARI_EN_SHIFT) 392*4882a593Smuzhiyun #define I40E_GLPCI_CNF2 0x000BE494 /* Reset: PCIR */ 393*4882a593Smuzhiyun #define I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT 2 394*4882a593Smuzhiyun #define I40E_GLPCI_CNF2_MSI_X_PF_N_MASK I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT) 395*4882a593Smuzhiyun #define I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT 13 396*4882a593Smuzhiyun #define I40E_GLPCI_CNF2_MSI_X_VF_N_MASK I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT) 397*4882a593Smuzhiyun #define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR */ 398*4882a593Smuzhiyun #define I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT 6 399*4882a593Smuzhiyun #define I40E_GLPCI_LBARCTRL_FL_SIZE_MASK I40E_MASK(0x7, I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT) 400*4882a593Smuzhiyun #define I40E_PF_FUNC_RID 0x0009C000 /* Reset: PCIR */ 401*4882a593Smuzhiyun #define I40E_PF_PCI_CIAA 0x0009C080 /* Reset: FLR */ 402*4882a593Smuzhiyun #define I40E_PF_PCI_CIAA_VF_NUM_SHIFT 12 403*4882a593Smuzhiyun #define I40E_PF_PCI_CIAD 0x0009C100 /* Reset: FLR */ 404*4882a593Smuzhiyun #define I40E_PRTPM_EEE_STAT 0x001E4320 /* Reset: GLOBR */ 405*4882a593Smuzhiyun #define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT 30 406*4882a593Smuzhiyun #define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT) 407*4882a593Smuzhiyun #define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT 31 408*4882a593Smuzhiyun #define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT) 409*4882a593Smuzhiyun #define I40E_PRTPM_RLPIC 0x001E43A0 /* Reset: GLOBR */ 410*4882a593Smuzhiyun #define I40E_PRTPM_TLPIC 0x001E43C0 /* Reset: GLOBR */ 411*4882a593Smuzhiyun #define I40E_GLQF_FDCNT_0 0x00269BAC /* Reset: CORER */ 412*4882a593Smuzhiyun #define I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT 0 413*4882a593Smuzhiyun #define I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT) 414*4882a593Smuzhiyun #define I40E_GLQF_FDCNT_0_BESTCNT_SHIFT 13 415*4882a593Smuzhiyun #define I40E_GLQF_FDCNT_0_BESTCNT_MASK I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_BESTCNT_SHIFT) 416*4882a593Smuzhiyun #define I40E_GLQF_HKEY(_i) (0x00270140 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */ 417*4882a593Smuzhiyun #define I40E_GLQF_HKEY_MAX_INDEX 12 418*4882a593Smuzhiyun #define I40E_GLQF_PCNT(_i) (0x00266800 + ((_i) * 4)) /* _i=0...511 */ /* Reset: CORER */ 419*4882a593Smuzhiyun #define I40E_PFQF_CTL_0 0x001C0AC0 /* Reset: CORER */ 420*4882a593Smuzhiyun #define I40E_PFQF_CTL_0_PEHSIZE_SHIFT 0 421*4882a593Smuzhiyun #define I40E_PFQF_CTL_0_PEHSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_0_PEHSIZE_SHIFT) 422*4882a593Smuzhiyun #define I40E_PFQF_CTL_0_PEDSIZE_SHIFT 5 423*4882a593Smuzhiyun #define I40E_PFQF_CTL_0_PEDSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_0_PEDSIZE_SHIFT) 424*4882a593Smuzhiyun #define I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT 10 425*4882a593Smuzhiyun #define I40E_PFQF_CTL_0_PFFCHSIZE_MASK I40E_MASK(0xF, I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) 426*4882a593Smuzhiyun #define I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT 14 427*4882a593Smuzhiyun #define I40E_PFQF_CTL_0_PFFCDSIZE_MASK I40E_MASK(0x3, I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) 428*4882a593Smuzhiyun #define I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT 16 429*4882a593Smuzhiyun #define I40E_PFQF_CTL_0_HASHLUTSIZE_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) 430*4882a593Smuzhiyun #define I40E_PFQF_CTL_0_FD_ENA_SHIFT 17 431*4882a593Smuzhiyun #define I40E_PFQF_CTL_0_FD_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_FD_ENA_SHIFT) 432*4882a593Smuzhiyun #define I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT 18 433*4882a593Smuzhiyun #define I40E_PFQF_CTL_0_ETYPE_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT) 434*4882a593Smuzhiyun #define I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT 19 435*4882a593Smuzhiyun #define I40E_PFQF_CTL_0_MACVLAN_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT) 436*4882a593Smuzhiyun #define I40E_PFQF_CTL_1 0x00245D80 /* Reset: CORER */ 437*4882a593Smuzhiyun #define I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT 0 438*4882a593Smuzhiyun #define I40E_PFQF_CTL_1_CLEARFDTABLE_MASK I40E_MASK(0x1, I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT) 439*4882a593Smuzhiyun #define I40E_PFQF_FDSTAT 0x00246380 /* Reset: CORER */ 440*4882a593Smuzhiyun #define I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT 0 441*4882a593Smuzhiyun #define I40E_PFQF_FDSTAT_GUARANT_CNT_MASK I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT) 442*4882a593Smuzhiyun #define I40E_PFQF_FDSTAT_BEST_CNT_SHIFT 16 443*4882a593Smuzhiyun #define I40E_PFQF_FDSTAT_BEST_CNT_MASK I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_BEST_CNT_SHIFT) 444*4882a593Smuzhiyun #define I40E_PFQF_HENA(_i) (0x00245900 + ((_i) * 128)) /* _i=0...1 */ /* Reset: CORER */ 445*4882a593Smuzhiyun #define I40E_PFQF_HKEY(_i) (0x00244800 + ((_i) * 128)) /* _i=0...12 */ /* Reset: CORER */ 446*4882a593Smuzhiyun #define I40E_PFQF_HKEY_MAX_INDEX 12 447*4882a593Smuzhiyun #define I40E_PFQF_HLUT(_i) (0x00240000 + ((_i) * 128)) /* _i=0...127 */ /* Reset: CORER */ 448*4882a593Smuzhiyun #define I40E_PFQF_HLUT_MAX_INDEX 127 449*4882a593Smuzhiyun #define I40E_PRTQF_FD_INSET(_i, _j) (0x00250000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */ 450*4882a593Smuzhiyun #define I40E_PRTQF_FD_INSET_MAX_INDEX 63 451*4882a593Smuzhiyun #define I40E_PRTQF_FD_INSET_INSET_SHIFT 0 452*4882a593Smuzhiyun #define I40E_PRTQF_FD_INSET_INSET_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTQF_FD_INSET_INSET_SHIFT) 453*4882a593Smuzhiyun #define I40E_PRTQF_FD_INSET(_i, _j) (0x00250000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */ 454*4882a593Smuzhiyun #define I40E_PRTQF_FD_INSET_MAX_INDEX 63 455*4882a593Smuzhiyun #define I40E_PRTQF_FD_INSET_INSET_SHIFT 0 456*4882a593Smuzhiyun #define I40E_PRTQF_FD_INSET_INSET_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTQF_FD_INSET_INSET_SHIFT) 457*4882a593Smuzhiyun #define I40E_PRTQF_FLX_PIT(_i) (0x00255200 + ((_i) * 32)) /* _i=0...8 */ /* Reset: CORER */ 458*4882a593Smuzhiyun #define I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT 0 459*4882a593Smuzhiyun #define I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK I40E_MASK(0x1F, I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) 460*4882a593Smuzhiyun #define I40E_PRTQF_FLX_PIT_FSIZE_SHIFT 5 461*4882a593Smuzhiyun #define I40E_PRTQF_FLX_PIT_FSIZE_MASK I40E_MASK(0x1F, I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) 462*4882a593Smuzhiyun #define I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT 10 463*4882a593Smuzhiyun #define I40E_PRTQF_FLX_PIT_DEST_OFF_MASK I40E_MASK(0x3F, I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) 464*4882a593Smuzhiyun #define I40E_VFQF_HENA1(_i, _VF) (0x00230800 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...1, _VF=0...127 */ /* Reset: CORER */ 465*4882a593Smuzhiyun #define I40E_VFQF_HKEY1(_i, _VF) (0x00228000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...12, _VF=0...127 */ /* Reset: CORER */ 466*4882a593Smuzhiyun #define I40E_VFQF_HKEY1_MAX_INDEX 12 467*4882a593Smuzhiyun #define I40E_VFQF_HLUT1(_i, _VF) (0x00220000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: CORER */ 468*4882a593Smuzhiyun #define I40E_VFQF_HLUT1_MAX_INDEX 15 469*4882a593Smuzhiyun #define I40E_GL_RXERR1H(_i) (0x00318004 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 470*4882a593Smuzhiyun #define I40E_GL_RXERR1H_MAX_INDEX 143 471*4882a593Smuzhiyun #define I40E_GL_RXERR1H_RXERR1H_SHIFT 0 472*4882a593Smuzhiyun #define I40E_GL_RXERR1H_RXERR1H_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1H_RXERR1H_SHIFT) 473*4882a593Smuzhiyun #define I40E_GL_RXERR1L(_i) (0x00318000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 474*4882a593Smuzhiyun #define I40E_GL_RXERR1L_MAX_INDEX 143 475*4882a593Smuzhiyun #define I40E_GL_RXERR1L_RXERR1L_SHIFT 0 476*4882a593Smuzhiyun #define I40E_GL_RXERR1L_RXERR1L_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1L_RXERR1L_SHIFT) 477*4882a593Smuzhiyun #define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 478*4882a593Smuzhiyun #define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 479*4882a593Smuzhiyun #define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 480*4882a593Smuzhiyun #define I40E_GLPRT_BPTCL(_i) (0x00300A00 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 481*4882a593Smuzhiyun #define I40E_GLPRT_CRCERRS(_i) (0x00300080 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 482*4882a593Smuzhiyun #define I40E_GLPRT_GORCH(_i) (0x00300004 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 483*4882a593Smuzhiyun #define I40E_GLPRT_GORCL(_i) (0x00300000 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 484*4882a593Smuzhiyun #define I40E_GLPRT_GOTCH(_i) (0x00300684 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 485*4882a593Smuzhiyun #define I40E_GLPRT_GOTCL(_i) (0x00300680 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 486*4882a593Smuzhiyun #define I40E_GLPRT_ILLERRC(_i) (0x003000E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 487*4882a593Smuzhiyun #define I40E_GLPRT_LXOFFRXC(_i) (0x00300160 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 488*4882a593Smuzhiyun #define I40E_GLPRT_LXOFFTXC(_i) (0x003009A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 489*4882a593Smuzhiyun #define I40E_GLPRT_LXONRXC(_i) (0x00300140 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 490*4882a593Smuzhiyun #define I40E_GLPRT_LXONTXC(_i) (0x00300980 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 491*4882a593Smuzhiyun #define I40E_GLPRT_MLFC(_i) (0x00300020 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 492*4882a593Smuzhiyun #define I40E_GLPRT_MPRCH(_i) (0x003005C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 493*4882a593Smuzhiyun #define I40E_GLPRT_MPRCL(_i) (0x003005C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 494*4882a593Smuzhiyun #define I40E_GLPRT_MPTCH(_i) (0x003009E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 495*4882a593Smuzhiyun #define I40E_GLPRT_MPTCL(_i) (0x003009E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 496*4882a593Smuzhiyun #define I40E_GLPRT_MRFC(_i) (0x00300040 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 497*4882a593Smuzhiyun #define I40E_GLPRT_PRC1023H(_i) (0x00300504 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 498*4882a593Smuzhiyun #define I40E_GLPRT_PRC1023L(_i) (0x00300500 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 499*4882a593Smuzhiyun #define I40E_GLPRT_PRC127H(_i) (0x003004A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 500*4882a593Smuzhiyun #define I40E_GLPRT_PRC127L(_i) (0x003004A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 501*4882a593Smuzhiyun #define I40E_GLPRT_PRC1522H(_i) (0x00300524 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 502*4882a593Smuzhiyun #define I40E_GLPRT_PRC1522L(_i) (0x00300520 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 503*4882a593Smuzhiyun #define I40E_GLPRT_PRC255H(_i) (0x003004C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 504*4882a593Smuzhiyun #define I40E_GLPRT_PRC255L(_i) (0x003004C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 505*4882a593Smuzhiyun #define I40E_GLPRT_PRC511H(_i) (0x003004E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 506*4882a593Smuzhiyun #define I40E_GLPRT_PRC511L(_i) (0x003004E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 507*4882a593Smuzhiyun #define I40E_GLPRT_PRC64H(_i) (0x00300484 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 508*4882a593Smuzhiyun #define I40E_GLPRT_PRC64L(_i) (0x00300480 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 509*4882a593Smuzhiyun #define I40E_GLPRT_PRC9522H(_i) (0x00300544 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 510*4882a593Smuzhiyun #define I40E_GLPRT_PRC9522L(_i) (0x00300540 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 511*4882a593Smuzhiyun #define I40E_GLPRT_PTC1023H(_i) (0x00300724 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 512*4882a593Smuzhiyun #define I40E_GLPRT_PTC1023L(_i) (0x00300720 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 513*4882a593Smuzhiyun #define I40E_GLPRT_PTC127H(_i) (0x003006C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 514*4882a593Smuzhiyun #define I40E_GLPRT_PTC127L(_i) (0x003006C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 515*4882a593Smuzhiyun #define I40E_GLPRT_PTC1522H(_i) (0x00300744 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 516*4882a593Smuzhiyun #define I40E_GLPRT_PTC1522L(_i) (0x00300740 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 517*4882a593Smuzhiyun #define I40E_GLPRT_PTC255H(_i) (0x003006E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 518*4882a593Smuzhiyun #define I40E_GLPRT_PTC255L(_i) (0x003006E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 519*4882a593Smuzhiyun #define I40E_GLPRT_PTC511H(_i) (0x00300704 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 520*4882a593Smuzhiyun #define I40E_GLPRT_PTC511L(_i) (0x00300700 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 521*4882a593Smuzhiyun #define I40E_GLPRT_PTC64H(_i) (0x003006A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 522*4882a593Smuzhiyun #define I40E_GLPRT_PTC64L(_i) (0x003006A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 523*4882a593Smuzhiyun #define I40E_GLPRT_PTC9522H(_i) (0x00300764 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 524*4882a593Smuzhiyun #define I40E_GLPRT_PTC9522L(_i) (0x00300760 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 525*4882a593Smuzhiyun #define I40E_GLPRT_PXOFFRXC(_i, _j) (0x00300280 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 526*4882a593Smuzhiyun #define I40E_GLPRT_PXOFFTXC(_i, _j) (0x00300880 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 527*4882a593Smuzhiyun #define I40E_GLPRT_PXONRXC(_i, _j) (0x00300180 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 528*4882a593Smuzhiyun #define I40E_GLPRT_PXONTXC(_i, _j) (0x00300780 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 529*4882a593Smuzhiyun #define I40E_GLPRT_RDPC(_i) (0x00300600 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 530*4882a593Smuzhiyun #define I40E_GLPRT_RFC(_i) (0x00300560 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 531*4882a593Smuzhiyun #define I40E_GLPRT_RJC(_i) (0x00300580 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 532*4882a593Smuzhiyun #define I40E_GLPRT_RLEC(_i) (0x003000A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 533*4882a593Smuzhiyun #define I40E_GLPRT_ROC(_i) (0x00300120 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 534*4882a593Smuzhiyun #define I40E_GLPRT_RUC(_i) (0x00300100 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 535*4882a593Smuzhiyun #define I40E_GLPRT_RXON2OFFCNT(_i, _j) (0x00300380 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 536*4882a593Smuzhiyun #define I40E_GLPRT_TDOLD(_i) (0x00300A20 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 537*4882a593Smuzhiyun #define I40E_GLPRT_UPRCH(_i) (0x003005A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 538*4882a593Smuzhiyun #define I40E_GLPRT_UPRCL(_i) (0x003005A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 539*4882a593Smuzhiyun #define I40E_GLPRT_UPTCH(_i) (0x003009C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 540*4882a593Smuzhiyun #define I40E_GLPRT_UPTCL(_i) (0x003009C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 541*4882a593Smuzhiyun #define I40E_GLSW_BPRCH(_i) (0x00370104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 542*4882a593Smuzhiyun #define I40E_GLSW_BPRCL(_i) (0x00370100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 543*4882a593Smuzhiyun #define I40E_GLSW_BPTCH(_i) (0x00340104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 544*4882a593Smuzhiyun #define I40E_GLSW_BPTCL(_i) (0x00340100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 545*4882a593Smuzhiyun #define I40E_GLSW_GORCH(_i) (0x0035C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 546*4882a593Smuzhiyun #define I40E_GLSW_GORCL(_i) (0x0035c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 547*4882a593Smuzhiyun #define I40E_GLSW_GOTCH(_i) (0x0032C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 548*4882a593Smuzhiyun #define I40E_GLSW_GOTCL(_i) (0x0032c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 549*4882a593Smuzhiyun #define I40E_GLSW_MPRCH(_i) (0x00370084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 550*4882a593Smuzhiyun #define I40E_GLSW_MPRCL(_i) (0x00370080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 551*4882a593Smuzhiyun #define I40E_GLSW_MPTCH(_i) (0x00340084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 552*4882a593Smuzhiyun #define I40E_GLSW_MPTCL(_i) (0x00340080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 553*4882a593Smuzhiyun #define I40E_GLSW_RUPP(_i) (0x00370180 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 554*4882a593Smuzhiyun #define I40E_GLSW_TDPC(_i) (0x00348000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 555*4882a593Smuzhiyun #define I40E_GLSW_UPRCH(_i) (0x00370004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 556*4882a593Smuzhiyun #define I40E_GLSW_UPRCL(_i) (0x00370000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 557*4882a593Smuzhiyun #define I40E_GLSW_UPTCH(_i) (0x00340004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 558*4882a593Smuzhiyun #define I40E_GLSW_UPTCL(_i) (0x00340000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 559*4882a593Smuzhiyun #define I40E_GLV_BPRCH(_i) (0x0036D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 560*4882a593Smuzhiyun #define I40E_GLV_BPRCL(_i) (0x0036d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 561*4882a593Smuzhiyun #define I40E_GLV_BPTCH(_i) (0x0033D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 562*4882a593Smuzhiyun #define I40E_GLV_BPTCL(_i) (0x0033d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 563*4882a593Smuzhiyun #define I40E_GLV_GORCH(_i) (0x00358004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 564*4882a593Smuzhiyun #define I40E_GLV_GORCL(_i) (0x00358000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 565*4882a593Smuzhiyun #define I40E_GLV_GOTCH(_i) (0x00328004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 566*4882a593Smuzhiyun #define I40E_GLV_GOTCL(_i) (0x00328000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 567*4882a593Smuzhiyun #define I40E_GLV_MPRCH(_i) (0x0036CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 568*4882a593Smuzhiyun #define I40E_GLV_MPRCL(_i) (0x0036cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 569*4882a593Smuzhiyun #define I40E_GLV_MPTCH(_i) (0x0033CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 570*4882a593Smuzhiyun #define I40E_GLV_MPTCL(_i) (0x0033cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 571*4882a593Smuzhiyun #define I40E_GLV_RDPC(_i) (0x00310000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 572*4882a593Smuzhiyun #define I40E_GLV_RUPP(_i) (0x0036E400 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 573*4882a593Smuzhiyun #define I40E_GLV_TEPC(_i) (0x00344000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 574*4882a593Smuzhiyun #define I40E_GLV_UPRCH(_i) (0x0036C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 575*4882a593Smuzhiyun #define I40E_GLV_UPRCL(_i) (0x0036c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 576*4882a593Smuzhiyun #define I40E_GLV_UPTCH(_i) (0x0033C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 577*4882a593Smuzhiyun #define I40E_GLV_UPTCL(_i) (0x0033c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 578*4882a593Smuzhiyun #define I40E_GLVEBTC_RBCH(_i, _j) (0x00364004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 579*4882a593Smuzhiyun #define I40E_GLVEBTC_RBCL(_i, _j) (0x00364000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 580*4882a593Smuzhiyun #define I40E_GLVEBTC_RPCH(_i, _j) (0x00368004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 581*4882a593Smuzhiyun #define I40E_GLVEBTC_RPCL(_i, _j) (0x00368000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 582*4882a593Smuzhiyun #define I40E_GLVEBTC_TBCH(_i, _j) (0x00334004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 583*4882a593Smuzhiyun #define I40E_GLVEBTC_TBCL(_i, _j) (0x00334000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 584*4882a593Smuzhiyun #define I40E_GLVEBTC_TPCH(_i, _j) (0x00338004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 585*4882a593Smuzhiyun #define I40E_GLVEBTC_TPCL(_i, _j) (0x00338000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 586*4882a593Smuzhiyun #define I40E_PRTTSYN_CTL0 0x001E4200 /* Reset: GLOBR */ 587*4882a593Smuzhiyun #define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT 1 588*4882a593Smuzhiyun #define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT) 589*4882a593Smuzhiyun #define I40E_PRTTSYN_CTL0_PF_ID_SHIFT 8 590*4882a593Smuzhiyun #define I40E_PRTTSYN_CTL0_PF_ID_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL0_PF_ID_SHIFT) 591*4882a593Smuzhiyun #define I40E_PRTTSYN_CTL0_TSYNENA_SHIFT 31 592*4882a593Smuzhiyun #define I40E_PRTTSYN_CTL0_TSYNENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TSYNENA_SHIFT) 593*4882a593Smuzhiyun #define I40E_PRTTSYN_CTL1 0x00085020 /* Reset: CORER */ 594*4882a593Smuzhiyun #define I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT 0 595*4882a593Smuzhiyun #define I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK I40E_MASK(0xFF, I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT) 596*4882a593Smuzhiyun #define I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT 16 597*4882a593Smuzhiyun #define I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT) 598*4882a593Smuzhiyun #define I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT 24 599*4882a593Smuzhiyun #define I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT 26 600*4882a593Smuzhiyun #define I40E_PRTTSYN_CTL1_UDP_ENA_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT) 601*4882a593Smuzhiyun #define I40E_PRTTSYN_CTL1_TSYNENA_SHIFT 31 602*4882a593Smuzhiyun #define I40E_PRTTSYN_CTL1_TSYNENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL1_TSYNENA_SHIFT) 603*4882a593Smuzhiyun #define I40E_PRTTSYN_INC_H 0x001E4060 /* Reset: GLOBR */ 604*4882a593Smuzhiyun #define I40E_PRTTSYN_INC_L 0x001E4040 /* Reset: GLOBR */ 605*4882a593Smuzhiyun #define I40E_PRTTSYN_RXTIME_H(_i) (0x00085040 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */ 606*4882a593Smuzhiyun #define I40E_PRTTSYN_RXTIME_L(_i) (0x000850C0 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */ 607*4882a593Smuzhiyun #define I40E_PRTTSYN_STAT_0 0x001E4220 /* Reset: GLOBR */ 608*4882a593Smuzhiyun #define I40E_PRTTSYN_STAT_0_TXTIME_SHIFT 4 609*4882a593Smuzhiyun #define I40E_PRTTSYN_STAT_0_TXTIME_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TXTIME_SHIFT) 610*4882a593Smuzhiyun #define I40E_PRTTSYN_STAT_1 0x00085140 /* Reset: CORER */ 611*4882a593Smuzhiyun #define I40E_PRTTSYN_TIME_H 0x001E4120 /* Reset: GLOBR */ 612*4882a593Smuzhiyun #define I40E_PRTTSYN_TIME_L 0x001E4100 /* Reset: GLOBR */ 613*4882a593Smuzhiyun #define I40E_PRTTSYN_TXTIME_H 0x001E41E0 /* Reset: GLOBR */ 614*4882a593Smuzhiyun #define I40E_PRTTSYN_TXTIME_L 0x001E41C0 /* Reset: GLOBR */ 615*4882a593Smuzhiyun #define I40E_GL_MDET_RX 0x0012A510 /* Reset: CORER */ 616*4882a593Smuzhiyun #define I40E_GL_MDET_RX_FUNCTION_SHIFT 0 617*4882a593Smuzhiyun #define I40E_GL_MDET_RX_FUNCTION_MASK I40E_MASK(0xFF, I40E_GL_MDET_RX_FUNCTION_SHIFT) 618*4882a593Smuzhiyun #define I40E_GL_MDET_RX_EVENT_SHIFT 8 619*4882a593Smuzhiyun #define I40E_GL_MDET_RX_EVENT_MASK I40E_MASK(0x1FF, I40E_GL_MDET_RX_EVENT_SHIFT) 620*4882a593Smuzhiyun #define I40E_GL_MDET_RX_QUEUE_SHIFT 17 621*4882a593Smuzhiyun #define I40E_GL_MDET_RX_QUEUE_MASK I40E_MASK(0x3FFF, I40E_GL_MDET_RX_QUEUE_SHIFT) 622*4882a593Smuzhiyun #define I40E_GL_MDET_RX_VALID_SHIFT 31 623*4882a593Smuzhiyun #define I40E_GL_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_GL_MDET_RX_VALID_SHIFT) 624*4882a593Smuzhiyun #define I40E_GL_MDET_TX 0x000E6480 /* Reset: CORER */ 625*4882a593Smuzhiyun #define I40E_GL_MDET_TX_QUEUE_SHIFT 0 626*4882a593Smuzhiyun #define I40E_GL_MDET_TX_QUEUE_MASK I40E_MASK(0xFFF, I40E_GL_MDET_TX_QUEUE_SHIFT) 627*4882a593Smuzhiyun #define I40E_GL_MDET_TX_VF_NUM_SHIFT 12 628*4882a593Smuzhiyun #define I40E_GL_MDET_TX_VF_NUM_MASK I40E_MASK(0x1FF, I40E_GL_MDET_TX_VF_NUM_SHIFT) 629*4882a593Smuzhiyun #define I40E_GL_MDET_TX_PF_NUM_SHIFT 21 630*4882a593Smuzhiyun #define I40E_GL_MDET_TX_PF_NUM_MASK I40E_MASK(0xF, I40E_GL_MDET_TX_PF_NUM_SHIFT) 631*4882a593Smuzhiyun #define I40E_GL_MDET_TX_EVENT_SHIFT 25 632*4882a593Smuzhiyun #define I40E_GL_MDET_TX_EVENT_MASK I40E_MASK(0x1F, I40E_GL_MDET_TX_EVENT_SHIFT) 633*4882a593Smuzhiyun #define I40E_GL_MDET_TX_VALID_SHIFT 31 634*4882a593Smuzhiyun #define I40E_GL_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_GL_MDET_TX_VALID_SHIFT) 635*4882a593Smuzhiyun #define I40E_PF_MDET_RX 0x0012A400 /* Reset: CORER */ 636*4882a593Smuzhiyun #define I40E_PF_MDET_RX_VALID_SHIFT 0 637*4882a593Smuzhiyun #define I40E_PF_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_PF_MDET_RX_VALID_SHIFT) 638*4882a593Smuzhiyun #define I40E_PF_MDET_TX 0x000E6400 /* Reset: CORER */ 639*4882a593Smuzhiyun #define I40E_PF_MDET_TX_VALID_SHIFT 0 640*4882a593Smuzhiyun #define I40E_PF_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_PF_MDET_TX_VALID_SHIFT) 641*4882a593Smuzhiyun #define I40E_PF_VT_PFALLOC 0x001C0500 /* Reset: CORER */ 642*4882a593Smuzhiyun #define I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT 0 643*4882a593Smuzhiyun #define I40E_PF_VT_PFALLOC_FIRSTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT) 644*4882a593Smuzhiyun #define I40E_PF_VT_PFALLOC_LASTVF_SHIFT 8 645*4882a593Smuzhiyun #define I40E_PF_VT_PFALLOC_LASTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_LASTVF_SHIFT) 646*4882a593Smuzhiyun #define I40E_PF_VT_PFALLOC_VALID_SHIFT 31 647*4882a593Smuzhiyun #define I40E_PF_VT_PFALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PF_VT_PFALLOC_VALID_SHIFT) 648*4882a593Smuzhiyun #define I40E_VP_MDET_RX(_VF) (0x0012A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 649*4882a593Smuzhiyun #define I40E_VP_MDET_RX_VALID_SHIFT 0 650*4882a593Smuzhiyun #define I40E_VP_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_RX_VALID_SHIFT) 651*4882a593Smuzhiyun #define I40E_VP_MDET_TX(_VF) (0x000E6000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 652*4882a593Smuzhiyun #define I40E_VP_MDET_TX_VALID_SHIFT 0 653*4882a593Smuzhiyun #define I40E_VP_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_TX_VALID_SHIFT) 654*4882a593Smuzhiyun #define I40E_PFPM_APM 0x000B8080 /* Reset: POR */ 655*4882a593Smuzhiyun #define I40E_PFPM_APM_APME_SHIFT 0 656*4882a593Smuzhiyun #define I40E_PFPM_APM_APME_MASK I40E_MASK(0x1, I40E_PFPM_APM_APME_SHIFT) 657*4882a593Smuzhiyun #define I40E_PFPM_WUFC 0x0006B400 /* Reset: POR */ 658*4882a593Smuzhiyun #define I40E_PFPM_WUFC_MAG_SHIFT 1 659*4882a593Smuzhiyun #define I40E_PFPM_WUFC_MAG_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_MAG_SHIFT) 660*4882a593Smuzhiyun #define I40E_VF_ARQBAH1 0x00006000 /* Reset: EMPR */ 661*4882a593Smuzhiyun #define I40E_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */ 662*4882a593Smuzhiyun #define I40E_VF_ARQH1 0x00007400 /* Reset: EMPR */ 663*4882a593Smuzhiyun #define I40E_VF_ARQLEN1 0x00008000 /* Reset: EMPR */ 664*4882a593Smuzhiyun #define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */ 665*4882a593Smuzhiyun #define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */ 666*4882a593Smuzhiyun #define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */ 667*4882a593Smuzhiyun #define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */ 668*4882a593Smuzhiyun #define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */ 669*4882a593Smuzhiyun #define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */ 670*4882a593Smuzhiyun #define I40E_VFQF_HLUT_MAX_INDEX 15 671*4882a593Smuzhiyun 672*4882a593Smuzhiyun 673*4882a593Smuzhiyun 674*4882a593Smuzhiyun 675*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTL0_WB_ON_ITR_SHIFT 30 676*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_WB_ON_ITR_SHIFT) 677*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTLN_WB_ON_ITR_SHIFT 30 678*4882a593Smuzhiyun #define I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_WB_ON_ITR_SHIFT) 679*4882a593Smuzhiyun #define I40E_GLNVM_FLA 0x000B6108 /* Reset: POR */ 680*4882a593Smuzhiyun #define I40E_GLNVM_FLA_LOCKED_SHIFT 6 681*4882a593Smuzhiyun #define I40E_GLNVM_FLA_LOCKED_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_LOCKED_SHIFT) 682*4882a593Smuzhiyun 683*4882a593Smuzhiyun #define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */ 684*4882a593Smuzhiyun 685*4882a593Smuzhiyun 686*4882a593Smuzhiyun 687*4882a593Smuzhiyun #define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */ 688*4882a593Smuzhiyun #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4)) /* _i=0...63 */ /* Reset: CORER */ 689*4882a593Smuzhiyun #define I40E_GLQF_ORT_PIT_INDX_SHIFT 0 690*4882a593Smuzhiyun #define I40E_GLQF_ORT_PIT_INDX_MASK I40E_MASK(0x1F, I40E_GLQF_ORT_PIT_INDX_SHIFT) 691*4882a593Smuzhiyun #define I40E_GLQF_ORT_FIELD_CNT_SHIFT 5 692*4882a593Smuzhiyun #define I40E_GLQF_ORT_FIELD_CNT_MASK I40E_MASK(0x3, I40E_GLQF_ORT_FIELD_CNT_SHIFT) 693*4882a593Smuzhiyun #define I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT 7 694*4882a593Smuzhiyun #define I40E_GLQF_ORT_FLX_PAYLOAD_MASK I40E_MASK(0x1, I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) 695*4882a593Smuzhiyun #define I40E_GLQF_FDEVICTENA(_i) (0x00270384 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */ 696*4882a593Smuzhiyun /* Redefined for X722 family */ 697*4882a593Smuzhiyun #define I40E_GLGEN_STAT_CLEAR 0x00390004 /* Reset: CORER */ 698*4882a593Smuzhiyun #endif /* _I40E_REGISTER_H_ */ 699