1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _I40E_OSDEP_H_ 5*4882a593Smuzhiyun #define _I40E_OSDEP_H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <linux/types.h> 8*4882a593Smuzhiyun #include <linux/if_ether.h> 9*4882a593Smuzhiyun #include <linux/if_vlan.h> 10*4882a593Smuzhiyun #include <linux/tcp.h> 11*4882a593Smuzhiyun #include <linux/pci.h> 12*4882a593Smuzhiyun #include <linux/highuid.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* get readq/writeq support for 32 bit kernels, use the low-first version */ 15*4882a593Smuzhiyun #include <linux/io-64-nonatomic-lo-hi.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* File to be the magic between shared code and 18*4882a593Smuzhiyun * actual OS primitives 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define hw_dbg(hw, S, A...) \ 22*4882a593Smuzhiyun do { \ 23*4882a593Smuzhiyun dev_dbg(&((struct i40e_pf *)hw->back)->pdev->dev, S, ##A); \ 24*4882a593Smuzhiyun } while (0) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg))) 27*4882a593Smuzhiyun #define rd32(a, reg) readl((a)->hw_addr + (reg)) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define rd64(a, reg) readq((a)->hw_addr + (reg)) 30*4882a593Smuzhiyun #define i40e_flush(a) readl((a)->hw_addr + I40E_GLGEN_STAT) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* memory allocation tracking */ 33*4882a593Smuzhiyun struct i40e_dma_mem { 34*4882a593Smuzhiyun void *va; 35*4882a593Smuzhiyun dma_addr_t pa; 36*4882a593Smuzhiyun u32 size; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define i40e_allocate_dma_mem(h, m, unused, s, a) \ 40*4882a593Smuzhiyun i40e_allocate_dma_mem_d(h, m, s, a) 41*4882a593Smuzhiyun #define i40e_free_dma_mem(h, m) i40e_free_dma_mem_d(h, m) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun struct i40e_virt_mem { 44*4882a593Smuzhiyun void *va; 45*4882a593Smuzhiyun u32 size; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define i40e_allocate_virt_mem(h, m, s) i40e_allocate_virt_mem_d(h, m, s) 49*4882a593Smuzhiyun #define i40e_free_virt_mem(h, m) i40e_free_virt_mem_d(h, m) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define i40e_debug(h, m, s, ...) \ 52*4882a593Smuzhiyun do { \ 53*4882a593Smuzhiyun if (((m) & (h)->debug_mask)) \ 54*4882a593Smuzhiyun pr_info("i40e %02x:%02x.%x " s, \ 55*4882a593Smuzhiyun (h)->bus.bus_id, (h)->bus.device, \ 56*4882a593Smuzhiyun (h)->bus.func, ##__VA_ARGS__); \ 57*4882a593Smuzhiyun } while (0) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun typedef enum i40e_status_code i40e_status; 60*4882a593Smuzhiyun #endif /* _I40E_OSDEP_H_ */ 61