1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _I40E_DIAG_H_ 5*4882a593Smuzhiyun #define _I40E_DIAG_H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include "i40e_type.h" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun enum i40e_lb_mode { 10*4882a593Smuzhiyun I40E_LB_MODE_NONE = 0x0, 11*4882a593Smuzhiyun I40E_LB_MODE_PHY_LOCAL = I40E_AQ_LB_PHY_LOCAL, 12*4882a593Smuzhiyun I40E_LB_MODE_PHY_REMOTE = I40E_AQ_LB_PHY_REMOTE, 13*4882a593Smuzhiyun I40E_LB_MODE_MAC_LOCAL = I40E_AQ_LB_MAC_LOCAL, 14*4882a593Smuzhiyun }; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun struct i40e_diag_reg_test_info { 17*4882a593Smuzhiyun u32 offset; /* the base register */ 18*4882a593Smuzhiyun u32 mask; /* bits that can be tested */ 19*4882a593Smuzhiyun u32 elements; /* number of elements if array */ 20*4882a593Smuzhiyun u32 stride; /* bytes between each element */ 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun extern struct i40e_diag_reg_test_info i40e_reg_list[]; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun i40e_status i40e_diag_reg_test(struct i40e_hw *hw); 26*4882a593Smuzhiyun i40e_status i40e_diag_eeprom_test(struct i40e_hw *hw); 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #endif /* _I40E_DIAG_H_ */ 29