1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 2013 - 2018 Intel Corporation. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _I40E_ALLOC_H_ 5*4882a593Smuzhiyun #define _I40E_ALLOC_H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun struct i40e_hw; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* Memory allocation types */ 10*4882a593Smuzhiyun enum i40e_memory_type { 11*4882a593Smuzhiyun i40e_mem_arq_buf = 0, /* ARQ indirect command buffer */ 12*4882a593Smuzhiyun i40e_mem_asq_buf = 1, 13*4882a593Smuzhiyun i40e_mem_atq_buf = 2, /* ATQ indirect command buffer */ 14*4882a593Smuzhiyun i40e_mem_arq_ring = 3, /* ARQ descriptor ring */ 15*4882a593Smuzhiyun i40e_mem_atq_ring = 4, /* ATQ descriptor ring */ 16*4882a593Smuzhiyun i40e_mem_pd = 5, /* Page Descriptor */ 17*4882a593Smuzhiyun i40e_mem_bp = 6, /* Backing Page - 4KB */ 18*4882a593Smuzhiyun i40e_mem_bp_jumbo = 7, /* Backing Page - > 4KB */ 19*4882a593Smuzhiyun i40e_mem_reserved 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* prototype for functions used for dynamic memory allocation */ 23*4882a593Smuzhiyun i40e_status i40e_allocate_dma_mem(struct i40e_hw *hw, 24*4882a593Smuzhiyun struct i40e_dma_mem *mem, 25*4882a593Smuzhiyun enum i40e_memory_type type, 26*4882a593Smuzhiyun u64 size, u32 alignment); 27*4882a593Smuzhiyun i40e_status i40e_free_dma_mem(struct i40e_hw *hw, 28*4882a593Smuzhiyun struct i40e_dma_mem *mem); 29*4882a593Smuzhiyun i40e_status i40e_allocate_virt_mem(struct i40e_hw *hw, 30*4882a593Smuzhiyun struct i40e_virt_mem *mem, 31*4882a593Smuzhiyun u32 size); 32*4882a593Smuzhiyun i40e_status i40e_free_virt_mem(struct i40e_hw *hw, 33*4882a593Smuzhiyun struct i40e_virt_mem *mem); 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #endif /* _I40E_ALLOC_H_ */ 36