1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /* Copyright(c) 2013 - 2018 Intel Corporation. */
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #ifndef _I40E_ADMINQ_H_
5*4882a593Smuzhiyun #define _I40E_ADMINQ_H_
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include "i40e_osdep.h"
8*4882a593Smuzhiyun #include "i40e_status.h"
9*4882a593Smuzhiyun #include "i40e_adminq_cmd.h"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #define I40E_ADMINQ_DESC(R, i) \
12*4882a593Smuzhiyun (&(((struct i40e_aq_desc *)((R).desc_buf.va))[i]))
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define I40E_ADMINQ_DESC_ALIGNMENT 4096
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun struct i40e_adminq_ring {
17*4882a593Smuzhiyun struct i40e_virt_mem dma_head; /* space for dma structures */
18*4882a593Smuzhiyun struct i40e_dma_mem desc_buf; /* descriptor ring memory */
19*4882a593Smuzhiyun struct i40e_virt_mem cmd_buf; /* command buffer memory */
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun union {
22*4882a593Smuzhiyun struct i40e_dma_mem *asq_bi;
23*4882a593Smuzhiyun struct i40e_dma_mem *arq_bi;
24*4882a593Smuzhiyun } r;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun u16 count; /* Number of descriptors */
27*4882a593Smuzhiyun u16 rx_buf_len; /* Admin Receive Queue buffer length */
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* used for interrupt processing */
30*4882a593Smuzhiyun u16 next_to_use;
31*4882a593Smuzhiyun u16 next_to_clean;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* used for queue tracking */
34*4882a593Smuzhiyun u32 head;
35*4882a593Smuzhiyun u32 tail;
36*4882a593Smuzhiyun u32 len;
37*4882a593Smuzhiyun u32 bah;
38*4882a593Smuzhiyun u32 bal;
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* ASQ transaction details */
42*4882a593Smuzhiyun struct i40e_asq_cmd_details {
43*4882a593Smuzhiyun void *callback; /* cast from type I40E_ADMINQ_CALLBACK */
44*4882a593Smuzhiyun u64 cookie;
45*4882a593Smuzhiyun u16 flags_ena;
46*4882a593Smuzhiyun u16 flags_dis;
47*4882a593Smuzhiyun bool async;
48*4882a593Smuzhiyun bool postpone;
49*4882a593Smuzhiyun struct i40e_aq_desc *wb_desc;
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun #define I40E_ADMINQ_DETAILS(R, i) \
53*4882a593Smuzhiyun (&(((struct i40e_asq_cmd_details *)((R).cmd_buf.va))[i]))
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* ARQ event information */
56*4882a593Smuzhiyun struct i40e_arq_event_info {
57*4882a593Smuzhiyun struct i40e_aq_desc desc;
58*4882a593Smuzhiyun u16 msg_len;
59*4882a593Smuzhiyun u16 buf_len;
60*4882a593Smuzhiyun u8 *msg_buf;
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* Admin Queue information */
64*4882a593Smuzhiyun struct i40e_adminq_info {
65*4882a593Smuzhiyun struct i40e_adminq_ring arq; /* receive queue */
66*4882a593Smuzhiyun struct i40e_adminq_ring asq; /* send queue */
67*4882a593Smuzhiyun u32 asq_cmd_timeout; /* send queue cmd write back timeout*/
68*4882a593Smuzhiyun u16 num_arq_entries; /* receive queue depth */
69*4882a593Smuzhiyun u16 num_asq_entries; /* send queue depth */
70*4882a593Smuzhiyun u16 arq_buf_size; /* receive queue buffer size */
71*4882a593Smuzhiyun u16 asq_buf_size; /* send queue buffer size */
72*4882a593Smuzhiyun u16 fw_maj_ver; /* firmware major version */
73*4882a593Smuzhiyun u16 fw_min_ver; /* firmware minor version */
74*4882a593Smuzhiyun u32 fw_build; /* firmware build number */
75*4882a593Smuzhiyun u16 api_maj_ver; /* api major version */
76*4882a593Smuzhiyun u16 api_min_ver; /* api minor version */
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun struct mutex asq_mutex; /* Send queue lock */
79*4882a593Smuzhiyun struct mutex arq_mutex; /* Receive queue lock */
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* last status values on send and receive queues */
82*4882a593Smuzhiyun enum i40e_admin_queue_err asq_last_status;
83*4882a593Smuzhiyun enum i40e_admin_queue_err arq_last_status;
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /**
87*4882a593Smuzhiyun * i40e_aq_rc_to_posix - convert errors to user-land codes
88*4882a593Smuzhiyun * @aq_ret: AdminQ handler error code can override aq_rc
89*4882a593Smuzhiyun * @aq_rc: AdminQ firmware error code to convert
90*4882a593Smuzhiyun **/
i40e_aq_rc_to_posix(int aq_ret,int aq_rc)91*4882a593Smuzhiyun static inline int i40e_aq_rc_to_posix(int aq_ret, int aq_rc)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun int aq_to_posix[] = {
94*4882a593Smuzhiyun 0, /* I40E_AQ_RC_OK */
95*4882a593Smuzhiyun -EPERM, /* I40E_AQ_RC_EPERM */
96*4882a593Smuzhiyun -ENOENT, /* I40E_AQ_RC_ENOENT */
97*4882a593Smuzhiyun -ESRCH, /* I40E_AQ_RC_ESRCH */
98*4882a593Smuzhiyun -EINTR, /* I40E_AQ_RC_EINTR */
99*4882a593Smuzhiyun -EIO, /* I40E_AQ_RC_EIO */
100*4882a593Smuzhiyun -ENXIO, /* I40E_AQ_RC_ENXIO */
101*4882a593Smuzhiyun -E2BIG, /* I40E_AQ_RC_E2BIG */
102*4882a593Smuzhiyun -EAGAIN, /* I40E_AQ_RC_EAGAIN */
103*4882a593Smuzhiyun -ENOMEM, /* I40E_AQ_RC_ENOMEM */
104*4882a593Smuzhiyun -EACCES, /* I40E_AQ_RC_EACCES */
105*4882a593Smuzhiyun -EFAULT, /* I40E_AQ_RC_EFAULT */
106*4882a593Smuzhiyun -EBUSY, /* I40E_AQ_RC_EBUSY */
107*4882a593Smuzhiyun -EEXIST, /* I40E_AQ_RC_EEXIST */
108*4882a593Smuzhiyun -EINVAL, /* I40E_AQ_RC_EINVAL */
109*4882a593Smuzhiyun -ENOTTY, /* I40E_AQ_RC_ENOTTY */
110*4882a593Smuzhiyun -ENOSPC, /* I40E_AQ_RC_ENOSPC */
111*4882a593Smuzhiyun -ENOSYS, /* I40E_AQ_RC_ENOSYS */
112*4882a593Smuzhiyun -ERANGE, /* I40E_AQ_RC_ERANGE */
113*4882a593Smuzhiyun -EPIPE, /* I40E_AQ_RC_EFLUSHED */
114*4882a593Smuzhiyun -ESPIPE, /* I40E_AQ_RC_BAD_ADDR */
115*4882a593Smuzhiyun -EROFS, /* I40E_AQ_RC_EMODE */
116*4882a593Smuzhiyun -EFBIG, /* I40E_AQ_RC_EFBIG */
117*4882a593Smuzhiyun };
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun /* aq_rc is invalid if AQ timed out */
120*4882a593Smuzhiyun if (aq_ret == I40E_ERR_ADMIN_QUEUE_TIMEOUT)
121*4882a593Smuzhiyun return -EAGAIN;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun if (!((u32)aq_rc < (sizeof(aq_to_posix) / sizeof((aq_to_posix)[0]))))
124*4882a593Smuzhiyun return -ERANGE;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun return aq_to_posix[aq_rc];
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun /* general information */
130*4882a593Smuzhiyun #define I40E_AQ_LARGE_BUF 512
131*4882a593Smuzhiyun #define I40E_ASQ_CMD_TIMEOUT 250000 /* usecs */
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
134*4882a593Smuzhiyun u16 opcode);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun #endif /* _I40E_ADMINQ_H_ */
137