1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /* Copyright(c) 2013 - 2019 Intel Corporation. */
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include "fm10k_vf.h"
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun /**
7*4882a593Smuzhiyun * fm10k_stop_hw_vf - Stop Tx/Rx units
8*4882a593Smuzhiyun * @hw: pointer to hardware structure
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun **/
fm10k_stop_hw_vf(struct fm10k_hw * hw)11*4882a593Smuzhiyun static s32 fm10k_stop_hw_vf(struct fm10k_hw *hw)
12*4882a593Smuzhiyun {
13*4882a593Smuzhiyun u8 *perm_addr = hw->mac.perm_addr;
14*4882a593Smuzhiyun u32 bal = 0, bah = 0, tdlen;
15*4882a593Smuzhiyun s32 err;
16*4882a593Smuzhiyun u16 i;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /* we need to disable the queues before taking further steps */
19*4882a593Smuzhiyun err = fm10k_stop_hw_generic(hw);
20*4882a593Smuzhiyun if (err && err != FM10K_ERR_REQUESTS_PENDING)
21*4882a593Smuzhiyun return err;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /* If permanent address is set then we need to restore it */
24*4882a593Smuzhiyun if (is_valid_ether_addr(perm_addr)) {
25*4882a593Smuzhiyun bal = (((u32)perm_addr[3]) << 24) |
26*4882a593Smuzhiyun (((u32)perm_addr[4]) << 16) |
27*4882a593Smuzhiyun (((u32)perm_addr[5]) << 8);
28*4882a593Smuzhiyun bah = (((u32)0xFF) << 24) |
29*4882a593Smuzhiyun (((u32)perm_addr[0]) << 16) |
30*4882a593Smuzhiyun (((u32)perm_addr[1]) << 8) |
31*4882a593Smuzhiyun ((u32)perm_addr[2]);
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* restore default itr_scale for next VF initialization */
35*4882a593Smuzhiyun tdlen = hw->mac.itr_scale << FM10K_TDLEN_ITR_SCALE_SHIFT;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* The queues have already been disabled so we just need to
38*4882a593Smuzhiyun * update their base address registers
39*4882a593Smuzhiyun */
40*4882a593Smuzhiyun for (i = 0; i < hw->mac.max_queues; i++) {
41*4882a593Smuzhiyun fm10k_write_reg(hw, FM10K_TDBAL(i), bal);
42*4882a593Smuzhiyun fm10k_write_reg(hw, FM10K_TDBAH(i), bah);
43*4882a593Smuzhiyun fm10k_write_reg(hw, FM10K_RDBAL(i), bal);
44*4882a593Smuzhiyun fm10k_write_reg(hw, FM10K_RDBAH(i), bah);
45*4882a593Smuzhiyun /* Restore ITR scale in software-defined mechanism in TDLEN
46*4882a593Smuzhiyun * for next VF initialization. See definition of
47*4882a593Smuzhiyun * FM10K_TDLEN_ITR_SCALE_SHIFT for more details on the use of
48*4882a593Smuzhiyun * TDLEN here.
49*4882a593Smuzhiyun */
50*4882a593Smuzhiyun fm10k_write_reg(hw, FM10K_TDLEN(i), tdlen);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun return err;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /**
57*4882a593Smuzhiyun * fm10k_reset_hw_vf - VF hardware reset
58*4882a593Smuzhiyun * @hw: pointer to hardware structure
59*4882a593Smuzhiyun *
60*4882a593Smuzhiyun * This function should return the hardware to a state similar to the
61*4882a593Smuzhiyun * one it is in after just being initialized.
62*4882a593Smuzhiyun **/
fm10k_reset_hw_vf(struct fm10k_hw * hw)63*4882a593Smuzhiyun static s32 fm10k_reset_hw_vf(struct fm10k_hw *hw)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun s32 err;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* shut down queues we own and reset DMA configuration */
68*4882a593Smuzhiyun err = fm10k_stop_hw_vf(hw);
69*4882a593Smuzhiyun if (err == FM10K_ERR_REQUESTS_PENDING)
70*4882a593Smuzhiyun hw->mac.reset_while_pending++;
71*4882a593Smuzhiyun else if (err)
72*4882a593Smuzhiyun return err;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* Inititate VF reset */
75*4882a593Smuzhiyun fm10k_write_reg(hw, FM10K_VFCTRL, FM10K_VFCTRL_RST);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* Flush write and allow 100us for reset to complete */
78*4882a593Smuzhiyun fm10k_write_flush(hw);
79*4882a593Smuzhiyun udelay(FM10K_RESET_TIMEOUT);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* Clear reset bit and verify it was cleared */
82*4882a593Smuzhiyun fm10k_write_reg(hw, FM10K_VFCTRL, 0);
83*4882a593Smuzhiyun if (fm10k_read_reg(hw, FM10K_VFCTRL) & FM10K_VFCTRL_RST)
84*4882a593Smuzhiyun return FM10K_ERR_RESET_FAILED;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun return 0;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /**
90*4882a593Smuzhiyun * fm10k_init_hw_vf - VF hardware initialization
91*4882a593Smuzhiyun * @hw: pointer to hardware structure
92*4882a593Smuzhiyun *
93*4882a593Smuzhiyun **/
fm10k_init_hw_vf(struct fm10k_hw * hw)94*4882a593Smuzhiyun static s32 fm10k_init_hw_vf(struct fm10k_hw *hw)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun u32 tqdloc, tqdloc0 = ~fm10k_read_reg(hw, FM10K_TQDLOC(0));
97*4882a593Smuzhiyun s32 err;
98*4882a593Smuzhiyun u16 i;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun /* verify we have at least 1 queue */
101*4882a593Smuzhiyun if (!~fm10k_read_reg(hw, FM10K_TXQCTL(0)) ||
102*4882a593Smuzhiyun !~fm10k_read_reg(hw, FM10K_RXQCTL(0))) {
103*4882a593Smuzhiyun err = FM10K_ERR_NO_RESOURCES;
104*4882a593Smuzhiyun goto reset_max_queues;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* determine how many queues we have */
108*4882a593Smuzhiyun for (i = 1; tqdloc0 && (i < FM10K_MAX_QUEUES_POOL); i++) {
109*4882a593Smuzhiyun /* verify the Descriptor cache offsets are increasing */
110*4882a593Smuzhiyun tqdloc = ~fm10k_read_reg(hw, FM10K_TQDLOC(i));
111*4882a593Smuzhiyun if (!tqdloc || (tqdloc == tqdloc0))
112*4882a593Smuzhiyun break;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* check to verify the PF doesn't own any of our queues */
115*4882a593Smuzhiyun if (!~fm10k_read_reg(hw, FM10K_TXQCTL(i)) ||
116*4882a593Smuzhiyun !~fm10k_read_reg(hw, FM10K_RXQCTL(i)))
117*4882a593Smuzhiyun break;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /* shut down queues we own and reset DMA configuration */
121*4882a593Smuzhiyun err = fm10k_disable_queues_generic(hw, i);
122*4882a593Smuzhiyun if (err)
123*4882a593Smuzhiyun goto reset_max_queues;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun /* record maximum queue count */
126*4882a593Smuzhiyun hw->mac.max_queues = i;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun /* fetch default VLAN and ITR scale */
129*4882a593Smuzhiyun hw->mac.default_vid = (fm10k_read_reg(hw, FM10K_TXQCTL(0)) &
130*4882a593Smuzhiyun FM10K_TXQCTL_VID_MASK) >> FM10K_TXQCTL_VID_SHIFT;
131*4882a593Smuzhiyun /* Read the ITR scale from TDLEN. See the definition of
132*4882a593Smuzhiyun * FM10K_TDLEN_ITR_SCALE_SHIFT for more information about how TDLEN is
133*4882a593Smuzhiyun * used here.
134*4882a593Smuzhiyun */
135*4882a593Smuzhiyun hw->mac.itr_scale = (fm10k_read_reg(hw, FM10K_TDLEN(0)) &
136*4882a593Smuzhiyun FM10K_TDLEN_ITR_SCALE_MASK) >>
137*4882a593Smuzhiyun FM10K_TDLEN_ITR_SCALE_SHIFT;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun return 0;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun reset_max_queues:
142*4882a593Smuzhiyun hw->mac.max_queues = 0;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun return err;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun /* This structure defines the attibutes to be parsed below */
148*4882a593Smuzhiyun const struct fm10k_tlv_attr fm10k_mac_vlan_msg_attr[] = {
149*4882a593Smuzhiyun FM10K_TLV_ATTR_U32(FM10K_MAC_VLAN_MSG_VLAN),
150*4882a593Smuzhiyun FM10K_TLV_ATTR_BOOL(FM10K_MAC_VLAN_MSG_SET),
151*4882a593Smuzhiyun FM10K_TLV_ATTR_MAC_ADDR(FM10K_MAC_VLAN_MSG_MAC),
152*4882a593Smuzhiyun FM10K_TLV_ATTR_MAC_ADDR(FM10K_MAC_VLAN_MSG_DEFAULT_MAC),
153*4882a593Smuzhiyun FM10K_TLV_ATTR_MAC_ADDR(FM10K_MAC_VLAN_MSG_MULTICAST),
154*4882a593Smuzhiyun FM10K_TLV_ATTR_LAST
155*4882a593Smuzhiyun };
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun /**
158*4882a593Smuzhiyun * fm10k_update_vlan_vf - Update status of VLAN ID in VLAN filter table
159*4882a593Smuzhiyun * @hw: pointer to hardware structure
160*4882a593Smuzhiyun * @vid: VLAN ID to add to table
161*4882a593Smuzhiyun * @vsi: Reserved, should always be 0
162*4882a593Smuzhiyun * @set: Indicates if this is a set or clear operation
163*4882a593Smuzhiyun *
164*4882a593Smuzhiyun * This function adds or removes the corresponding VLAN ID from the VLAN
165*4882a593Smuzhiyun * filter table for this VF.
166*4882a593Smuzhiyun **/
fm10k_update_vlan_vf(struct fm10k_hw * hw,u32 vid,u8 vsi,bool set)167*4882a593Smuzhiyun static s32 fm10k_update_vlan_vf(struct fm10k_hw *hw, u32 vid, u8 vsi, bool set)
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun struct fm10k_mbx_info *mbx = &hw->mbx;
170*4882a593Smuzhiyun u32 msg[4];
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun /* verify the index is not set */
173*4882a593Smuzhiyun if (vsi)
174*4882a593Smuzhiyun return FM10K_ERR_PARAM;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun /* clever trick to verify reserved bits in both vid and length */
177*4882a593Smuzhiyun if ((vid << 16 | vid) >> 28)
178*4882a593Smuzhiyun return FM10K_ERR_PARAM;
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun /* encode set bit into the VLAN ID */
181*4882a593Smuzhiyun if (!set)
182*4882a593Smuzhiyun vid |= FM10K_VLAN_CLEAR;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun /* generate VLAN request */
185*4882a593Smuzhiyun fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN);
186*4882a593Smuzhiyun fm10k_tlv_attr_put_u32(msg, FM10K_MAC_VLAN_MSG_VLAN, vid);
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun /* load onto outgoing mailbox */
189*4882a593Smuzhiyun return mbx->ops.enqueue_tx(hw, mbx, msg);
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun /**
193*4882a593Smuzhiyun * fm10k_msg_mac_vlan_vf - Read device MAC address from mailbox message
194*4882a593Smuzhiyun * @hw: pointer to the HW structure
195*4882a593Smuzhiyun * @results: Attributes for message
196*4882a593Smuzhiyun * @mbx: unused mailbox data
197*4882a593Smuzhiyun *
198*4882a593Smuzhiyun * This function should determine the MAC address for the VF
199*4882a593Smuzhiyun **/
fm10k_msg_mac_vlan_vf(struct fm10k_hw * hw,u32 ** results,struct fm10k_mbx_info __always_unused * mbx)200*4882a593Smuzhiyun s32 fm10k_msg_mac_vlan_vf(struct fm10k_hw *hw, u32 **results,
201*4882a593Smuzhiyun struct fm10k_mbx_info __always_unused *mbx)
202*4882a593Smuzhiyun {
203*4882a593Smuzhiyun u8 perm_addr[ETH_ALEN];
204*4882a593Smuzhiyun u16 vid;
205*4882a593Smuzhiyun s32 err;
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun /* record MAC address requested */
208*4882a593Smuzhiyun err = fm10k_tlv_attr_get_mac_vlan(
209*4882a593Smuzhiyun results[FM10K_MAC_VLAN_MSG_DEFAULT_MAC],
210*4882a593Smuzhiyun perm_addr, &vid);
211*4882a593Smuzhiyun if (err)
212*4882a593Smuzhiyun return err;
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun ether_addr_copy(hw->mac.perm_addr, perm_addr);
215*4882a593Smuzhiyun hw->mac.default_vid = vid & (FM10K_VLAN_TABLE_VID_MAX - 1);
216*4882a593Smuzhiyun hw->mac.vlan_override = !!(vid & FM10K_VLAN_OVERRIDE);
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun return 0;
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun /**
222*4882a593Smuzhiyun * fm10k_read_mac_addr_vf - Read device MAC address
223*4882a593Smuzhiyun * @hw: pointer to the HW structure
224*4882a593Smuzhiyun *
225*4882a593Smuzhiyun * This function should determine the MAC address for the VF
226*4882a593Smuzhiyun **/
fm10k_read_mac_addr_vf(struct fm10k_hw * hw)227*4882a593Smuzhiyun static s32 fm10k_read_mac_addr_vf(struct fm10k_hw *hw)
228*4882a593Smuzhiyun {
229*4882a593Smuzhiyun u8 perm_addr[ETH_ALEN];
230*4882a593Smuzhiyun u32 base_addr;
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun base_addr = fm10k_read_reg(hw, FM10K_TDBAL(0));
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun /* last byte should be 0 */
235*4882a593Smuzhiyun if (base_addr << 24)
236*4882a593Smuzhiyun return FM10K_ERR_INVALID_MAC_ADDR;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun perm_addr[3] = (u8)(base_addr >> 24);
239*4882a593Smuzhiyun perm_addr[4] = (u8)(base_addr >> 16);
240*4882a593Smuzhiyun perm_addr[5] = (u8)(base_addr >> 8);
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun base_addr = fm10k_read_reg(hw, FM10K_TDBAH(0));
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun /* first byte should be all 1's */
245*4882a593Smuzhiyun if ((~base_addr) >> 24)
246*4882a593Smuzhiyun return FM10K_ERR_INVALID_MAC_ADDR;
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun perm_addr[0] = (u8)(base_addr >> 16);
249*4882a593Smuzhiyun perm_addr[1] = (u8)(base_addr >> 8);
250*4882a593Smuzhiyun perm_addr[2] = (u8)(base_addr);
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun ether_addr_copy(hw->mac.perm_addr, perm_addr);
253*4882a593Smuzhiyun ether_addr_copy(hw->mac.addr, perm_addr);
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun return 0;
256*4882a593Smuzhiyun }
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun /**
259*4882a593Smuzhiyun * fm10k_update_uc_addr_vf - Update device unicast addresses
260*4882a593Smuzhiyun * @hw: pointer to the HW structure
261*4882a593Smuzhiyun * @glort: unused
262*4882a593Smuzhiyun * @mac: MAC address to add/remove from table
263*4882a593Smuzhiyun * @vid: VLAN ID to add/remove from table
264*4882a593Smuzhiyun * @add: Indicates if this is an add or remove operation
265*4882a593Smuzhiyun * @flags: flags field to indicate add and secure - unused
266*4882a593Smuzhiyun *
267*4882a593Smuzhiyun * This function is used to add or remove unicast MAC addresses for
268*4882a593Smuzhiyun * the VF.
269*4882a593Smuzhiyun **/
fm10k_update_uc_addr_vf(struct fm10k_hw * hw,u16 __always_unused glort,const u8 * mac,u16 vid,bool add,u8 __always_unused flags)270*4882a593Smuzhiyun static s32 fm10k_update_uc_addr_vf(struct fm10k_hw *hw,
271*4882a593Smuzhiyun u16 __always_unused glort,
272*4882a593Smuzhiyun const u8 *mac, u16 vid, bool add,
273*4882a593Smuzhiyun u8 __always_unused flags)
274*4882a593Smuzhiyun {
275*4882a593Smuzhiyun struct fm10k_mbx_info *mbx = &hw->mbx;
276*4882a593Smuzhiyun u32 msg[7];
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun /* verify VLAN ID is valid */
279*4882a593Smuzhiyun if (vid >= FM10K_VLAN_TABLE_VID_MAX)
280*4882a593Smuzhiyun return FM10K_ERR_PARAM;
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun /* verify MAC address is valid */
283*4882a593Smuzhiyun if (!is_valid_ether_addr(mac))
284*4882a593Smuzhiyun return FM10K_ERR_PARAM;
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun /* verify we are not locked down on the MAC address */
287*4882a593Smuzhiyun if (is_valid_ether_addr(hw->mac.perm_addr) &&
288*4882a593Smuzhiyun !ether_addr_equal(hw->mac.perm_addr, mac))
289*4882a593Smuzhiyun return FM10K_ERR_PARAM;
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun /* add bit to notify us if this is a set or clear operation */
292*4882a593Smuzhiyun if (!add)
293*4882a593Smuzhiyun vid |= FM10K_VLAN_CLEAR;
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun /* generate VLAN request */
296*4882a593Smuzhiyun fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN);
297*4882a593Smuzhiyun fm10k_tlv_attr_put_mac_vlan(msg, FM10K_MAC_VLAN_MSG_MAC, mac, vid);
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun /* load onto outgoing mailbox */
300*4882a593Smuzhiyun return mbx->ops.enqueue_tx(hw, mbx, msg);
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun /**
304*4882a593Smuzhiyun * fm10k_update_mc_addr_vf - Update device multicast addresses
305*4882a593Smuzhiyun * @hw: pointer to the HW structure
306*4882a593Smuzhiyun * @glort: unused
307*4882a593Smuzhiyun * @mac: MAC address to add/remove from table
308*4882a593Smuzhiyun * @vid: VLAN ID to add/remove from table
309*4882a593Smuzhiyun * @add: Indicates if this is an add or remove operation
310*4882a593Smuzhiyun *
311*4882a593Smuzhiyun * This function is used to add or remove multicast MAC addresses for
312*4882a593Smuzhiyun * the VF.
313*4882a593Smuzhiyun **/
fm10k_update_mc_addr_vf(struct fm10k_hw * hw,u16 __always_unused glort,const u8 * mac,u16 vid,bool add)314*4882a593Smuzhiyun static s32 fm10k_update_mc_addr_vf(struct fm10k_hw *hw,
315*4882a593Smuzhiyun u16 __always_unused glort,
316*4882a593Smuzhiyun const u8 *mac, u16 vid, bool add)
317*4882a593Smuzhiyun {
318*4882a593Smuzhiyun struct fm10k_mbx_info *mbx = &hw->mbx;
319*4882a593Smuzhiyun u32 msg[7];
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun /* verify VLAN ID is valid */
322*4882a593Smuzhiyun if (vid >= FM10K_VLAN_TABLE_VID_MAX)
323*4882a593Smuzhiyun return FM10K_ERR_PARAM;
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun /* verify multicast address is valid */
326*4882a593Smuzhiyun if (!is_multicast_ether_addr(mac))
327*4882a593Smuzhiyun return FM10K_ERR_PARAM;
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun /* add bit to notify us if this is a set or clear operation */
330*4882a593Smuzhiyun if (!add)
331*4882a593Smuzhiyun vid |= FM10K_VLAN_CLEAR;
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun /* generate VLAN request */
334*4882a593Smuzhiyun fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN);
335*4882a593Smuzhiyun fm10k_tlv_attr_put_mac_vlan(msg, FM10K_MAC_VLAN_MSG_MULTICAST,
336*4882a593Smuzhiyun mac, vid);
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun /* load onto outgoing mailbox */
339*4882a593Smuzhiyun return mbx->ops.enqueue_tx(hw, mbx, msg);
340*4882a593Smuzhiyun }
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun /**
343*4882a593Smuzhiyun * fm10k_update_int_moderator_vf - Request update of interrupt moderator list
344*4882a593Smuzhiyun * @hw: pointer to hardware structure
345*4882a593Smuzhiyun *
346*4882a593Smuzhiyun * This function will issue a request to the PF to rescan our MSI-X table
347*4882a593Smuzhiyun * and to update the interrupt moderator linked list.
348*4882a593Smuzhiyun **/
fm10k_update_int_moderator_vf(struct fm10k_hw * hw)349*4882a593Smuzhiyun static void fm10k_update_int_moderator_vf(struct fm10k_hw *hw)
350*4882a593Smuzhiyun {
351*4882a593Smuzhiyun struct fm10k_mbx_info *mbx = &hw->mbx;
352*4882a593Smuzhiyun u32 msg[1];
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun /* generate MSI-X request */
355*4882a593Smuzhiyun fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MSIX);
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun /* load onto outgoing mailbox */
358*4882a593Smuzhiyun mbx->ops.enqueue_tx(hw, mbx, msg);
359*4882a593Smuzhiyun }
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun /* This structure defines the attibutes to be parsed below */
362*4882a593Smuzhiyun const struct fm10k_tlv_attr fm10k_lport_state_msg_attr[] = {
363*4882a593Smuzhiyun FM10K_TLV_ATTR_BOOL(FM10K_LPORT_STATE_MSG_DISABLE),
364*4882a593Smuzhiyun FM10K_TLV_ATTR_U8(FM10K_LPORT_STATE_MSG_XCAST_MODE),
365*4882a593Smuzhiyun FM10K_TLV_ATTR_BOOL(FM10K_LPORT_STATE_MSG_READY),
366*4882a593Smuzhiyun FM10K_TLV_ATTR_LAST
367*4882a593Smuzhiyun };
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun /**
370*4882a593Smuzhiyun * fm10k_msg_lport_state_vf - Message handler for lport_state message from PF
371*4882a593Smuzhiyun * @hw: Pointer to hardware structure
372*4882a593Smuzhiyun * @results: pointer array containing parsed data
373*4882a593Smuzhiyun * @mbx: Pointer to mailbox information structure
374*4882a593Smuzhiyun *
375*4882a593Smuzhiyun * This handler is meant to capture the indication from the PF that we
376*4882a593Smuzhiyun * are ready to bring up the interface.
377*4882a593Smuzhiyun **/
fm10k_msg_lport_state_vf(struct fm10k_hw * hw,u32 ** results,struct fm10k_mbx_info __always_unused * mbx)378*4882a593Smuzhiyun s32 fm10k_msg_lport_state_vf(struct fm10k_hw *hw, u32 **results,
379*4882a593Smuzhiyun struct fm10k_mbx_info __always_unused *mbx)
380*4882a593Smuzhiyun {
381*4882a593Smuzhiyun hw->mac.dglort_map = !results[FM10K_LPORT_STATE_MSG_READY] ?
382*4882a593Smuzhiyun FM10K_DGLORTMAP_NONE : FM10K_DGLORTMAP_ZERO;
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun return 0;
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun /**
388*4882a593Smuzhiyun * fm10k_update_lport_state_vf - Update device state in lower device
389*4882a593Smuzhiyun * @hw: pointer to the HW structure
390*4882a593Smuzhiyun * @glort: unused
391*4882a593Smuzhiyun * @count: number of logical ports to enable - unused (always 1)
392*4882a593Smuzhiyun * @enable: boolean value indicating if this is an enable or disable request
393*4882a593Smuzhiyun *
394*4882a593Smuzhiyun * Notify the lower device of a state change. If the lower device is
395*4882a593Smuzhiyun * enabled we can add filters, if it is disabled all filters for this
396*4882a593Smuzhiyun * logical port are flushed.
397*4882a593Smuzhiyun **/
fm10k_update_lport_state_vf(struct fm10k_hw * hw,u16 __always_unused glort,u16 __always_unused count,bool enable)398*4882a593Smuzhiyun static s32 fm10k_update_lport_state_vf(struct fm10k_hw *hw,
399*4882a593Smuzhiyun u16 __always_unused glort,
400*4882a593Smuzhiyun u16 __always_unused count, bool enable)
401*4882a593Smuzhiyun {
402*4882a593Smuzhiyun struct fm10k_mbx_info *mbx = &hw->mbx;
403*4882a593Smuzhiyun u32 msg[2];
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun /* reset glort mask 0 as we have to wait to be enabled */
406*4882a593Smuzhiyun hw->mac.dglort_map = FM10K_DGLORTMAP_NONE;
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun /* generate port state request */
409*4882a593Smuzhiyun fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
410*4882a593Smuzhiyun if (!enable)
411*4882a593Smuzhiyun fm10k_tlv_attr_put_bool(msg, FM10K_LPORT_STATE_MSG_DISABLE);
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun /* load onto outgoing mailbox */
414*4882a593Smuzhiyun return mbx->ops.enqueue_tx(hw, mbx, msg);
415*4882a593Smuzhiyun }
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun /**
418*4882a593Smuzhiyun * fm10k_update_xcast_mode_vf - Request update of multicast mode
419*4882a593Smuzhiyun * @hw: pointer to hardware structure
420*4882a593Smuzhiyun * @glort: unused
421*4882a593Smuzhiyun * @mode: integer value indicating mode being requested
422*4882a593Smuzhiyun *
423*4882a593Smuzhiyun * This function will attempt to request a higher mode for the port
424*4882a593Smuzhiyun * so that it can enable either multicast, multicast promiscuous, or
425*4882a593Smuzhiyun * promiscuous mode of operation.
426*4882a593Smuzhiyun **/
fm10k_update_xcast_mode_vf(struct fm10k_hw * hw,u16 __always_unused glort,u8 mode)427*4882a593Smuzhiyun static s32 fm10k_update_xcast_mode_vf(struct fm10k_hw *hw,
428*4882a593Smuzhiyun u16 __always_unused glort, u8 mode)
429*4882a593Smuzhiyun {
430*4882a593Smuzhiyun struct fm10k_mbx_info *mbx = &hw->mbx;
431*4882a593Smuzhiyun u32 msg[3];
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun if (mode > FM10K_XCAST_MODE_NONE)
434*4882a593Smuzhiyun return FM10K_ERR_PARAM;
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun /* generate message requesting to change xcast mode */
437*4882a593Smuzhiyun fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
438*4882a593Smuzhiyun fm10k_tlv_attr_put_u8(msg, FM10K_LPORT_STATE_MSG_XCAST_MODE, mode);
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun /* load onto outgoing mailbox */
441*4882a593Smuzhiyun return mbx->ops.enqueue_tx(hw, mbx, msg);
442*4882a593Smuzhiyun }
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun /**
445*4882a593Smuzhiyun * fm10k_update_hw_stats_vf - Updates hardware related statistics of VF
446*4882a593Smuzhiyun * @hw: pointer to hardware structure
447*4882a593Smuzhiyun * @stats: pointer to statistics structure
448*4882a593Smuzhiyun *
449*4882a593Smuzhiyun * This function collects and aggregates per queue hardware statistics.
450*4882a593Smuzhiyun **/
fm10k_update_hw_stats_vf(struct fm10k_hw * hw,struct fm10k_hw_stats * stats)451*4882a593Smuzhiyun static void fm10k_update_hw_stats_vf(struct fm10k_hw *hw,
452*4882a593Smuzhiyun struct fm10k_hw_stats *stats)
453*4882a593Smuzhiyun {
454*4882a593Smuzhiyun fm10k_update_hw_stats_q(hw, stats->q, 0, hw->mac.max_queues);
455*4882a593Smuzhiyun }
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun /**
458*4882a593Smuzhiyun * fm10k_rebind_hw_stats_vf - Resets base for hardware statistics of VF
459*4882a593Smuzhiyun * @hw: pointer to hardware structure
460*4882a593Smuzhiyun * @stats: pointer to the stats structure to update
461*4882a593Smuzhiyun *
462*4882a593Smuzhiyun * This function resets the base for queue hardware statistics.
463*4882a593Smuzhiyun **/
fm10k_rebind_hw_stats_vf(struct fm10k_hw * hw,struct fm10k_hw_stats * stats)464*4882a593Smuzhiyun static void fm10k_rebind_hw_stats_vf(struct fm10k_hw *hw,
465*4882a593Smuzhiyun struct fm10k_hw_stats *stats)
466*4882a593Smuzhiyun {
467*4882a593Smuzhiyun /* Unbind Queue Statistics */
468*4882a593Smuzhiyun fm10k_unbind_hw_stats_q(stats->q, 0, hw->mac.max_queues);
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun /* Reinitialize bases for all stats */
471*4882a593Smuzhiyun fm10k_update_hw_stats_vf(hw, stats);
472*4882a593Smuzhiyun }
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun /**
475*4882a593Smuzhiyun * fm10k_configure_dglort_map_vf - Configures GLORT entry and queues
476*4882a593Smuzhiyun * @hw: pointer to hardware structure
477*4882a593Smuzhiyun * @dglort: pointer to dglort configuration structure
478*4882a593Smuzhiyun *
479*4882a593Smuzhiyun * Reads the configuration structure contained in dglort_cfg and uses
480*4882a593Smuzhiyun * that information to then populate a DGLORTMAP/DEC entry and the queues
481*4882a593Smuzhiyun * to which it has been assigned.
482*4882a593Smuzhiyun **/
fm10k_configure_dglort_map_vf(struct fm10k_hw __always_unused * hw,struct fm10k_dglort_cfg * dglort)483*4882a593Smuzhiyun static s32 fm10k_configure_dglort_map_vf(struct fm10k_hw __always_unused *hw,
484*4882a593Smuzhiyun struct fm10k_dglort_cfg *dglort)
485*4882a593Smuzhiyun {
486*4882a593Smuzhiyun /* verify the dglort pointer */
487*4882a593Smuzhiyun if (!dglort)
488*4882a593Smuzhiyun return FM10K_ERR_PARAM;
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun /* stub for now until we determine correct message for this */
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun return 0;
493*4882a593Smuzhiyun }
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun static const struct fm10k_msg_data fm10k_msg_data_vf[] = {
496*4882a593Smuzhiyun FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
497*4882a593Smuzhiyun FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_msg_mac_vlan_vf),
498*4882a593Smuzhiyun FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_msg_lport_state_vf),
499*4882a593Smuzhiyun FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
500*4882a593Smuzhiyun };
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun static const struct fm10k_mac_ops mac_ops_vf = {
503*4882a593Smuzhiyun .get_bus_info = fm10k_get_bus_info_generic,
504*4882a593Smuzhiyun .reset_hw = fm10k_reset_hw_vf,
505*4882a593Smuzhiyun .init_hw = fm10k_init_hw_vf,
506*4882a593Smuzhiyun .start_hw = fm10k_start_hw_generic,
507*4882a593Smuzhiyun .stop_hw = fm10k_stop_hw_vf,
508*4882a593Smuzhiyun .update_vlan = fm10k_update_vlan_vf,
509*4882a593Smuzhiyun .read_mac_addr = fm10k_read_mac_addr_vf,
510*4882a593Smuzhiyun .update_uc_addr = fm10k_update_uc_addr_vf,
511*4882a593Smuzhiyun .update_mc_addr = fm10k_update_mc_addr_vf,
512*4882a593Smuzhiyun .update_xcast_mode = fm10k_update_xcast_mode_vf,
513*4882a593Smuzhiyun .update_int_moderator = fm10k_update_int_moderator_vf,
514*4882a593Smuzhiyun .update_lport_state = fm10k_update_lport_state_vf,
515*4882a593Smuzhiyun .update_hw_stats = fm10k_update_hw_stats_vf,
516*4882a593Smuzhiyun .rebind_hw_stats = fm10k_rebind_hw_stats_vf,
517*4882a593Smuzhiyun .configure_dglort_map = fm10k_configure_dglort_map_vf,
518*4882a593Smuzhiyun .get_host_state = fm10k_get_host_state_generic,
519*4882a593Smuzhiyun };
520*4882a593Smuzhiyun
fm10k_get_invariants_vf(struct fm10k_hw * hw)521*4882a593Smuzhiyun static s32 fm10k_get_invariants_vf(struct fm10k_hw *hw)
522*4882a593Smuzhiyun {
523*4882a593Smuzhiyun fm10k_get_invariants_generic(hw);
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun return fm10k_pfvf_mbx_init(hw, &hw->mbx, fm10k_msg_data_vf, 0);
526*4882a593Smuzhiyun }
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun const struct fm10k_info fm10k_vf_info = {
529*4882a593Smuzhiyun .mac = fm10k_mac_vf,
530*4882a593Smuzhiyun .get_invariants = fm10k_get_invariants_vf,
531*4882a593Smuzhiyun .mac_ops = &mac_ops_vf,
532*4882a593Smuzhiyun };
533