xref: /OK3568_Linux_fs/kernel/drivers/net/ethernet/intel/fm10k/fm10k_pci.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /* Copyright(c) 2013 - 2019 Intel Corporation. */
3*4882a593Smuzhiyun 
4*4882a593Smuzhiyun #include <linux/module.h>
5*4882a593Smuzhiyun #include <linux/interrupt.h>
6*4882a593Smuzhiyun #include <linux/aer.h>
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include "fm10k.h"
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun static const struct fm10k_info *fm10k_info_tbl[] = {
11*4882a593Smuzhiyun 	[fm10k_device_pf] = &fm10k_pf_info,
12*4882a593Smuzhiyun 	[fm10k_device_vf] = &fm10k_vf_info,
13*4882a593Smuzhiyun };
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun /*
16*4882a593Smuzhiyun  * fm10k_pci_tbl - PCI Device ID Table
17*4882a593Smuzhiyun  *
18*4882a593Smuzhiyun  * Wildcard entries (PCI_ANY_ID) should come last
19*4882a593Smuzhiyun  * Last entry must be all 0s
20*4882a593Smuzhiyun  *
21*4882a593Smuzhiyun  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
22*4882a593Smuzhiyun  *   Class, Class Mask, private data (not used) }
23*4882a593Smuzhiyun  */
24*4882a593Smuzhiyun static const struct pci_device_id fm10k_pci_tbl[] = {
25*4882a593Smuzhiyun 	{ PCI_VDEVICE(INTEL, FM10K_DEV_ID_PF), fm10k_device_pf },
26*4882a593Smuzhiyun 	{ PCI_VDEVICE(INTEL, FM10K_DEV_ID_SDI_FM10420_QDA2), fm10k_device_pf },
27*4882a593Smuzhiyun 	{ PCI_VDEVICE(INTEL, FM10K_DEV_ID_SDI_FM10420_DA2), fm10k_device_pf },
28*4882a593Smuzhiyun 	{ PCI_VDEVICE(INTEL, FM10K_DEV_ID_VF), fm10k_device_vf },
29*4882a593Smuzhiyun 	/* required last entry */
30*4882a593Smuzhiyun 	{ 0, }
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, fm10k_pci_tbl);
33*4882a593Smuzhiyun 
fm10k_read_pci_cfg_word(struct fm10k_hw * hw,u32 reg)34*4882a593Smuzhiyun u16 fm10k_read_pci_cfg_word(struct fm10k_hw *hw, u32 reg)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun 	struct fm10k_intfc *interface = hw->back;
37*4882a593Smuzhiyun 	u16 value = 0;
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun 	if (FM10K_REMOVED(hw->hw_addr))
40*4882a593Smuzhiyun 		return ~value;
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun 	pci_read_config_word(interface->pdev, reg, &value);
43*4882a593Smuzhiyun 	if (value == 0xFFFF)
44*4882a593Smuzhiyun 		fm10k_write_flush(hw);
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	return value;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun 
fm10k_read_reg(struct fm10k_hw * hw,int reg)49*4882a593Smuzhiyun u32 fm10k_read_reg(struct fm10k_hw *hw, int reg)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun 	u32 __iomem *hw_addr = READ_ONCE(hw->hw_addr);
52*4882a593Smuzhiyun 	u32 value = 0;
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 	if (FM10K_REMOVED(hw_addr))
55*4882a593Smuzhiyun 		return ~value;
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	value = readl(&hw_addr[reg]);
58*4882a593Smuzhiyun 	if (!(~value) && (!reg || !(~readl(hw_addr)))) {
59*4882a593Smuzhiyun 		struct fm10k_intfc *interface = hw->back;
60*4882a593Smuzhiyun 		struct net_device *netdev = interface->netdev;
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 		hw->hw_addr = NULL;
63*4882a593Smuzhiyun 		netif_device_detach(netdev);
64*4882a593Smuzhiyun 		netdev_err(netdev, "PCIe link lost, device now detached\n");
65*4882a593Smuzhiyun 	}
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	return value;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun 
fm10k_hw_ready(struct fm10k_intfc * interface)70*4882a593Smuzhiyun static int fm10k_hw_ready(struct fm10k_intfc *interface)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun 	struct fm10k_hw *hw = &interface->hw;
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	fm10k_write_flush(hw);
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	return FM10K_REMOVED(hw->hw_addr) ? -ENODEV : 0;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun /**
80*4882a593Smuzhiyun  * fm10k_macvlan_schedule - Schedule MAC/VLAN queue task
81*4882a593Smuzhiyun  * @interface: fm10k private interface structure
82*4882a593Smuzhiyun  *
83*4882a593Smuzhiyun  * Schedule the MAC/VLAN queue monitor task. If the MAC/VLAN task cannot be
84*4882a593Smuzhiyun  * started immediately, request that it be restarted when possible.
85*4882a593Smuzhiyun  */
fm10k_macvlan_schedule(struct fm10k_intfc * interface)86*4882a593Smuzhiyun void fm10k_macvlan_schedule(struct fm10k_intfc *interface)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun 	/* Avoid processing the MAC/VLAN queue when the service task is
89*4882a593Smuzhiyun 	 * disabled, or when we're resetting the device.
90*4882a593Smuzhiyun 	 */
91*4882a593Smuzhiyun 	if (!test_bit(__FM10K_MACVLAN_DISABLE, interface->state) &&
92*4882a593Smuzhiyun 	    !test_and_set_bit(__FM10K_MACVLAN_SCHED, interface->state)) {
93*4882a593Smuzhiyun 		clear_bit(__FM10K_MACVLAN_REQUEST, interface->state);
94*4882a593Smuzhiyun 		/* We delay the actual start of execution in order to allow
95*4882a593Smuzhiyun 		 * multiple MAC/VLAN updates to accumulate before handling
96*4882a593Smuzhiyun 		 * them, and to allow some time to let the mailbox drain
97*4882a593Smuzhiyun 		 * between runs.
98*4882a593Smuzhiyun 		 */
99*4882a593Smuzhiyun 		queue_delayed_work(fm10k_workqueue,
100*4882a593Smuzhiyun 				   &interface->macvlan_task, 10);
101*4882a593Smuzhiyun 	} else {
102*4882a593Smuzhiyun 		set_bit(__FM10K_MACVLAN_REQUEST, interface->state);
103*4882a593Smuzhiyun 	}
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun /**
107*4882a593Smuzhiyun  * fm10k_stop_macvlan_task - Stop the MAC/VLAN queue monitor
108*4882a593Smuzhiyun  * @interface: fm10k private interface structure
109*4882a593Smuzhiyun  *
110*4882a593Smuzhiyun  * Wait until the MAC/VLAN queue task has stopped, and cancel any future
111*4882a593Smuzhiyun  * requests.
112*4882a593Smuzhiyun  */
fm10k_stop_macvlan_task(struct fm10k_intfc * interface)113*4882a593Smuzhiyun static void fm10k_stop_macvlan_task(struct fm10k_intfc *interface)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun 	/* Disable the MAC/VLAN work item */
116*4882a593Smuzhiyun 	set_bit(__FM10K_MACVLAN_DISABLE, interface->state);
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	/* Make sure we waited until any current invocations have stopped */
119*4882a593Smuzhiyun 	cancel_delayed_work_sync(&interface->macvlan_task);
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	/* We set the __FM10K_MACVLAN_SCHED bit when we schedule the task.
122*4882a593Smuzhiyun 	 * However, it may not be unset of the MAC/VLAN task never actually
123*4882a593Smuzhiyun 	 * got a chance to run. Since we've canceled the task here, and it
124*4882a593Smuzhiyun 	 * cannot be rescheuled right now, we need to ensure the scheduled bit
125*4882a593Smuzhiyun 	 * gets unset.
126*4882a593Smuzhiyun 	 */
127*4882a593Smuzhiyun 	clear_bit(__FM10K_MACVLAN_SCHED, interface->state);
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun /**
131*4882a593Smuzhiyun  * fm10k_resume_macvlan_task - Restart the MAC/VLAN queue monitor
132*4882a593Smuzhiyun  * @interface: fm10k private interface structure
133*4882a593Smuzhiyun  *
134*4882a593Smuzhiyun  * Clear the __FM10K_MACVLAN_DISABLE bit and, if a request occurred, schedule
135*4882a593Smuzhiyun  * the MAC/VLAN work monitor.
136*4882a593Smuzhiyun  */
fm10k_resume_macvlan_task(struct fm10k_intfc * interface)137*4882a593Smuzhiyun static void fm10k_resume_macvlan_task(struct fm10k_intfc *interface)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun 	/* Re-enable the MAC/VLAN work item */
140*4882a593Smuzhiyun 	clear_bit(__FM10K_MACVLAN_DISABLE, interface->state);
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	/* We might have received a MAC/VLAN request while disabled. If so,
143*4882a593Smuzhiyun 	 * kick off the queue now.
144*4882a593Smuzhiyun 	 */
145*4882a593Smuzhiyun 	if (test_bit(__FM10K_MACVLAN_REQUEST, interface->state))
146*4882a593Smuzhiyun 		fm10k_macvlan_schedule(interface);
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun 
fm10k_service_event_schedule(struct fm10k_intfc * interface)149*4882a593Smuzhiyun void fm10k_service_event_schedule(struct fm10k_intfc *interface)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun 	if (!test_bit(__FM10K_SERVICE_DISABLE, interface->state) &&
152*4882a593Smuzhiyun 	    !test_and_set_bit(__FM10K_SERVICE_SCHED, interface->state)) {
153*4882a593Smuzhiyun 		clear_bit(__FM10K_SERVICE_REQUEST, interface->state);
154*4882a593Smuzhiyun 		queue_work(fm10k_workqueue, &interface->service_task);
155*4882a593Smuzhiyun 	} else {
156*4882a593Smuzhiyun 		set_bit(__FM10K_SERVICE_REQUEST, interface->state);
157*4882a593Smuzhiyun 	}
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun 
fm10k_service_event_complete(struct fm10k_intfc * interface)160*4882a593Smuzhiyun static void fm10k_service_event_complete(struct fm10k_intfc *interface)
161*4882a593Smuzhiyun {
162*4882a593Smuzhiyun 	WARN_ON(!test_bit(__FM10K_SERVICE_SCHED, interface->state));
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	/* flush memory to make sure state is correct before next watchog */
165*4882a593Smuzhiyun 	smp_mb__before_atomic();
166*4882a593Smuzhiyun 	clear_bit(__FM10K_SERVICE_SCHED, interface->state);
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	/* If a service event was requested since we started, immediately
169*4882a593Smuzhiyun 	 * re-schedule now. This ensures we don't drop a request until the
170*4882a593Smuzhiyun 	 * next timer event.
171*4882a593Smuzhiyun 	 */
172*4882a593Smuzhiyun 	if (test_bit(__FM10K_SERVICE_REQUEST, interface->state))
173*4882a593Smuzhiyun 		fm10k_service_event_schedule(interface);
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun 
fm10k_stop_service_event(struct fm10k_intfc * interface)176*4882a593Smuzhiyun static void fm10k_stop_service_event(struct fm10k_intfc *interface)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun 	set_bit(__FM10K_SERVICE_DISABLE, interface->state);
179*4882a593Smuzhiyun 	cancel_work_sync(&interface->service_task);
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	/* It's possible that cancel_work_sync stopped the service task from
182*4882a593Smuzhiyun 	 * running before it could actually start. In this case the
183*4882a593Smuzhiyun 	 * __FM10K_SERVICE_SCHED bit will never be cleared. Since we know that
184*4882a593Smuzhiyun 	 * the service task cannot be running at this point, we need to clear
185*4882a593Smuzhiyun 	 * the scheduled bit, as otherwise the service task may never be
186*4882a593Smuzhiyun 	 * restarted.
187*4882a593Smuzhiyun 	 */
188*4882a593Smuzhiyun 	clear_bit(__FM10K_SERVICE_SCHED, interface->state);
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun 
fm10k_start_service_event(struct fm10k_intfc * interface)191*4882a593Smuzhiyun static void fm10k_start_service_event(struct fm10k_intfc *interface)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun 	clear_bit(__FM10K_SERVICE_DISABLE, interface->state);
194*4882a593Smuzhiyun 	fm10k_service_event_schedule(interface);
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun /**
198*4882a593Smuzhiyun  * fm10k_service_timer - Timer Call-back
199*4882a593Smuzhiyun  * @t: pointer to timer data
200*4882a593Smuzhiyun  **/
fm10k_service_timer(struct timer_list * t)201*4882a593Smuzhiyun static void fm10k_service_timer(struct timer_list *t)
202*4882a593Smuzhiyun {
203*4882a593Smuzhiyun 	struct fm10k_intfc *interface = from_timer(interface, t,
204*4882a593Smuzhiyun 						   service_timer);
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 	/* Reset the timer */
207*4882a593Smuzhiyun 	mod_timer(&interface->service_timer, (HZ * 2) + jiffies);
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	fm10k_service_event_schedule(interface);
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun /**
213*4882a593Smuzhiyun  * fm10k_prepare_for_reset - Prepare the driver and device for a pending reset
214*4882a593Smuzhiyun  * @interface: fm10k private data structure
215*4882a593Smuzhiyun  *
216*4882a593Smuzhiyun  * This function prepares for a device reset by shutting as much down as we
217*4882a593Smuzhiyun  * can. It does nothing and returns false if __FM10K_RESETTING was already set
218*4882a593Smuzhiyun  * prior to calling this function. It returns true if it actually did work.
219*4882a593Smuzhiyun  */
fm10k_prepare_for_reset(struct fm10k_intfc * interface)220*4882a593Smuzhiyun static bool fm10k_prepare_for_reset(struct fm10k_intfc *interface)
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun 	struct net_device *netdev = interface->netdev;
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	/* put off any impending NetWatchDogTimeout */
225*4882a593Smuzhiyun 	netif_trans_update(netdev);
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 	/* Nothing to do if a reset is already in progress */
228*4882a593Smuzhiyun 	if (test_and_set_bit(__FM10K_RESETTING, interface->state))
229*4882a593Smuzhiyun 		return false;
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 	/* As the MAC/VLAN task will be accessing registers it must not be
232*4882a593Smuzhiyun 	 * running while we reset. Although the task will not be scheduled
233*4882a593Smuzhiyun 	 * once we start resetting it may already be running
234*4882a593Smuzhiyun 	 */
235*4882a593Smuzhiyun 	fm10k_stop_macvlan_task(interface);
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	rtnl_lock();
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 	fm10k_iov_suspend(interface->pdev);
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 	if (netif_running(netdev))
242*4882a593Smuzhiyun 		fm10k_close(netdev);
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	fm10k_mbx_free_irq(interface);
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	/* free interrupts */
247*4882a593Smuzhiyun 	fm10k_clear_queueing_scheme(interface);
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun 	/* delay any future reset requests */
250*4882a593Smuzhiyun 	interface->last_reset = jiffies + (10 * HZ);
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	rtnl_unlock();
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	return true;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun 
fm10k_handle_reset(struct fm10k_intfc * interface)257*4882a593Smuzhiyun static int fm10k_handle_reset(struct fm10k_intfc *interface)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun 	struct net_device *netdev = interface->netdev;
260*4882a593Smuzhiyun 	struct fm10k_hw *hw = &interface->hw;
261*4882a593Smuzhiyun 	int err;
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	WARN_ON(!test_bit(__FM10K_RESETTING, interface->state));
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	rtnl_lock();
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 	pci_set_master(interface->pdev);
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	/* reset and initialize the hardware so it is in a known state */
270*4882a593Smuzhiyun 	err = hw->mac.ops.reset_hw(hw);
271*4882a593Smuzhiyun 	if (err) {
272*4882a593Smuzhiyun 		dev_err(&interface->pdev->dev, "reset_hw failed: %d\n", err);
273*4882a593Smuzhiyun 		goto reinit_err;
274*4882a593Smuzhiyun 	}
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 	err = hw->mac.ops.init_hw(hw);
277*4882a593Smuzhiyun 	if (err) {
278*4882a593Smuzhiyun 		dev_err(&interface->pdev->dev, "init_hw failed: %d\n", err);
279*4882a593Smuzhiyun 		goto reinit_err;
280*4882a593Smuzhiyun 	}
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun 	err = fm10k_init_queueing_scheme(interface);
283*4882a593Smuzhiyun 	if (err) {
284*4882a593Smuzhiyun 		dev_err(&interface->pdev->dev,
285*4882a593Smuzhiyun 			"init_queueing_scheme failed: %d\n", err);
286*4882a593Smuzhiyun 		goto reinit_err;
287*4882a593Smuzhiyun 	}
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun 	/* re-associate interrupts */
290*4882a593Smuzhiyun 	err = fm10k_mbx_request_irq(interface);
291*4882a593Smuzhiyun 	if (err)
292*4882a593Smuzhiyun 		goto err_mbx_irq;
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun 	err = fm10k_hw_ready(interface);
295*4882a593Smuzhiyun 	if (err)
296*4882a593Smuzhiyun 		goto err_open;
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 	/* update hardware address for VFs if perm_addr has changed */
299*4882a593Smuzhiyun 	if (hw->mac.type == fm10k_mac_vf) {
300*4882a593Smuzhiyun 		if (is_valid_ether_addr(hw->mac.perm_addr)) {
301*4882a593Smuzhiyun 			ether_addr_copy(hw->mac.addr, hw->mac.perm_addr);
302*4882a593Smuzhiyun 			ether_addr_copy(netdev->perm_addr, hw->mac.perm_addr);
303*4882a593Smuzhiyun 			ether_addr_copy(netdev->dev_addr, hw->mac.perm_addr);
304*4882a593Smuzhiyun 			netdev->addr_assign_type &= ~NET_ADDR_RANDOM;
305*4882a593Smuzhiyun 		}
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 		if (hw->mac.vlan_override)
308*4882a593Smuzhiyun 			netdev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
309*4882a593Smuzhiyun 		else
310*4882a593Smuzhiyun 			netdev->features |= NETIF_F_HW_VLAN_CTAG_RX;
311*4882a593Smuzhiyun 	}
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 	err = netif_running(netdev) ? fm10k_open(netdev) : 0;
314*4882a593Smuzhiyun 	if (err)
315*4882a593Smuzhiyun 		goto err_open;
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun 	fm10k_iov_resume(interface->pdev);
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun 	rtnl_unlock();
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 	fm10k_resume_macvlan_task(interface);
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun 	clear_bit(__FM10K_RESETTING, interface->state);
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 	return err;
326*4882a593Smuzhiyun err_open:
327*4882a593Smuzhiyun 	fm10k_mbx_free_irq(interface);
328*4882a593Smuzhiyun err_mbx_irq:
329*4882a593Smuzhiyun 	fm10k_clear_queueing_scheme(interface);
330*4882a593Smuzhiyun reinit_err:
331*4882a593Smuzhiyun 	netif_device_detach(netdev);
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun 	rtnl_unlock();
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun 	clear_bit(__FM10K_RESETTING, interface->state);
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun 	return err;
338*4882a593Smuzhiyun }
339*4882a593Smuzhiyun 
fm10k_detach_subtask(struct fm10k_intfc * interface)340*4882a593Smuzhiyun static void fm10k_detach_subtask(struct fm10k_intfc *interface)
341*4882a593Smuzhiyun {
342*4882a593Smuzhiyun 	struct net_device *netdev = interface->netdev;
343*4882a593Smuzhiyun 	u32 __iomem *hw_addr;
344*4882a593Smuzhiyun 	u32 value;
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun 	/* do nothing if netdev is still present or hw_addr is set */
347*4882a593Smuzhiyun 	if (netif_device_present(netdev) || interface->hw.hw_addr)
348*4882a593Smuzhiyun 		return;
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun 	/* We've lost the PCIe register space, and can no longer access the
351*4882a593Smuzhiyun 	 * device. Shut everything except the detach subtask down and prepare
352*4882a593Smuzhiyun 	 * to reset the device in case we recover. If we actually prepare for
353*4882a593Smuzhiyun 	 * reset, indicate that we're detached.
354*4882a593Smuzhiyun 	 */
355*4882a593Smuzhiyun 	if (fm10k_prepare_for_reset(interface))
356*4882a593Smuzhiyun 		set_bit(__FM10K_RESET_DETACHED, interface->state);
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun 	/* check the real address space to see if we've recovered */
359*4882a593Smuzhiyun 	hw_addr = READ_ONCE(interface->uc_addr);
360*4882a593Smuzhiyun 	value = readl(hw_addr);
361*4882a593Smuzhiyun 	if (~value) {
362*4882a593Smuzhiyun 		int err;
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun 		/* Make sure the reset was initiated because we detached,
365*4882a593Smuzhiyun 		 * otherwise we might race with a different reset flow.
366*4882a593Smuzhiyun 		 */
367*4882a593Smuzhiyun 		if (!test_and_clear_bit(__FM10K_RESET_DETACHED,
368*4882a593Smuzhiyun 					interface->state))
369*4882a593Smuzhiyun 			return;
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun 		/* Restore the hardware address */
372*4882a593Smuzhiyun 		interface->hw.hw_addr = interface->uc_addr;
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun 		/* PCIe link has been restored, and the device is active
375*4882a593Smuzhiyun 		 * again. Restore everything and reset the device.
376*4882a593Smuzhiyun 		 */
377*4882a593Smuzhiyun 		err = fm10k_handle_reset(interface);
378*4882a593Smuzhiyun 		if (err) {
379*4882a593Smuzhiyun 			netdev_err(netdev, "Unable to reset device: %d\n", err);
380*4882a593Smuzhiyun 			interface->hw.hw_addr = NULL;
381*4882a593Smuzhiyun 			return;
382*4882a593Smuzhiyun 		}
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 		/* Re-attach the netdev */
385*4882a593Smuzhiyun 		netif_device_attach(netdev);
386*4882a593Smuzhiyun 		netdev_warn(netdev, "PCIe link restored, device now attached\n");
387*4882a593Smuzhiyun 		return;
388*4882a593Smuzhiyun 	}
389*4882a593Smuzhiyun }
390*4882a593Smuzhiyun 
fm10k_reset_subtask(struct fm10k_intfc * interface)391*4882a593Smuzhiyun static void fm10k_reset_subtask(struct fm10k_intfc *interface)
392*4882a593Smuzhiyun {
393*4882a593Smuzhiyun 	int err;
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun 	if (!test_and_clear_bit(FM10K_FLAG_RESET_REQUESTED,
396*4882a593Smuzhiyun 				interface->flags))
397*4882a593Smuzhiyun 		return;
398*4882a593Smuzhiyun 
399*4882a593Smuzhiyun 	/* If another thread has already prepared to reset the device, we
400*4882a593Smuzhiyun 	 * should not attempt to handle a reset here, since we'd race with
401*4882a593Smuzhiyun 	 * that thread. This may happen if we suspend the device or if the
402*4882a593Smuzhiyun 	 * PCIe link is lost. In this case, we'll just ignore the RESET
403*4882a593Smuzhiyun 	 * request, as it will (eventually) be taken care of when the thread
404*4882a593Smuzhiyun 	 * which actually started the reset is finished.
405*4882a593Smuzhiyun 	 */
406*4882a593Smuzhiyun 	if (!fm10k_prepare_for_reset(interface))
407*4882a593Smuzhiyun 		return;
408*4882a593Smuzhiyun 
409*4882a593Smuzhiyun 	netdev_err(interface->netdev, "Reset interface\n");
410*4882a593Smuzhiyun 
411*4882a593Smuzhiyun 	err = fm10k_handle_reset(interface);
412*4882a593Smuzhiyun 	if (err)
413*4882a593Smuzhiyun 		dev_err(&interface->pdev->dev,
414*4882a593Smuzhiyun 			"fm10k_handle_reset failed: %d\n", err);
415*4882a593Smuzhiyun }
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun /**
418*4882a593Smuzhiyun  * fm10k_configure_swpri_map - Configure Receive SWPRI to PC mapping
419*4882a593Smuzhiyun  * @interface: board private structure
420*4882a593Smuzhiyun  *
421*4882a593Smuzhiyun  * Configure the SWPRI to PC mapping for the port.
422*4882a593Smuzhiyun  **/
fm10k_configure_swpri_map(struct fm10k_intfc * interface)423*4882a593Smuzhiyun static void fm10k_configure_swpri_map(struct fm10k_intfc *interface)
424*4882a593Smuzhiyun {
425*4882a593Smuzhiyun 	struct net_device *netdev = interface->netdev;
426*4882a593Smuzhiyun 	struct fm10k_hw *hw = &interface->hw;
427*4882a593Smuzhiyun 	int i;
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun 	/* clear flag indicating update is needed */
430*4882a593Smuzhiyun 	clear_bit(FM10K_FLAG_SWPRI_CONFIG, interface->flags);
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun 	/* these registers are only available on the PF */
433*4882a593Smuzhiyun 	if (hw->mac.type != fm10k_mac_pf)
434*4882a593Smuzhiyun 		return;
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun 	/* configure SWPRI to PC map */
437*4882a593Smuzhiyun 	for (i = 0; i < FM10K_SWPRI_MAX; i++)
438*4882a593Smuzhiyun 		fm10k_write_reg(hw, FM10K_SWPRI_MAP(i),
439*4882a593Smuzhiyun 				netdev_get_prio_tc_map(netdev, i));
440*4882a593Smuzhiyun }
441*4882a593Smuzhiyun 
442*4882a593Smuzhiyun /**
443*4882a593Smuzhiyun  * fm10k_watchdog_update_host_state - Update the link status based on host.
444*4882a593Smuzhiyun  * @interface: board private structure
445*4882a593Smuzhiyun  **/
fm10k_watchdog_update_host_state(struct fm10k_intfc * interface)446*4882a593Smuzhiyun static void fm10k_watchdog_update_host_state(struct fm10k_intfc *interface)
447*4882a593Smuzhiyun {
448*4882a593Smuzhiyun 	struct fm10k_hw *hw = &interface->hw;
449*4882a593Smuzhiyun 	s32 err;
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun 	if (test_bit(__FM10K_LINK_DOWN, interface->state)) {
452*4882a593Smuzhiyun 		interface->host_ready = false;
453*4882a593Smuzhiyun 		if (time_is_after_jiffies(interface->link_down_event))
454*4882a593Smuzhiyun 			return;
455*4882a593Smuzhiyun 		clear_bit(__FM10K_LINK_DOWN, interface->state);
456*4882a593Smuzhiyun 	}
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun 	if (test_bit(FM10K_FLAG_SWPRI_CONFIG, interface->flags)) {
459*4882a593Smuzhiyun 		if (rtnl_trylock()) {
460*4882a593Smuzhiyun 			fm10k_configure_swpri_map(interface);
461*4882a593Smuzhiyun 			rtnl_unlock();
462*4882a593Smuzhiyun 		}
463*4882a593Smuzhiyun 	}
464*4882a593Smuzhiyun 
465*4882a593Smuzhiyun 	/* lock the mailbox for transmit and receive */
466*4882a593Smuzhiyun 	fm10k_mbx_lock(interface);
467*4882a593Smuzhiyun 
468*4882a593Smuzhiyun 	err = hw->mac.ops.get_host_state(hw, &interface->host_ready);
469*4882a593Smuzhiyun 	if (err && time_is_before_jiffies(interface->last_reset))
470*4882a593Smuzhiyun 		set_bit(FM10K_FLAG_RESET_REQUESTED, interface->flags);
471*4882a593Smuzhiyun 
472*4882a593Smuzhiyun 	/* free the lock */
473*4882a593Smuzhiyun 	fm10k_mbx_unlock(interface);
474*4882a593Smuzhiyun }
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun /**
477*4882a593Smuzhiyun  * fm10k_mbx_subtask - Process upstream and downstream mailboxes
478*4882a593Smuzhiyun  * @interface: board private structure
479*4882a593Smuzhiyun  *
480*4882a593Smuzhiyun  * This function will process both the upstream and downstream mailboxes.
481*4882a593Smuzhiyun  **/
fm10k_mbx_subtask(struct fm10k_intfc * interface)482*4882a593Smuzhiyun static void fm10k_mbx_subtask(struct fm10k_intfc *interface)
483*4882a593Smuzhiyun {
484*4882a593Smuzhiyun 	/* If we're resetting, bail out */
485*4882a593Smuzhiyun 	if (test_bit(__FM10K_RESETTING, interface->state))
486*4882a593Smuzhiyun 		return;
487*4882a593Smuzhiyun 
488*4882a593Smuzhiyun 	/* process upstream mailbox and update device state */
489*4882a593Smuzhiyun 	fm10k_watchdog_update_host_state(interface);
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun 	/* process downstream mailboxes */
492*4882a593Smuzhiyun 	fm10k_iov_mbx(interface);
493*4882a593Smuzhiyun }
494*4882a593Smuzhiyun 
495*4882a593Smuzhiyun /**
496*4882a593Smuzhiyun  * fm10k_watchdog_host_is_ready - Update netdev status based on host ready
497*4882a593Smuzhiyun  * @interface: board private structure
498*4882a593Smuzhiyun  **/
fm10k_watchdog_host_is_ready(struct fm10k_intfc * interface)499*4882a593Smuzhiyun static void fm10k_watchdog_host_is_ready(struct fm10k_intfc *interface)
500*4882a593Smuzhiyun {
501*4882a593Smuzhiyun 	struct net_device *netdev = interface->netdev;
502*4882a593Smuzhiyun 
503*4882a593Smuzhiyun 	/* only continue if link state is currently down */
504*4882a593Smuzhiyun 	if (netif_carrier_ok(netdev))
505*4882a593Smuzhiyun 		return;
506*4882a593Smuzhiyun 
507*4882a593Smuzhiyun 	netif_info(interface, drv, netdev, "NIC Link is up\n");
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun 	netif_carrier_on(netdev);
510*4882a593Smuzhiyun 	netif_tx_wake_all_queues(netdev);
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun 
513*4882a593Smuzhiyun /**
514*4882a593Smuzhiyun  * fm10k_watchdog_host_not_ready - Update netdev status based on host not ready
515*4882a593Smuzhiyun  * @interface: board private structure
516*4882a593Smuzhiyun  **/
fm10k_watchdog_host_not_ready(struct fm10k_intfc * interface)517*4882a593Smuzhiyun static void fm10k_watchdog_host_not_ready(struct fm10k_intfc *interface)
518*4882a593Smuzhiyun {
519*4882a593Smuzhiyun 	struct net_device *netdev = interface->netdev;
520*4882a593Smuzhiyun 
521*4882a593Smuzhiyun 	/* only continue if link state is currently up */
522*4882a593Smuzhiyun 	if (!netif_carrier_ok(netdev))
523*4882a593Smuzhiyun 		return;
524*4882a593Smuzhiyun 
525*4882a593Smuzhiyun 	netif_info(interface, drv, netdev, "NIC Link is down\n");
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun 	netif_carrier_off(netdev);
528*4882a593Smuzhiyun 	netif_tx_stop_all_queues(netdev);
529*4882a593Smuzhiyun }
530*4882a593Smuzhiyun 
531*4882a593Smuzhiyun /**
532*4882a593Smuzhiyun  * fm10k_update_stats - Update the board statistics counters.
533*4882a593Smuzhiyun  * @interface: board private structure
534*4882a593Smuzhiyun  **/
fm10k_update_stats(struct fm10k_intfc * interface)535*4882a593Smuzhiyun void fm10k_update_stats(struct fm10k_intfc *interface)
536*4882a593Smuzhiyun {
537*4882a593Smuzhiyun 	struct net_device_stats *net_stats = &interface->netdev->stats;
538*4882a593Smuzhiyun 	struct fm10k_hw *hw = &interface->hw;
539*4882a593Smuzhiyun 	u64 hw_csum_tx_good = 0, hw_csum_rx_good = 0, rx_length_errors = 0;
540*4882a593Smuzhiyun 	u64 rx_switch_errors = 0, rx_drops = 0, rx_pp_errors = 0;
541*4882a593Smuzhiyun 	u64 rx_link_errors = 0;
542*4882a593Smuzhiyun 	u64 rx_errors = 0, rx_csum_errors = 0, tx_csum_errors = 0;
543*4882a593Smuzhiyun 	u64 restart_queue = 0, tx_busy = 0, alloc_failed = 0;
544*4882a593Smuzhiyun 	u64 rx_bytes_nic = 0, rx_pkts_nic = 0, rx_drops_nic = 0;
545*4882a593Smuzhiyun 	u64 tx_bytes_nic = 0, tx_pkts_nic = 0;
546*4882a593Smuzhiyun 	u64 bytes, pkts;
547*4882a593Smuzhiyun 	int i;
548*4882a593Smuzhiyun 
549*4882a593Smuzhiyun 	/* ensure only one thread updates stats at a time */
550*4882a593Smuzhiyun 	if (test_and_set_bit(__FM10K_UPDATING_STATS, interface->state))
551*4882a593Smuzhiyun 		return;
552*4882a593Smuzhiyun 
553*4882a593Smuzhiyun 	/* do not allow stats update via service task for next second */
554*4882a593Smuzhiyun 	interface->next_stats_update = jiffies + HZ;
555*4882a593Smuzhiyun 
556*4882a593Smuzhiyun 	/* gather some stats to the interface struct that are per queue */
557*4882a593Smuzhiyun 	for (bytes = 0, pkts = 0, i = 0; i < interface->num_tx_queues; i++) {
558*4882a593Smuzhiyun 		struct fm10k_ring *tx_ring = READ_ONCE(interface->tx_ring[i]);
559*4882a593Smuzhiyun 
560*4882a593Smuzhiyun 		if (!tx_ring)
561*4882a593Smuzhiyun 			continue;
562*4882a593Smuzhiyun 
563*4882a593Smuzhiyun 		restart_queue += tx_ring->tx_stats.restart_queue;
564*4882a593Smuzhiyun 		tx_busy += tx_ring->tx_stats.tx_busy;
565*4882a593Smuzhiyun 		tx_csum_errors += tx_ring->tx_stats.csum_err;
566*4882a593Smuzhiyun 		bytes += tx_ring->stats.bytes;
567*4882a593Smuzhiyun 		pkts += tx_ring->stats.packets;
568*4882a593Smuzhiyun 		hw_csum_tx_good += tx_ring->tx_stats.csum_good;
569*4882a593Smuzhiyun 	}
570*4882a593Smuzhiyun 
571*4882a593Smuzhiyun 	interface->restart_queue = restart_queue;
572*4882a593Smuzhiyun 	interface->tx_busy = tx_busy;
573*4882a593Smuzhiyun 	net_stats->tx_bytes = bytes;
574*4882a593Smuzhiyun 	net_stats->tx_packets = pkts;
575*4882a593Smuzhiyun 	interface->tx_csum_errors = tx_csum_errors;
576*4882a593Smuzhiyun 	interface->hw_csum_tx_good = hw_csum_tx_good;
577*4882a593Smuzhiyun 
578*4882a593Smuzhiyun 	/* gather some stats to the interface struct that are per queue */
579*4882a593Smuzhiyun 	for (bytes = 0, pkts = 0, i = 0; i < interface->num_rx_queues; i++) {
580*4882a593Smuzhiyun 		struct fm10k_ring *rx_ring = READ_ONCE(interface->rx_ring[i]);
581*4882a593Smuzhiyun 
582*4882a593Smuzhiyun 		if (!rx_ring)
583*4882a593Smuzhiyun 			continue;
584*4882a593Smuzhiyun 
585*4882a593Smuzhiyun 		bytes += rx_ring->stats.bytes;
586*4882a593Smuzhiyun 		pkts += rx_ring->stats.packets;
587*4882a593Smuzhiyun 		alloc_failed += rx_ring->rx_stats.alloc_failed;
588*4882a593Smuzhiyun 		rx_csum_errors += rx_ring->rx_stats.csum_err;
589*4882a593Smuzhiyun 		rx_errors += rx_ring->rx_stats.errors;
590*4882a593Smuzhiyun 		hw_csum_rx_good += rx_ring->rx_stats.csum_good;
591*4882a593Smuzhiyun 		rx_switch_errors += rx_ring->rx_stats.switch_errors;
592*4882a593Smuzhiyun 		rx_drops += rx_ring->rx_stats.drops;
593*4882a593Smuzhiyun 		rx_pp_errors += rx_ring->rx_stats.pp_errors;
594*4882a593Smuzhiyun 		rx_link_errors += rx_ring->rx_stats.link_errors;
595*4882a593Smuzhiyun 		rx_length_errors += rx_ring->rx_stats.length_errors;
596*4882a593Smuzhiyun 	}
597*4882a593Smuzhiyun 
598*4882a593Smuzhiyun 	net_stats->rx_bytes = bytes;
599*4882a593Smuzhiyun 	net_stats->rx_packets = pkts;
600*4882a593Smuzhiyun 	interface->alloc_failed = alloc_failed;
601*4882a593Smuzhiyun 	interface->rx_csum_errors = rx_csum_errors;
602*4882a593Smuzhiyun 	interface->hw_csum_rx_good = hw_csum_rx_good;
603*4882a593Smuzhiyun 	interface->rx_switch_errors = rx_switch_errors;
604*4882a593Smuzhiyun 	interface->rx_drops = rx_drops;
605*4882a593Smuzhiyun 	interface->rx_pp_errors = rx_pp_errors;
606*4882a593Smuzhiyun 	interface->rx_link_errors = rx_link_errors;
607*4882a593Smuzhiyun 	interface->rx_length_errors = rx_length_errors;
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun 	hw->mac.ops.update_hw_stats(hw, &interface->stats);
610*4882a593Smuzhiyun 
611*4882a593Smuzhiyun 	for (i = 0; i < hw->mac.max_queues; i++) {
612*4882a593Smuzhiyun 		struct fm10k_hw_stats_q *q = &interface->stats.q[i];
613*4882a593Smuzhiyun 
614*4882a593Smuzhiyun 		tx_bytes_nic += q->tx_bytes.count;
615*4882a593Smuzhiyun 		tx_pkts_nic += q->tx_packets.count;
616*4882a593Smuzhiyun 		rx_bytes_nic += q->rx_bytes.count;
617*4882a593Smuzhiyun 		rx_pkts_nic += q->rx_packets.count;
618*4882a593Smuzhiyun 		rx_drops_nic += q->rx_drops.count;
619*4882a593Smuzhiyun 	}
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun 	interface->tx_bytes_nic = tx_bytes_nic;
622*4882a593Smuzhiyun 	interface->tx_packets_nic = tx_pkts_nic;
623*4882a593Smuzhiyun 	interface->rx_bytes_nic = rx_bytes_nic;
624*4882a593Smuzhiyun 	interface->rx_packets_nic = rx_pkts_nic;
625*4882a593Smuzhiyun 	interface->rx_drops_nic = rx_drops_nic;
626*4882a593Smuzhiyun 
627*4882a593Smuzhiyun 	/* Fill out the OS statistics structure */
628*4882a593Smuzhiyun 	net_stats->rx_errors = rx_errors;
629*4882a593Smuzhiyun 	net_stats->rx_dropped = interface->stats.nodesc_drop.count;
630*4882a593Smuzhiyun 
631*4882a593Smuzhiyun 	/* Update VF statistics */
632*4882a593Smuzhiyun 	fm10k_iov_update_stats(interface);
633*4882a593Smuzhiyun 
634*4882a593Smuzhiyun 	clear_bit(__FM10K_UPDATING_STATS, interface->state);
635*4882a593Smuzhiyun }
636*4882a593Smuzhiyun 
637*4882a593Smuzhiyun /**
638*4882a593Smuzhiyun  * fm10k_watchdog_flush_tx - flush queues on host not ready
639*4882a593Smuzhiyun  * @interface: pointer to the device interface structure
640*4882a593Smuzhiyun  **/
fm10k_watchdog_flush_tx(struct fm10k_intfc * interface)641*4882a593Smuzhiyun static void fm10k_watchdog_flush_tx(struct fm10k_intfc *interface)
642*4882a593Smuzhiyun {
643*4882a593Smuzhiyun 	int some_tx_pending = 0;
644*4882a593Smuzhiyun 	int i;
645*4882a593Smuzhiyun 
646*4882a593Smuzhiyun 	/* nothing to do if carrier is up */
647*4882a593Smuzhiyun 	if (netif_carrier_ok(interface->netdev))
648*4882a593Smuzhiyun 		return;
649*4882a593Smuzhiyun 
650*4882a593Smuzhiyun 	for (i = 0; i < interface->num_tx_queues; i++) {
651*4882a593Smuzhiyun 		struct fm10k_ring *tx_ring = interface->tx_ring[i];
652*4882a593Smuzhiyun 
653*4882a593Smuzhiyun 		if (tx_ring->next_to_use != tx_ring->next_to_clean) {
654*4882a593Smuzhiyun 			some_tx_pending = 1;
655*4882a593Smuzhiyun 			break;
656*4882a593Smuzhiyun 		}
657*4882a593Smuzhiyun 	}
658*4882a593Smuzhiyun 
659*4882a593Smuzhiyun 	/* We've lost link, so the controller stops DMA, but we've got
660*4882a593Smuzhiyun 	 * queued Tx work that's never going to get done, so reset
661*4882a593Smuzhiyun 	 * controller to flush Tx.
662*4882a593Smuzhiyun 	 */
663*4882a593Smuzhiyun 	if (some_tx_pending)
664*4882a593Smuzhiyun 		set_bit(FM10K_FLAG_RESET_REQUESTED, interface->flags);
665*4882a593Smuzhiyun }
666*4882a593Smuzhiyun 
667*4882a593Smuzhiyun /**
668*4882a593Smuzhiyun  * fm10k_watchdog_subtask - check and bring link up
669*4882a593Smuzhiyun  * @interface: pointer to the device interface structure
670*4882a593Smuzhiyun  **/
fm10k_watchdog_subtask(struct fm10k_intfc * interface)671*4882a593Smuzhiyun static void fm10k_watchdog_subtask(struct fm10k_intfc *interface)
672*4882a593Smuzhiyun {
673*4882a593Smuzhiyun 	/* if interface is down do nothing */
674*4882a593Smuzhiyun 	if (test_bit(__FM10K_DOWN, interface->state) ||
675*4882a593Smuzhiyun 	    test_bit(__FM10K_RESETTING, interface->state))
676*4882a593Smuzhiyun 		return;
677*4882a593Smuzhiyun 
678*4882a593Smuzhiyun 	if (interface->host_ready)
679*4882a593Smuzhiyun 		fm10k_watchdog_host_is_ready(interface);
680*4882a593Smuzhiyun 	else
681*4882a593Smuzhiyun 		fm10k_watchdog_host_not_ready(interface);
682*4882a593Smuzhiyun 
683*4882a593Smuzhiyun 	/* update stats only once every second */
684*4882a593Smuzhiyun 	if (time_is_before_jiffies(interface->next_stats_update))
685*4882a593Smuzhiyun 		fm10k_update_stats(interface);
686*4882a593Smuzhiyun 
687*4882a593Smuzhiyun 	/* flush any uncompleted work */
688*4882a593Smuzhiyun 	fm10k_watchdog_flush_tx(interface);
689*4882a593Smuzhiyun }
690*4882a593Smuzhiyun 
691*4882a593Smuzhiyun /**
692*4882a593Smuzhiyun  * fm10k_check_hang_subtask - check for hung queues and dropped interrupts
693*4882a593Smuzhiyun  * @interface: pointer to the device interface structure
694*4882a593Smuzhiyun  *
695*4882a593Smuzhiyun  * This function serves two purposes.  First it strobes the interrupt lines
696*4882a593Smuzhiyun  * in order to make certain interrupts are occurring.  Secondly it sets the
697*4882a593Smuzhiyun  * bits needed to check for TX hangs.  As a result we should immediately
698*4882a593Smuzhiyun  * determine if a hang has occurred.
699*4882a593Smuzhiyun  */
fm10k_check_hang_subtask(struct fm10k_intfc * interface)700*4882a593Smuzhiyun static void fm10k_check_hang_subtask(struct fm10k_intfc *interface)
701*4882a593Smuzhiyun {
702*4882a593Smuzhiyun 	/* If we're down or resetting, just bail */
703*4882a593Smuzhiyun 	if (test_bit(__FM10K_DOWN, interface->state) ||
704*4882a593Smuzhiyun 	    test_bit(__FM10K_RESETTING, interface->state))
705*4882a593Smuzhiyun 		return;
706*4882a593Smuzhiyun 
707*4882a593Smuzhiyun 	/* rate limit tx hang checks to only once every 2 seconds */
708*4882a593Smuzhiyun 	if (time_is_after_eq_jiffies(interface->next_tx_hang_check))
709*4882a593Smuzhiyun 		return;
710*4882a593Smuzhiyun 	interface->next_tx_hang_check = jiffies + (2 * HZ);
711*4882a593Smuzhiyun 
712*4882a593Smuzhiyun 	if (netif_carrier_ok(interface->netdev)) {
713*4882a593Smuzhiyun 		int i;
714*4882a593Smuzhiyun 
715*4882a593Smuzhiyun 		/* Force detection of hung controller */
716*4882a593Smuzhiyun 		for (i = 0; i < interface->num_tx_queues; i++)
717*4882a593Smuzhiyun 			set_check_for_tx_hang(interface->tx_ring[i]);
718*4882a593Smuzhiyun 
719*4882a593Smuzhiyun 		/* Rearm all in-use q_vectors for immediate firing */
720*4882a593Smuzhiyun 		for (i = 0; i < interface->num_q_vectors; i++) {
721*4882a593Smuzhiyun 			struct fm10k_q_vector *qv = interface->q_vector[i];
722*4882a593Smuzhiyun 
723*4882a593Smuzhiyun 			if (!qv->tx.count && !qv->rx.count)
724*4882a593Smuzhiyun 				continue;
725*4882a593Smuzhiyun 			writel(FM10K_ITR_ENABLE | FM10K_ITR_PENDING2, qv->itr);
726*4882a593Smuzhiyun 		}
727*4882a593Smuzhiyun 	}
728*4882a593Smuzhiyun }
729*4882a593Smuzhiyun 
730*4882a593Smuzhiyun /**
731*4882a593Smuzhiyun  * fm10k_service_task - manages and runs subtasks
732*4882a593Smuzhiyun  * @work: pointer to work_struct containing our data
733*4882a593Smuzhiyun  **/
fm10k_service_task(struct work_struct * work)734*4882a593Smuzhiyun static void fm10k_service_task(struct work_struct *work)
735*4882a593Smuzhiyun {
736*4882a593Smuzhiyun 	struct fm10k_intfc *interface;
737*4882a593Smuzhiyun 
738*4882a593Smuzhiyun 	interface = container_of(work, struct fm10k_intfc, service_task);
739*4882a593Smuzhiyun 
740*4882a593Smuzhiyun 	/* Check whether we're detached first */
741*4882a593Smuzhiyun 	fm10k_detach_subtask(interface);
742*4882a593Smuzhiyun 
743*4882a593Smuzhiyun 	/* tasks run even when interface is down */
744*4882a593Smuzhiyun 	fm10k_mbx_subtask(interface);
745*4882a593Smuzhiyun 	fm10k_reset_subtask(interface);
746*4882a593Smuzhiyun 
747*4882a593Smuzhiyun 	/* tasks only run when interface is up */
748*4882a593Smuzhiyun 	fm10k_watchdog_subtask(interface);
749*4882a593Smuzhiyun 	fm10k_check_hang_subtask(interface);
750*4882a593Smuzhiyun 
751*4882a593Smuzhiyun 	/* release lock on service events to allow scheduling next event */
752*4882a593Smuzhiyun 	fm10k_service_event_complete(interface);
753*4882a593Smuzhiyun }
754*4882a593Smuzhiyun 
755*4882a593Smuzhiyun /**
756*4882a593Smuzhiyun  * fm10k_macvlan_task - send queued MAC/VLAN requests to switch manager
757*4882a593Smuzhiyun  * @work: pointer to work_struct containing our data
758*4882a593Smuzhiyun  *
759*4882a593Smuzhiyun  * This work item handles sending MAC/VLAN updates to the switch manager. When
760*4882a593Smuzhiyun  * the interface is up, it will attempt to queue mailbox messages to the
761*4882a593Smuzhiyun  * switch manager requesting updates for MAC/VLAN pairs. If the Tx fifo of the
762*4882a593Smuzhiyun  * mailbox is full, it will reschedule itself to try again in a short while.
763*4882a593Smuzhiyun  * This ensures that the driver does not overload the switch mailbox with too
764*4882a593Smuzhiyun  * many simultaneous requests, causing an unnecessary reset.
765*4882a593Smuzhiyun  **/
fm10k_macvlan_task(struct work_struct * work)766*4882a593Smuzhiyun static void fm10k_macvlan_task(struct work_struct *work)
767*4882a593Smuzhiyun {
768*4882a593Smuzhiyun 	struct fm10k_macvlan_request *item;
769*4882a593Smuzhiyun 	struct fm10k_intfc *interface;
770*4882a593Smuzhiyun 	struct delayed_work *dwork;
771*4882a593Smuzhiyun 	struct list_head *requests;
772*4882a593Smuzhiyun 	struct fm10k_hw *hw;
773*4882a593Smuzhiyun 	unsigned long flags;
774*4882a593Smuzhiyun 
775*4882a593Smuzhiyun 	dwork = to_delayed_work(work);
776*4882a593Smuzhiyun 	interface = container_of(dwork, struct fm10k_intfc, macvlan_task);
777*4882a593Smuzhiyun 	hw = &interface->hw;
778*4882a593Smuzhiyun 	requests = &interface->macvlan_requests;
779*4882a593Smuzhiyun 
780*4882a593Smuzhiyun 	do {
781*4882a593Smuzhiyun 		/* Pop the first item off the list */
782*4882a593Smuzhiyun 		spin_lock_irqsave(&interface->macvlan_lock, flags);
783*4882a593Smuzhiyun 		item = list_first_entry_or_null(requests,
784*4882a593Smuzhiyun 						struct fm10k_macvlan_request,
785*4882a593Smuzhiyun 						list);
786*4882a593Smuzhiyun 		if (item)
787*4882a593Smuzhiyun 			list_del_init(&item->list);
788*4882a593Smuzhiyun 
789*4882a593Smuzhiyun 		spin_unlock_irqrestore(&interface->macvlan_lock, flags);
790*4882a593Smuzhiyun 
791*4882a593Smuzhiyun 		/* We have no more items to process */
792*4882a593Smuzhiyun 		if (!item)
793*4882a593Smuzhiyun 			goto done;
794*4882a593Smuzhiyun 
795*4882a593Smuzhiyun 		fm10k_mbx_lock(interface);
796*4882a593Smuzhiyun 
797*4882a593Smuzhiyun 		/* Check that we have plenty of space to send the message. We
798*4882a593Smuzhiyun 		 * want to ensure that the mailbox stays low enough to avoid a
799*4882a593Smuzhiyun 		 * change in the host state, otherwise we may see spurious
800*4882a593Smuzhiyun 		 * link up / link down notifications.
801*4882a593Smuzhiyun 		 */
802*4882a593Smuzhiyun 		if (!hw->mbx.ops.tx_ready(&hw->mbx, FM10K_VFMBX_MSG_MTU + 5)) {
803*4882a593Smuzhiyun 			hw->mbx.ops.process(hw, &hw->mbx);
804*4882a593Smuzhiyun 			set_bit(__FM10K_MACVLAN_REQUEST, interface->state);
805*4882a593Smuzhiyun 			fm10k_mbx_unlock(interface);
806*4882a593Smuzhiyun 
807*4882a593Smuzhiyun 			/* Put the request back on the list */
808*4882a593Smuzhiyun 			spin_lock_irqsave(&interface->macvlan_lock, flags);
809*4882a593Smuzhiyun 			list_add(&item->list, requests);
810*4882a593Smuzhiyun 			spin_unlock_irqrestore(&interface->macvlan_lock, flags);
811*4882a593Smuzhiyun 			break;
812*4882a593Smuzhiyun 		}
813*4882a593Smuzhiyun 
814*4882a593Smuzhiyun 		switch (item->type) {
815*4882a593Smuzhiyun 		case FM10K_MC_MAC_REQUEST:
816*4882a593Smuzhiyun 			hw->mac.ops.update_mc_addr(hw,
817*4882a593Smuzhiyun 						   item->mac.glort,
818*4882a593Smuzhiyun 						   item->mac.addr,
819*4882a593Smuzhiyun 						   item->mac.vid,
820*4882a593Smuzhiyun 						   item->set);
821*4882a593Smuzhiyun 			break;
822*4882a593Smuzhiyun 		case FM10K_UC_MAC_REQUEST:
823*4882a593Smuzhiyun 			hw->mac.ops.update_uc_addr(hw,
824*4882a593Smuzhiyun 						   item->mac.glort,
825*4882a593Smuzhiyun 						   item->mac.addr,
826*4882a593Smuzhiyun 						   item->mac.vid,
827*4882a593Smuzhiyun 						   item->set,
828*4882a593Smuzhiyun 						   0);
829*4882a593Smuzhiyun 			break;
830*4882a593Smuzhiyun 		case FM10K_VLAN_REQUEST:
831*4882a593Smuzhiyun 			hw->mac.ops.update_vlan(hw,
832*4882a593Smuzhiyun 						item->vlan.vid,
833*4882a593Smuzhiyun 						item->vlan.vsi,
834*4882a593Smuzhiyun 						item->set);
835*4882a593Smuzhiyun 			break;
836*4882a593Smuzhiyun 		default:
837*4882a593Smuzhiyun 			break;
838*4882a593Smuzhiyun 		}
839*4882a593Smuzhiyun 
840*4882a593Smuzhiyun 		fm10k_mbx_unlock(interface);
841*4882a593Smuzhiyun 
842*4882a593Smuzhiyun 		/* Free the item now that we've sent the update */
843*4882a593Smuzhiyun 		kfree(item);
844*4882a593Smuzhiyun 	} while (true);
845*4882a593Smuzhiyun 
846*4882a593Smuzhiyun done:
847*4882a593Smuzhiyun 	WARN_ON(!test_bit(__FM10K_MACVLAN_SCHED, interface->state));
848*4882a593Smuzhiyun 
849*4882a593Smuzhiyun 	/* flush memory to make sure state is correct */
850*4882a593Smuzhiyun 	smp_mb__before_atomic();
851*4882a593Smuzhiyun 	clear_bit(__FM10K_MACVLAN_SCHED, interface->state);
852*4882a593Smuzhiyun 
853*4882a593Smuzhiyun 	/* If a MAC/VLAN request was scheduled since we started, we should
854*4882a593Smuzhiyun 	 * re-schedule. However, there is no reason to re-schedule if there is
855*4882a593Smuzhiyun 	 * no work to do.
856*4882a593Smuzhiyun 	 */
857*4882a593Smuzhiyun 	if (test_bit(__FM10K_MACVLAN_REQUEST, interface->state))
858*4882a593Smuzhiyun 		fm10k_macvlan_schedule(interface);
859*4882a593Smuzhiyun }
860*4882a593Smuzhiyun 
861*4882a593Smuzhiyun /**
862*4882a593Smuzhiyun  * fm10k_configure_tx_ring - Configure Tx ring after Reset
863*4882a593Smuzhiyun  * @interface: board private structure
864*4882a593Smuzhiyun  * @ring: structure containing ring specific data
865*4882a593Smuzhiyun  *
866*4882a593Smuzhiyun  * Configure the Tx descriptor ring after a reset.
867*4882a593Smuzhiyun  **/
fm10k_configure_tx_ring(struct fm10k_intfc * interface,struct fm10k_ring * ring)868*4882a593Smuzhiyun static void fm10k_configure_tx_ring(struct fm10k_intfc *interface,
869*4882a593Smuzhiyun 				    struct fm10k_ring *ring)
870*4882a593Smuzhiyun {
871*4882a593Smuzhiyun 	struct fm10k_hw *hw = &interface->hw;
872*4882a593Smuzhiyun 	u64 tdba = ring->dma;
873*4882a593Smuzhiyun 	u32 size = ring->count * sizeof(struct fm10k_tx_desc);
874*4882a593Smuzhiyun 	u32 txint = FM10K_INT_MAP_DISABLE;
875*4882a593Smuzhiyun 	u32 txdctl = BIT(FM10K_TXDCTL_MAX_TIME_SHIFT) | FM10K_TXDCTL_ENABLE;
876*4882a593Smuzhiyun 	u8 reg_idx = ring->reg_idx;
877*4882a593Smuzhiyun 
878*4882a593Smuzhiyun 	/* disable queue to avoid issues while updating state */
879*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_TXDCTL(reg_idx), 0);
880*4882a593Smuzhiyun 	fm10k_write_flush(hw);
881*4882a593Smuzhiyun 
882*4882a593Smuzhiyun 	/* possible poll here to verify ring resources have been cleaned */
883*4882a593Smuzhiyun 
884*4882a593Smuzhiyun 	/* set location and size for descriptor ring */
885*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_TDBAL(reg_idx), tdba & DMA_BIT_MASK(32));
886*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_TDBAH(reg_idx), tdba >> 32);
887*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_TDLEN(reg_idx), size);
888*4882a593Smuzhiyun 
889*4882a593Smuzhiyun 	/* reset head and tail pointers */
890*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_TDH(reg_idx), 0);
891*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_TDT(reg_idx), 0);
892*4882a593Smuzhiyun 
893*4882a593Smuzhiyun 	/* store tail pointer */
894*4882a593Smuzhiyun 	ring->tail = &interface->uc_addr[FM10K_TDT(reg_idx)];
895*4882a593Smuzhiyun 
896*4882a593Smuzhiyun 	/* reset ntu and ntc to place SW in sync with hardware */
897*4882a593Smuzhiyun 	ring->next_to_clean = 0;
898*4882a593Smuzhiyun 	ring->next_to_use = 0;
899*4882a593Smuzhiyun 
900*4882a593Smuzhiyun 	/* Map interrupt */
901*4882a593Smuzhiyun 	if (ring->q_vector) {
902*4882a593Smuzhiyun 		txint = ring->q_vector->v_idx + NON_Q_VECTORS;
903*4882a593Smuzhiyun 		txint |= FM10K_INT_MAP_TIMER0;
904*4882a593Smuzhiyun 	}
905*4882a593Smuzhiyun 
906*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_TXINT(reg_idx), txint);
907*4882a593Smuzhiyun 
908*4882a593Smuzhiyun 	/* enable use of FTAG bit in Tx descriptor, register is RO for VF */
909*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_PFVTCTL(reg_idx),
910*4882a593Smuzhiyun 			FM10K_PFVTCTL_FTAG_DESC_ENABLE);
911*4882a593Smuzhiyun 
912*4882a593Smuzhiyun 	/* Initialize XPS */
913*4882a593Smuzhiyun 	if (!test_and_set_bit(__FM10K_TX_XPS_INIT_DONE, ring->state) &&
914*4882a593Smuzhiyun 	    ring->q_vector)
915*4882a593Smuzhiyun 		netif_set_xps_queue(ring->netdev,
916*4882a593Smuzhiyun 				    &ring->q_vector->affinity_mask,
917*4882a593Smuzhiyun 				    ring->queue_index);
918*4882a593Smuzhiyun 
919*4882a593Smuzhiyun 	/* enable queue */
920*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_TXDCTL(reg_idx), txdctl);
921*4882a593Smuzhiyun }
922*4882a593Smuzhiyun 
923*4882a593Smuzhiyun /**
924*4882a593Smuzhiyun  * fm10k_enable_tx_ring - Verify Tx ring is enabled after configuration
925*4882a593Smuzhiyun  * @interface: board private structure
926*4882a593Smuzhiyun  * @ring: structure containing ring specific data
927*4882a593Smuzhiyun  *
928*4882a593Smuzhiyun  * Verify the Tx descriptor ring is ready for transmit.
929*4882a593Smuzhiyun  **/
fm10k_enable_tx_ring(struct fm10k_intfc * interface,struct fm10k_ring * ring)930*4882a593Smuzhiyun static void fm10k_enable_tx_ring(struct fm10k_intfc *interface,
931*4882a593Smuzhiyun 				 struct fm10k_ring *ring)
932*4882a593Smuzhiyun {
933*4882a593Smuzhiyun 	struct fm10k_hw *hw = &interface->hw;
934*4882a593Smuzhiyun 	int wait_loop = 10;
935*4882a593Smuzhiyun 	u32 txdctl;
936*4882a593Smuzhiyun 	u8 reg_idx = ring->reg_idx;
937*4882a593Smuzhiyun 
938*4882a593Smuzhiyun 	/* if we are already enabled just exit */
939*4882a593Smuzhiyun 	if (fm10k_read_reg(hw, FM10K_TXDCTL(reg_idx)) & FM10K_TXDCTL_ENABLE)
940*4882a593Smuzhiyun 		return;
941*4882a593Smuzhiyun 
942*4882a593Smuzhiyun 	/* poll to verify queue is enabled */
943*4882a593Smuzhiyun 	do {
944*4882a593Smuzhiyun 		usleep_range(1000, 2000);
945*4882a593Smuzhiyun 		txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(reg_idx));
946*4882a593Smuzhiyun 	} while (!(txdctl & FM10K_TXDCTL_ENABLE) && --wait_loop);
947*4882a593Smuzhiyun 	if (!wait_loop)
948*4882a593Smuzhiyun 		netif_err(interface, drv, interface->netdev,
949*4882a593Smuzhiyun 			  "Could not enable Tx Queue %d\n", reg_idx);
950*4882a593Smuzhiyun }
951*4882a593Smuzhiyun 
952*4882a593Smuzhiyun /**
953*4882a593Smuzhiyun  * fm10k_configure_tx - Configure Transmit Unit after Reset
954*4882a593Smuzhiyun  * @interface: board private structure
955*4882a593Smuzhiyun  *
956*4882a593Smuzhiyun  * Configure the Tx unit of the MAC after a reset.
957*4882a593Smuzhiyun  **/
fm10k_configure_tx(struct fm10k_intfc * interface)958*4882a593Smuzhiyun static void fm10k_configure_tx(struct fm10k_intfc *interface)
959*4882a593Smuzhiyun {
960*4882a593Smuzhiyun 	int i;
961*4882a593Smuzhiyun 
962*4882a593Smuzhiyun 	/* Setup the HW Tx Head and Tail descriptor pointers */
963*4882a593Smuzhiyun 	for (i = 0; i < interface->num_tx_queues; i++)
964*4882a593Smuzhiyun 		fm10k_configure_tx_ring(interface, interface->tx_ring[i]);
965*4882a593Smuzhiyun 
966*4882a593Smuzhiyun 	/* poll here to verify that Tx rings are now enabled */
967*4882a593Smuzhiyun 	for (i = 0; i < interface->num_tx_queues; i++)
968*4882a593Smuzhiyun 		fm10k_enable_tx_ring(interface, interface->tx_ring[i]);
969*4882a593Smuzhiyun }
970*4882a593Smuzhiyun 
971*4882a593Smuzhiyun /**
972*4882a593Smuzhiyun  * fm10k_configure_rx_ring - Configure Rx ring after Reset
973*4882a593Smuzhiyun  * @interface: board private structure
974*4882a593Smuzhiyun  * @ring: structure containing ring specific data
975*4882a593Smuzhiyun  *
976*4882a593Smuzhiyun  * Configure the Rx descriptor ring after a reset.
977*4882a593Smuzhiyun  **/
fm10k_configure_rx_ring(struct fm10k_intfc * interface,struct fm10k_ring * ring)978*4882a593Smuzhiyun static void fm10k_configure_rx_ring(struct fm10k_intfc *interface,
979*4882a593Smuzhiyun 				    struct fm10k_ring *ring)
980*4882a593Smuzhiyun {
981*4882a593Smuzhiyun 	u64 rdba = ring->dma;
982*4882a593Smuzhiyun 	struct fm10k_hw *hw = &interface->hw;
983*4882a593Smuzhiyun 	u32 size = ring->count * sizeof(union fm10k_rx_desc);
984*4882a593Smuzhiyun 	u32 rxqctl, rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;
985*4882a593Smuzhiyun 	u32 srrctl = FM10K_SRRCTL_BUFFER_CHAINING_EN;
986*4882a593Smuzhiyun 	u32 rxint = FM10K_INT_MAP_DISABLE;
987*4882a593Smuzhiyun 	u8 rx_pause = interface->rx_pause;
988*4882a593Smuzhiyun 	u8 reg_idx = ring->reg_idx;
989*4882a593Smuzhiyun 
990*4882a593Smuzhiyun 	/* disable queue to avoid issues while updating state */
991*4882a593Smuzhiyun 	rxqctl = fm10k_read_reg(hw, FM10K_RXQCTL(reg_idx));
992*4882a593Smuzhiyun 	rxqctl &= ~FM10K_RXQCTL_ENABLE;
993*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_RXQCTL(reg_idx), rxqctl);
994*4882a593Smuzhiyun 	fm10k_write_flush(hw);
995*4882a593Smuzhiyun 
996*4882a593Smuzhiyun 	/* possible poll here to verify ring resources have been cleaned */
997*4882a593Smuzhiyun 
998*4882a593Smuzhiyun 	/* set location and size for descriptor ring */
999*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_RDBAL(reg_idx), rdba & DMA_BIT_MASK(32));
1000*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_RDBAH(reg_idx), rdba >> 32);
1001*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_RDLEN(reg_idx), size);
1002*4882a593Smuzhiyun 
1003*4882a593Smuzhiyun 	/* reset head and tail pointers */
1004*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_RDH(reg_idx), 0);
1005*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_RDT(reg_idx), 0);
1006*4882a593Smuzhiyun 
1007*4882a593Smuzhiyun 	/* store tail pointer */
1008*4882a593Smuzhiyun 	ring->tail = &interface->uc_addr[FM10K_RDT(reg_idx)];
1009*4882a593Smuzhiyun 
1010*4882a593Smuzhiyun 	/* reset ntu and ntc to place SW in sync with hardware */
1011*4882a593Smuzhiyun 	ring->next_to_clean = 0;
1012*4882a593Smuzhiyun 	ring->next_to_use = 0;
1013*4882a593Smuzhiyun 	ring->next_to_alloc = 0;
1014*4882a593Smuzhiyun 
1015*4882a593Smuzhiyun 	/* Configure the Rx buffer size for one buff without split */
1016*4882a593Smuzhiyun 	srrctl |= FM10K_RX_BUFSZ >> FM10K_SRRCTL_BSIZEPKT_SHIFT;
1017*4882a593Smuzhiyun 
1018*4882a593Smuzhiyun 	/* Configure the Rx ring to suppress loopback packets */
1019*4882a593Smuzhiyun 	srrctl |= FM10K_SRRCTL_LOOPBACK_SUPPRESS;
1020*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_SRRCTL(reg_idx), srrctl);
1021*4882a593Smuzhiyun 
1022*4882a593Smuzhiyun 	/* Enable drop on empty */
1023*4882a593Smuzhiyun #ifdef CONFIG_DCB
1024*4882a593Smuzhiyun 	if (interface->pfc_en)
1025*4882a593Smuzhiyun 		rx_pause = interface->pfc_en;
1026*4882a593Smuzhiyun #endif
1027*4882a593Smuzhiyun 	if (!(rx_pause & BIT(ring->qos_pc)))
1028*4882a593Smuzhiyun 		rxdctl |= FM10K_RXDCTL_DROP_ON_EMPTY;
1029*4882a593Smuzhiyun 
1030*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_RXDCTL(reg_idx), rxdctl);
1031*4882a593Smuzhiyun 
1032*4882a593Smuzhiyun 	/* assign default VLAN to queue */
1033*4882a593Smuzhiyun 	ring->vid = hw->mac.default_vid;
1034*4882a593Smuzhiyun 
1035*4882a593Smuzhiyun 	/* if we have an active VLAN, disable default VLAN ID */
1036*4882a593Smuzhiyun 	if (test_bit(hw->mac.default_vid, interface->active_vlans))
1037*4882a593Smuzhiyun 		ring->vid |= FM10K_VLAN_CLEAR;
1038*4882a593Smuzhiyun 
1039*4882a593Smuzhiyun 	/* Map interrupt */
1040*4882a593Smuzhiyun 	if (ring->q_vector) {
1041*4882a593Smuzhiyun 		rxint = ring->q_vector->v_idx + NON_Q_VECTORS;
1042*4882a593Smuzhiyun 		rxint |= FM10K_INT_MAP_TIMER1;
1043*4882a593Smuzhiyun 	}
1044*4882a593Smuzhiyun 
1045*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_RXINT(reg_idx), rxint);
1046*4882a593Smuzhiyun 
1047*4882a593Smuzhiyun 	/* enable queue */
1048*4882a593Smuzhiyun 	rxqctl = fm10k_read_reg(hw, FM10K_RXQCTL(reg_idx));
1049*4882a593Smuzhiyun 	rxqctl |= FM10K_RXQCTL_ENABLE;
1050*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_RXQCTL(reg_idx), rxqctl);
1051*4882a593Smuzhiyun 
1052*4882a593Smuzhiyun 	/* place buffers on ring for receive data */
1053*4882a593Smuzhiyun 	fm10k_alloc_rx_buffers(ring, fm10k_desc_unused(ring));
1054*4882a593Smuzhiyun }
1055*4882a593Smuzhiyun 
1056*4882a593Smuzhiyun /**
1057*4882a593Smuzhiyun  * fm10k_update_rx_drop_en - Configures the drop enable bits for Rx rings
1058*4882a593Smuzhiyun  * @interface: board private structure
1059*4882a593Smuzhiyun  *
1060*4882a593Smuzhiyun  * Configure the drop enable bits for the Rx rings.
1061*4882a593Smuzhiyun  **/
fm10k_update_rx_drop_en(struct fm10k_intfc * interface)1062*4882a593Smuzhiyun void fm10k_update_rx_drop_en(struct fm10k_intfc *interface)
1063*4882a593Smuzhiyun {
1064*4882a593Smuzhiyun 	struct fm10k_hw *hw = &interface->hw;
1065*4882a593Smuzhiyun 	u8 rx_pause = interface->rx_pause;
1066*4882a593Smuzhiyun 	int i;
1067*4882a593Smuzhiyun 
1068*4882a593Smuzhiyun #ifdef CONFIG_DCB
1069*4882a593Smuzhiyun 	if (interface->pfc_en)
1070*4882a593Smuzhiyun 		rx_pause = interface->pfc_en;
1071*4882a593Smuzhiyun 
1072*4882a593Smuzhiyun #endif
1073*4882a593Smuzhiyun 	for (i = 0; i < interface->num_rx_queues; i++) {
1074*4882a593Smuzhiyun 		struct fm10k_ring *ring = interface->rx_ring[i];
1075*4882a593Smuzhiyun 		u32 rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;
1076*4882a593Smuzhiyun 		u8 reg_idx = ring->reg_idx;
1077*4882a593Smuzhiyun 
1078*4882a593Smuzhiyun 		if (!(rx_pause & BIT(ring->qos_pc)))
1079*4882a593Smuzhiyun 			rxdctl |= FM10K_RXDCTL_DROP_ON_EMPTY;
1080*4882a593Smuzhiyun 
1081*4882a593Smuzhiyun 		fm10k_write_reg(hw, FM10K_RXDCTL(reg_idx), rxdctl);
1082*4882a593Smuzhiyun 	}
1083*4882a593Smuzhiyun }
1084*4882a593Smuzhiyun 
1085*4882a593Smuzhiyun /**
1086*4882a593Smuzhiyun  * fm10k_configure_dglort - Configure Receive DGLORT after reset
1087*4882a593Smuzhiyun  * @interface: board private structure
1088*4882a593Smuzhiyun  *
1089*4882a593Smuzhiyun  * Configure the DGLORT description and RSS tables.
1090*4882a593Smuzhiyun  **/
fm10k_configure_dglort(struct fm10k_intfc * interface)1091*4882a593Smuzhiyun static void fm10k_configure_dglort(struct fm10k_intfc *interface)
1092*4882a593Smuzhiyun {
1093*4882a593Smuzhiyun 	struct fm10k_dglort_cfg dglort = { 0 };
1094*4882a593Smuzhiyun 	struct fm10k_hw *hw = &interface->hw;
1095*4882a593Smuzhiyun 	int i;
1096*4882a593Smuzhiyun 	u32 mrqc;
1097*4882a593Smuzhiyun 
1098*4882a593Smuzhiyun 	/* Fill out hash function seeds */
1099*4882a593Smuzhiyun 	for (i = 0; i < FM10K_RSSRK_SIZE; i++)
1100*4882a593Smuzhiyun 		fm10k_write_reg(hw, FM10K_RSSRK(0, i), interface->rssrk[i]);
1101*4882a593Smuzhiyun 
1102*4882a593Smuzhiyun 	/* Write RETA table to hardware */
1103*4882a593Smuzhiyun 	for (i = 0; i < FM10K_RETA_SIZE; i++)
1104*4882a593Smuzhiyun 		fm10k_write_reg(hw, FM10K_RETA(0, i), interface->reta[i]);
1105*4882a593Smuzhiyun 
1106*4882a593Smuzhiyun 	/* Generate RSS hash based on packet types, TCP/UDP
1107*4882a593Smuzhiyun 	 * port numbers and/or IPv4/v6 src and dst addresses
1108*4882a593Smuzhiyun 	 */
1109*4882a593Smuzhiyun 	mrqc = FM10K_MRQC_IPV4 |
1110*4882a593Smuzhiyun 	       FM10K_MRQC_TCP_IPV4 |
1111*4882a593Smuzhiyun 	       FM10K_MRQC_IPV6 |
1112*4882a593Smuzhiyun 	       FM10K_MRQC_TCP_IPV6;
1113*4882a593Smuzhiyun 
1114*4882a593Smuzhiyun 	if (test_bit(FM10K_FLAG_RSS_FIELD_IPV4_UDP, interface->flags))
1115*4882a593Smuzhiyun 		mrqc |= FM10K_MRQC_UDP_IPV4;
1116*4882a593Smuzhiyun 	if (test_bit(FM10K_FLAG_RSS_FIELD_IPV6_UDP, interface->flags))
1117*4882a593Smuzhiyun 		mrqc |= FM10K_MRQC_UDP_IPV6;
1118*4882a593Smuzhiyun 
1119*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_MRQC(0), mrqc);
1120*4882a593Smuzhiyun 
1121*4882a593Smuzhiyun 	/* configure default DGLORT mapping for RSS/DCB */
1122*4882a593Smuzhiyun 	dglort.inner_rss = 1;
1123*4882a593Smuzhiyun 	dglort.rss_l = fls(interface->ring_feature[RING_F_RSS].mask);
1124*4882a593Smuzhiyun 	dglort.pc_l = fls(interface->ring_feature[RING_F_QOS].mask);
1125*4882a593Smuzhiyun 	hw->mac.ops.configure_dglort_map(hw, &dglort);
1126*4882a593Smuzhiyun 
1127*4882a593Smuzhiyun 	/* assign GLORT per queue for queue mapped testing */
1128*4882a593Smuzhiyun 	if (interface->glort_count > 64) {
1129*4882a593Smuzhiyun 		memset(&dglort, 0, sizeof(dglort));
1130*4882a593Smuzhiyun 		dglort.inner_rss = 1;
1131*4882a593Smuzhiyun 		dglort.glort = interface->glort + 64;
1132*4882a593Smuzhiyun 		dglort.idx = fm10k_dglort_pf_queue;
1133*4882a593Smuzhiyun 		dglort.queue_l = fls(interface->num_rx_queues - 1);
1134*4882a593Smuzhiyun 		hw->mac.ops.configure_dglort_map(hw, &dglort);
1135*4882a593Smuzhiyun 	}
1136*4882a593Smuzhiyun 
1137*4882a593Smuzhiyun 	/* assign glort value for RSS/DCB specific to this interface */
1138*4882a593Smuzhiyun 	memset(&dglort, 0, sizeof(dglort));
1139*4882a593Smuzhiyun 	dglort.inner_rss = 1;
1140*4882a593Smuzhiyun 	dglort.glort = interface->glort;
1141*4882a593Smuzhiyun 	dglort.rss_l = fls(interface->ring_feature[RING_F_RSS].mask);
1142*4882a593Smuzhiyun 	dglort.pc_l = fls(interface->ring_feature[RING_F_QOS].mask);
1143*4882a593Smuzhiyun 	/* configure DGLORT mapping for RSS/DCB */
1144*4882a593Smuzhiyun 	dglort.idx = fm10k_dglort_pf_rss;
1145*4882a593Smuzhiyun 	if (interface->l2_accel)
1146*4882a593Smuzhiyun 		dglort.shared_l = fls(interface->l2_accel->size);
1147*4882a593Smuzhiyun 	hw->mac.ops.configure_dglort_map(hw, &dglort);
1148*4882a593Smuzhiyun }
1149*4882a593Smuzhiyun 
1150*4882a593Smuzhiyun /**
1151*4882a593Smuzhiyun  * fm10k_configure_rx - Configure Receive Unit after Reset
1152*4882a593Smuzhiyun  * @interface: board private structure
1153*4882a593Smuzhiyun  *
1154*4882a593Smuzhiyun  * Configure the Rx unit of the MAC after a reset.
1155*4882a593Smuzhiyun  **/
fm10k_configure_rx(struct fm10k_intfc * interface)1156*4882a593Smuzhiyun static void fm10k_configure_rx(struct fm10k_intfc *interface)
1157*4882a593Smuzhiyun {
1158*4882a593Smuzhiyun 	int i;
1159*4882a593Smuzhiyun 
1160*4882a593Smuzhiyun 	/* Configure SWPRI to PC map */
1161*4882a593Smuzhiyun 	fm10k_configure_swpri_map(interface);
1162*4882a593Smuzhiyun 
1163*4882a593Smuzhiyun 	/* Configure RSS and DGLORT map */
1164*4882a593Smuzhiyun 	fm10k_configure_dglort(interface);
1165*4882a593Smuzhiyun 
1166*4882a593Smuzhiyun 	/* Setup the HW Rx Head and Tail descriptor pointers */
1167*4882a593Smuzhiyun 	for (i = 0; i < interface->num_rx_queues; i++)
1168*4882a593Smuzhiyun 		fm10k_configure_rx_ring(interface, interface->rx_ring[i]);
1169*4882a593Smuzhiyun 
1170*4882a593Smuzhiyun 	/* possible poll here to verify that Rx rings are now enabled */
1171*4882a593Smuzhiyun }
1172*4882a593Smuzhiyun 
fm10k_napi_enable_all(struct fm10k_intfc * interface)1173*4882a593Smuzhiyun static void fm10k_napi_enable_all(struct fm10k_intfc *interface)
1174*4882a593Smuzhiyun {
1175*4882a593Smuzhiyun 	struct fm10k_q_vector *q_vector;
1176*4882a593Smuzhiyun 	int q_idx;
1177*4882a593Smuzhiyun 
1178*4882a593Smuzhiyun 	for (q_idx = 0; q_idx < interface->num_q_vectors; q_idx++) {
1179*4882a593Smuzhiyun 		q_vector = interface->q_vector[q_idx];
1180*4882a593Smuzhiyun 		napi_enable(&q_vector->napi);
1181*4882a593Smuzhiyun 	}
1182*4882a593Smuzhiyun }
1183*4882a593Smuzhiyun 
fm10k_msix_clean_rings(int __always_unused irq,void * data)1184*4882a593Smuzhiyun static irqreturn_t fm10k_msix_clean_rings(int __always_unused irq, void *data)
1185*4882a593Smuzhiyun {
1186*4882a593Smuzhiyun 	struct fm10k_q_vector *q_vector = data;
1187*4882a593Smuzhiyun 
1188*4882a593Smuzhiyun 	if (q_vector->rx.count || q_vector->tx.count)
1189*4882a593Smuzhiyun 		napi_schedule_irqoff(&q_vector->napi);
1190*4882a593Smuzhiyun 
1191*4882a593Smuzhiyun 	return IRQ_HANDLED;
1192*4882a593Smuzhiyun }
1193*4882a593Smuzhiyun 
fm10k_msix_mbx_vf(int __always_unused irq,void * data)1194*4882a593Smuzhiyun static irqreturn_t fm10k_msix_mbx_vf(int __always_unused irq, void *data)
1195*4882a593Smuzhiyun {
1196*4882a593Smuzhiyun 	struct fm10k_intfc *interface = data;
1197*4882a593Smuzhiyun 	struct fm10k_hw *hw = &interface->hw;
1198*4882a593Smuzhiyun 	struct fm10k_mbx_info *mbx = &hw->mbx;
1199*4882a593Smuzhiyun 
1200*4882a593Smuzhiyun 	/* re-enable mailbox interrupt and indicate 20us delay */
1201*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_VFITR(FM10K_MBX_VECTOR),
1202*4882a593Smuzhiyun 			(FM10K_MBX_INT_DELAY >> hw->mac.itr_scale) |
1203*4882a593Smuzhiyun 			FM10K_ITR_ENABLE);
1204*4882a593Smuzhiyun 
1205*4882a593Smuzhiyun 	/* service upstream mailbox */
1206*4882a593Smuzhiyun 	if (fm10k_mbx_trylock(interface)) {
1207*4882a593Smuzhiyun 		mbx->ops.process(hw, mbx);
1208*4882a593Smuzhiyun 		fm10k_mbx_unlock(interface);
1209*4882a593Smuzhiyun 	}
1210*4882a593Smuzhiyun 
1211*4882a593Smuzhiyun 	hw->mac.get_host_state = true;
1212*4882a593Smuzhiyun 	fm10k_service_event_schedule(interface);
1213*4882a593Smuzhiyun 
1214*4882a593Smuzhiyun 	return IRQ_HANDLED;
1215*4882a593Smuzhiyun }
1216*4882a593Smuzhiyun 
1217*4882a593Smuzhiyun #define FM10K_ERR_MSG(type) case (type): error = #type; break
fm10k_handle_fault(struct fm10k_intfc * interface,int type,struct fm10k_fault * fault)1218*4882a593Smuzhiyun static void fm10k_handle_fault(struct fm10k_intfc *interface, int type,
1219*4882a593Smuzhiyun 			       struct fm10k_fault *fault)
1220*4882a593Smuzhiyun {
1221*4882a593Smuzhiyun 	struct pci_dev *pdev = interface->pdev;
1222*4882a593Smuzhiyun 	struct fm10k_hw *hw = &interface->hw;
1223*4882a593Smuzhiyun 	struct fm10k_iov_data *iov_data = interface->iov_data;
1224*4882a593Smuzhiyun 	char *error;
1225*4882a593Smuzhiyun 
1226*4882a593Smuzhiyun 	switch (type) {
1227*4882a593Smuzhiyun 	case FM10K_PCA_FAULT:
1228*4882a593Smuzhiyun 		switch (fault->type) {
1229*4882a593Smuzhiyun 		default:
1230*4882a593Smuzhiyun 			error = "Unknown PCA error";
1231*4882a593Smuzhiyun 			break;
1232*4882a593Smuzhiyun 		FM10K_ERR_MSG(PCA_NO_FAULT);
1233*4882a593Smuzhiyun 		FM10K_ERR_MSG(PCA_UNMAPPED_ADDR);
1234*4882a593Smuzhiyun 		FM10K_ERR_MSG(PCA_BAD_QACCESS_PF);
1235*4882a593Smuzhiyun 		FM10K_ERR_MSG(PCA_BAD_QACCESS_VF);
1236*4882a593Smuzhiyun 		FM10K_ERR_MSG(PCA_MALICIOUS_REQ);
1237*4882a593Smuzhiyun 		FM10K_ERR_MSG(PCA_POISONED_TLP);
1238*4882a593Smuzhiyun 		FM10K_ERR_MSG(PCA_TLP_ABORT);
1239*4882a593Smuzhiyun 		}
1240*4882a593Smuzhiyun 		break;
1241*4882a593Smuzhiyun 	case FM10K_THI_FAULT:
1242*4882a593Smuzhiyun 		switch (fault->type) {
1243*4882a593Smuzhiyun 		default:
1244*4882a593Smuzhiyun 			error = "Unknown THI error";
1245*4882a593Smuzhiyun 			break;
1246*4882a593Smuzhiyun 		FM10K_ERR_MSG(THI_NO_FAULT);
1247*4882a593Smuzhiyun 		FM10K_ERR_MSG(THI_MAL_DIS_Q_FAULT);
1248*4882a593Smuzhiyun 		}
1249*4882a593Smuzhiyun 		break;
1250*4882a593Smuzhiyun 	case FM10K_FUM_FAULT:
1251*4882a593Smuzhiyun 		switch (fault->type) {
1252*4882a593Smuzhiyun 		default:
1253*4882a593Smuzhiyun 			error = "Unknown FUM error";
1254*4882a593Smuzhiyun 			break;
1255*4882a593Smuzhiyun 		FM10K_ERR_MSG(FUM_NO_FAULT);
1256*4882a593Smuzhiyun 		FM10K_ERR_MSG(FUM_UNMAPPED_ADDR);
1257*4882a593Smuzhiyun 		FM10K_ERR_MSG(FUM_BAD_VF_QACCESS);
1258*4882a593Smuzhiyun 		FM10K_ERR_MSG(FUM_ADD_DECODE_ERR);
1259*4882a593Smuzhiyun 		FM10K_ERR_MSG(FUM_RO_ERROR);
1260*4882a593Smuzhiyun 		FM10K_ERR_MSG(FUM_QPRC_CRC_ERROR);
1261*4882a593Smuzhiyun 		FM10K_ERR_MSG(FUM_CSR_TIMEOUT);
1262*4882a593Smuzhiyun 		FM10K_ERR_MSG(FUM_INVALID_TYPE);
1263*4882a593Smuzhiyun 		FM10K_ERR_MSG(FUM_INVALID_LENGTH);
1264*4882a593Smuzhiyun 		FM10K_ERR_MSG(FUM_INVALID_BE);
1265*4882a593Smuzhiyun 		FM10K_ERR_MSG(FUM_INVALID_ALIGN);
1266*4882a593Smuzhiyun 		}
1267*4882a593Smuzhiyun 		break;
1268*4882a593Smuzhiyun 	default:
1269*4882a593Smuzhiyun 		error = "Undocumented fault";
1270*4882a593Smuzhiyun 		break;
1271*4882a593Smuzhiyun 	}
1272*4882a593Smuzhiyun 
1273*4882a593Smuzhiyun 	dev_warn(&pdev->dev,
1274*4882a593Smuzhiyun 		 "%s Address: 0x%llx SpecInfo: 0x%x Func: %02x.%0x\n",
1275*4882a593Smuzhiyun 		 error, fault->address, fault->specinfo,
1276*4882a593Smuzhiyun 		 PCI_SLOT(fault->func), PCI_FUNC(fault->func));
1277*4882a593Smuzhiyun 
1278*4882a593Smuzhiyun 	/* For VF faults, clear out the respective LPORT, reset the queue
1279*4882a593Smuzhiyun 	 * resources, and then reconnect to the mailbox. This allows the
1280*4882a593Smuzhiyun 	 * VF in question to resume behavior. For transient faults that are
1281*4882a593Smuzhiyun 	 * the result of non-malicious behavior this will log the fault and
1282*4882a593Smuzhiyun 	 * allow the VF to resume functionality. Obviously for malicious VFs
1283*4882a593Smuzhiyun 	 * they will be able to attempt malicious behavior again. In this
1284*4882a593Smuzhiyun 	 * case, the system administrator will need to step in and manually
1285*4882a593Smuzhiyun 	 * remove or disable the VF in question.
1286*4882a593Smuzhiyun 	 */
1287*4882a593Smuzhiyun 	if (fault->func && iov_data) {
1288*4882a593Smuzhiyun 		int vf = fault->func - 1;
1289*4882a593Smuzhiyun 		struct fm10k_vf_info *vf_info = &iov_data->vf_info[vf];
1290*4882a593Smuzhiyun 
1291*4882a593Smuzhiyun 		hw->iov.ops.reset_lport(hw, vf_info);
1292*4882a593Smuzhiyun 		hw->iov.ops.reset_resources(hw, vf_info);
1293*4882a593Smuzhiyun 
1294*4882a593Smuzhiyun 		/* reset_lport disables the VF, so re-enable it */
1295*4882a593Smuzhiyun 		hw->iov.ops.set_lport(hw, vf_info, vf,
1296*4882a593Smuzhiyun 				      FM10K_VF_FLAG_MULTI_CAPABLE);
1297*4882a593Smuzhiyun 
1298*4882a593Smuzhiyun 		/* reset_resources will disconnect from the mbx  */
1299*4882a593Smuzhiyun 		vf_info->mbx.ops.connect(hw, &vf_info->mbx);
1300*4882a593Smuzhiyun 	}
1301*4882a593Smuzhiyun }
1302*4882a593Smuzhiyun 
fm10k_report_fault(struct fm10k_intfc * interface,u32 eicr)1303*4882a593Smuzhiyun static void fm10k_report_fault(struct fm10k_intfc *interface, u32 eicr)
1304*4882a593Smuzhiyun {
1305*4882a593Smuzhiyun 	struct fm10k_hw *hw = &interface->hw;
1306*4882a593Smuzhiyun 	struct fm10k_fault fault = { 0 };
1307*4882a593Smuzhiyun 	int type, err;
1308*4882a593Smuzhiyun 
1309*4882a593Smuzhiyun 	for (eicr &= FM10K_EICR_FAULT_MASK, type = FM10K_PCA_FAULT;
1310*4882a593Smuzhiyun 	     eicr;
1311*4882a593Smuzhiyun 	     eicr >>= 1, type += FM10K_FAULT_SIZE) {
1312*4882a593Smuzhiyun 		/* only check if there is an error reported */
1313*4882a593Smuzhiyun 		if (!(eicr & 0x1))
1314*4882a593Smuzhiyun 			continue;
1315*4882a593Smuzhiyun 
1316*4882a593Smuzhiyun 		/* retrieve fault info */
1317*4882a593Smuzhiyun 		err = hw->mac.ops.get_fault(hw, type, &fault);
1318*4882a593Smuzhiyun 		if (err) {
1319*4882a593Smuzhiyun 			dev_err(&interface->pdev->dev,
1320*4882a593Smuzhiyun 				"error reading fault\n");
1321*4882a593Smuzhiyun 			continue;
1322*4882a593Smuzhiyun 		}
1323*4882a593Smuzhiyun 
1324*4882a593Smuzhiyun 		fm10k_handle_fault(interface, type, &fault);
1325*4882a593Smuzhiyun 	}
1326*4882a593Smuzhiyun }
1327*4882a593Smuzhiyun 
fm10k_reset_drop_on_empty(struct fm10k_intfc * interface,u32 eicr)1328*4882a593Smuzhiyun static void fm10k_reset_drop_on_empty(struct fm10k_intfc *interface, u32 eicr)
1329*4882a593Smuzhiyun {
1330*4882a593Smuzhiyun 	struct fm10k_hw *hw = &interface->hw;
1331*4882a593Smuzhiyun 	const u32 rxdctl = FM10K_RXDCTL_WRITE_BACK_MIN_DELAY;
1332*4882a593Smuzhiyun 	u32 maxholdq;
1333*4882a593Smuzhiyun 	int q;
1334*4882a593Smuzhiyun 
1335*4882a593Smuzhiyun 	if (!(eicr & FM10K_EICR_MAXHOLDTIME))
1336*4882a593Smuzhiyun 		return;
1337*4882a593Smuzhiyun 
1338*4882a593Smuzhiyun 	maxholdq = fm10k_read_reg(hw, FM10K_MAXHOLDQ(7));
1339*4882a593Smuzhiyun 	if (maxholdq)
1340*4882a593Smuzhiyun 		fm10k_write_reg(hw, FM10K_MAXHOLDQ(7), maxholdq);
1341*4882a593Smuzhiyun 	for (q = 255;;) {
1342*4882a593Smuzhiyun 		if (maxholdq & BIT(31)) {
1343*4882a593Smuzhiyun 			if (q < FM10K_MAX_QUEUES_PF) {
1344*4882a593Smuzhiyun 				interface->rx_overrun_pf++;
1345*4882a593Smuzhiyun 				fm10k_write_reg(hw, FM10K_RXDCTL(q), rxdctl);
1346*4882a593Smuzhiyun 			} else {
1347*4882a593Smuzhiyun 				interface->rx_overrun_vf++;
1348*4882a593Smuzhiyun 			}
1349*4882a593Smuzhiyun 		}
1350*4882a593Smuzhiyun 
1351*4882a593Smuzhiyun 		maxholdq *= 2;
1352*4882a593Smuzhiyun 		if (!maxholdq)
1353*4882a593Smuzhiyun 			q &= ~(32 - 1);
1354*4882a593Smuzhiyun 
1355*4882a593Smuzhiyun 		if (!q)
1356*4882a593Smuzhiyun 			break;
1357*4882a593Smuzhiyun 
1358*4882a593Smuzhiyun 		if (q-- % 32)
1359*4882a593Smuzhiyun 			continue;
1360*4882a593Smuzhiyun 
1361*4882a593Smuzhiyun 		maxholdq = fm10k_read_reg(hw, FM10K_MAXHOLDQ(q / 32));
1362*4882a593Smuzhiyun 		if (maxholdq)
1363*4882a593Smuzhiyun 			fm10k_write_reg(hw, FM10K_MAXHOLDQ(q / 32), maxholdq);
1364*4882a593Smuzhiyun 	}
1365*4882a593Smuzhiyun }
1366*4882a593Smuzhiyun 
fm10k_msix_mbx_pf(int __always_unused irq,void * data)1367*4882a593Smuzhiyun static irqreturn_t fm10k_msix_mbx_pf(int __always_unused irq, void *data)
1368*4882a593Smuzhiyun {
1369*4882a593Smuzhiyun 	struct fm10k_intfc *interface = data;
1370*4882a593Smuzhiyun 	struct fm10k_hw *hw = &interface->hw;
1371*4882a593Smuzhiyun 	struct fm10k_mbx_info *mbx = &hw->mbx;
1372*4882a593Smuzhiyun 	u32 eicr;
1373*4882a593Smuzhiyun 	s32 err = 0;
1374*4882a593Smuzhiyun 
1375*4882a593Smuzhiyun 	/* unmask any set bits related to this interrupt */
1376*4882a593Smuzhiyun 	eicr = fm10k_read_reg(hw, FM10K_EICR);
1377*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_EICR, eicr & (FM10K_EICR_MAILBOX |
1378*4882a593Smuzhiyun 						FM10K_EICR_SWITCHREADY |
1379*4882a593Smuzhiyun 						FM10K_EICR_SWITCHNOTREADY));
1380*4882a593Smuzhiyun 
1381*4882a593Smuzhiyun 	/* report any faults found to the message log */
1382*4882a593Smuzhiyun 	fm10k_report_fault(interface, eicr);
1383*4882a593Smuzhiyun 
1384*4882a593Smuzhiyun 	/* reset any queues disabled due to receiver overrun */
1385*4882a593Smuzhiyun 	fm10k_reset_drop_on_empty(interface, eicr);
1386*4882a593Smuzhiyun 
1387*4882a593Smuzhiyun 	/* service mailboxes */
1388*4882a593Smuzhiyun 	if (fm10k_mbx_trylock(interface)) {
1389*4882a593Smuzhiyun 		err = mbx->ops.process(hw, mbx);
1390*4882a593Smuzhiyun 		/* handle VFLRE events */
1391*4882a593Smuzhiyun 		fm10k_iov_event(interface);
1392*4882a593Smuzhiyun 		fm10k_mbx_unlock(interface);
1393*4882a593Smuzhiyun 	}
1394*4882a593Smuzhiyun 
1395*4882a593Smuzhiyun 	if (err == FM10K_ERR_RESET_REQUESTED)
1396*4882a593Smuzhiyun 		set_bit(FM10K_FLAG_RESET_REQUESTED, interface->flags);
1397*4882a593Smuzhiyun 
1398*4882a593Smuzhiyun 	/* if switch toggled state we should reset GLORTs */
1399*4882a593Smuzhiyun 	if (eicr & FM10K_EICR_SWITCHNOTREADY) {
1400*4882a593Smuzhiyun 		/* force link down for at least 4 seconds */
1401*4882a593Smuzhiyun 		interface->link_down_event = jiffies + (4 * HZ);
1402*4882a593Smuzhiyun 		set_bit(__FM10K_LINK_DOWN, interface->state);
1403*4882a593Smuzhiyun 
1404*4882a593Smuzhiyun 		/* reset dglort_map back to no config */
1405*4882a593Smuzhiyun 		hw->mac.dglort_map = FM10K_DGLORTMAP_NONE;
1406*4882a593Smuzhiyun 	}
1407*4882a593Smuzhiyun 
1408*4882a593Smuzhiyun 	/* we should validate host state after interrupt event */
1409*4882a593Smuzhiyun 	hw->mac.get_host_state = true;
1410*4882a593Smuzhiyun 
1411*4882a593Smuzhiyun 	/* validate host state, and handle VF mailboxes in the service task */
1412*4882a593Smuzhiyun 	fm10k_service_event_schedule(interface);
1413*4882a593Smuzhiyun 
1414*4882a593Smuzhiyun 	/* re-enable mailbox interrupt and indicate 20us delay */
1415*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_ITR(FM10K_MBX_VECTOR),
1416*4882a593Smuzhiyun 			(FM10K_MBX_INT_DELAY >> hw->mac.itr_scale) |
1417*4882a593Smuzhiyun 			FM10K_ITR_ENABLE);
1418*4882a593Smuzhiyun 
1419*4882a593Smuzhiyun 	return IRQ_HANDLED;
1420*4882a593Smuzhiyun }
1421*4882a593Smuzhiyun 
fm10k_mbx_free_irq(struct fm10k_intfc * interface)1422*4882a593Smuzhiyun void fm10k_mbx_free_irq(struct fm10k_intfc *interface)
1423*4882a593Smuzhiyun {
1424*4882a593Smuzhiyun 	struct fm10k_hw *hw = &interface->hw;
1425*4882a593Smuzhiyun 	struct msix_entry *entry;
1426*4882a593Smuzhiyun 	int itr_reg;
1427*4882a593Smuzhiyun 
1428*4882a593Smuzhiyun 	/* no mailbox IRQ to free if MSI-X is not enabled */
1429*4882a593Smuzhiyun 	if (!interface->msix_entries)
1430*4882a593Smuzhiyun 		return;
1431*4882a593Smuzhiyun 
1432*4882a593Smuzhiyun 	entry = &interface->msix_entries[FM10K_MBX_VECTOR];
1433*4882a593Smuzhiyun 
1434*4882a593Smuzhiyun 	/* disconnect the mailbox */
1435*4882a593Smuzhiyun 	hw->mbx.ops.disconnect(hw, &hw->mbx);
1436*4882a593Smuzhiyun 
1437*4882a593Smuzhiyun 	/* disable Mailbox cause */
1438*4882a593Smuzhiyun 	if (hw->mac.type == fm10k_mac_pf) {
1439*4882a593Smuzhiyun 		fm10k_write_reg(hw, FM10K_EIMR,
1440*4882a593Smuzhiyun 				FM10K_EIMR_DISABLE(PCA_FAULT) |
1441*4882a593Smuzhiyun 				FM10K_EIMR_DISABLE(FUM_FAULT) |
1442*4882a593Smuzhiyun 				FM10K_EIMR_DISABLE(MAILBOX) |
1443*4882a593Smuzhiyun 				FM10K_EIMR_DISABLE(SWITCHREADY) |
1444*4882a593Smuzhiyun 				FM10K_EIMR_DISABLE(SWITCHNOTREADY) |
1445*4882a593Smuzhiyun 				FM10K_EIMR_DISABLE(SRAMERROR) |
1446*4882a593Smuzhiyun 				FM10K_EIMR_DISABLE(VFLR) |
1447*4882a593Smuzhiyun 				FM10K_EIMR_DISABLE(MAXHOLDTIME));
1448*4882a593Smuzhiyun 		itr_reg = FM10K_ITR(FM10K_MBX_VECTOR);
1449*4882a593Smuzhiyun 	} else {
1450*4882a593Smuzhiyun 		itr_reg = FM10K_VFITR(FM10K_MBX_VECTOR);
1451*4882a593Smuzhiyun 	}
1452*4882a593Smuzhiyun 
1453*4882a593Smuzhiyun 	fm10k_write_reg(hw, itr_reg, FM10K_ITR_MASK_SET);
1454*4882a593Smuzhiyun 
1455*4882a593Smuzhiyun 	free_irq(entry->vector, interface);
1456*4882a593Smuzhiyun }
1457*4882a593Smuzhiyun 
fm10k_mbx_mac_addr(struct fm10k_hw * hw,u32 ** results,struct fm10k_mbx_info * mbx)1458*4882a593Smuzhiyun static s32 fm10k_mbx_mac_addr(struct fm10k_hw *hw, u32 **results,
1459*4882a593Smuzhiyun 			      struct fm10k_mbx_info *mbx)
1460*4882a593Smuzhiyun {
1461*4882a593Smuzhiyun 	bool vlan_override = hw->mac.vlan_override;
1462*4882a593Smuzhiyun 	u16 default_vid = hw->mac.default_vid;
1463*4882a593Smuzhiyun 	struct fm10k_intfc *interface;
1464*4882a593Smuzhiyun 	s32 err;
1465*4882a593Smuzhiyun 
1466*4882a593Smuzhiyun 	err = fm10k_msg_mac_vlan_vf(hw, results, mbx);
1467*4882a593Smuzhiyun 	if (err)
1468*4882a593Smuzhiyun 		return err;
1469*4882a593Smuzhiyun 
1470*4882a593Smuzhiyun 	interface = container_of(hw, struct fm10k_intfc, hw);
1471*4882a593Smuzhiyun 
1472*4882a593Smuzhiyun 	/* MAC was changed so we need reset */
1473*4882a593Smuzhiyun 	if (is_valid_ether_addr(hw->mac.perm_addr) &&
1474*4882a593Smuzhiyun 	    !ether_addr_equal(hw->mac.perm_addr, hw->mac.addr))
1475*4882a593Smuzhiyun 		set_bit(FM10K_FLAG_RESET_REQUESTED, interface->flags);
1476*4882a593Smuzhiyun 
1477*4882a593Smuzhiyun 	/* VLAN override was changed, or default VLAN changed */
1478*4882a593Smuzhiyun 	if ((vlan_override != hw->mac.vlan_override) ||
1479*4882a593Smuzhiyun 	    (default_vid != hw->mac.default_vid))
1480*4882a593Smuzhiyun 		set_bit(FM10K_FLAG_RESET_REQUESTED, interface->flags);
1481*4882a593Smuzhiyun 
1482*4882a593Smuzhiyun 	return 0;
1483*4882a593Smuzhiyun }
1484*4882a593Smuzhiyun 
1485*4882a593Smuzhiyun /* generic error handler for mailbox issues */
fm10k_mbx_error(struct fm10k_hw * hw,u32 ** results,struct fm10k_mbx_info __always_unused * mbx)1486*4882a593Smuzhiyun static s32 fm10k_mbx_error(struct fm10k_hw *hw, u32 **results,
1487*4882a593Smuzhiyun 			   struct fm10k_mbx_info __always_unused *mbx)
1488*4882a593Smuzhiyun {
1489*4882a593Smuzhiyun 	struct fm10k_intfc *interface;
1490*4882a593Smuzhiyun 	struct pci_dev *pdev;
1491*4882a593Smuzhiyun 
1492*4882a593Smuzhiyun 	interface = container_of(hw, struct fm10k_intfc, hw);
1493*4882a593Smuzhiyun 	pdev = interface->pdev;
1494*4882a593Smuzhiyun 
1495*4882a593Smuzhiyun 	dev_err(&pdev->dev, "Unknown message ID %u\n",
1496*4882a593Smuzhiyun 		**results & FM10K_TLV_ID_MASK);
1497*4882a593Smuzhiyun 
1498*4882a593Smuzhiyun 	return 0;
1499*4882a593Smuzhiyun }
1500*4882a593Smuzhiyun 
1501*4882a593Smuzhiyun static const struct fm10k_msg_data vf_mbx_data[] = {
1502*4882a593Smuzhiyun 	FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
1503*4882a593Smuzhiyun 	FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_mbx_mac_addr),
1504*4882a593Smuzhiyun 	FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_msg_lport_state_vf),
1505*4882a593Smuzhiyun 	FM10K_TLV_MSG_ERROR_HANDLER(fm10k_mbx_error),
1506*4882a593Smuzhiyun };
1507*4882a593Smuzhiyun 
fm10k_mbx_request_irq_vf(struct fm10k_intfc * interface)1508*4882a593Smuzhiyun static int fm10k_mbx_request_irq_vf(struct fm10k_intfc *interface)
1509*4882a593Smuzhiyun {
1510*4882a593Smuzhiyun 	struct msix_entry *entry = &interface->msix_entries[FM10K_MBX_VECTOR];
1511*4882a593Smuzhiyun 	struct net_device *dev = interface->netdev;
1512*4882a593Smuzhiyun 	struct fm10k_hw *hw = &interface->hw;
1513*4882a593Smuzhiyun 	int err;
1514*4882a593Smuzhiyun 
1515*4882a593Smuzhiyun 	/* Use timer0 for interrupt moderation on the mailbox */
1516*4882a593Smuzhiyun 	u32 itr = entry->entry | FM10K_INT_MAP_TIMER0;
1517*4882a593Smuzhiyun 
1518*4882a593Smuzhiyun 	/* register mailbox handlers */
1519*4882a593Smuzhiyun 	err = hw->mbx.ops.register_handlers(&hw->mbx, vf_mbx_data);
1520*4882a593Smuzhiyun 	if (err)
1521*4882a593Smuzhiyun 		return err;
1522*4882a593Smuzhiyun 
1523*4882a593Smuzhiyun 	/* request the IRQ */
1524*4882a593Smuzhiyun 	err = request_irq(entry->vector, fm10k_msix_mbx_vf, 0,
1525*4882a593Smuzhiyun 			  dev->name, interface);
1526*4882a593Smuzhiyun 	if (err) {
1527*4882a593Smuzhiyun 		netif_err(interface, probe, dev,
1528*4882a593Smuzhiyun 			  "request_irq for msix_mbx failed: %d\n", err);
1529*4882a593Smuzhiyun 		return err;
1530*4882a593Smuzhiyun 	}
1531*4882a593Smuzhiyun 
1532*4882a593Smuzhiyun 	/* map all of the interrupt sources */
1533*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_VFINT_MAP, itr);
1534*4882a593Smuzhiyun 
1535*4882a593Smuzhiyun 	/* enable interrupt */
1536*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_VFITR(entry->entry), FM10K_ITR_ENABLE);
1537*4882a593Smuzhiyun 
1538*4882a593Smuzhiyun 	return 0;
1539*4882a593Smuzhiyun }
1540*4882a593Smuzhiyun 
fm10k_lport_map(struct fm10k_hw * hw,u32 ** results,struct fm10k_mbx_info * mbx)1541*4882a593Smuzhiyun static s32 fm10k_lport_map(struct fm10k_hw *hw, u32 **results,
1542*4882a593Smuzhiyun 			   struct fm10k_mbx_info *mbx)
1543*4882a593Smuzhiyun {
1544*4882a593Smuzhiyun 	struct fm10k_intfc *interface;
1545*4882a593Smuzhiyun 	u32 dglort_map = hw->mac.dglort_map;
1546*4882a593Smuzhiyun 	s32 err;
1547*4882a593Smuzhiyun 
1548*4882a593Smuzhiyun 	interface = container_of(hw, struct fm10k_intfc, hw);
1549*4882a593Smuzhiyun 
1550*4882a593Smuzhiyun 	err = fm10k_msg_err_pf(hw, results, mbx);
1551*4882a593Smuzhiyun 	if (!err && hw->swapi.status) {
1552*4882a593Smuzhiyun 		/* force link down for a reasonable delay */
1553*4882a593Smuzhiyun 		interface->link_down_event = jiffies + (2 * HZ);
1554*4882a593Smuzhiyun 		set_bit(__FM10K_LINK_DOWN, interface->state);
1555*4882a593Smuzhiyun 
1556*4882a593Smuzhiyun 		/* reset dglort_map back to no config */
1557*4882a593Smuzhiyun 		hw->mac.dglort_map = FM10K_DGLORTMAP_NONE;
1558*4882a593Smuzhiyun 
1559*4882a593Smuzhiyun 		fm10k_service_event_schedule(interface);
1560*4882a593Smuzhiyun 
1561*4882a593Smuzhiyun 		/* prevent overloading kernel message buffer */
1562*4882a593Smuzhiyun 		if (interface->lport_map_failed)
1563*4882a593Smuzhiyun 			return 0;
1564*4882a593Smuzhiyun 
1565*4882a593Smuzhiyun 		interface->lport_map_failed = true;
1566*4882a593Smuzhiyun 
1567*4882a593Smuzhiyun 		if (hw->swapi.status == FM10K_MSG_ERR_PEP_NOT_SCHEDULED)
1568*4882a593Smuzhiyun 			dev_warn(&interface->pdev->dev,
1569*4882a593Smuzhiyun 				 "cannot obtain link because the host interface is configured for a PCIe host interface bandwidth of zero\n");
1570*4882a593Smuzhiyun 		dev_warn(&interface->pdev->dev,
1571*4882a593Smuzhiyun 			 "request logical port map failed: %d\n",
1572*4882a593Smuzhiyun 			 hw->swapi.status);
1573*4882a593Smuzhiyun 
1574*4882a593Smuzhiyun 		return 0;
1575*4882a593Smuzhiyun 	}
1576*4882a593Smuzhiyun 
1577*4882a593Smuzhiyun 	err = fm10k_msg_lport_map_pf(hw, results, mbx);
1578*4882a593Smuzhiyun 	if (err)
1579*4882a593Smuzhiyun 		return err;
1580*4882a593Smuzhiyun 
1581*4882a593Smuzhiyun 	interface->lport_map_failed = false;
1582*4882a593Smuzhiyun 
1583*4882a593Smuzhiyun 	/* we need to reset if port count was just updated */
1584*4882a593Smuzhiyun 	if (dglort_map != hw->mac.dglort_map)
1585*4882a593Smuzhiyun 		set_bit(FM10K_FLAG_RESET_REQUESTED, interface->flags);
1586*4882a593Smuzhiyun 
1587*4882a593Smuzhiyun 	return 0;
1588*4882a593Smuzhiyun }
1589*4882a593Smuzhiyun 
fm10k_update_pvid(struct fm10k_hw * hw,u32 ** results,struct fm10k_mbx_info __always_unused * mbx)1590*4882a593Smuzhiyun static s32 fm10k_update_pvid(struct fm10k_hw *hw, u32 **results,
1591*4882a593Smuzhiyun 			     struct fm10k_mbx_info __always_unused *mbx)
1592*4882a593Smuzhiyun {
1593*4882a593Smuzhiyun 	struct fm10k_intfc *interface;
1594*4882a593Smuzhiyun 	u16 glort, pvid;
1595*4882a593Smuzhiyun 	u32 pvid_update;
1596*4882a593Smuzhiyun 	s32 err;
1597*4882a593Smuzhiyun 
1598*4882a593Smuzhiyun 	err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_UPDATE_PVID],
1599*4882a593Smuzhiyun 				     &pvid_update);
1600*4882a593Smuzhiyun 	if (err)
1601*4882a593Smuzhiyun 		return err;
1602*4882a593Smuzhiyun 
1603*4882a593Smuzhiyun 	/* extract values from the pvid update */
1604*4882a593Smuzhiyun 	glort = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_GLORT);
1605*4882a593Smuzhiyun 	pvid = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_PVID);
1606*4882a593Smuzhiyun 
1607*4882a593Smuzhiyun 	/* if glort is not valid return error */
1608*4882a593Smuzhiyun 	if (!fm10k_glort_valid_pf(hw, glort))
1609*4882a593Smuzhiyun 		return FM10K_ERR_PARAM;
1610*4882a593Smuzhiyun 
1611*4882a593Smuzhiyun 	/* verify VLAN ID is valid */
1612*4882a593Smuzhiyun 	if (pvid >= FM10K_VLAN_TABLE_VID_MAX)
1613*4882a593Smuzhiyun 		return FM10K_ERR_PARAM;
1614*4882a593Smuzhiyun 
1615*4882a593Smuzhiyun 	interface = container_of(hw, struct fm10k_intfc, hw);
1616*4882a593Smuzhiyun 
1617*4882a593Smuzhiyun 	/* check to see if this belongs to one of the VFs */
1618*4882a593Smuzhiyun 	err = fm10k_iov_update_pvid(interface, glort, pvid);
1619*4882a593Smuzhiyun 	if (!err)
1620*4882a593Smuzhiyun 		return 0;
1621*4882a593Smuzhiyun 
1622*4882a593Smuzhiyun 	/* we need to reset if default VLAN was just updated */
1623*4882a593Smuzhiyun 	if (pvid != hw->mac.default_vid)
1624*4882a593Smuzhiyun 		set_bit(FM10K_FLAG_RESET_REQUESTED, interface->flags);
1625*4882a593Smuzhiyun 
1626*4882a593Smuzhiyun 	hw->mac.default_vid = pvid;
1627*4882a593Smuzhiyun 
1628*4882a593Smuzhiyun 	return 0;
1629*4882a593Smuzhiyun }
1630*4882a593Smuzhiyun 
1631*4882a593Smuzhiyun static const struct fm10k_msg_data pf_mbx_data[] = {
1632*4882a593Smuzhiyun 	FM10K_PF_MSG_ERR_HANDLER(XCAST_MODES, fm10k_msg_err_pf),
1633*4882a593Smuzhiyun 	FM10K_PF_MSG_ERR_HANDLER(UPDATE_MAC_FWD_RULE, fm10k_msg_err_pf),
1634*4882a593Smuzhiyun 	FM10K_PF_MSG_LPORT_MAP_HANDLER(fm10k_lport_map),
1635*4882a593Smuzhiyun 	FM10K_PF_MSG_ERR_HANDLER(LPORT_CREATE, fm10k_msg_err_pf),
1636*4882a593Smuzhiyun 	FM10K_PF_MSG_ERR_HANDLER(LPORT_DELETE, fm10k_msg_err_pf),
1637*4882a593Smuzhiyun 	FM10K_PF_MSG_UPDATE_PVID_HANDLER(fm10k_update_pvid),
1638*4882a593Smuzhiyun 	FM10K_TLV_MSG_ERROR_HANDLER(fm10k_mbx_error),
1639*4882a593Smuzhiyun };
1640*4882a593Smuzhiyun 
fm10k_mbx_request_irq_pf(struct fm10k_intfc * interface)1641*4882a593Smuzhiyun static int fm10k_mbx_request_irq_pf(struct fm10k_intfc *interface)
1642*4882a593Smuzhiyun {
1643*4882a593Smuzhiyun 	struct msix_entry *entry = &interface->msix_entries[FM10K_MBX_VECTOR];
1644*4882a593Smuzhiyun 	struct net_device *dev = interface->netdev;
1645*4882a593Smuzhiyun 	struct fm10k_hw *hw = &interface->hw;
1646*4882a593Smuzhiyun 	int err;
1647*4882a593Smuzhiyun 
1648*4882a593Smuzhiyun 	/* Use timer0 for interrupt moderation on the mailbox */
1649*4882a593Smuzhiyun 	u32 mbx_itr = entry->entry | FM10K_INT_MAP_TIMER0;
1650*4882a593Smuzhiyun 	u32 other_itr = entry->entry | FM10K_INT_MAP_IMMEDIATE;
1651*4882a593Smuzhiyun 
1652*4882a593Smuzhiyun 	/* register mailbox handlers */
1653*4882a593Smuzhiyun 	err = hw->mbx.ops.register_handlers(&hw->mbx, pf_mbx_data);
1654*4882a593Smuzhiyun 	if (err)
1655*4882a593Smuzhiyun 		return err;
1656*4882a593Smuzhiyun 
1657*4882a593Smuzhiyun 	/* request the IRQ */
1658*4882a593Smuzhiyun 	err = request_irq(entry->vector, fm10k_msix_mbx_pf, 0,
1659*4882a593Smuzhiyun 			  dev->name, interface);
1660*4882a593Smuzhiyun 	if (err) {
1661*4882a593Smuzhiyun 		netif_err(interface, probe, dev,
1662*4882a593Smuzhiyun 			  "request_irq for msix_mbx failed: %d\n", err);
1663*4882a593Smuzhiyun 		return err;
1664*4882a593Smuzhiyun 	}
1665*4882a593Smuzhiyun 
1666*4882a593Smuzhiyun 	/* Enable interrupts w/ no moderation for "other" interrupts */
1667*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_pcie_fault), other_itr);
1668*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_switch_up_down), other_itr);
1669*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_sram), other_itr);
1670*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_max_hold_time), other_itr);
1671*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_vflr), other_itr);
1672*4882a593Smuzhiyun 
1673*4882a593Smuzhiyun 	/* Enable interrupts w/ moderation for mailbox */
1674*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_INT_MAP(fm10k_int_mailbox), mbx_itr);
1675*4882a593Smuzhiyun 
1676*4882a593Smuzhiyun 	/* Enable individual interrupt causes */
1677*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_EIMR, FM10K_EIMR_ENABLE(PCA_FAULT) |
1678*4882a593Smuzhiyun 					FM10K_EIMR_ENABLE(FUM_FAULT) |
1679*4882a593Smuzhiyun 					FM10K_EIMR_ENABLE(MAILBOX) |
1680*4882a593Smuzhiyun 					FM10K_EIMR_ENABLE(SWITCHREADY) |
1681*4882a593Smuzhiyun 					FM10K_EIMR_ENABLE(SWITCHNOTREADY) |
1682*4882a593Smuzhiyun 					FM10K_EIMR_ENABLE(SRAMERROR) |
1683*4882a593Smuzhiyun 					FM10K_EIMR_ENABLE(VFLR) |
1684*4882a593Smuzhiyun 					FM10K_EIMR_ENABLE(MAXHOLDTIME));
1685*4882a593Smuzhiyun 
1686*4882a593Smuzhiyun 	/* enable interrupt */
1687*4882a593Smuzhiyun 	fm10k_write_reg(hw, FM10K_ITR(entry->entry), FM10K_ITR_ENABLE);
1688*4882a593Smuzhiyun 
1689*4882a593Smuzhiyun 	return 0;
1690*4882a593Smuzhiyun }
1691*4882a593Smuzhiyun 
fm10k_mbx_request_irq(struct fm10k_intfc * interface)1692*4882a593Smuzhiyun int fm10k_mbx_request_irq(struct fm10k_intfc *interface)
1693*4882a593Smuzhiyun {
1694*4882a593Smuzhiyun 	struct fm10k_hw *hw = &interface->hw;
1695*4882a593Smuzhiyun 	int err;
1696*4882a593Smuzhiyun 
1697*4882a593Smuzhiyun 	/* enable Mailbox cause */
1698*4882a593Smuzhiyun 	if (hw->mac.type == fm10k_mac_pf)
1699*4882a593Smuzhiyun 		err = fm10k_mbx_request_irq_pf(interface);
1700*4882a593Smuzhiyun 	else
1701*4882a593Smuzhiyun 		err = fm10k_mbx_request_irq_vf(interface);
1702*4882a593Smuzhiyun 	if (err)
1703*4882a593Smuzhiyun 		return err;
1704*4882a593Smuzhiyun 
1705*4882a593Smuzhiyun 	/* connect mailbox */
1706*4882a593Smuzhiyun 	err = hw->mbx.ops.connect(hw, &hw->mbx);
1707*4882a593Smuzhiyun 
1708*4882a593Smuzhiyun 	/* if the mailbox failed to connect, then free IRQ */
1709*4882a593Smuzhiyun 	if (err)
1710*4882a593Smuzhiyun 		fm10k_mbx_free_irq(interface);
1711*4882a593Smuzhiyun 
1712*4882a593Smuzhiyun 	return err;
1713*4882a593Smuzhiyun }
1714*4882a593Smuzhiyun 
1715*4882a593Smuzhiyun /**
1716*4882a593Smuzhiyun  * fm10k_qv_free_irq - release interrupts associated with queue vectors
1717*4882a593Smuzhiyun  * @interface: board private structure
1718*4882a593Smuzhiyun  *
1719*4882a593Smuzhiyun  * Release all interrupts associated with this interface
1720*4882a593Smuzhiyun  **/
fm10k_qv_free_irq(struct fm10k_intfc * interface)1721*4882a593Smuzhiyun void fm10k_qv_free_irq(struct fm10k_intfc *interface)
1722*4882a593Smuzhiyun {
1723*4882a593Smuzhiyun 	int vector = interface->num_q_vectors;
1724*4882a593Smuzhiyun 	struct msix_entry *entry;
1725*4882a593Smuzhiyun 
1726*4882a593Smuzhiyun 	entry = &interface->msix_entries[NON_Q_VECTORS + vector];
1727*4882a593Smuzhiyun 
1728*4882a593Smuzhiyun 	while (vector) {
1729*4882a593Smuzhiyun 		struct fm10k_q_vector *q_vector;
1730*4882a593Smuzhiyun 
1731*4882a593Smuzhiyun 		vector--;
1732*4882a593Smuzhiyun 		entry--;
1733*4882a593Smuzhiyun 		q_vector = interface->q_vector[vector];
1734*4882a593Smuzhiyun 
1735*4882a593Smuzhiyun 		if (!q_vector->tx.count && !q_vector->rx.count)
1736*4882a593Smuzhiyun 			continue;
1737*4882a593Smuzhiyun 
1738*4882a593Smuzhiyun 		/* clear the affinity_mask in the IRQ descriptor */
1739*4882a593Smuzhiyun 		irq_set_affinity_hint(entry->vector, NULL);
1740*4882a593Smuzhiyun 
1741*4882a593Smuzhiyun 		/* disable interrupts */
1742*4882a593Smuzhiyun 		writel(FM10K_ITR_MASK_SET, q_vector->itr);
1743*4882a593Smuzhiyun 
1744*4882a593Smuzhiyun 		free_irq(entry->vector, q_vector);
1745*4882a593Smuzhiyun 	}
1746*4882a593Smuzhiyun }
1747*4882a593Smuzhiyun 
1748*4882a593Smuzhiyun /**
1749*4882a593Smuzhiyun  * fm10k_qv_request_irq - initialize interrupts for queue vectors
1750*4882a593Smuzhiyun  * @interface: board private structure
1751*4882a593Smuzhiyun  *
1752*4882a593Smuzhiyun  * Attempts to configure interrupts using the best available
1753*4882a593Smuzhiyun  * capabilities of the hardware and kernel.
1754*4882a593Smuzhiyun  **/
fm10k_qv_request_irq(struct fm10k_intfc * interface)1755*4882a593Smuzhiyun int fm10k_qv_request_irq(struct fm10k_intfc *interface)
1756*4882a593Smuzhiyun {
1757*4882a593Smuzhiyun 	struct net_device *dev = interface->netdev;
1758*4882a593Smuzhiyun 	struct fm10k_hw *hw = &interface->hw;
1759*4882a593Smuzhiyun 	struct msix_entry *entry;
1760*4882a593Smuzhiyun 	unsigned int ri = 0, ti = 0;
1761*4882a593Smuzhiyun 	int vector, err;
1762*4882a593Smuzhiyun 
1763*4882a593Smuzhiyun 	entry = &interface->msix_entries[NON_Q_VECTORS];
1764*4882a593Smuzhiyun 
1765*4882a593Smuzhiyun 	for (vector = 0; vector < interface->num_q_vectors; vector++) {
1766*4882a593Smuzhiyun 		struct fm10k_q_vector *q_vector = interface->q_vector[vector];
1767*4882a593Smuzhiyun 
1768*4882a593Smuzhiyun 		/* name the vector */
1769*4882a593Smuzhiyun 		if (q_vector->tx.count && q_vector->rx.count) {
1770*4882a593Smuzhiyun 			snprintf(q_vector->name, sizeof(q_vector->name),
1771*4882a593Smuzhiyun 				 "%s-TxRx-%u", dev->name, ri++);
1772*4882a593Smuzhiyun 			ti++;
1773*4882a593Smuzhiyun 		} else if (q_vector->rx.count) {
1774*4882a593Smuzhiyun 			snprintf(q_vector->name, sizeof(q_vector->name),
1775*4882a593Smuzhiyun 				 "%s-rx-%u", dev->name, ri++);
1776*4882a593Smuzhiyun 		} else if (q_vector->tx.count) {
1777*4882a593Smuzhiyun 			snprintf(q_vector->name, sizeof(q_vector->name),
1778*4882a593Smuzhiyun 				 "%s-tx-%u", dev->name, ti++);
1779*4882a593Smuzhiyun 		} else {
1780*4882a593Smuzhiyun 			/* skip this unused q_vector */
1781*4882a593Smuzhiyun 			continue;
1782*4882a593Smuzhiyun 		}
1783*4882a593Smuzhiyun 
1784*4882a593Smuzhiyun 		/* Assign ITR register to q_vector */
1785*4882a593Smuzhiyun 		q_vector->itr = (hw->mac.type == fm10k_mac_pf) ?
1786*4882a593Smuzhiyun 				&interface->uc_addr[FM10K_ITR(entry->entry)] :
1787*4882a593Smuzhiyun 				&interface->uc_addr[FM10K_VFITR(entry->entry)];
1788*4882a593Smuzhiyun 
1789*4882a593Smuzhiyun 		/* request the IRQ */
1790*4882a593Smuzhiyun 		err = request_irq(entry->vector, &fm10k_msix_clean_rings, 0,
1791*4882a593Smuzhiyun 				  q_vector->name, q_vector);
1792*4882a593Smuzhiyun 		if (err) {
1793*4882a593Smuzhiyun 			netif_err(interface, probe, dev,
1794*4882a593Smuzhiyun 				  "request_irq failed for MSIX interrupt Error: %d\n",
1795*4882a593Smuzhiyun 				  err);
1796*4882a593Smuzhiyun 			goto err_out;
1797*4882a593Smuzhiyun 		}
1798*4882a593Smuzhiyun 
1799*4882a593Smuzhiyun 		/* assign the mask for this irq */
1800*4882a593Smuzhiyun 		irq_set_affinity_hint(entry->vector, &q_vector->affinity_mask);
1801*4882a593Smuzhiyun 
1802*4882a593Smuzhiyun 		/* Enable q_vector */
1803*4882a593Smuzhiyun 		writel(FM10K_ITR_ENABLE, q_vector->itr);
1804*4882a593Smuzhiyun 
1805*4882a593Smuzhiyun 		entry++;
1806*4882a593Smuzhiyun 	}
1807*4882a593Smuzhiyun 
1808*4882a593Smuzhiyun 	return 0;
1809*4882a593Smuzhiyun 
1810*4882a593Smuzhiyun err_out:
1811*4882a593Smuzhiyun 	/* wind through the ring freeing all entries and vectors */
1812*4882a593Smuzhiyun 	while (vector) {
1813*4882a593Smuzhiyun 		struct fm10k_q_vector *q_vector;
1814*4882a593Smuzhiyun 
1815*4882a593Smuzhiyun 		entry--;
1816*4882a593Smuzhiyun 		vector--;
1817*4882a593Smuzhiyun 		q_vector = interface->q_vector[vector];
1818*4882a593Smuzhiyun 
1819*4882a593Smuzhiyun 		if (!q_vector->tx.count && !q_vector->rx.count)
1820*4882a593Smuzhiyun 			continue;
1821*4882a593Smuzhiyun 
1822*4882a593Smuzhiyun 		/* clear the affinity_mask in the IRQ descriptor */
1823*4882a593Smuzhiyun 		irq_set_affinity_hint(entry->vector, NULL);
1824*4882a593Smuzhiyun 
1825*4882a593Smuzhiyun 		/* disable interrupts */
1826*4882a593Smuzhiyun 		writel(FM10K_ITR_MASK_SET, q_vector->itr);
1827*4882a593Smuzhiyun 
1828*4882a593Smuzhiyun 		free_irq(entry->vector, q_vector);
1829*4882a593Smuzhiyun 	}
1830*4882a593Smuzhiyun 
1831*4882a593Smuzhiyun 	return err;
1832*4882a593Smuzhiyun }
1833*4882a593Smuzhiyun 
fm10k_up(struct fm10k_intfc * interface)1834*4882a593Smuzhiyun void fm10k_up(struct fm10k_intfc *interface)
1835*4882a593Smuzhiyun {
1836*4882a593Smuzhiyun 	struct fm10k_hw *hw = &interface->hw;
1837*4882a593Smuzhiyun 
1838*4882a593Smuzhiyun 	/* Enable Tx/Rx DMA */
1839*4882a593Smuzhiyun 	hw->mac.ops.start_hw(hw);
1840*4882a593Smuzhiyun 
1841*4882a593Smuzhiyun 	/* configure Tx descriptor rings */
1842*4882a593Smuzhiyun 	fm10k_configure_tx(interface);
1843*4882a593Smuzhiyun 
1844*4882a593Smuzhiyun 	/* configure Rx descriptor rings */
1845*4882a593Smuzhiyun 	fm10k_configure_rx(interface);
1846*4882a593Smuzhiyun 
1847*4882a593Smuzhiyun 	/* configure interrupts */
1848*4882a593Smuzhiyun 	hw->mac.ops.update_int_moderator(hw);
1849*4882a593Smuzhiyun 
1850*4882a593Smuzhiyun 	/* enable statistics capture again */
1851*4882a593Smuzhiyun 	clear_bit(__FM10K_UPDATING_STATS, interface->state);
1852*4882a593Smuzhiyun 
1853*4882a593Smuzhiyun 	/* clear down bit to indicate we are ready to go */
1854*4882a593Smuzhiyun 	clear_bit(__FM10K_DOWN, interface->state);
1855*4882a593Smuzhiyun 
1856*4882a593Smuzhiyun 	/* enable polling cleanups */
1857*4882a593Smuzhiyun 	fm10k_napi_enable_all(interface);
1858*4882a593Smuzhiyun 
1859*4882a593Smuzhiyun 	/* re-establish Rx filters */
1860*4882a593Smuzhiyun 	fm10k_restore_rx_state(interface);
1861*4882a593Smuzhiyun 
1862*4882a593Smuzhiyun 	/* enable transmits */
1863*4882a593Smuzhiyun 	netif_tx_start_all_queues(interface->netdev);
1864*4882a593Smuzhiyun 
1865*4882a593Smuzhiyun 	/* kick off the service timer now */
1866*4882a593Smuzhiyun 	hw->mac.get_host_state = true;
1867*4882a593Smuzhiyun 	mod_timer(&interface->service_timer, jiffies);
1868*4882a593Smuzhiyun }
1869*4882a593Smuzhiyun 
fm10k_napi_disable_all(struct fm10k_intfc * interface)1870*4882a593Smuzhiyun static void fm10k_napi_disable_all(struct fm10k_intfc *interface)
1871*4882a593Smuzhiyun {
1872*4882a593Smuzhiyun 	struct fm10k_q_vector *q_vector;
1873*4882a593Smuzhiyun 	int q_idx;
1874*4882a593Smuzhiyun 
1875*4882a593Smuzhiyun 	for (q_idx = 0; q_idx < interface->num_q_vectors; q_idx++) {
1876*4882a593Smuzhiyun 		q_vector = interface->q_vector[q_idx];
1877*4882a593Smuzhiyun 		napi_disable(&q_vector->napi);
1878*4882a593Smuzhiyun 	}
1879*4882a593Smuzhiyun }
1880*4882a593Smuzhiyun 
fm10k_down(struct fm10k_intfc * interface)1881*4882a593Smuzhiyun void fm10k_down(struct fm10k_intfc *interface)
1882*4882a593Smuzhiyun {
1883*4882a593Smuzhiyun 	struct net_device *netdev = interface->netdev;
1884*4882a593Smuzhiyun 	struct fm10k_hw *hw = &interface->hw;
1885*4882a593Smuzhiyun 	int err, i = 0, count = 0;
1886*4882a593Smuzhiyun 
1887*4882a593Smuzhiyun 	/* signal that we are down to the interrupt handler and service task */
1888*4882a593Smuzhiyun 	if (test_and_set_bit(__FM10K_DOWN, interface->state))
1889*4882a593Smuzhiyun 		return;
1890*4882a593Smuzhiyun 
1891*4882a593Smuzhiyun 	/* call carrier off first to avoid false dev_watchdog timeouts */
1892*4882a593Smuzhiyun 	netif_carrier_off(netdev);
1893*4882a593Smuzhiyun 
1894*4882a593Smuzhiyun 	/* disable transmits */
1895*4882a593Smuzhiyun 	netif_tx_stop_all_queues(netdev);
1896*4882a593Smuzhiyun 	netif_tx_disable(netdev);
1897*4882a593Smuzhiyun 
1898*4882a593Smuzhiyun 	/* reset Rx filters */
1899*4882a593Smuzhiyun 	fm10k_reset_rx_state(interface);
1900*4882a593Smuzhiyun 
1901*4882a593Smuzhiyun 	/* disable polling routines */
1902*4882a593Smuzhiyun 	fm10k_napi_disable_all(interface);
1903*4882a593Smuzhiyun 
1904*4882a593Smuzhiyun 	/* capture stats one last time before stopping interface */
1905*4882a593Smuzhiyun 	fm10k_update_stats(interface);
1906*4882a593Smuzhiyun 
1907*4882a593Smuzhiyun 	/* prevent updating statistics while we're down */
1908*4882a593Smuzhiyun 	while (test_and_set_bit(__FM10K_UPDATING_STATS, interface->state))
1909*4882a593Smuzhiyun 		usleep_range(1000, 2000);
1910*4882a593Smuzhiyun 
1911*4882a593Smuzhiyun 	/* skip waiting for TX DMA if we lost PCIe link */
1912*4882a593Smuzhiyun 	if (FM10K_REMOVED(hw->hw_addr))
1913*4882a593Smuzhiyun 		goto skip_tx_dma_drain;
1914*4882a593Smuzhiyun 
1915*4882a593Smuzhiyun 	/* In some rare circumstances it can take a while for Tx queues to
1916*4882a593Smuzhiyun 	 * quiesce and be fully disabled. Attempt to .stop_hw() first, and
1917*4882a593Smuzhiyun 	 * then if we get ERR_REQUESTS_PENDING, go ahead and wait in a loop
1918*4882a593Smuzhiyun 	 * until the Tx queues have emptied, or until a number of retries. If
1919*4882a593Smuzhiyun 	 * we fail to clear within the retry loop, we will issue a warning
1920*4882a593Smuzhiyun 	 * indicating that Tx DMA is probably hung. Note this means we call
1921*4882a593Smuzhiyun 	 * .stop_hw() twice but this shouldn't cause any problems.
1922*4882a593Smuzhiyun 	 */
1923*4882a593Smuzhiyun 	err = hw->mac.ops.stop_hw(hw);
1924*4882a593Smuzhiyun 	if (err != FM10K_ERR_REQUESTS_PENDING)
1925*4882a593Smuzhiyun 		goto skip_tx_dma_drain;
1926*4882a593Smuzhiyun 
1927*4882a593Smuzhiyun #define TX_DMA_DRAIN_RETRIES 25
1928*4882a593Smuzhiyun 	for (count = 0; count < TX_DMA_DRAIN_RETRIES; count++) {
1929*4882a593Smuzhiyun 		usleep_range(10000, 20000);
1930*4882a593Smuzhiyun 
1931*4882a593Smuzhiyun 		/* start checking at the last ring to have pending Tx */
1932*4882a593Smuzhiyun 		for (; i < interface->num_tx_queues; i++)
1933*4882a593Smuzhiyun 			if (fm10k_get_tx_pending(interface->tx_ring[i], false))
1934*4882a593Smuzhiyun 				break;
1935*4882a593Smuzhiyun 
1936*4882a593Smuzhiyun 		/* if all the queues are drained, we can break now */
1937*4882a593Smuzhiyun 		if (i == interface->num_tx_queues)
1938*4882a593Smuzhiyun 			break;
1939*4882a593Smuzhiyun 	}
1940*4882a593Smuzhiyun 
1941*4882a593Smuzhiyun 	if (count >= TX_DMA_DRAIN_RETRIES)
1942*4882a593Smuzhiyun 		dev_err(&interface->pdev->dev,
1943*4882a593Smuzhiyun 			"Tx queues failed to drain after %d tries. Tx DMA is probably hung.\n",
1944*4882a593Smuzhiyun 			count);
1945*4882a593Smuzhiyun skip_tx_dma_drain:
1946*4882a593Smuzhiyun 	/* Disable DMA engine for Tx/Rx */
1947*4882a593Smuzhiyun 	err = hw->mac.ops.stop_hw(hw);
1948*4882a593Smuzhiyun 	if (err == FM10K_ERR_REQUESTS_PENDING)
1949*4882a593Smuzhiyun 		dev_err(&interface->pdev->dev,
1950*4882a593Smuzhiyun 			"due to pending requests hw was not shut down gracefully\n");
1951*4882a593Smuzhiyun 	else if (err)
1952*4882a593Smuzhiyun 		dev_err(&interface->pdev->dev, "stop_hw failed: %d\n", err);
1953*4882a593Smuzhiyun 
1954*4882a593Smuzhiyun 	/* free any buffers still on the rings */
1955*4882a593Smuzhiyun 	fm10k_clean_all_tx_rings(interface);
1956*4882a593Smuzhiyun 	fm10k_clean_all_rx_rings(interface);
1957*4882a593Smuzhiyun }
1958*4882a593Smuzhiyun 
1959*4882a593Smuzhiyun /**
1960*4882a593Smuzhiyun  * fm10k_sw_init - Initialize general software structures
1961*4882a593Smuzhiyun  * @interface: host interface private structure to initialize
1962*4882a593Smuzhiyun  * @ent: PCI device ID entry
1963*4882a593Smuzhiyun  *
1964*4882a593Smuzhiyun  * fm10k_sw_init initializes the interface private data structure.
1965*4882a593Smuzhiyun  * Fields are initialized based on PCI device information and
1966*4882a593Smuzhiyun  * OS network device settings (MTU size).
1967*4882a593Smuzhiyun  **/
fm10k_sw_init(struct fm10k_intfc * interface,const struct pci_device_id * ent)1968*4882a593Smuzhiyun static int fm10k_sw_init(struct fm10k_intfc *interface,
1969*4882a593Smuzhiyun 			 const struct pci_device_id *ent)
1970*4882a593Smuzhiyun {
1971*4882a593Smuzhiyun 	const struct fm10k_info *fi = fm10k_info_tbl[ent->driver_data];
1972*4882a593Smuzhiyun 	struct fm10k_hw *hw = &interface->hw;
1973*4882a593Smuzhiyun 	struct pci_dev *pdev = interface->pdev;
1974*4882a593Smuzhiyun 	struct net_device *netdev = interface->netdev;
1975*4882a593Smuzhiyun 	u32 rss_key[FM10K_RSSRK_SIZE];
1976*4882a593Smuzhiyun 	unsigned int rss;
1977*4882a593Smuzhiyun 	int err;
1978*4882a593Smuzhiyun 
1979*4882a593Smuzhiyun 	/* initialize back pointer */
1980*4882a593Smuzhiyun 	hw->back = interface;
1981*4882a593Smuzhiyun 	hw->hw_addr = interface->uc_addr;
1982*4882a593Smuzhiyun 
1983*4882a593Smuzhiyun 	/* PCI config space info */
1984*4882a593Smuzhiyun 	hw->vendor_id = pdev->vendor;
1985*4882a593Smuzhiyun 	hw->device_id = pdev->device;
1986*4882a593Smuzhiyun 	hw->revision_id = pdev->revision;
1987*4882a593Smuzhiyun 	hw->subsystem_vendor_id = pdev->subsystem_vendor;
1988*4882a593Smuzhiyun 	hw->subsystem_device_id = pdev->subsystem_device;
1989*4882a593Smuzhiyun 
1990*4882a593Smuzhiyun 	/* Setup hw api */
1991*4882a593Smuzhiyun 	memcpy(&hw->mac.ops, fi->mac_ops, sizeof(hw->mac.ops));
1992*4882a593Smuzhiyun 	hw->mac.type = fi->mac;
1993*4882a593Smuzhiyun 
1994*4882a593Smuzhiyun 	/* Setup IOV handlers */
1995*4882a593Smuzhiyun 	if (fi->iov_ops)
1996*4882a593Smuzhiyun 		memcpy(&hw->iov.ops, fi->iov_ops, sizeof(hw->iov.ops));
1997*4882a593Smuzhiyun 
1998*4882a593Smuzhiyun 	/* Set common capability flags and settings */
1999*4882a593Smuzhiyun 	rss = min_t(int, FM10K_MAX_RSS_INDICES, num_online_cpus());
2000*4882a593Smuzhiyun 	interface->ring_feature[RING_F_RSS].limit = rss;
2001*4882a593Smuzhiyun 	fi->get_invariants(hw);
2002*4882a593Smuzhiyun 
2003*4882a593Smuzhiyun 	/* pick up the PCIe bus settings for reporting later */
2004*4882a593Smuzhiyun 	if (hw->mac.ops.get_bus_info)
2005*4882a593Smuzhiyun 		hw->mac.ops.get_bus_info(hw);
2006*4882a593Smuzhiyun 
2007*4882a593Smuzhiyun 	/* limit the usable DMA range */
2008*4882a593Smuzhiyun 	if (hw->mac.ops.set_dma_mask)
2009*4882a593Smuzhiyun 		hw->mac.ops.set_dma_mask(hw, dma_get_mask(&pdev->dev));
2010*4882a593Smuzhiyun 
2011*4882a593Smuzhiyun 	/* update netdev with DMA restrictions */
2012*4882a593Smuzhiyun 	if (dma_get_mask(&pdev->dev) > DMA_BIT_MASK(32)) {
2013*4882a593Smuzhiyun 		netdev->features |= NETIF_F_HIGHDMA;
2014*4882a593Smuzhiyun 		netdev->vlan_features |= NETIF_F_HIGHDMA;
2015*4882a593Smuzhiyun 	}
2016*4882a593Smuzhiyun 
2017*4882a593Smuzhiyun 	/* reset and initialize the hardware so it is in a known state */
2018*4882a593Smuzhiyun 	err = hw->mac.ops.reset_hw(hw);
2019*4882a593Smuzhiyun 	if (err) {
2020*4882a593Smuzhiyun 		dev_err(&pdev->dev, "reset_hw failed: %d\n", err);
2021*4882a593Smuzhiyun 		return err;
2022*4882a593Smuzhiyun 	}
2023*4882a593Smuzhiyun 
2024*4882a593Smuzhiyun 	err = hw->mac.ops.init_hw(hw);
2025*4882a593Smuzhiyun 	if (err) {
2026*4882a593Smuzhiyun 		dev_err(&pdev->dev, "init_hw failed: %d\n", err);
2027*4882a593Smuzhiyun 		return err;
2028*4882a593Smuzhiyun 	}
2029*4882a593Smuzhiyun 
2030*4882a593Smuzhiyun 	/* initialize hardware statistics */
2031*4882a593Smuzhiyun 	hw->mac.ops.update_hw_stats(hw, &interface->stats);
2032*4882a593Smuzhiyun 
2033*4882a593Smuzhiyun 	/* Set upper limit on IOV VFs that can be allocated */
2034*4882a593Smuzhiyun 	pci_sriov_set_totalvfs(pdev, hw->iov.total_vfs);
2035*4882a593Smuzhiyun 
2036*4882a593Smuzhiyun 	/* Start with random Ethernet address */
2037*4882a593Smuzhiyun 	eth_random_addr(hw->mac.addr);
2038*4882a593Smuzhiyun 
2039*4882a593Smuzhiyun 	/* Initialize MAC address from hardware */
2040*4882a593Smuzhiyun 	err = hw->mac.ops.read_mac_addr(hw);
2041*4882a593Smuzhiyun 	if (err) {
2042*4882a593Smuzhiyun 		dev_warn(&pdev->dev,
2043*4882a593Smuzhiyun 			 "Failed to obtain MAC address defaulting to random\n");
2044*4882a593Smuzhiyun 		/* tag address assignment as random */
2045*4882a593Smuzhiyun 		netdev->addr_assign_type |= NET_ADDR_RANDOM;
2046*4882a593Smuzhiyun 	}
2047*4882a593Smuzhiyun 
2048*4882a593Smuzhiyun 	ether_addr_copy(netdev->dev_addr, hw->mac.addr);
2049*4882a593Smuzhiyun 	ether_addr_copy(netdev->perm_addr, hw->mac.addr);
2050*4882a593Smuzhiyun 
2051*4882a593Smuzhiyun 	if (!is_valid_ether_addr(netdev->perm_addr)) {
2052*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Invalid MAC Address\n");
2053*4882a593Smuzhiyun 		return -EIO;
2054*4882a593Smuzhiyun 	}
2055*4882a593Smuzhiyun 
2056*4882a593Smuzhiyun 	/* initialize DCBNL interface */
2057*4882a593Smuzhiyun 	fm10k_dcbnl_set_ops(netdev);
2058*4882a593Smuzhiyun 
2059*4882a593Smuzhiyun 	/* set default ring sizes */
2060*4882a593Smuzhiyun 	interface->tx_ring_count = FM10K_DEFAULT_TXD;
2061*4882a593Smuzhiyun 	interface->rx_ring_count = FM10K_DEFAULT_RXD;
2062*4882a593Smuzhiyun 
2063*4882a593Smuzhiyun 	/* set default interrupt moderation */
2064*4882a593Smuzhiyun 	interface->tx_itr = FM10K_TX_ITR_DEFAULT;
2065*4882a593Smuzhiyun 	interface->rx_itr = FM10K_ITR_ADAPTIVE | FM10K_RX_ITR_DEFAULT;
2066*4882a593Smuzhiyun 
2067*4882a593Smuzhiyun 	/* Initialize the MAC/VLAN queue */
2068*4882a593Smuzhiyun 	INIT_LIST_HEAD(&interface->macvlan_requests);
2069*4882a593Smuzhiyun 
2070*4882a593Smuzhiyun 	netdev_rss_key_fill(rss_key, sizeof(rss_key));
2071*4882a593Smuzhiyun 	memcpy(interface->rssrk, rss_key, sizeof(rss_key));
2072*4882a593Smuzhiyun 
2073*4882a593Smuzhiyun 	/* Initialize the mailbox lock */
2074*4882a593Smuzhiyun 	spin_lock_init(&interface->mbx_lock);
2075*4882a593Smuzhiyun 	spin_lock_init(&interface->macvlan_lock);
2076*4882a593Smuzhiyun 
2077*4882a593Smuzhiyun 	/* Start off interface as being down */
2078*4882a593Smuzhiyun 	set_bit(__FM10K_DOWN, interface->state);
2079*4882a593Smuzhiyun 	set_bit(__FM10K_UPDATING_STATS, interface->state);
2080*4882a593Smuzhiyun 
2081*4882a593Smuzhiyun 	return 0;
2082*4882a593Smuzhiyun }
2083*4882a593Smuzhiyun 
2084*4882a593Smuzhiyun /**
2085*4882a593Smuzhiyun  * fm10k_probe - Device Initialization Routine
2086*4882a593Smuzhiyun  * @pdev: PCI device information struct
2087*4882a593Smuzhiyun  * @ent: entry in fm10k_pci_tbl
2088*4882a593Smuzhiyun  *
2089*4882a593Smuzhiyun  * Returns 0 on success, negative on failure
2090*4882a593Smuzhiyun  *
2091*4882a593Smuzhiyun  * fm10k_probe initializes an interface identified by a pci_dev structure.
2092*4882a593Smuzhiyun  * The OS initialization, configuring of the interface private structure,
2093*4882a593Smuzhiyun  * and a hardware reset occur.
2094*4882a593Smuzhiyun  **/
fm10k_probe(struct pci_dev * pdev,const struct pci_device_id * ent)2095*4882a593Smuzhiyun static int fm10k_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2096*4882a593Smuzhiyun {
2097*4882a593Smuzhiyun 	struct net_device *netdev;
2098*4882a593Smuzhiyun 	struct fm10k_intfc *interface;
2099*4882a593Smuzhiyun 	int err;
2100*4882a593Smuzhiyun 
2101*4882a593Smuzhiyun 	if (pdev->error_state != pci_channel_io_normal) {
2102*4882a593Smuzhiyun 		dev_err(&pdev->dev,
2103*4882a593Smuzhiyun 			"PCI device still in an error state. Unable to load...\n");
2104*4882a593Smuzhiyun 		return -EIO;
2105*4882a593Smuzhiyun 	}
2106*4882a593Smuzhiyun 
2107*4882a593Smuzhiyun 	err = pci_enable_device_mem(pdev);
2108*4882a593Smuzhiyun 	if (err) {
2109*4882a593Smuzhiyun 		dev_err(&pdev->dev,
2110*4882a593Smuzhiyun 			"PCI enable device failed: %d\n", err);
2111*4882a593Smuzhiyun 		return err;
2112*4882a593Smuzhiyun 	}
2113*4882a593Smuzhiyun 
2114*4882a593Smuzhiyun 	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48));
2115*4882a593Smuzhiyun 	if (err)
2116*4882a593Smuzhiyun 		err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2117*4882a593Smuzhiyun 	if (err) {
2118*4882a593Smuzhiyun 		dev_err(&pdev->dev,
2119*4882a593Smuzhiyun 			"DMA configuration failed: %d\n", err);
2120*4882a593Smuzhiyun 		goto err_dma;
2121*4882a593Smuzhiyun 	}
2122*4882a593Smuzhiyun 
2123*4882a593Smuzhiyun 	err = pci_request_mem_regions(pdev, fm10k_driver_name);
2124*4882a593Smuzhiyun 	if (err) {
2125*4882a593Smuzhiyun 		dev_err(&pdev->dev,
2126*4882a593Smuzhiyun 			"pci_request_selected_regions failed: %d\n", err);
2127*4882a593Smuzhiyun 		goto err_pci_reg;
2128*4882a593Smuzhiyun 	}
2129*4882a593Smuzhiyun 
2130*4882a593Smuzhiyun 	pci_enable_pcie_error_reporting(pdev);
2131*4882a593Smuzhiyun 
2132*4882a593Smuzhiyun 	pci_set_master(pdev);
2133*4882a593Smuzhiyun 	pci_save_state(pdev);
2134*4882a593Smuzhiyun 
2135*4882a593Smuzhiyun 	netdev = fm10k_alloc_netdev(fm10k_info_tbl[ent->driver_data]);
2136*4882a593Smuzhiyun 	if (!netdev) {
2137*4882a593Smuzhiyun 		err = -ENOMEM;
2138*4882a593Smuzhiyun 		goto err_alloc_netdev;
2139*4882a593Smuzhiyun 	}
2140*4882a593Smuzhiyun 
2141*4882a593Smuzhiyun 	SET_NETDEV_DEV(netdev, &pdev->dev);
2142*4882a593Smuzhiyun 
2143*4882a593Smuzhiyun 	interface = netdev_priv(netdev);
2144*4882a593Smuzhiyun 	pci_set_drvdata(pdev, interface);
2145*4882a593Smuzhiyun 
2146*4882a593Smuzhiyun 	interface->netdev = netdev;
2147*4882a593Smuzhiyun 	interface->pdev = pdev;
2148*4882a593Smuzhiyun 
2149*4882a593Smuzhiyun 	interface->uc_addr = ioremap(pci_resource_start(pdev, 0),
2150*4882a593Smuzhiyun 				     FM10K_UC_ADDR_SIZE);
2151*4882a593Smuzhiyun 	if (!interface->uc_addr) {
2152*4882a593Smuzhiyun 		err = -EIO;
2153*4882a593Smuzhiyun 		goto err_ioremap;
2154*4882a593Smuzhiyun 	}
2155*4882a593Smuzhiyun 
2156*4882a593Smuzhiyun 	err = fm10k_sw_init(interface, ent);
2157*4882a593Smuzhiyun 	if (err)
2158*4882a593Smuzhiyun 		goto err_sw_init;
2159*4882a593Smuzhiyun 
2160*4882a593Smuzhiyun 	/* enable debugfs support */
2161*4882a593Smuzhiyun 	fm10k_dbg_intfc_init(interface);
2162*4882a593Smuzhiyun 
2163*4882a593Smuzhiyun 	err = fm10k_init_queueing_scheme(interface);
2164*4882a593Smuzhiyun 	if (err)
2165*4882a593Smuzhiyun 		goto err_sw_init;
2166*4882a593Smuzhiyun 
2167*4882a593Smuzhiyun 	/* the mbx interrupt might attempt to schedule the service task, so we
2168*4882a593Smuzhiyun 	 * must ensure it is disabled since we haven't yet requested the timer
2169*4882a593Smuzhiyun 	 * or work item.
2170*4882a593Smuzhiyun 	 */
2171*4882a593Smuzhiyun 	set_bit(__FM10K_SERVICE_DISABLE, interface->state);
2172*4882a593Smuzhiyun 
2173*4882a593Smuzhiyun 	err = fm10k_mbx_request_irq(interface);
2174*4882a593Smuzhiyun 	if (err)
2175*4882a593Smuzhiyun 		goto err_mbx_interrupt;
2176*4882a593Smuzhiyun 
2177*4882a593Smuzhiyun 	/* final check of hardware state before registering the interface */
2178*4882a593Smuzhiyun 	err = fm10k_hw_ready(interface);
2179*4882a593Smuzhiyun 	if (err)
2180*4882a593Smuzhiyun 		goto err_register;
2181*4882a593Smuzhiyun 
2182*4882a593Smuzhiyun 	err = register_netdev(netdev);
2183*4882a593Smuzhiyun 	if (err)
2184*4882a593Smuzhiyun 		goto err_register;
2185*4882a593Smuzhiyun 
2186*4882a593Smuzhiyun 	/* carrier off reporting is important to ethtool even BEFORE open */
2187*4882a593Smuzhiyun 	netif_carrier_off(netdev);
2188*4882a593Smuzhiyun 
2189*4882a593Smuzhiyun 	/* stop all the transmit queues from transmitting until link is up */
2190*4882a593Smuzhiyun 	netif_tx_stop_all_queues(netdev);
2191*4882a593Smuzhiyun 
2192*4882a593Smuzhiyun 	/* Initialize service timer and service task late in order to avoid
2193*4882a593Smuzhiyun 	 * cleanup issues.
2194*4882a593Smuzhiyun 	 */
2195*4882a593Smuzhiyun 	timer_setup(&interface->service_timer, fm10k_service_timer, 0);
2196*4882a593Smuzhiyun 	INIT_WORK(&interface->service_task, fm10k_service_task);
2197*4882a593Smuzhiyun 
2198*4882a593Smuzhiyun 	/* Setup the MAC/VLAN queue */
2199*4882a593Smuzhiyun 	INIT_DELAYED_WORK(&interface->macvlan_task, fm10k_macvlan_task);
2200*4882a593Smuzhiyun 
2201*4882a593Smuzhiyun 	/* kick off service timer now, even when interface is down */
2202*4882a593Smuzhiyun 	mod_timer(&interface->service_timer, (HZ * 2) + jiffies);
2203*4882a593Smuzhiyun 
2204*4882a593Smuzhiyun 	/* print warning for non-optimal configurations */
2205*4882a593Smuzhiyun 	pcie_print_link_status(interface->pdev);
2206*4882a593Smuzhiyun 
2207*4882a593Smuzhiyun 	/* report MAC address for logging */
2208*4882a593Smuzhiyun 	dev_info(&pdev->dev, "%pM\n", netdev->dev_addr);
2209*4882a593Smuzhiyun 
2210*4882a593Smuzhiyun 	/* enable SR-IOV after registering netdev to enforce PF/VF ordering */
2211*4882a593Smuzhiyun 	fm10k_iov_configure(pdev, 0);
2212*4882a593Smuzhiyun 
2213*4882a593Smuzhiyun 	/* clear the service task disable bit and kick off service task */
2214*4882a593Smuzhiyun 	clear_bit(__FM10K_SERVICE_DISABLE, interface->state);
2215*4882a593Smuzhiyun 	fm10k_service_event_schedule(interface);
2216*4882a593Smuzhiyun 
2217*4882a593Smuzhiyun 	return 0;
2218*4882a593Smuzhiyun 
2219*4882a593Smuzhiyun err_register:
2220*4882a593Smuzhiyun 	fm10k_mbx_free_irq(interface);
2221*4882a593Smuzhiyun err_mbx_interrupt:
2222*4882a593Smuzhiyun 	fm10k_clear_queueing_scheme(interface);
2223*4882a593Smuzhiyun err_sw_init:
2224*4882a593Smuzhiyun 	if (interface->sw_addr)
2225*4882a593Smuzhiyun 		iounmap(interface->sw_addr);
2226*4882a593Smuzhiyun 	iounmap(interface->uc_addr);
2227*4882a593Smuzhiyun err_ioremap:
2228*4882a593Smuzhiyun 	free_netdev(netdev);
2229*4882a593Smuzhiyun err_alloc_netdev:
2230*4882a593Smuzhiyun 	pci_disable_pcie_error_reporting(pdev);
2231*4882a593Smuzhiyun 	pci_release_mem_regions(pdev);
2232*4882a593Smuzhiyun err_pci_reg:
2233*4882a593Smuzhiyun err_dma:
2234*4882a593Smuzhiyun 	pci_disable_device(pdev);
2235*4882a593Smuzhiyun 	return err;
2236*4882a593Smuzhiyun }
2237*4882a593Smuzhiyun 
2238*4882a593Smuzhiyun /**
2239*4882a593Smuzhiyun  * fm10k_remove - Device Removal Routine
2240*4882a593Smuzhiyun  * @pdev: PCI device information struct
2241*4882a593Smuzhiyun  *
2242*4882a593Smuzhiyun  * fm10k_remove is called by the PCI subsystem to alert the driver
2243*4882a593Smuzhiyun  * that it should release a PCI device.  The could be caused by a
2244*4882a593Smuzhiyun  * Hot-Plug event, or because the driver is going to be removed from
2245*4882a593Smuzhiyun  * memory.
2246*4882a593Smuzhiyun  **/
fm10k_remove(struct pci_dev * pdev)2247*4882a593Smuzhiyun static void fm10k_remove(struct pci_dev *pdev)
2248*4882a593Smuzhiyun {
2249*4882a593Smuzhiyun 	struct fm10k_intfc *interface = pci_get_drvdata(pdev);
2250*4882a593Smuzhiyun 	struct net_device *netdev = interface->netdev;
2251*4882a593Smuzhiyun 
2252*4882a593Smuzhiyun 	del_timer_sync(&interface->service_timer);
2253*4882a593Smuzhiyun 
2254*4882a593Smuzhiyun 	fm10k_stop_service_event(interface);
2255*4882a593Smuzhiyun 	fm10k_stop_macvlan_task(interface);
2256*4882a593Smuzhiyun 
2257*4882a593Smuzhiyun 	/* Remove all pending MAC/VLAN requests */
2258*4882a593Smuzhiyun 	fm10k_clear_macvlan_queue(interface, interface->glort, true);
2259*4882a593Smuzhiyun 
2260*4882a593Smuzhiyun 	/* free netdev, this may bounce the interrupts due to setup_tc */
2261*4882a593Smuzhiyun 	if (netdev->reg_state == NETREG_REGISTERED)
2262*4882a593Smuzhiyun 		unregister_netdev(netdev);
2263*4882a593Smuzhiyun 
2264*4882a593Smuzhiyun 	/* release VFs */
2265*4882a593Smuzhiyun 	fm10k_iov_disable(pdev);
2266*4882a593Smuzhiyun 
2267*4882a593Smuzhiyun 	/* disable mailbox interrupt */
2268*4882a593Smuzhiyun 	fm10k_mbx_free_irq(interface);
2269*4882a593Smuzhiyun 
2270*4882a593Smuzhiyun 	/* free interrupts */
2271*4882a593Smuzhiyun 	fm10k_clear_queueing_scheme(interface);
2272*4882a593Smuzhiyun 
2273*4882a593Smuzhiyun 	/* remove any debugfs interfaces */
2274*4882a593Smuzhiyun 	fm10k_dbg_intfc_exit(interface);
2275*4882a593Smuzhiyun 
2276*4882a593Smuzhiyun 	if (interface->sw_addr)
2277*4882a593Smuzhiyun 		iounmap(interface->sw_addr);
2278*4882a593Smuzhiyun 	iounmap(interface->uc_addr);
2279*4882a593Smuzhiyun 
2280*4882a593Smuzhiyun 	free_netdev(netdev);
2281*4882a593Smuzhiyun 
2282*4882a593Smuzhiyun 	pci_release_mem_regions(pdev);
2283*4882a593Smuzhiyun 
2284*4882a593Smuzhiyun 	pci_disable_pcie_error_reporting(pdev);
2285*4882a593Smuzhiyun 
2286*4882a593Smuzhiyun 	pci_disable_device(pdev);
2287*4882a593Smuzhiyun }
2288*4882a593Smuzhiyun 
fm10k_prepare_suspend(struct fm10k_intfc * interface)2289*4882a593Smuzhiyun static void fm10k_prepare_suspend(struct fm10k_intfc *interface)
2290*4882a593Smuzhiyun {
2291*4882a593Smuzhiyun 	/* the watchdog task reads from registers, which might appear like
2292*4882a593Smuzhiyun 	 * a surprise remove if the PCIe device is disabled while we're
2293*4882a593Smuzhiyun 	 * stopped. We stop the watchdog task until after we resume software
2294*4882a593Smuzhiyun 	 * activity.
2295*4882a593Smuzhiyun 	 *
2296*4882a593Smuzhiyun 	 * Note that the MAC/VLAN task will be stopped as part of preparing
2297*4882a593Smuzhiyun 	 * for reset so we don't need to handle it here.
2298*4882a593Smuzhiyun 	 */
2299*4882a593Smuzhiyun 	fm10k_stop_service_event(interface);
2300*4882a593Smuzhiyun 
2301*4882a593Smuzhiyun 	if (fm10k_prepare_for_reset(interface))
2302*4882a593Smuzhiyun 		set_bit(__FM10K_RESET_SUSPENDED, interface->state);
2303*4882a593Smuzhiyun }
2304*4882a593Smuzhiyun 
fm10k_handle_resume(struct fm10k_intfc * interface)2305*4882a593Smuzhiyun static int fm10k_handle_resume(struct fm10k_intfc *interface)
2306*4882a593Smuzhiyun {
2307*4882a593Smuzhiyun 	struct fm10k_hw *hw = &interface->hw;
2308*4882a593Smuzhiyun 	int err;
2309*4882a593Smuzhiyun 
2310*4882a593Smuzhiyun 	/* Even if we didn't properly prepare for reset in
2311*4882a593Smuzhiyun 	 * fm10k_prepare_suspend, we'll attempt to resume anyways.
2312*4882a593Smuzhiyun 	 */
2313*4882a593Smuzhiyun 	if (!test_and_clear_bit(__FM10K_RESET_SUSPENDED, interface->state))
2314*4882a593Smuzhiyun 		dev_warn(&interface->pdev->dev,
2315*4882a593Smuzhiyun 			 "Device was shut down as part of suspend... Attempting to recover\n");
2316*4882a593Smuzhiyun 
2317*4882a593Smuzhiyun 	/* reset statistics starting values */
2318*4882a593Smuzhiyun 	hw->mac.ops.rebind_hw_stats(hw, &interface->stats);
2319*4882a593Smuzhiyun 
2320*4882a593Smuzhiyun 	err = fm10k_handle_reset(interface);
2321*4882a593Smuzhiyun 	if (err)
2322*4882a593Smuzhiyun 		return err;
2323*4882a593Smuzhiyun 
2324*4882a593Smuzhiyun 	/* assume host is not ready, to prevent race with watchdog in case we
2325*4882a593Smuzhiyun 	 * actually don't have connection to the switch
2326*4882a593Smuzhiyun 	 */
2327*4882a593Smuzhiyun 	interface->host_ready = false;
2328*4882a593Smuzhiyun 	fm10k_watchdog_host_not_ready(interface);
2329*4882a593Smuzhiyun 
2330*4882a593Smuzhiyun 	/* force link to stay down for a second to prevent link flutter */
2331*4882a593Smuzhiyun 	interface->link_down_event = jiffies + (HZ);
2332*4882a593Smuzhiyun 	set_bit(__FM10K_LINK_DOWN, interface->state);
2333*4882a593Smuzhiyun 
2334*4882a593Smuzhiyun 	/* restart the service task */
2335*4882a593Smuzhiyun 	fm10k_start_service_event(interface);
2336*4882a593Smuzhiyun 
2337*4882a593Smuzhiyun 	/* Restart the MAC/VLAN request queue in-case of outstanding events */
2338*4882a593Smuzhiyun 	fm10k_macvlan_schedule(interface);
2339*4882a593Smuzhiyun 
2340*4882a593Smuzhiyun 	return 0;
2341*4882a593Smuzhiyun }
2342*4882a593Smuzhiyun 
2343*4882a593Smuzhiyun /**
2344*4882a593Smuzhiyun  * fm10k_resume - Generic PM resume hook
2345*4882a593Smuzhiyun  * @dev: generic device structure
2346*4882a593Smuzhiyun  *
2347*4882a593Smuzhiyun  * Generic PM hook used when waking the device from a low power state after
2348*4882a593Smuzhiyun  * suspend or hibernation. This function does not need to handle lower PCIe
2349*4882a593Smuzhiyun  * device state as the stack takes care of that for us.
2350*4882a593Smuzhiyun  **/
fm10k_resume(struct device * dev)2351*4882a593Smuzhiyun static int __maybe_unused fm10k_resume(struct device *dev)
2352*4882a593Smuzhiyun {
2353*4882a593Smuzhiyun 	struct fm10k_intfc *interface = dev_get_drvdata(dev);
2354*4882a593Smuzhiyun 	struct net_device *netdev = interface->netdev;
2355*4882a593Smuzhiyun 	struct fm10k_hw *hw = &interface->hw;
2356*4882a593Smuzhiyun 	int err;
2357*4882a593Smuzhiyun 
2358*4882a593Smuzhiyun 	/* refresh hw_addr in case it was dropped */
2359*4882a593Smuzhiyun 	hw->hw_addr = interface->uc_addr;
2360*4882a593Smuzhiyun 
2361*4882a593Smuzhiyun 	err = fm10k_handle_resume(interface);
2362*4882a593Smuzhiyun 	if (err)
2363*4882a593Smuzhiyun 		return err;
2364*4882a593Smuzhiyun 
2365*4882a593Smuzhiyun 	netif_device_attach(netdev);
2366*4882a593Smuzhiyun 
2367*4882a593Smuzhiyun 	return 0;
2368*4882a593Smuzhiyun }
2369*4882a593Smuzhiyun 
2370*4882a593Smuzhiyun /**
2371*4882a593Smuzhiyun  * fm10k_suspend - Generic PM suspend hook
2372*4882a593Smuzhiyun  * @dev: generic device structure
2373*4882a593Smuzhiyun  *
2374*4882a593Smuzhiyun  * Generic PM hook used when setting the device into a low power state for
2375*4882a593Smuzhiyun  * system suspend or hibernation. This function does not need to handle lower
2376*4882a593Smuzhiyun  * PCIe device state as the stack takes care of that for us.
2377*4882a593Smuzhiyun  **/
fm10k_suspend(struct device * dev)2378*4882a593Smuzhiyun static int __maybe_unused fm10k_suspend(struct device *dev)
2379*4882a593Smuzhiyun {
2380*4882a593Smuzhiyun 	struct fm10k_intfc *interface = dev_get_drvdata(dev);
2381*4882a593Smuzhiyun 	struct net_device *netdev = interface->netdev;
2382*4882a593Smuzhiyun 
2383*4882a593Smuzhiyun 	netif_device_detach(netdev);
2384*4882a593Smuzhiyun 
2385*4882a593Smuzhiyun 	fm10k_prepare_suspend(interface);
2386*4882a593Smuzhiyun 
2387*4882a593Smuzhiyun 	return 0;
2388*4882a593Smuzhiyun }
2389*4882a593Smuzhiyun 
2390*4882a593Smuzhiyun /**
2391*4882a593Smuzhiyun  * fm10k_io_error_detected - called when PCI error is detected
2392*4882a593Smuzhiyun  * @pdev: Pointer to PCI device
2393*4882a593Smuzhiyun  * @state: The current pci connection state
2394*4882a593Smuzhiyun  *
2395*4882a593Smuzhiyun  * This function is called after a PCI bus error affecting
2396*4882a593Smuzhiyun  * this device has been detected.
2397*4882a593Smuzhiyun  */
fm10k_io_error_detected(struct pci_dev * pdev,pci_channel_state_t state)2398*4882a593Smuzhiyun static pci_ers_result_t fm10k_io_error_detected(struct pci_dev *pdev,
2399*4882a593Smuzhiyun 						pci_channel_state_t state)
2400*4882a593Smuzhiyun {
2401*4882a593Smuzhiyun 	struct fm10k_intfc *interface = pci_get_drvdata(pdev);
2402*4882a593Smuzhiyun 	struct net_device *netdev = interface->netdev;
2403*4882a593Smuzhiyun 
2404*4882a593Smuzhiyun 	netif_device_detach(netdev);
2405*4882a593Smuzhiyun 
2406*4882a593Smuzhiyun 	if (state == pci_channel_io_perm_failure)
2407*4882a593Smuzhiyun 		return PCI_ERS_RESULT_DISCONNECT;
2408*4882a593Smuzhiyun 
2409*4882a593Smuzhiyun 	fm10k_prepare_suspend(interface);
2410*4882a593Smuzhiyun 
2411*4882a593Smuzhiyun 	/* Request a slot reset. */
2412*4882a593Smuzhiyun 	return PCI_ERS_RESULT_NEED_RESET;
2413*4882a593Smuzhiyun }
2414*4882a593Smuzhiyun 
2415*4882a593Smuzhiyun /**
2416*4882a593Smuzhiyun  * fm10k_io_slot_reset - called after the pci bus has been reset.
2417*4882a593Smuzhiyun  * @pdev: Pointer to PCI device
2418*4882a593Smuzhiyun  *
2419*4882a593Smuzhiyun  * Restart the card from scratch, as if from a cold-boot.
2420*4882a593Smuzhiyun  */
fm10k_io_slot_reset(struct pci_dev * pdev)2421*4882a593Smuzhiyun static pci_ers_result_t fm10k_io_slot_reset(struct pci_dev *pdev)
2422*4882a593Smuzhiyun {
2423*4882a593Smuzhiyun 	pci_ers_result_t result;
2424*4882a593Smuzhiyun 
2425*4882a593Smuzhiyun 	if (pci_reenable_device(pdev)) {
2426*4882a593Smuzhiyun 		dev_err(&pdev->dev,
2427*4882a593Smuzhiyun 			"Cannot re-enable PCI device after reset.\n");
2428*4882a593Smuzhiyun 		result = PCI_ERS_RESULT_DISCONNECT;
2429*4882a593Smuzhiyun 	} else {
2430*4882a593Smuzhiyun 		pci_set_master(pdev);
2431*4882a593Smuzhiyun 		pci_restore_state(pdev);
2432*4882a593Smuzhiyun 
2433*4882a593Smuzhiyun 		/* After second error pci->state_saved is false, this
2434*4882a593Smuzhiyun 		 * resets it so EEH doesn't break.
2435*4882a593Smuzhiyun 		 */
2436*4882a593Smuzhiyun 		pci_save_state(pdev);
2437*4882a593Smuzhiyun 
2438*4882a593Smuzhiyun 		pci_wake_from_d3(pdev, false);
2439*4882a593Smuzhiyun 
2440*4882a593Smuzhiyun 		result = PCI_ERS_RESULT_RECOVERED;
2441*4882a593Smuzhiyun 	}
2442*4882a593Smuzhiyun 
2443*4882a593Smuzhiyun 	return result;
2444*4882a593Smuzhiyun }
2445*4882a593Smuzhiyun 
2446*4882a593Smuzhiyun /**
2447*4882a593Smuzhiyun  * fm10k_io_resume - called when traffic can start flowing again.
2448*4882a593Smuzhiyun  * @pdev: Pointer to PCI device
2449*4882a593Smuzhiyun  *
2450*4882a593Smuzhiyun  * This callback is called when the error recovery driver tells us that
2451*4882a593Smuzhiyun  * its OK to resume normal operation.
2452*4882a593Smuzhiyun  */
fm10k_io_resume(struct pci_dev * pdev)2453*4882a593Smuzhiyun static void fm10k_io_resume(struct pci_dev *pdev)
2454*4882a593Smuzhiyun {
2455*4882a593Smuzhiyun 	struct fm10k_intfc *interface = pci_get_drvdata(pdev);
2456*4882a593Smuzhiyun 	struct net_device *netdev = interface->netdev;
2457*4882a593Smuzhiyun 	int err;
2458*4882a593Smuzhiyun 
2459*4882a593Smuzhiyun 	err = fm10k_handle_resume(interface);
2460*4882a593Smuzhiyun 
2461*4882a593Smuzhiyun 	if (err)
2462*4882a593Smuzhiyun 		dev_warn(&pdev->dev,
2463*4882a593Smuzhiyun 			 "%s failed: %d\n", __func__, err);
2464*4882a593Smuzhiyun 	else
2465*4882a593Smuzhiyun 		netif_device_attach(netdev);
2466*4882a593Smuzhiyun }
2467*4882a593Smuzhiyun 
2468*4882a593Smuzhiyun /**
2469*4882a593Smuzhiyun  * fm10k_io_reset_prepare - called when PCI function is about to be reset
2470*4882a593Smuzhiyun  * @pdev: Pointer to PCI device
2471*4882a593Smuzhiyun  *
2472*4882a593Smuzhiyun  * This callback is called when the PCI function is about to be reset,
2473*4882a593Smuzhiyun  * allowing the device driver to prepare for it.
2474*4882a593Smuzhiyun  */
fm10k_io_reset_prepare(struct pci_dev * pdev)2475*4882a593Smuzhiyun static void fm10k_io_reset_prepare(struct pci_dev *pdev)
2476*4882a593Smuzhiyun {
2477*4882a593Smuzhiyun 	/* warn incase we have any active VF devices */
2478*4882a593Smuzhiyun 	if (pci_num_vf(pdev))
2479*4882a593Smuzhiyun 		dev_warn(&pdev->dev,
2480*4882a593Smuzhiyun 			 "PCIe FLR may cause issues for any active VF devices\n");
2481*4882a593Smuzhiyun 	fm10k_prepare_suspend(pci_get_drvdata(pdev));
2482*4882a593Smuzhiyun }
2483*4882a593Smuzhiyun 
2484*4882a593Smuzhiyun /**
2485*4882a593Smuzhiyun  * fm10k_io_reset_done - called when PCI function has finished resetting
2486*4882a593Smuzhiyun  * @pdev: Pointer to PCI device
2487*4882a593Smuzhiyun  *
2488*4882a593Smuzhiyun  * This callback is called just after the PCI function is reset, such as via
2489*4882a593Smuzhiyun  * /sys/class/net/<enpX>/device/reset or similar.
2490*4882a593Smuzhiyun  */
fm10k_io_reset_done(struct pci_dev * pdev)2491*4882a593Smuzhiyun static void fm10k_io_reset_done(struct pci_dev *pdev)
2492*4882a593Smuzhiyun {
2493*4882a593Smuzhiyun 	struct fm10k_intfc *interface = pci_get_drvdata(pdev);
2494*4882a593Smuzhiyun 	int err = fm10k_handle_resume(interface);
2495*4882a593Smuzhiyun 
2496*4882a593Smuzhiyun 	if (err) {
2497*4882a593Smuzhiyun 		dev_warn(&pdev->dev,
2498*4882a593Smuzhiyun 			 "%s failed: %d\n", __func__, err);
2499*4882a593Smuzhiyun 		netif_device_detach(interface->netdev);
2500*4882a593Smuzhiyun 	}
2501*4882a593Smuzhiyun }
2502*4882a593Smuzhiyun 
2503*4882a593Smuzhiyun static const struct pci_error_handlers fm10k_err_handler = {
2504*4882a593Smuzhiyun 	.error_detected = fm10k_io_error_detected,
2505*4882a593Smuzhiyun 	.slot_reset = fm10k_io_slot_reset,
2506*4882a593Smuzhiyun 	.resume = fm10k_io_resume,
2507*4882a593Smuzhiyun 	.reset_prepare = fm10k_io_reset_prepare,
2508*4882a593Smuzhiyun 	.reset_done = fm10k_io_reset_done,
2509*4882a593Smuzhiyun };
2510*4882a593Smuzhiyun 
2511*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(fm10k_pm_ops, fm10k_suspend, fm10k_resume);
2512*4882a593Smuzhiyun 
2513*4882a593Smuzhiyun static struct pci_driver fm10k_driver = {
2514*4882a593Smuzhiyun 	.name			= fm10k_driver_name,
2515*4882a593Smuzhiyun 	.id_table		= fm10k_pci_tbl,
2516*4882a593Smuzhiyun 	.probe			= fm10k_probe,
2517*4882a593Smuzhiyun 	.remove			= fm10k_remove,
2518*4882a593Smuzhiyun 	.driver = {
2519*4882a593Smuzhiyun 		.pm		= &fm10k_pm_ops,
2520*4882a593Smuzhiyun 	},
2521*4882a593Smuzhiyun 	.sriov_configure	= fm10k_iov_configure,
2522*4882a593Smuzhiyun 	.err_handler		= &fm10k_err_handler
2523*4882a593Smuzhiyun };
2524*4882a593Smuzhiyun 
2525*4882a593Smuzhiyun /**
2526*4882a593Smuzhiyun  * fm10k_register_pci_driver - register driver interface
2527*4882a593Smuzhiyun  *
2528*4882a593Smuzhiyun  * This function is called on module load in order to register the driver.
2529*4882a593Smuzhiyun  **/
fm10k_register_pci_driver(void)2530*4882a593Smuzhiyun int fm10k_register_pci_driver(void)
2531*4882a593Smuzhiyun {
2532*4882a593Smuzhiyun 	return pci_register_driver(&fm10k_driver);
2533*4882a593Smuzhiyun }
2534*4882a593Smuzhiyun 
2535*4882a593Smuzhiyun /**
2536*4882a593Smuzhiyun  * fm10k_unregister_pci_driver - unregister driver interface
2537*4882a593Smuzhiyun  *
2538*4882a593Smuzhiyun  * This function is called on module unload in order to remove the driver.
2539*4882a593Smuzhiyun  **/
fm10k_unregister_pci_driver(void)2540*4882a593Smuzhiyun void fm10k_unregister_pci_driver(void)
2541*4882a593Smuzhiyun {
2542*4882a593Smuzhiyun 	pci_unregister_driver(&fm10k_driver);
2543*4882a593Smuzhiyun }
2544