1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _E1000E_MANAGE_H_ 5*4882a593Smuzhiyun #define _E1000E_MANAGE_H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun bool e1000e_check_mng_mode_generic(struct e1000_hw *hw); 8*4882a593Smuzhiyun bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw); 9*4882a593Smuzhiyun s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length); 10*4882a593Smuzhiyun bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw); 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun enum e1000_mng_mode { 13*4882a593Smuzhiyun e1000_mng_mode_none = 0, 14*4882a593Smuzhiyun e1000_mng_mode_asf, 15*4882a593Smuzhiyun e1000_mng_mode_pt, 16*4882a593Smuzhiyun e1000_mng_mode_ipmi, 17*4882a593Smuzhiyun e1000_mng_mode_host_if_only 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define E1000_FACTPS_MNGCG 0x20000000 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define E1000_FWSM_MODE_MASK 0xE 23*4882a593Smuzhiyun #define E1000_FWSM_MODE_SHIFT 1 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define E1000_MNG_IAMT_MODE 0x3 26*4882a593Smuzhiyun #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 27*4882a593Smuzhiyun #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 28*4882a593Smuzhiyun #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 29*4882a593Smuzhiyun #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 30*4882a593Smuzhiyun #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1 31*4882a593Smuzhiyun #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN 0x2 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define E1000_VFTA_ENTRY_SHIFT 5 34*4882a593Smuzhiyun #define E1000_VFTA_ENTRY_MASK 0x7F 35*4882a593Smuzhiyun #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define E1000_HICR_EN 0x01 /* Enable bit - RO */ 38*4882a593Smuzhiyun /* Driver sets this bit when done to put command in RAM */ 39*4882a593Smuzhiyun #define E1000_HICR_C 0x02 40*4882a593Smuzhiyun #define E1000_HICR_SV 0x04 /* Status Validity */ 41*4882a593Smuzhiyun #define E1000_HICR_FW_RESET_ENABLE 0x40 42*4882a593Smuzhiyun #define E1000_HICR_FW_RESET 0x80 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Intel(R) Active Management Technology signature */ 45*4882a593Smuzhiyun #define E1000_IAMT_SIGNATURE 0x544D4149 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #endif 48