1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _E1000E_MAC_H_ 5*4882a593Smuzhiyun #define _E1000E_MAC_H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun s32 e1000e_blink_led_generic(struct e1000_hw *hw); 8*4882a593Smuzhiyun s32 e1000e_check_for_copper_link(struct e1000_hw *hw); 9*4882a593Smuzhiyun s32 e1000e_check_for_fiber_link(struct e1000_hw *hw); 10*4882a593Smuzhiyun s32 e1000e_check_for_serdes_link(struct e1000_hw *hw); 11*4882a593Smuzhiyun s32 e1000e_cleanup_led_generic(struct e1000_hw *hw); 12*4882a593Smuzhiyun s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw); 13*4882a593Smuzhiyun s32 e1000e_disable_pcie_master(struct e1000_hw *hw); 14*4882a593Smuzhiyun s32 e1000e_force_mac_fc(struct e1000_hw *hw); 15*4882a593Smuzhiyun s32 e1000e_get_auto_rd_done(struct e1000_hw *hw); 16*4882a593Smuzhiyun s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw); 17*4882a593Smuzhiyun void e1000_set_lan_id_single_port(struct e1000_hw *hw); 18*4882a593Smuzhiyun s32 e1000e_get_hw_semaphore(struct e1000_hw *hw); 19*4882a593Smuzhiyun s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, 20*4882a593Smuzhiyun u16 *duplex); 21*4882a593Smuzhiyun s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, 22*4882a593Smuzhiyun u16 *speed, u16 *duplex); 23*4882a593Smuzhiyun s32 e1000e_id_led_init_generic(struct e1000_hw *hw); 24*4882a593Smuzhiyun s32 e1000e_led_on_generic(struct e1000_hw *hw); 25*4882a593Smuzhiyun s32 e1000e_led_off_generic(struct e1000_hw *hw); 26*4882a593Smuzhiyun void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw, 27*4882a593Smuzhiyun u8 *mc_addr_list, u32 mc_addr_count); 28*4882a593Smuzhiyun s32 e1000e_set_fc_watermarks(struct e1000_hw *hw); 29*4882a593Smuzhiyun s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw); 30*4882a593Smuzhiyun s32 e1000e_setup_led_generic(struct e1000_hw *hw); 31*4882a593Smuzhiyun s32 e1000e_setup_link_generic(struct e1000_hw *hw); 32*4882a593Smuzhiyun s32 e1000e_validate_mdi_setting_generic(struct e1000_hw *hw); 33*4882a593Smuzhiyun s32 e1000e_validate_mdi_setting_crossover_generic(struct e1000_hw *hw); 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw); 36*4882a593Smuzhiyun void e1000_clear_vfta_generic(struct e1000_hw *hw); 37*4882a593Smuzhiyun void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count); 38*4882a593Smuzhiyun void e1000e_put_hw_semaphore(struct e1000_hw *hw); 39*4882a593Smuzhiyun s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw); 40*4882a593Smuzhiyun void e1000e_reset_adaptive(struct e1000_hw *hw); 41*4882a593Smuzhiyun void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop); 42*4882a593Smuzhiyun void e1000e_update_adaptive(struct e1000_hw *hw); 43*4882a593Smuzhiyun void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value); 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 46*4882a593Smuzhiyun u32 e1000e_rar_get_count_generic(struct e1000_hw *hw); 47*4882a593Smuzhiyun int e1000e_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index); 48*4882a593Smuzhiyun void e1000e_config_collision_dist_generic(struct e1000_hw *hw); 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #endif 51