1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _E1000E_82571_H_ 5*4882a593Smuzhiyun #define _E1000E_82571_H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define ID_LED_RESERVED_F746 0xF746 8*4882a593Smuzhiyun #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \ 9*4882a593Smuzhiyun (ID_LED_OFF1_ON2 << 8) | \ 10*4882a593Smuzhiyun (ID_LED_DEF1_DEF2 << 4) | \ 11*4882a593Smuzhiyun (ID_LED_DEF1_DEF2)) 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 14*4882a593Smuzhiyun #define AN_RETRY_COUNT 5 /* Autoneg Retry Count value */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Intr Throttling - RW */ 17*4882a593Smuzhiyun #define E1000_EITR_82574(_n) (0x000E8 + (0x4 * (_n))) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define E1000_EIAC_82574 0x000DC /* Ext. Interrupt Auto Clear - RW */ 20*4882a593Smuzhiyun #define E1000_EIAC_MASK_82574 0x01F00000 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define E1000_IVAR_INT_ALLOC_VALID 0x8 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* Manageability Operation Mode mask */ 25*4882a593Smuzhiyun #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define E1000_BASE1000T_STATUS 10 28*4882a593Smuzhiyun #define E1000_IDLE_ERROR_COUNT_MASK 0xFF 29*4882a593Smuzhiyun #define E1000_RECEIVE_ERROR_COUNTER 21 30*4882a593Smuzhiyun #define E1000_RECEIVE_ERROR_MAX 0xFFFF 31*4882a593Smuzhiyun bool e1000_check_phy_82574(struct e1000_hw *hw); 32*4882a593Smuzhiyun bool e1000e_get_laa_state_82571(struct e1000_hw *hw); 33*4882a593Smuzhiyun void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state); 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #endif 36