1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef _E1000E_80003ES2LAN_H_ 5*4882a593Smuzhiyun #define _E1000E_80003ES2LAN_H_ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00 8*4882a593Smuzhiyun #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02 9*4882a593Smuzhiyun #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10 10*4882a593Smuzhiyun #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008 13*4882a593Smuzhiyun #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800 14*4882a593Smuzhiyun #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004 17*4882a593Smuzhiyun #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000 18*4882a593Smuzhiyun #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C 21*4882a593Smuzhiyun #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gig Carry Extend Padding */ 24*4882a593Smuzhiyun #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8 27*4882a593Smuzhiyun #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* GG82563 PHY Specific Status Register (Page 0, Register 16 */ 30*4882a593Smuzhiyun #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Dis */ 31*4882a593Smuzhiyun #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 32*4882a593Smuzhiyun #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */ 33*4882a593Smuzhiyun #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */ 34*4882a593Smuzhiyun #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* PHY Specific Control Register 2 (Page 0, Register 26) */ 37*4882a593Smuzhiyun #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Neg */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* MAC Specific Control Register (Page 2, Register 21) */ 40*4882a593Smuzhiyun /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ 41*4882a593Smuzhiyun #define GG82563_MSCR_TX_CLK_MASK 0x0007 42*4882a593Smuzhiyun #define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004 43*4882a593Smuzhiyun #define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005 44*4882a593Smuzhiyun #define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* DSP Distance Register (Page 5, Register 26) 49*4882a593Smuzhiyun * 0 = <50M 50*4882a593Smuzhiyun * 1 = 50-80M 51*4882a593Smuzhiyun * 2 = 80-100M 52*4882a593Smuzhiyun * 3 = 110-140M 53*4882a593Smuzhiyun * 4 = >140M 54*4882a593Smuzhiyun */ 55*4882a593Smuzhiyun #define GG82563_DSPD_CABLE_LENGTH 0x0007 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* Kumeran Mode Control Register (Page 193, Register 16) */ 58*4882a593Smuzhiyun #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* Max number of times Kumeran read/write should be validated */ 61*4882a593Smuzhiyun #define GG82563_MAX_KMRN_RETRY 0x5 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* Power Management Control Register (Page 193, Register 20) */ 64*4882a593Smuzhiyun /* 1=Enable SERDES Electrical Idle */ 65*4882a593Smuzhiyun #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* In-Band Control Register (Page 194, Register 18) */ 68*4882a593Smuzhiyun #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */ 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #endif 71