1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * linux/drivers/net/ethernet/ibm/ehea/ehea.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * eHEA ethernet device driver for IBM eServer System p 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * (C) Copyright IBM Corp. 2006 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Authors: 10*4882a593Smuzhiyun * Christoph Raisch <raisch@de.ibm.com> 11*4882a593Smuzhiyun * Jan-Bernd Themann <themann@de.ibm.com> 12*4882a593Smuzhiyun * Thomas Klein <tklein@de.ibm.com> 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef __EHEA_H__ 16*4882a593Smuzhiyun #define __EHEA_H__ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #include <linux/module.h> 19*4882a593Smuzhiyun #include <linux/ethtool.h> 20*4882a593Smuzhiyun #include <linux/vmalloc.h> 21*4882a593Smuzhiyun #include <linux/if_vlan.h> 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #include <asm/ibmebus.h> 24*4882a593Smuzhiyun #include <asm/io.h> 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define DRV_NAME "ehea" 27*4882a593Smuzhiyun #define DRV_VERSION "EHEA_0107" 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* eHEA capability flags */ 30*4882a593Smuzhiyun #define DLPAR_PORT_ADD_REM 1 31*4882a593Smuzhiyun #define DLPAR_MEM_ADD 2 32*4882a593Smuzhiyun #define DLPAR_MEM_REM 4 33*4882a593Smuzhiyun #define EHEA_CAPABILITIES (DLPAR_PORT_ADD_REM | DLPAR_MEM_ADD | DLPAR_MEM_REM) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define EHEA_MSG_DEFAULT (NETIF_MSG_LINK | NETIF_MSG_TIMER \ 36*4882a593Smuzhiyun | NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define EHEA_MAX_ENTRIES_RQ1 32767 39*4882a593Smuzhiyun #define EHEA_MAX_ENTRIES_RQ2 16383 40*4882a593Smuzhiyun #define EHEA_MAX_ENTRIES_RQ3 16383 41*4882a593Smuzhiyun #define EHEA_MAX_ENTRIES_SQ 32767 42*4882a593Smuzhiyun #define EHEA_MIN_ENTRIES_QP 127 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define EHEA_SMALL_QUEUES 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #ifdef EHEA_SMALL_QUEUES 47*4882a593Smuzhiyun #define EHEA_MAX_CQE_COUNT 1023 48*4882a593Smuzhiyun #define EHEA_DEF_ENTRIES_SQ 1023 49*4882a593Smuzhiyun #define EHEA_DEF_ENTRIES_RQ1 1023 50*4882a593Smuzhiyun #define EHEA_DEF_ENTRIES_RQ2 1023 51*4882a593Smuzhiyun #define EHEA_DEF_ENTRIES_RQ3 511 52*4882a593Smuzhiyun #else 53*4882a593Smuzhiyun #define EHEA_MAX_CQE_COUNT 4080 54*4882a593Smuzhiyun #define EHEA_DEF_ENTRIES_SQ 4080 55*4882a593Smuzhiyun #define EHEA_DEF_ENTRIES_RQ1 8160 56*4882a593Smuzhiyun #define EHEA_DEF_ENTRIES_RQ2 2040 57*4882a593Smuzhiyun #define EHEA_DEF_ENTRIES_RQ3 2040 58*4882a593Smuzhiyun #endif 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define EHEA_MAX_ENTRIES_EQ 20 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define EHEA_SG_SQ 2 63*4882a593Smuzhiyun #define EHEA_SG_RQ1 1 64*4882a593Smuzhiyun #define EHEA_SG_RQ2 0 65*4882a593Smuzhiyun #define EHEA_SG_RQ3 0 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define EHEA_MAX_PACKET_SIZE 9022 /* for jumbo frames */ 68*4882a593Smuzhiyun #define EHEA_RQ2_PKT_SIZE 2048 69*4882a593Smuzhiyun #define EHEA_L_PKT_SIZE 256 /* low latency */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* Send completion signaling */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* Protection Domain Identifier */ 74*4882a593Smuzhiyun #define EHEA_PD_ID 0xaabcdeff 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define EHEA_RQ2_THRESHOLD 1 77*4882a593Smuzhiyun #define EHEA_RQ3_THRESHOLD 4 /* use RQ3 threshold of 2048 bytes */ 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define EHEA_SPEED_10G 10000 80*4882a593Smuzhiyun #define EHEA_SPEED_1G 1000 81*4882a593Smuzhiyun #define EHEA_SPEED_100M 100 82*4882a593Smuzhiyun #define EHEA_SPEED_10M 10 83*4882a593Smuzhiyun #define EHEA_SPEED_AUTONEG 0 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* Broadcast/Multicast registration types */ 86*4882a593Smuzhiyun #define EHEA_BCMC_SCOPE_ALL 0x08 87*4882a593Smuzhiyun #define EHEA_BCMC_SCOPE_SINGLE 0x00 88*4882a593Smuzhiyun #define EHEA_BCMC_MULTICAST 0x04 89*4882a593Smuzhiyun #define EHEA_BCMC_BROADCAST 0x00 90*4882a593Smuzhiyun #define EHEA_BCMC_UNTAGGED 0x02 91*4882a593Smuzhiyun #define EHEA_BCMC_TAGGED 0x00 92*4882a593Smuzhiyun #define EHEA_BCMC_VLANID_ALL 0x01 93*4882a593Smuzhiyun #define EHEA_BCMC_VLANID_SINGLE 0x00 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define EHEA_CACHE_LINE 128 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* Memory Regions */ 98*4882a593Smuzhiyun #define EHEA_MR_ACC_CTRL 0x00800000 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define EHEA_BUSMAP_START 0x8000000000000000ULL 101*4882a593Smuzhiyun #define EHEA_INVAL_ADDR 0xFFFFFFFFFFFFFFFFULL 102*4882a593Smuzhiyun #define EHEA_DIR_INDEX_SHIFT 13 /* 8k Entries in 64k block */ 103*4882a593Smuzhiyun #define EHEA_TOP_INDEX_SHIFT (EHEA_DIR_INDEX_SHIFT * 2) 104*4882a593Smuzhiyun #define EHEA_MAP_ENTRIES (1 << EHEA_DIR_INDEX_SHIFT) 105*4882a593Smuzhiyun #define EHEA_MAP_SIZE (0x10000) /* currently fixed map size */ 106*4882a593Smuzhiyun #define EHEA_INDEX_MASK (EHEA_MAP_ENTRIES - 1) 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define EHEA_WATCH_DOG_TIMEOUT 10*HZ 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* utility functions */ 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun void ehea_dump(void *adr, int len, char *msg); 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define EHEA_BMASK(pos, length) (((pos) << 16) + (length)) 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define EHEA_BMASK_IBM(from, to) (((63 - to) << 16) + ((to) - (from) + 1)) 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define EHEA_BMASK_SHIFTPOS(mask) (((mask) >> 16) & 0xffff) 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define EHEA_BMASK_MASK(mask) \ 122*4882a593Smuzhiyun (0xffffffffffffffffULL >> ((64 - (mask)) & 0xffff)) 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #define EHEA_BMASK_SET(mask, value) \ 125*4882a593Smuzhiyun ((EHEA_BMASK_MASK(mask) & ((u64)(value))) << EHEA_BMASK_SHIFTPOS(mask)) 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define EHEA_BMASK_GET(mask, value) \ 128*4882a593Smuzhiyun (EHEA_BMASK_MASK(mask) & (((u64)(value)) >> EHEA_BMASK_SHIFTPOS(mask))) 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* 131*4882a593Smuzhiyun * Generic ehea page 132*4882a593Smuzhiyun */ 133*4882a593Smuzhiyun struct ehea_page { 134*4882a593Smuzhiyun u8 entries[PAGE_SIZE]; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun /* 138*4882a593Smuzhiyun * Generic queue in linux kernel virtual memory 139*4882a593Smuzhiyun */ 140*4882a593Smuzhiyun struct hw_queue { 141*4882a593Smuzhiyun u64 current_q_offset; /* current queue entry */ 142*4882a593Smuzhiyun struct ehea_page **queue_pages; /* array of pages belonging to queue */ 143*4882a593Smuzhiyun u32 qe_size; /* queue entry size */ 144*4882a593Smuzhiyun u32 queue_length; /* queue length allocated in bytes */ 145*4882a593Smuzhiyun u32 pagesize; 146*4882a593Smuzhiyun u32 toggle_state; /* toggle flag - per page */ 147*4882a593Smuzhiyun u32 reserved; /* 64 bit alignment */ 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun /* 151*4882a593Smuzhiyun * For pSeries this is a 64bit memory address where 152*4882a593Smuzhiyun * I/O memory is mapped into CPU address space 153*4882a593Smuzhiyun */ 154*4882a593Smuzhiyun struct h_epa { 155*4882a593Smuzhiyun void __iomem *addr; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun struct h_epa_user { 159*4882a593Smuzhiyun u64 addr; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun struct h_epas { 163*4882a593Smuzhiyun struct h_epa kernel; /* kernel space accessible resource, 164*4882a593Smuzhiyun set to 0 if unused */ 165*4882a593Smuzhiyun struct h_epa_user user; /* user space accessible resource 166*4882a593Smuzhiyun set to 0 if unused */ 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun /* 170*4882a593Smuzhiyun * Memory map data structures 171*4882a593Smuzhiyun */ 172*4882a593Smuzhiyun struct ehea_dir_bmap 173*4882a593Smuzhiyun { 174*4882a593Smuzhiyun u64 ent[EHEA_MAP_ENTRIES]; 175*4882a593Smuzhiyun }; 176*4882a593Smuzhiyun struct ehea_top_bmap 177*4882a593Smuzhiyun { 178*4882a593Smuzhiyun struct ehea_dir_bmap *dir[EHEA_MAP_ENTRIES]; 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun struct ehea_bmap 181*4882a593Smuzhiyun { 182*4882a593Smuzhiyun struct ehea_top_bmap *top[EHEA_MAP_ENTRIES]; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun struct ehea_qp; 186*4882a593Smuzhiyun struct ehea_cq; 187*4882a593Smuzhiyun struct ehea_eq; 188*4882a593Smuzhiyun struct ehea_port; 189*4882a593Smuzhiyun struct ehea_av; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun /* 192*4882a593Smuzhiyun * Queue attributes passed to ehea_create_qp() 193*4882a593Smuzhiyun */ 194*4882a593Smuzhiyun struct ehea_qp_init_attr { 195*4882a593Smuzhiyun /* input parameter */ 196*4882a593Smuzhiyun u32 qp_token; /* queue token */ 197*4882a593Smuzhiyun u8 low_lat_rq1; 198*4882a593Smuzhiyun u8 signalingtype; /* cqe generation flag */ 199*4882a593Smuzhiyun u8 rq_count; /* num of receive queues */ 200*4882a593Smuzhiyun u8 eqe_gen; /* eqe generation flag */ 201*4882a593Smuzhiyun u16 max_nr_send_wqes; /* max number of send wqes */ 202*4882a593Smuzhiyun u16 max_nr_rwqes_rq1; /* max number of receive wqes */ 203*4882a593Smuzhiyun u16 max_nr_rwqes_rq2; 204*4882a593Smuzhiyun u16 max_nr_rwqes_rq3; 205*4882a593Smuzhiyun u8 wqe_size_enc_sq; 206*4882a593Smuzhiyun u8 wqe_size_enc_rq1; 207*4882a593Smuzhiyun u8 wqe_size_enc_rq2; 208*4882a593Smuzhiyun u8 wqe_size_enc_rq3; 209*4882a593Smuzhiyun u8 swqe_imm_data_len; /* immediate data length for swqes */ 210*4882a593Smuzhiyun u16 port_nr; 211*4882a593Smuzhiyun u16 rq2_threshold; 212*4882a593Smuzhiyun u16 rq3_threshold; 213*4882a593Smuzhiyun u64 send_cq_handle; 214*4882a593Smuzhiyun u64 recv_cq_handle; 215*4882a593Smuzhiyun u64 aff_eq_handle; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun /* output parameter */ 218*4882a593Smuzhiyun u32 qp_nr; 219*4882a593Smuzhiyun u16 act_nr_send_wqes; 220*4882a593Smuzhiyun u16 act_nr_rwqes_rq1; 221*4882a593Smuzhiyun u16 act_nr_rwqes_rq2; 222*4882a593Smuzhiyun u16 act_nr_rwqes_rq3; 223*4882a593Smuzhiyun u8 act_wqe_size_enc_sq; 224*4882a593Smuzhiyun u8 act_wqe_size_enc_rq1; 225*4882a593Smuzhiyun u8 act_wqe_size_enc_rq2; 226*4882a593Smuzhiyun u8 act_wqe_size_enc_rq3; 227*4882a593Smuzhiyun u32 nr_sq_pages; 228*4882a593Smuzhiyun u32 nr_rq1_pages; 229*4882a593Smuzhiyun u32 nr_rq2_pages; 230*4882a593Smuzhiyun u32 nr_rq3_pages; 231*4882a593Smuzhiyun u32 liobn_sq; 232*4882a593Smuzhiyun u32 liobn_rq1; 233*4882a593Smuzhiyun u32 liobn_rq2; 234*4882a593Smuzhiyun u32 liobn_rq3; 235*4882a593Smuzhiyun }; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun /* 238*4882a593Smuzhiyun * Event Queue attributes, passed as parameter 239*4882a593Smuzhiyun */ 240*4882a593Smuzhiyun struct ehea_eq_attr { 241*4882a593Smuzhiyun u32 type; 242*4882a593Smuzhiyun u32 max_nr_of_eqes; 243*4882a593Smuzhiyun u8 eqe_gen; /* generate eqe flag */ 244*4882a593Smuzhiyun u64 eq_handle; 245*4882a593Smuzhiyun u32 act_nr_of_eqes; 246*4882a593Smuzhiyun u32 nr_pages; 247*4882a593Smuzhiyun u32 ist1; /* Interrupt service token */ 248*4882a593Smuzhiyun u32 ist2; 249*4882a593Smuzhiyun u32 ist3; 250*4882a593Smuzhiyun u32 ist4; 251*4882a593Smuzhiyun }; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun /* 255*4882a593Smuzhiyun * Event Queue 256*4882a593Smuzhiyun */ 257*4882a593Smuzhiyun struct ehea_eq { 258*4882a593Smuzhiyun struct ehea_adapter *adapter; 259*4882a593Smuzhiyun struct hw_queue hw_queue; 260*4882a593Smuzhiyun u64 fw_handle; 261*4882a593Smuzhiyun struct h_epas epas; 262*4882a593Smuzhiyun spinlock_t spinlock; 263*4882a593Smuzhiyun struct ehea_eq_attr attr; 264*4882a593Smuzhiyun }; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun /* 267*4882a593Smuzhiyun * HEA Queues 268*4882a593Smuzhiyun */ 269*4882a593Smuzhiyun struct ehea_qp { 270*4882a593Smuzhiyun struct ehea_adapter *adapter; 271*4882a593Smuzhiyun u64 fw_handle; /* QP handle for firmware calls */ 272*4882a593Smuzhiyun struct hw_queue hw_squeue; 273*4882a593Smuzhiyun struct hw_queue hw_rqueue1; 274*4882a593Smuzhiyun struct hw_queue hw_rqueue2; 275*4882a593Smuzhiyun struct hw_queue hw_rqueue3; 276*4882a593Smuzhiyun struct h_epas epas; 277*4882a593Smuzhiyun struct ehea_qp_init_attr init_attr; 278*4882a593Smuzhiyun }; 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun /* 281*4882a593Smuzhiyun * Completion Queue attributes 282*4882a593Smuzhiyun */ 283*4882a593Smuzhiyun struct ehea_cq_attr { 284*4882a593Smuzhiyun /* input parameter */ 285*4882a593Smuzhiyun u32 max_nr_of_cqes; 286*4882a593Smuzhiyun u32 cq_token; 287*4882a593Smuzhiyun u64 eq_handle; 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun /* output parameter */ 290*4882a593Smuzhiyun u32 act_nr_of_cqes; 291*4882a593Smuzhiyun u32 nr_pages; 292*4882a593Smuzhiyun }; 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun /* 295*4882a593Smuzhiyun * Completion Queue 296*4882a593Smuzhiyun */ 297*4882a593Smuzhiyun struct ehea_cq { 298*4882a593Smuzhiyun struct ehea_adapter *adapter; 299*4882a593Smuzhiyun u64 fw_handle; 300*4882a593Smuzhiyun struct hw_queue hw_queue; 301*4882a593Smuzhiyun struct h_epas epas; 302*4882a593Smuzhiyun struct ehea_cq_attr attr; 303*4882a593Smuzhiyun }; 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun /* 306*4882a593Smuzhiyun * Memory Region 307*4882a593Smuzhiyun */ 308*4882a593Smuzhiyun struct ehea_mr { 309*4882a593Smuzhiyun struct ehea_adapter *adapter; 310*4882a593Smuzhiyun u64 handle; 311*4882a593Smuzhiyun u64 vaddr; 312*4882a593Smuzhiyun u32 lkey; 313*4882a593Smuzhiyun }; 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun /* 316*4882a593Smuzhiyun * Port state information 317*4882a593Smuzhiyun */ 318*4882a593Smuzhiyun struct port_stats { 319*4882a593Smuzhiyun int poll_receive_errors; 320*4882a593Smuzhiyun int queue_stopped; 321*4882a593Smuzhiyun int err_tcp_cksum; 322*4882a593Smuzhiyun int err_ip_cksum; 323*4882a593Smuzhiyun int err_frame_crc; 324*4882a593Smuzhiyun }; 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun #define EHEA_IRQ_NAME_SIZE 20 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun /* 329*4882a593Smuzhiyun * Queue SKB Array 330*4882a593Smuzhiyun */ 331*4882a593Smuzhiyun struct ehea_q_skb_arr { 332*4882a593Smuzhiyun struct sk_buff **arr; /* skb array for queue */ 333*4882a593Smuzhiyun int len; /* array length */ 334*4882a593Smuzhiyun int index; /* array index */ 335*4882a593Smuzhiyun int os_skbs; /* rq2/rq3 only: outstanding skbs */ 336*4882a593Smuzhiyun }; 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun /* 339*4882a593Smuzhiyun * Port resources 340*4882a593Smuzhiyun */ 341*4882a593Smuzhiyun struct ehea_port_res { 342*4882a593Smuzhiyun struct napi_struct napi; 343*4882a593Smuzhiyun struct port_stats p_stats; 344*4882a593Smuzhiyun struct ehea_mr send_mr; /* send memory region */ 345*4882a593Smuzhiyun struct ehea_mr recv_mr; /* receive memory region */ 346*4882a593Smuzhiyun struct ehea_port *port; 347*4882a593Smuzhiyun char int_recv_name[EHEA_IRQ_NAME_SIZE]; 348*4882a593Smuzhiyun char int_send_name[EHEA_IRQ_NAME_SIZE]; 349*4882a593Smuzhiyun struct ehea_qp *qp; 350*4882a593Smuzhiyun struct ehea_cq *send_cq; 351*4882a593Smuzhiyun struct ehea_cq *recv_cq; 352*4882a593Smuzhiyun struct ehea_eq *eq; 353*4882a593Smuzhiyun struct ehea_q_skb_arr rq1_skba; 354*4882a593Smuzhiyun struct ehea_q_skb_arr rq2_skba; 355*4882a593Smuzhiyun struct ehea_q_skb_arr rq3_skba; 356*4882a593Smuzhiyun struct ehea_q_skb_arr sq_skba; 357*4882a593Smuzhiyun int sq_skba_size; 358*4882a593Smuzhiyun int swqe_refill_th; 359*4882a593Smuzhiyun atomic_t swqe_avail; 360*4882a593Smuzhiyun int swqe_ll_count; 361*4882a593Smuzhiyun u32 swqe_id_counter; 362*4882a593Smuzhiyun u64 tx_packets; 363*4882a593Smuzhiyun u64 tx_bytes; 364*4882a593Smuzhiyun u64 rx_packets; 365*4882a593Smuzhiyun u64 rx_bytes; 366*4882a593Smuzhiyun int sq_restart_flag; 367*4882a593Smuzhiyun }; 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun 370*4882a593Smuzhiyun #define EHEA_MAX_PORTS 16 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun #define EHEA_NUM_PORTRES_FW_HANDLES 6 /* QP handle, SendCQ handle, 373*4882a593Smuzhiyun RecvCQ handle, EQ handle, 374*4882a593Smuzhiyun SendMR handle, RecvMR handle */ 375*4882a593Smuzhiyun #define EHEA_NUM_PORT_FW_HANDLES 1 /* EQ handle */ 376*4882a593Smuzhiyun #define EHEA_NUM_ADAPTER_FW_HANDLES 2 /* MR handle, NEQ handle */ 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun struct ehea_adapter { 379*4882a593Smuzhiyun u64 handle; 380*4882a593Smuzhiyun struct platform_device *ofdev; 381*4882a593Smuzhiyun struct ehea_port *port[EHEA_MAX_PORTS]; 382*4882a593Smuzhiyun struct ehea_eq *neq; /* notification event queue */ 383*4882a593Smuzhiyun struct tasklet_struct neq_tasklet; 384*4882a593Smuzhiyun struct ehea_mr mr; 385*4882a593Smuzhiyun u32 pd; /* protection domain */ 386*4882a593Smuzhiyun u64 max_mc_mac; /* max number of multicast mac addresses */ 387*4882a593Smuzhiyun int active_ports; 388*4882a593Smuzhiyun struct list_head list; 389*4882a593Smuzhiyun }; 390*4882a593Smuzhiyun 391*4882a593Smuzhiyun 392*4882a593Smuzhiyun struct ehea_mc_list { 393*4882a593Smuzhiyun struct list_head list; 394*4882a593Smuzhiyun u64 macaddr; 395*4882a593Smuzhiyun }; 396*4882a593Smuzhiyun 397*4882a593Smuzhiyun /* kdump support */ 398*4882a593Smuzhiyun struct ehea_fw_handle_entry { 399*4882a593Smuzhiyun u64 adh; /* Adapter Handle */ 400*4882a593Smuzhiyun u64 fwh; /* Firmware Handle */ 401*4882a593Smuzhiyun }; 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun struct ehea_fw_handle_array { 404*4882a593Smuzhiyun struct ehea_fw_handle_entry *arr; 405*4882a593Smuzhiyun int num_entries; 406*4882a593Smuzhiyun struct mutex lock; 407*4882a593Smuzhiyun }; 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun struct ehea_bcmc_reg_entry { 410*4882a593Smuzhiyun u64 adh; /* Adapter Handle */ 411*4882a593Smuzhiyun u32 port_id; /* Logical Port Id */ 412*4882a593Smuzhiyun u8 reg_type; /* Registration Type */ 413*4882a593Smuzhiyun u64 macaddr; 414*4882a593Smuzhiyun }; 415*4882a593Smuzhiyun 416*4882a593Smuzhiyun struct ehea_bcmc_reg_array { 417*4882a593Smuzhiyun struct ehea_bcmc_reg_entry *arr; 418*4882a593Smuzhiyun int num_entries; 419*4882a593Smuzhiyun spinlock_t lock; 420*4882a593Smuzhiyun }; 421*4882a593Smuzhiyun 422*4882a593Smuzhiyun #define EHEA_PORT_UP 1 423*4882a593Smuzhiyun #define EHEA_PORT_DOWN 0 424*4882a593Smuzhiyun #define EHEA_PHY_LINK_UP 1 425*4882a593Smuzhiyun #define EHEA_PHY_LINK_DOWN 0 426*4882a593Smuzhiyun #define EHEA_MAX_PORT_RES 16 427*4882a593Smuzhiyun struct ehea_port { 428*4882a593Smuzhiyun struct ehea_adapter *adapter; /* adapter that owns this port */ 429*4882a593Smuzhiyun struct net_device *netdev; 430*4882a593Smuzhiyun struct rtnl_link_stats64 stats; 431*4882a593Smuzhiyun struct ehea_port_res port_res[EHEA_MAX_PORT_RES]; 432*4882a593Smuzhiyun struct platform_device ofdev; /* Open Firmware Device */ 433*4882a593Smuzhiyun struct ehea_mc_list *mc_list; /* Multicast MAC addresses */ 434*4882a593Smuzhiyun struct ehea_eq *qp_eq; 435*4882a593Smuzhiyun struct work_struct reset_task; 436*4882a593Smuzhiyun struct delayed_work stats_work; 437*4882a593Smuzhiyun struct mutex port_lock; 438*4882a593Smuzhiyun char int_aff_name[EHEA_IRQ_NAME_SIZE]; 439*4882a593Smuzhiyun int allmulti; /* Indicates IFF_ALLMULTI state */ 440*4882a593Smuzhiyun int promisc; /* Indicates IFF_PROMISC state */ 441*4882a593Smuzhiyun int num_mcs; 442*4882a593Smuzhiyun int resets; 443*4882a593Smuzhiyun unsigned long flags; 444*4882a593Smuzhiyun u64 mac_addr; 445*4882a593Smuzhiyun u32 logical_port_id; 446*4882a593Smuzhiyun u32 port_speed; 447*4882a593Smuzhiyun u32 msg_enable; 448*4882a593Smuzhiyun u32 sig_comp_iv; 449*4882a593Smuzhiyun u32 state; 450*4882a593Smuzhiyun u8 phy_link; 451*4882a593Smuzhiyun u8 full_duplex; 452*4882a593Smuzhiyun u8 autoneg; 453*4882a593Smuzhiyun u8 num_def_qps; 454*4882a593Smuzhiyun wait_queue_head_t swqe_avail_wq; 455*4882a593Smuzhiyun wait_queue_head_t restart_wq; 456*4882a593Smuzhiyun }; 457*4882a593Smuzhiyun 458*4882a593Smuzhiyun struct port_res_cfg { 459*4882a593Smuzhiyun int max_entries_rcq; 460*4882a593Smuzhiyun int max_entries_scq; 461*4882a593Smuzhiyun int max_entries_sq; 462*4882a593Smuzhiyun int max_entries_rq1; 463*4882a593Smuzhiyun int max_entries_rq2; 464*4882a593Smuzhiyun int max_entries_rq3; 465*4882a593Smuzhiyun }; 466*4882a593Smuzhiyun 467*4882a593Smuzhiyun enum ehea_flag_bits { 468*4882a593Smuzhiyun __EHEA_STOP_XFER, 469*4882a593Smuzhiyun __EHEA_DISABLE_PORT_RESET 470*4882a593Smuzhiyun }; 471*4882a593Smuzhiyun 472*4882a593Smuzhiyun void ehea_set_ethtool_ops(struct net_device *netdev); 473*4882a593Smuzhiyun int ehea_sense_port_attr(struct ehea_port *port); 474*4882a593Smuzhiyun int ehea_set_portspeed(struct ehea_port *port, u32 port_speed); 475*4882a593Smuzhiyun 476*4882a593Smuzhiyun #endif /* __EHEA_H__ */ 477