1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * linux/drivers/acorn/net/ether1.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 1996 Russell King 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Network driver for Acorn Ether1 cards. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _LINUX_ether1_H 11*4882a593Smuzhiyun #define _LINUX_ether1_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifdef __ETHER1_C 14*4882a593Smuzhiyun /* use 0 for production, 1 for verification, >2 for debug */ 15*4882a593Smuzhiyun #ifndef NET_DEBUG 16*4882a593Smuzhiyun #define NET_DEBUG 0 17*4882a593Smuzhiyun #endif 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define priv(dev) ((struct ether1_priv *)netdev_priv(dev)) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* Page register */ 22*4882a593Smuzhiyun #define REG_PAGE (priv(dev)->base + 0x0000) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* Control register */ 25*4882a593Smuzhiyun #define REG_CONTROL (priv(dev)->base + 0x0004) 26*4882a593Smuzhiyun #define CTRL_RST 0x01 27*4882a593Smuzhiyun #define CTRL_LOOPBACK 0x02 28*4882a593Smuzhiyun #define CTRL_CA 0x04 29*4882a593Smuzhiyun #define CTRL_ACK 0x08 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define ETHER1_RAM (priv(dev)->base + 0x2000) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* HW address */ 34*4882a593Smuzhiyun #define IDPROM_ADDRESS (priv(dev)->base + 0x0024) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun struct ether1_priv { 37*4882a593Smuzhiyun void __iomem *base; 38*4882a593Smuzhiyun unsigned int tx_link; 39*4882a593Smuzhiyun unsigned int tx_head; 40*4882a593Smuzhiyun volatile unsigned int tx_tail; 41*4882a593Smuzhiyun volatile unsigned int rx_head; 42*4882a593Smuzhiyun volatile unsigned int rx_tail; 43*4882a593Smuzhiyun unsigned char bus_type; 44*4882a593Smuzhiyun unsigned char resetting; 45*4882a593Smuzhiyun unsigned char initialising : 1; 46*4882a593Smuzhiyun unsigned char restart : 1; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define I82586_NULL (-1) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun typedef struct { /* tdr */ 52*4882a593Smuzhiyun unsigned short tdr_status; 53*4882a593Smuzhiyun unsigned short tdr_command; 54*4882a593Smuzhiyun unsigned short tdr_link; 55*4882a593Smuzhiyun unsigned short tdr_result; 56*4882a593Smuzhiyun #define TDR_TIME (0x7ff) 57*4882a593Smuzhiyun #define TDR_SHORT (1 << 12) 58*4882a593Smuzhiyun #define TDR_OPEN (1 << 13) 59*4882a593Smuzhiyun #define TDR_XCVRPROB (1 << 14) 60*4882a593Smuzhiyun #define TDR_LNKOK (1 << 15) 61*4882a593Smuzhiyun } tdr_t; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun typedef struct { /* transmit */ 64*4882a593Smuzhiyun unsigned short tx_status; 65*4882a593Smuzhiyun unsigned short tx_command; 66*4882a593Smuzhiyun unsigned short tx_link; 67*4882a593Smuzhiyun unsigned short tx_tbdoffset; 68*4882a593Smuzhiyun } tx_t; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun typedef struct { /* tbd */ 71*4882a593Smuzhiyun unsigned short tbd_opts; 72*4882a593Smuzhiyun #define TBD_CNT (0x3fff) 73*4882a593Smuzhiyun #define TBD_EOL (1 << 15) 74*4882a593Smuzhiyun unsigned short tbd_link; 75*4882a593Smuzhiyun unsigned short tbd_bufl; 76*4882a593Smuzhiyun unsigned short tbd_bufh; 77*4882a593Smuzhiyun } tbd_t; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun typedef struct { /* rfd */ 80*4882a593Smuzhiyun unsigned short rfd_status; 81*4882a593Smuzhiyun #define RFD_NOEOF (1 << 6) 82*4882a593Smuzhiyun #define RFD_FRAMESHORT (1 << 7) 83*4882a593Smuzhiyun #define RFD_DMAOVRN (1 << 8) 84*4882a593Smuzhiyun #define RFD_NORESOURCES (1 << 9) 85*4882a593Smuzhiyun #define RFD_ALIGNERROR (1 << 10) 86*4882a593Smuzhiyun #define RFD_CRCERROR (1 << 11) 87*4882a593Smuzhiyun #define RFD_OK (1 << 13) 88*4882a593Smuzhiyun #define RFD_FDCONSUMED (1 << 14) 89*4882a593Smuzhiyun #define RFD_COMPLETE (1 << 15) 90*4882a593Smuzhiyun unsigned short rfd_command; 91*4882a593Smuzhiyun #define RFD_CMDSUSPEND (1 << 14) 92*4882a593Smuzhiyun #define RFD_CMDEL (1 << 15) 93*4882a593Smuzhiyun unsigned short rfd_link; 94*4882a593Smuzhiyun unsigned short rfd_rbdoffset; 95*4882a593Smuzhiyun unsigned char rfd_dest[6]; 96*4882a593Smuzhiyun unsigned char rfd_src[6]; 97*4882a593Smuzhiyun unsigned short rfd_len; 98*4882a593Smuzhiyun } rfd_t; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun typedef struct { /* rbd */ 101*4882a593Smuzhiyun unsigned short rbd_status; 102*4882a593Smuzhiyun #define RBD_ACNT (0x3fff) 103*4882a593Smuzhiyun #define RBD_ACNTVALID (1 << 14) 104*4882a593Smuzhiyun #define RBD_EOF (1 << 15) 105*4882a593Smuzhiyun unsigned short rbd_link; 106*4882a593Smuzhiyun unsigned short rbd_bufl; 107*4882a593Smuzhiyun unsigned short rbd_bufh; 108*4882a593Smuzhiyun unsigned short rbd_len; 109*4882a593Smuzhiyun } rbd_t; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun typedef struct { /* nop */ 112*4882a593Smuzhiyun unsigned short nop_status; 113*4882a593Smuzhiyun unsigned short nop_command; 114*4882a593Smuzhiyun unsigned short nop_link; 115*4882a593Smuzhiyun } nop_t; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun typedef struct { /* set multicast */ 118*4882a593Smuzhiyun unsigned short mc_status; 119*4882a593Smuzhiyun unsigned short mc_command; 120*4882a593Smuzhiyun unsigned short mc_link; 121*4882a593Smuzhiyun unsigned short mc_cnt; 122*4882a593Smuzhiyun unsigned char mc_addrs[1][6]; 123*4882a593Smuzhiyun } mc_t; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun typedef struct { /* set address */ 126*4882a593Smuzhiyun unsigned short sa_status; 127*4882a593Smuzhiyun unsigned short sa_command; 128*4882a593Smuzhiyun unsigned short sa_link; 129*4882a593Smuzhiyun unsigned char sa_addr[6]; 130*4882a593Smuzhiyun } sa_t; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun typedef struct { /* config command */ 133*4882a593Smuzhiyun unsigned short cfg_status; 134*4882a593Smuzhiyun unsigned short cfg_command; 135*4882a593Smuzhiyun unsigned short cfg_link; 136*4882a593Smuzhiyun unsigned char cfg_bytecnt; /* size foll data: 4 - 12 */ 137*4882a593Smuzhiyun unsigned char cfg_fifolim; /* FIFO threshold */ 138*4882a593Smuzhiyun unsigned char cfg_byte8; 139*4882a593Smuzhiyun #define CFG8_SRDY (1 << 6) 140*4882a593Smuzhiyun #define CFG8_SAVEBADF (1 << 7) 141*4882a593Smuzhiyun unsigned char cfg_byte9; 142*4882a593Smuzhiyun #define CFG9_ADDRLEN(x) (x) 143*4882a593Smuzhiyun #define CFG9_ADDRLENBUF (1 << 3) 144*4882a593Smuzhiyun #define CFG9_PREAMB2 (0 << 4) 145*4882a593Smuzhiyun #define CFG9_PREAMB4 (1 << 4) 146*4882a593Smuzhiyun #define CFG9_PREAMB8 (2 << 4) 147*4882a593Smuzhiyun #define CFG9_PREAMB16 (3 << 4) 148*4882a593Smuzhiyun #define CFG9_ILOOPBACK (1 << 6) 149*4882a593Smuzhiyun #define CFG9_ELOOPBACK (1 << 7) 150*4882a593Smuzhiyun unsigned char cfg_byte10; 151*4882a593Smuzhiyun #define CFG10_LINPRI(x) (x) 152*4882a593Smuzhiyun #define CFG10_ACR(x) (x << 4) 153*4882a593Smuzhiyun #define CFG10_BOFMET (1 << 7) 154*4882a593Smuzhiyun unsigned char cfg_ifs; 155*4882a593Smuzhiyun unsigned char cfg_slotl; 156*4882a593Smuzhiyun unsigned char cfg_byte13; 157*4882a593Smuzhiyun #define CFG13_SLOTH(x) (x) 158*4882a593Smuzhiyun #define CFG13_RETRY(x) (x << 4) 159*4882a593Smuzhiyun unsigned char cfg_byte14; 160*4882a593Smuzhiyun #define CFG14_PROMISC (1 << 0) 161*4882a593Smuzhiyun #define CFG14_DISBRD (1 << 1) 162*4882a593Smuzhiyun #define CFG14_MANCH (1 << 2) 163*4882a593Smuzhiyun #define CFG14_TNCRS (1 << 3) 164*4882a593Smuzhiyun #define CFG14_NOCRC (1 << 4) 165*4882a593Smuzhiyun #define CFG14_CRC16 (1 << 5) 166*4882a593Smuzhiyun #define CFG14_BTSTF (1 << 6) 167*4882a593Smuzhiyun #define CFG14_FLGPAD (1 << 7) 168*4882a593Smuzhiyun unsigned char cfg_byte15; 169*4882a593Smuzhiyun #define CFG15_CSTF(x) (x) 170*4882a593Smuzhiyun #define CFG15_ICSS (1 << 3) 171*4882a593Smuzhiyun #define CFG15_CDTF(x) (x << 4) 172*4882a593Smuzhiyun #define CFG15_ICDS (1 << 7) 173*4882a593Smuzhiyun unsigned short cfg_minfrmlen; 174*4882a593Smuzhiyun } cfg_t; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun typedef struct { /* scb */ 177*4882a593Smuzhiyun unsigned short scb_status; /* status of 82586 */ 178*4882a593Smuzhiyun #define SCB_STRXMASK (7 << 4) /* Receive unit status */ 179*4882a593Smuzhiyun #define SCB_STRXIDLE (0 << 4) /* Idle */ 180*4882a593Smuzhiyun #define SCB_STRXSUSP (1 << 4) /* Suspended */ 181*4882a593Smuzhiyun #define SCB_STRXNRES (2 << 4) /* No resources */ 182*4882a593Smuzhiyun #define SCB_STRXRDY (4 << 4) /* Ready */ 183*4882a593Smuzhiyun #define SCB_STCUMASK (7 << 8) /* Command unit status */ 184*4882a593Smuzhiyun #define SCB_STCUIDLE (0 << 8) /* Idle */ 185*4882a593Smuzhiyun #define SCB_STCUSUSP (1 << 8) /* Suspended */ 186*4882a593Smuzhiyun #define SCB_STCUACTV (2 << 8) /* Active */ 187*4882a593Smuzhiyun #define SCB_STRNR (1 << 12) /* Receive unit not ready */ 188*4882a593Smuzhiyun #define SCB_STCNA (1 << 13) /* Command unit not ready */ 189*4882a593Smuzhiyun #define SCB_STFR (1 << 14) /* Frame received */ 190*4882a593Smuzhiyun #define SCB_STCX (1 << 15) /* Command completed */ 191*4882a593Smuzhiyun unsigned short scb_command; /* Next command */ 192*4882a593Smuzhiyun #define SCB_CMDRXSTART (1 << 4) /* Start (at rfa_offset) */ 193*4882a593Smuzhiyun #define SCB_CMDRXRESUME (2 << 4) /* Resume reception */ 194*4882a593Smuzhiyun #define SCB_CMDRXSUSPEND (3 << 4) /* Suspend reception */ 195*4882a593Smuzhiyun #define SCB_CMDRXABORT (4 << 4) /* Abort reception */ 196*4882a593Smuzhiyun #define SCB_CMDCUCSTART (1 << 8) /* Start (at cbl_offset) */ 197*4882a593Smuzhiyun #define SCB_CMDCUCRESUME (2 << 8) /* Resume execution */ 198*4882a593Smuzhiyun #define SCB_CMDCUCSUSPEND (3 << 8) /* Suspend execution */ 199*4882a593Smuzhiyun #define SCB_CMDCUCABORT (4 << 8) /* Abort execution */ 200*4882a593Smuzhiyun #define SCB_CMDACKRNR (1 << 12) /* Ack RU not ready */ 201*4882a593Smuzhiyun #define SCB_CMDACKCNA (1 << 13) /* Ack CU not ready */ 202*4882a593Smuzhiyun #define SCB_CMDACKFR (1 << 14) /* Ack Frame received */ 203*4882a593Smuzhiyun #define SCB_CMDACKCX (1 << 15) /* Ack Command complete */ 204*4882a593Smuzhiyun unsigned short scb_cbl_offset; /* Offset of first command unit */ 205*4882a593Smuzhiyun unsigned short scb_rfa_offset; /* Offset of first receive frame area */ 206*4882a593Smuzhiyun unsigned short scb_crc_errors; /* Properly aligned frame with CRC error*/ 207*4882a593Smuzhiyun unsigned short scb_aln_errors; /* Misaligned frames */ 208*4882a593Smuzhiyun unsigned short scb_rsc_errors; /* Frames lost due to no space */ 209*4882a593Smuzhiyun unsigned short scb_ovn_errors; /* Frames lost due to slow bus */ 210*4882a593Smuzhiyun } scb_t; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun typedef struct { /* iscp */ 213*4882a593Smuzhiyun unsigned short iscp_busy; /* set by CPU before CA */ 214*4882a593Smuzhiyun unsigned short iscp_offset; /* offset of SCB */ 215*4882a593Smuzhiyun unsigned short iscp_basel; /* base of SCB */ 216*4882a593Smuzhiyun unsigned short iscp_baseh; 217*4882a593Smuzhiyun } iscp_t; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun /* this address must be 0xfff6 */ 220*4882a593Smuzhiyun typedef struct { /* scp */ 221*4882a593Smuzhiyun unsigned short scp_sysbus; /* bus size */ 222*4882a593Smuzhiyun #define SCP_SY_16BBUS 0x00 223*4882a593Smuzhiyun #define SCP_SY_8BBUS 0x01 224*4882a593Smuzhiyun unsigned short scp_junk[2]; /* junk */ 225*4882a593Smuzhiyun unsigned short scp_iscpl; /* lower 16 bits of iscp */ 226*4882a593Smuzhiyun unsigned short scp_iscph; /* upper 16 bits of iscp */ 227*4882a593Smuzhiyun } scp_t; 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun /* commands */ 230*4882a593Smuzhiyun #define CMD_NOP 0 231*4882a593Smuzhiyun #define CMD_SETADDRESS 1 232*4882a593Smuzhiyun #define CMD_CONFIG 2 233*4882a593Smuzhiyun #define CMD_SETMULTICAST 3 234*4882a593Smuzhiyun #define CMD_TX 4 235*4882a593Smuzhiyun #define CMD_TDR 5 236*4882a593Smuzhiyun #define CMD_DUMP 6 237*4882a593Smuzhiyun #define CMD_DIAGNOSE 7 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun #define CMD_MASK 7 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun #define CMD_INTR (1 << 13) 242*4882a593Smuzhiyun #define CMD_SUSP (1 << 14) 243*4882a593Smuzhiyun #define CMD_EOL (1 << 15) 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun #define STAT_COLLISIONS (15) 246*4882a593Smuzhiyun #define STAT_COLLEXCESSIVE (1 << 5) 247*4882a593Smuzhiyun #define STAT_COLLAFTERTX (1 << 6) 248*4882a593Smuzhiyun #define STAT_TXDEFERRED (1 << 7) 249*4882a593Smuzhiyun #define STAT_TXSLOWDMA (1 << 8) 250*4882a593Smuzhiyun #define STAT_TXLOSTCTS (1 << 9) 251*4882a593Smuzhiyun #define STAT_NOCARRIER (1 << 10) 252*4882a593Smuzhiyun #define STAT_FAIL (1 << 11) 253*4882a593Smuzhiyun #define STAT_ABORTED (1 << 12) 254*4882a593Smuzhiyun #define STAT_OK (1 << 13) 255*4882a593Smuzhiyun #define STAT_BUSY (1 << 14) 256*4882a593Smuzhiyun #define STAT_COMPLETE (1 << 15) 257*4882a593Smuzhiyun #endif 258*4882a593Smuzhiyun #endif 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun /* 261*4882a593Smuzhiyun * Ether1 card definitions: 262*4882a593Smuzhiyun * 263*4882a593Smuzhiyun * FAST accesses: 264*4882a593Smuzhiyun * +0 Page register 265*4882a593Smuzhiyun * 16 pages 266*4882a593Smuzhiyun * +4 Control 267*4882a593Smuzhiyun * '1' = reset 268*4882a593Smuzhiyun * '2' = loopback 269*4882a593Smuzhiyun * '4' = CA 270*4882a593Smuzhiyun * '8' = int ack 271*4882a593Smuzhiyun * 272*4882a593Smuzhiyun * RAM at address + 0x2000 273*4882a593Smuzhiyun * Pod. Prod id = 3 274*4882a593Smuzhiyun * Words after ID block [base + 8 words] 275*4882a593Smuzhiyun * +0 pcb issue (0x0c and 0xf3 invalid) 276*4882a593Smuzhiyun * +1 - +6 eth hw address 277*4882a593Smuzhiyun */ 278