1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* Huawei HiNIC PCI Express Linux driver 3*4882a593Smuzhiyun * Copyright(c) 2017 Huawei Technologies Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __HINIC_DEVLINK_H__ 7*4882a593Smuzhiyun #define __HINIC_DEVLINK_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <net/devlink.h> 10*4882a593Smuzhiyun #include "hinic_dev.h" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define MAX_FW_TYPE_NUM 30 13*4882a593Smuzhiyun #define HINIC_MAGIC_NUM 0x18221100 14*4882a593Smuzhiyun #define UPDATEFW_IMAGE_HEAD_SIZE 1024 15*4882a593Smuzhiyun #define FW_UPDATE_COLD 0 16*4882a593Smuzhiyun #define FW_UPDATE_HOT 1 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define UP_TYPE_A 0x0 19*4882a593Smuzhiyun #define UP_TYPE_B 0x1 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define MAX_FW_FRAGMENT_LEN 1536 22*4882a593Smuzhiyun #define HINIC_FW_DISMATCH_ERROR 10 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun enum hinic_fw_type { 25*4882a593Smuzhiyun UP_FW_UPDATE_UP_TEXT_A = 0x0, 26*4882a593Smuzhiyun UP_FW_UPDATE_UP_DATA_A, 27*4882a593Smuzhiyun UP_FW_UPDATE_UP_TEXT_B, 28*4882a593Smuzhiyun UP_FW_UPDATE_UP_DATA_B, 29*4882a593Smuzhiyun UP_FW_UPDATE_UP_DICT, 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun UP_FW_UPDATE_HLINK_ONE = 0x5, 32*4882a593Smuzhiyun UP_FW_UPDATE_HLINK_TWO, 33*4882a593Smuzhiyun UP_FW_UPDATE_HLINK_THR, 34*4882a593Smuzhiyun UP_FW_UPDATE_PHY, 35*4882a593Smuzhiyun UP_FW_UPDATE_TILE_TEXT, 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun UP_FW_UPDATE_TILE_DATA = 0xa, 38*4882a593Smuzhiyun UP_FW_UPDATE_TILE_DICT, 39*4882a593Smuzhiyun UP_FW_UPDATE_PPE_STATE, 40*4882a593Smuzhiyun UP_FW_UPDATE_PPE_BRANCH, 41*4882a593Smuzhiyun UP_FW_UPDATE_PPE_EXTACT, 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun UP_FW_UPDATE_CLP_LEGACY = 0xf, 44*4882a593Smuzhiyun UP_FW_UPDATE_PXE_LEGACY, 45*4882a593Smuzhiyun UP_FW_UPDATE_ISCSI_LEGACY, 46*4882a593Smuzhiyun UP_FW_UPDATE_CLP_EFI, 47*4882a593Smuzhiyun UP_FW_UPDATE_PXE_EFI, 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun UP_FW_UPDATE_ISCSI_EFI = 0x14, 50*4882a593Smuzhiyun UP_FW_UPDATE_CFG, 51*4882a593Smuzhiyun UP_FW_UPDATE_BOOT, 52*4882a593Smuzhiyun UP_FW_UPDATE_VPD, 53*4882a593Smuzhiyun FILE_TYPE_TOTAL_NUM 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define _IMAGE_UP_ALL_IN ((1 << UP_FW_UPDATE_UP_TEXT_A) | \ 57*4882a593Smuzhiyun (1 << UP_FW_UPDATE_UP_DATA_A) | \ 58*4882a593Smuzhiyun (1 << UP_FW_UPDATE_UP_TEXT_B) | \ 59*4882a593Smuzhiyun (1 << UP_FW_UPDATE_UP_DATA_B) | \ 60*4882a593Smuzhiyun (1 << UP_FW_UPDATE_UP_DICT) | \ 61*4882a593Smuzhiyun (1 << UP_FW_UPDATE_BOOT) | \ 62*4882a593Smuzhiyun (1 << UP_FW_UPDATE_HLINK_ONE) | \ 63*4882a593Smuzhiyun (1 << UP_FW_UPDATE_HLINK_TWO) | \ 64*4882a593Smuzhiyun (1 << UP_FW_UPDATE_HLINK_THR)) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define _IMAGE_UCODE_ALL_IN ((1 << UP_FW_UPDATE_TILE_TEXT) | \ 67*4882a593Smuzhiyun (1 << UP_FW_UPDATE_TILE_DICT) | \ 68*4882a593Smuzhiyun (1 << UP_FW_UPDATE_PPE_STATE) | \ 69*4882a593Smuzhiyun (1 << UP_FW_UPDATE_PPE_BRANCH) | \ 70*4882a593Smuzhiyun (1 << UP_FW_UPDATE_PPE_EXTACT)) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define _IMAGE_COLD_SUB_MODULES_MUST_IN (_IMAGE_UP_ALL_IN | _IMAGE_UCODE_ALL_IN) 73*4882a593Smuzhiyun #define _IMAGE_HOT_SUB_MODULES_MUST_IN (_IMAGE_UP_ALL_IN | _IMAGE_UCODE_ALL_IN) 74*4882a593Smuzhiyun #define _IMAGE_CFG_SUB_MODULES_MUST_IN BIT(UP_FW_UPDATE_CFG) 75*4882a593Smuzhiyun #define UP_FW_UPDATE_UP_TEXT 0x0 76*4882a593Smuzhiyun #define UP_FW_UPDATE_UP_DATA 0x1 77*4882a593Smuzhiyun #define UP_FW_UPDATE_VPD_B 0x15 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun struct fw_section_info_st { 80*4882a593Smuzhiyun u32 fw_section_len; 81*4882a593Smuzhiyun u32 fw_section_offset; 82*4882a593Smuzhiyun u32 fw_section_version; 83*4882a593Smuzhiyun u32 fw_section_type; 84*4882a593Smuzhiyun u32 fw_section_crc; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun struct fw_image_st { 88*4882a593Smuzhiyun u32 fw_version; 89*4882a593Smuzhiyun u32 fw_len; 90*4882a593Smuzhiyun u32 fw_magic; 91*4882a593Smuzhiyun struct { 92*4882a593Smuzhiyun u32 fw_section_cnt:16; 93*4882a593Smuzhiyun u32 resd:16; 94*4882a593Smuzhiyun } fw_info; 95*4882a593Smuzhiyun struct fw_section_info_st fw_section_info[MAX_FW_TYPE_NUM]; 96*4882a593Smuzhiyun u32 device_id; 97*4882a593Smuzhiyun u32 res[101]; 98*4882a593Smuzhiyun void *bin_data; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun struct host_image_st { 102*4882a593Smuzhiyun struct fw_section_info_st image_section_info[MAX_FW_TYPE_NUM]; 103*4882a593Smuzhiyun struct { 104*4882a593Smuzhiyun u32 up_total_len; 105*4882a593Smuzhiyun u32 fw_version; 106*4882a593Smuzhiyun } image_info; 107*4882a593Smuzhiyun u32 section_type_num; 108*4882a593Smuzhiyun u32 device_id; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun struct devlink *hinic_devlink_alloc(void); 112*4882a593Smuzhiyun void hinic_devlink_free(struct devlink *devlink); 113*4882a593Smuzhiyun int hinic_devlink_register(struct hinic_devlink_priv *priv, struct device *dev); 114*4882a593Smuzhiyun void hinic_devlink_unregister(struct hinic_devlink_priv *priv); 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun int hinic_health_reporters_create(struct hinic_devlink_priv *priv); 117*4882a593Smuzhiyun void hinic_health_reporters_destroy(struct hinic_devlink_priv *priv); 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #endif /* __HINIC_DEVLINK_H__ */ 120