1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun // Copyright (c) 2016-2017 Hisilicon Limited. 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef __HNAE3_H 5*4882a593Smuzhiyun #define __HNAE3_H 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* Names used in this framework: 8*4882a593Smuzhiyun * ae handle (handle): 9*4882a593Smuzhiyun * a set of queues provided by AE 10*4882a593Smuzhiyun * ring buffer queue (rbq): 11*4882a593Smuzhiyun * the channel between upper layer and the AE, can do tx and rx 12*4882a593Smuzhiyun * ring: 13*4882a593Smuzhiyun * a tx or rx channel within a rbq 14*4882a593Smuzhiyun * ring description (desc): 15*4882a593Smuzhiyun * an element in the ring with packet information 16*4882a593Smuzhiyun * buffer: 17*4882a593Smuzhiyun * a memory region referred by desc with the full packet payload 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * "num" means a static number set as a parameter, "count" mean a dynamic 20*4882a593Smuzhiyun * number set while running 21*4882a593Smuzhiyun * "cb" means control block 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #include <linux/acpi.h> 25*4882a593Smuzhiyun #include <linux/dcbnl.h> 26*4882a593Smuzhiyun #include <linux/delay.h> 27*4882a593Smuzhiyun #include <linux/device.h> 28*4882a593Smuzhiyun #include <linux/module.h> 29*4882a593Smuzhiyun #include <linux/netdevice.h> 30*4882a593Smuzhiyun #include <linux/pci.h> 31*4882a593Smuzhiyun #include <linux/types.h> 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define HNAE3_MOD_VERSION "1.0" 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define HNAE3_MIN_VECTOR_NUM 2 /* first one for misc, another for IO */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Device version */ 38*4882a593Smuzhiyun #define HNAE3_DEVICE_VERSION_V1 0x00020 39*4882a593Smuzhiyun #define HNAE3_DEVICE_VERSION_V2 0x00021 40*4882a593Smuzhiyun #define HNAE3_DEVICE_VERSION_V3 0x00030 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define HNAE3_PCI_REVISION_BIT_SIZE 8 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Device IDs */ 45*4882a593Smuzhiyun #define HNAE3_DEV_ID_GE 0xA220 46*4882a593Smuzhiyun #define HNAE3_DEV_ID_25GE 0xA221 47*4882a593Smuzhiyun #define HNAE3_DEV_ID_25GE_RDMA 0xA222 48*4882a593Smuzhiyun #define HNAE3_DEV_ID_25GE_RDMA_MACSEC 0xA223 49*4882a593Smuzhiyun #define HNAE3_DEV_ID_50GE_RDMA 0xA224 50*4882a593Smuzhiyun #define HNAE3_DEV_ID_50GE_RDMA_MACSEC 0xA225 51*4882a593Smuzhiyun #define HNAE3_DEV_ID_100G_RDMA_MACSEC 0xA226 52*4882a593Smuzhiyun #define HNAE3_DEV_ID_200G_RDMA 0xA228 53*4882a593Smuzhiyun #define HNAE3_DEV_ID_VF 0xA22E 54*4882a593Smuzhiyun #define HNAE3_DEV_ID_RDMA_DCB_PFC_VF 0xA22F 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define HNAE3_CLASS_NAME_SIZE 16 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define HNAE3_DEV_INITED_B 0x0 59*4882a593Smuzhiyun #define HNAE3_DEV_SUPPORT_ROCE_B 0x1 60*4882a593Smuzhiyun #define HNAE3_DEV_SUPPORT_DCB_B 0x2 61*4882a593Smuzhiyun #define HNAE3_KNIC_CLIENT_INITED_B 0x3 62*4882a593Smuzhiyun #define HNAE3_UNIC_CLIENT_INITED_B 0x4 63*4882a593Smuzhiyun #define HNAE3_ROCE_CLIENT_INITED_B 0x5 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define HNAE3_DEV_SUPPORT_ROCE_DCB_BITS (BIT(HNAE3_DEV_SUPPORT_DCB_B) |\ 66*4882a593Smuzhiyun BIT(HNAE3_DEV_SUPPORT_ROCE_B)) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define hnae3_dev_roce_supported(hdev) \ 69*4882a593Smuzhiyun hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define hnae3_dev_dcb_supported(hdev) \ 72*4882a593Smuzhiyun hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun enum HNAE3_DEV_CAP_BITS { 75*4882a593Smuzhiyun HNAE3_DEV_SUPPORT_FD_B, 76*4882a593Smuzhiyun HNAE3_DEV_SUPPORT_GRO_B, 77*4882a593Smuzhiyun HNAE3_DEV_SUPPORT_FEC_B, 78*4882a593Smuzhiyun HNAE3_DEV_SUPPORT_UDP_GSO_B, 79*4882a593Smuzhiyun HNAE3_DEV_SUPPORT_QB_B, 80*4882a593Smuzhiyun HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, 81*4882a593Smuzhiyun HNAE3_DEV_SUPPORT_PTP_B, 82*4882a593Smuzhiyun HNAE3_DEV_SUPPORT_INT_QL_B, 83*4882a593Smuzhiyun HNAE3_DEV_SUPPORT_SIMPLE_BD_B, 84*4882a593Smuzhiyun HNAE3_DEV_SUPPORT_TX_PUSH_B, 85*4882a593Smuzhiyun HNAE3_DEV_SUPPORT_PHY_IMP_B, 86*4882a593Smuzhiyun HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, 87*4882a593Smuzhiyun HNAE3_DEV_SUPPORT_HW_PAD_B, 88*4882a593Smuzhiyun HNAE3_DEV_SUPPORT_STASH_B, 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define hnae3_dev_fd_supported(hdev) \ 92*4882a593Smuzhiyun test_bit(HNAE3_DEV_SUPPORT_FD_B, (hdev)->ae_dev->caps) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define hnae3_dev_gro_supported(hdev) \ 95*4882a593Smuzhiyun test_bit(HNAE3_DEV_SUPPORT_GRO_B, (hdev)->ae_dev->caps) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define hnae3_dev_fec_supported(hdev) \ 98*4882a593Smuzhiyun test_bit(HNAE3_DEV_SUPPORT_FEC_B, (hdev)->ae_dev->caps) 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define hnae3_dev_udp_gso_supported(hdev) \ 101*4882a593Smuzhiyun test_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, (hdev)->ae_dev->caps) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define hnae3_dev_qb_supported(hdev) \ 104*4882a593Smuzhiyun test_bit(HNAE3_DEV_SUPPORT_QB_B, (hdev)->ae_dev->caps) 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define hnae3_dev_fd_forward_tc_supported(hdev) \ 107*4882a593Smuzhiyun test_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, (hdev)->ae_dev->caps) 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define hnae3_dev_ptp_supported(hdev) \ 110*4882a593Smuzhiyun test_bit(HNAE3_DEV_SUPPORT_PTP_B, (hdev)->ae_dev->caps) 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define hnae3_dev_int_ql_supported(hdev) \ 113*4882a593Smuzhiyun test_bit(HNAE3_DEV_SUPPORT_INT_QL_B, (hdev)->ae_dev->caps) 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define hnae3_dev_simple_bd_supported(hdev) \ 116*4882a593Smuzhiyun test_bit(HNAE3_DEV_SUPPORT_SIMPLE_BD_B, (hdev)->ae_dev->caps) 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define hnae3_dev_tx_push_supported(hdev) \ 119*4882a593Smuzhiyun test_bit(HNAE3_DEV_SUPPORT_TX_PUSH_B, (hdev)->ae_dev->caps) 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define hnae3_dev_phy_imp_supported(hdev) \ 122*4882a593Smuzhiyun test_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, (hdev)->ae_dev->caps) 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #define hnae3_dev_tqp_txrx_indep_supported(hdev) \ 125*4882a593Smuzhiyun test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (hdev)->ae_dev->caps) 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define hnae3_dev_hw_pad_supported(hdev) \ 128*4882a593Smuzhiyun test_bit(HNAE3_DEV_SUPPORT_HW_PAD_B, (hdev)->ae_dev->caps) 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #define hnae3_dev_stash_supported(hdev) \ 131*4882a593Smuzhiyun test_bit(HNAE3_DEV_SUPPORT_STASH_B, (hdev)->ae_dev->caps) 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #define hnae3_ae_dev_tqp_txrx_indep_supported(ae_dev) \ 134*4882a593Smuzhiyun test_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, (ae_dev)->caps) 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #define ring_ptr_move_fw(ring, p) \ 137*4882a593Smuzhiyun ((ring)->p = ((ring)->p + 1) % (ring)->desc_num) 138*4882a593Smuzhiyun #define ring_ptr_move_bw(ring, p) \ 139*4882a593Smuzhiyun ((ring)->p = ((ring)->p - 1 + (ring)->desc_num) % (ring)->desc_num) 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun enum hns_desc_type { 142*4882a593Smuzhiyun DESC_TYPE_UNKNOWN, 143*4882a593Smuzhiyun DESC_TYPE_SKB, 144*4882a593Smuzhiyun DESC_TYPE_FRAGLIST_SKB, 145*4882a593Smuzhiyun DESC_TYPE_PAGE, 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun struct hnae3_handle; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun struct hnae3_queue { 151*4882a593Smuzhiyun void __iomem *io_base; 152*4882a593Smuzhiyun struct hnae3_ae_algo *ae_algo; 153*4882a593Smuzhiyun struct hnae3_handle *handle; 154*4882a593Smuzhiyun int tqp_index; /* index in a handle */ 155*4882a593Smuzhiyun u32 buf_size; /* size for hnae_desc->addr, preset by AE */ 156*4882a593Smuzhiyun u16 tx_desc_num; /* total number of tx desc */ 157*4882a593Smuzhiyun u16 rx_desc_num; /* total number of rx desc */ 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun struct hns3_mac_stats { 161*4882a593Smuzhiyun u64 tx_pause_cnt; 162*4882a593Smuzhiyun u64 rx_pause_cnt; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun /* hnae3 loop mode */ 166*4882a593Smuzhiyun enum hnae3_loop { 167*4882a593Smuzhiyun HNAE3_LOOP_APP, 168*4882a593Smuzhiyun HNAE3_LOOP_SERIAL_SERDES, 169*4882a593Smuzhiyun HNAE3_LOOP_PARALLEL_SERDES, 170*4882a593Smuzhiyun HNAE3_LOOP_PHY, 171*4882a593Smuzhiyun HNAE3_LOOP_NONE, 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun enum hnae3_client_type { 175*4882a593Smuzhiyun HNAE3_CLIENT_KNIC, 176*4882a593Smuzhiyun HNAE3_CLIENT_ROCE, 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun /* mac media type */ 180*4882a593Smuzhiyun enum hnae3_media_type { 181*4882a593Smuzhiyun HNAE3_MEDIA_TYPE_UNKNOWN, 182*4882a593Smuzhiyun HNAE3_MEDIA_TYPE_FIBER, 183*4882a593Smuzhiyun HNAE3_MEDIA_TYPE_COPPER, 184*4882a593Smuzhiyun HNAE3_MEDIA_TYPE_BACKPLANE, 185*4882a593Smuzhiyun HNAE3_MEDIA_TYPE_NONE, 186*4882a593Smuzhiyun }; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun /* must be consistent with definition in firmware */ 189*4882a593Smuzhiyun enum hnae3_module_type { 190*4882a593Smuzhiyun HNAE3_MODULE_TYPE_UNKNOWN = 0x00, 191*4882a593Smuzhiyun HNAE3_MODULE_TYPE_FIBRE_LR = 0x01, 192*4882a593Smuzhiyun HNAE3_MODULE_TYPE_FIBRE_SR = 0x02, 193*4882a593Smuzhiyun HNAE3_MODULE_TYPE_AOC = 0x03, 194*4882a593Smuzhiyun HNAE3_MODULE_TYPE_CR = 0x04, 195*4882a593Smuzhiyun HNAE3_MODULE_TYPE_KR = 0x05, 196*4882a593Smuzhiyun HNAE3_MODULE_TYPE_TP = 0x06, 197*4882a593Smuzhiyun }; 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun enum hnae3_fec_mode { 200*4882a593Smuzhiyun HNAE3_FEC_AUTO = 0, 201*4882a593Smuzhiyun HNAE3_FEC_BASER, 202*4882a593Smuzhiyun HNAE3_FEC_RS, 203*4882a593Smuzhiyun HNAE3_FEC_USER_DEF, 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun enum hnae3_reset_notify_type { 207*4882a593Smuzhiyun HNAE3_UP_CLIENT, 208*4882a593Smuzhiyun HNAE3_DOWN_CLIENT, 209*4882a593Smuzhiyun HNAE3_INIT_CLIENT, 210*4882a593Smuzhiyun HNAE3_UNINIT_CLIENT, 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun enum hnae3_hw_error_type { 214*4882a593Smuzhiyun HNAE3_PPU_POISON_ERROR, 215*4882a593Smuzhiyun HNAE3_CMDQ_ECC_ERROR, 216*4882a593Smuzhiyun HNAE3_IMP_RD_POISON_ERROR, 217*4882a593Smuzhiyun HNAE3_ROCEE_AXI_RESP_ERROR, 218*4882a593Smuzhiyun }; 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun enum hnae3_reset_type { 221*4882a593Smuzhiyun HNAE3_VF_RESET, 222*4882a593Smuzhiyun HNAE3_VF_FUNC_RESET, 223*4882a593Smuzhiyun HNAE3_VF_PF_FUNC_RESET, 224*4882a593Smuzhiyun HNAE3_VF_FULL_RESET, 225*4882a593Smuzhiyun HNAE3_FLR_RESET, 226*4882a593Smuzhiyun HNAE3_FUNC_RESET, 227*4882a593Smuzhiyun HNAE3_GLOBAL_RESET, 228*4882a593Smuzhiyun HNAE3_IMP_RESET, 229*4882a593Smuzhiyun HNAE3_UNKNOWN_RESET, 230*4882a593Smuzhiyun HNAE3_NONE_RESET, 231*4882a593Smuzhiyun HNAE3_MAX_RESET, 232*4882a593Smuzhiyun }; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun enum hnae3_port_base_vlan_state { 235*4882a593Smuzhiyun HNAE3_PORT_BASE_VLAN_DISABLE, 236*4882a593Smuzhiyun HNAE3_PORT_BASE_VLAN_ENABLE, 237*4882a593Smuzhiyun HNAE3_PORT_BASE_VLAN_MODIFY, 238*4882a593Smuzhiyun HNAE3_PORT_BASE_VLAN_NOCHANGE, 239*4882a593Smuzhiyun }; 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun struct hnae3_vector_info { 242*4882a593Smuzhiyun u8 __iomem *io_addr; 243*4882a593Smuzhiyun int vector; 244*4882a593Smuzhiyun }; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun #define HNAE3_RING_TYPE_B 0 247*4882a593Smuzhiyun #define HNAE3_RING_TYPE_TX 0 248*4882a593Smuzhiyun #define HNAE3_RING_TYPE_RX 1 249*4882a593Smuzhiyun #define HNAE3_RING_GL_IDX_S 0 250*4882a593Smuzhiyun #define HNAE3_RING_GL_IDX_M GENMASK(1, 0) 251*4882a593Smuzhiyun #define HNAE3_RING_GL_RX 0 252*4882a593Smuzhiyun #define HNAE3_RING_GL_TX 1 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun #define HNAE3_FW_VERSION_BYTE3_SHIFT 24 255*4882a593Smuzhiyun #define HNAE3_FW_VERSION_BYTE3_MASK GENMASK(31, 24) 256*4882a593Smuzhiyun #define HNAE3_FW_VERSION_BYTE2_SHIFT 16 257*4882a593Smuzhiyun #define HNAE3_FW_VERSION_BYTE2_MASK GENMASK(23, 16) 258*4882a593Smuzhiyun #define HNAE3_FW_VERSION_BYTE1_SHIFT 8 259*4882a593Smuzhiyun #define HNAE3_FW_VERSION_BYTE1_MASK GENMASK(15, 8) 260*4882a593Smuzhiyun #define HNAE3_FW_VERSION_BYTE0_SHIFT 0 261*4882a593Smuzhiyun #define HNAE3_FW_VERSION_BYTE0_MASK GENMASK(7, 0) 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun struct hnae3_ring_chain_node { 264*4882a593Smuzhiyun struct hnae3_ring_chain_node *next; 265*4882a593Smuzhiyun u32 tqp_index; 266*4882a593Smuzhiyun u32 flag; 267*4882a593Smuzhiyun u32 int_gl_idx; 268*4882a593Smuzhiyun }; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun #define HNAE3_IS_TX_RING(node) \ 271*4882a593Smuzhiyun (((node)->flag & (1 << HNAE3_RING_TYPE_B)) == HNAE3_RING_TYPE_TX) 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun /* device specification info from firmware */ 274*4882a593Smuzhiyun struct hnae3_dev_specs { 275*4882a593Smuzhiyun u32 mac_entry_num; /* number of mac-vlan table entry */ 276*4882a593Smuzhiyun u32 mng_entry_num; /* number of manager table entry */ 277*4882a593Smuzhiyun u32 max_tm_rate; 278*4882a593Smuzhiyun u16 rss_ind_tbl_size; 279*4882a593Smuzhiyun u16 rss_key_size; 280*4882a593Smuzhiyun u16 int_ql_max; /* max value of interrupt coalesce based on INT_QL */ 281*4882a593Smuzhiyun u8 max_non_tso_bd_num; /* max BD number of one non-TSO packet */ 282*4882a593Smuzhiyun }; 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun struct hnae3_client_ops { 285*4882a593Smuzhiyun int (*init_instance)(struct hnae3_handle *handle); 286*4882a593Smuzhiyun void (*uninit_instance)(struct hnae3_handle *handle, bool reset); 287*4882a593Smuzhiyun void (*link_status_change)(struct hnae3_handle *handle, bool state); 288*4882a593Smuzhiyun int (*setup_tc)(struct hnae3_handle *handle, u8 tc); 289*4882a593Smuzhiyun int (*reset_notify)(struct hnae3_handle *handle, 290*4882a593Smuzhiyun enum hnae3_reset_notify_type type); 291*4882a593Smuzhiyun void (*process_hw_error)(struct hnae3_handle *handle, 292*4882a593Smuzhiyun enum hnae3_hw_error_type); 293*4882a593Smuzhiyun }; 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun #define HNAE3_CLIENT_NAME_LENGTH 16 296*4882a593Smuzhiyun struct hnae3_client { 297*4882a593Smuzhiyun char name[HNAE3_CLIENT_NAME_LENGTH]; 298*4882a593Smuzhiyun unsigned long state; 299*4882a593Smuzhiyun enum hnae3_client_type type; 300*4882a593Smuzhiyun const struct hnae3_client_ops *ops; 301*4882a593Smuzhiyun struct list_head node; 302*4882a593Smuzhiyun }; 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun #define HNAE3_DEV_CAPS_MAX_NUM 96 305*4882a593Smuzhiyun struct hnae3_ae_dev { 306*4882a593Smuzhiyun struct pci_dev *pdev; 307*4882a593Smuzhiyun const struct hnae3_ae_ops *ops; 308*4882a593Smuzhiyun struct list_head node; 309*4882a593Smuzhiyun u32 flag; 310*4882a593Smuzhiyun unsigned long hw_err_reset_req; 311*4882a593Smuzhiyun struct hnae3_dev_specs dev_specs; 312*4882a593Smuzhiyun u32 dev_version; 313*4882a593Smuzhiyun unsigned long caps[BITS_TO_LONGS(HNAE3_DEV_CAPS_MAX_NUM)]; 314*4882a593Smuzhiyun void *priv; 315*4882a593Smuzhiyun }; 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun /* This struct defines the operation on the handle. 318*4882a593Smuzhiyun * 319*4882a593Smuzhiyun * init_ae_dev(): (mandatory) 320*4882a593Smuzhiyun * Get PF configure from pci_dev and initialize PF hardware 321*4882a593Smuzhiyun * uninit_ae_dev() 322*4882a593Smuzhiyun * Disable PF device and release PF resource 323*4882a593Smuzhiyun * register_client 324*4882a593Smuzhiyun * Register client to ae_dev 325*4882a593Smuzhiyun * unregister_client() 326*4882a593Smuzhiyun * Unregister client from ae_dev 327*4882a593Smuzhiyun * start() 328*4882a593Smuzhiyun * Enable the hardware 329*4882a593Smuzhiyun * stop() 330*4882a593Smuzhiyun * Disable the hardware 331*4882a593Smuzhiyun * start_client() 332*4882a593Smuzhiyun * Inform the hclge that client has been started 333*4882a593Smuzhiyun * stop_client() 334*4882a593Smuzhiyun * Inform the hclge that client has been stopped 335*4882a593Smuzhiyun * get_status() 336*4882a593Smuzhiyun * Get the carrier state of the back channel of the handle, 1 for ok, 0 for 337*4882a593Smuzhiyun * non-ok 338*4882a593Smuzhiyun * get_ksettings_an_result() 339*4882a593Smuzhiyun * Get negotiation status,speed and duplex 340*4882a593Smuzhiyun * get_media_type() 341*4882a593Smuzhiyun * Get media type of MAC 342*4882a593Smuzhiyun * check_port_speed() 343*4882a593Smuzhiyun * Check target speed whether is supported 344*4882a593Smuzhiyun * adjust_link() 345*4882a593Smuzhiyun * Adjust link status 346*4882a593Smuzhiyun * set_loopback() 347*4882a593Smuzhiyun * Set loopback 348*4882a593Smuzhiyun * set_promisc_mode 349*4882a593Smuzhiyun * Set promisc mode 350*4882a593Smuzhiyun * request_update_promisc_mode 351*4882a593Smuzhiyun * request to hclge(vf) to update promisc mode 352*4882a593Smuzhiyun * set_mtu() 353*4882a593Smuzhiyun * set mtu 354*4882a593Smuzhiyun * get_pauseparam() 355*4882a593Smuzhiyun * get tx and rx of pause frame use 356*4882a593Smuzhiyun * set_pauseparam() 357*4882a593Smuzhiyun * set tx and rx of pause frame use 358*4882a593Smuzhiyun * set_autoneg() 359*4882a593Smuzhiyun * set auto autonegotiation of pause frame use 360*4882a593Smuzhiyun * get_autoneg() 361*4882a593Smuzhiyun * get auto autonegotiation of pause frame use 362*4882a593Smuzhiyun * restart_autoneg() 363*4882a593Smuzhiyun * restart autonegotiation 364*4882a593Smuzhiyun * halt_autoneg() 365*4882a593Smuzhiyun * halt/resume autonegotiation when autonegotiation on 366*4882a593Smuzhiyun * get_coalesce_usecs() 367*4882a593Smuzhiyun * get usecs to delay a TX interrupt after a packet is sent 368*4882a593Smuzhiyun * get_rx_max_coalesced_frames() 369*4882a593Smuzhiyun * get Maximum number of packets to be sent before a TX interrupt. 370*4882a593Smuzhiyun * set_coalesce_usecs() 371*4882a593Smuzhiyun * set usecs to delay a TX interrupt after a packet is sent 372*4882a593Smuzhiyun * set_coalesce_frames() 373*4882a593Smuzhiyun * set Maximum number of packets to be sent before a TX interrupt. 374*4882a593Smuzhiyun * get_mac_addr() 375*4882a593Smuzhiyun * get mac address 376*4882a593Smuzhiyun * set_mac_addr() 377*4882a593Smuzhiyun * set mac address 378*4882a593Smuzhiyun * add_uc_addr 379*4882a593Smuzhiyun * Add unicast addr to mac table 380*4882a593Smuzhiyun * rm_uc_addr 381*4882a593Smuzhiyun * Remove unicast addr from mac table 382*4882a593Smuzhiyun * set_mc_addr() 383*4882a593Smuzhiyun * Set multicast address 384*4882a593Smuzhiyun * add_mc_addr 385*4882a593Smuzhiyun * Add multicast address to mac table 386*4882a593Smuzhiyun * rm_mc_addr 387*4882a593Smuzhiyun * Remove multicast address from mac table 388*4882a593Smuzhiyun * update_stats() 389*4882a593Smuzhiyun * Update Old network device statistics 390*4882a593Smuzhiyun * get_mac_stats() 391*4882a593Smuzhiyun * get mac pause statistics including tx_cnt and rx_cnt 392*4882a593Smuzhiyun * get_ethtool_stats() 393*4882a593Smuzhiyun * Get ethtool network device statistics 394*4882a593Smuzhiyun * get_strings() 395*4882a593Smuzhiyun * Get a set of strings that describe the requested objects 396*4882a593Smuzhiyun * get_sset_count() 397*4882a593Smuzhiyun * Get number of strings that @get_strings will write 398*4882a593Smuzhiyun * update_led_status() 399*4882a593Smuzhiyun * Update the led status 400*4882a593Smuzhiyun * set_led_id() 401*4882a593Smuzhiyun * Set led id 402*4882a593Smuzhiyun * get_regs() 403*4882a593Smuzhiyun * Get regs dump 404*4882a593Smuzhiyun * get_regs_len() 405*4882a593Smuzhiyun * Get the len of the regs dump 406*4882a593Smuzhiyun * get_rss_key_size() 407*4882a593Smuzhiyun * Get rss key size 408*4882a593Smuzhiyun * get_rss_indir_size() 409*4882a593Smuzhiyun * Get rss indirection table size 410*4882a593Smuzhiyun * get_rss() 411*4882a593Smuzhiyun * Get rss table 412*4882a593Smuzhiyun * set_rss() 413*4882a593Smuzhiyun * Set rss table 414*4882a593Smuzhiyun * get_tc_size() 415*4882a593Smuzhiyun * Get tc size of handle 416*4882a593Smuzhiyun * get_vector() 417*4882a593Smuzhiyun * Get vector number and vector information 418*4882a593Smuzhiyun * put_vector() 419*4882a593Smuzhiyun * Put the vector in hdev 420*4882a593Smuzhiyun * map_ring_to_vector() 421*4882a593Smuzhiyun * Map rings to vector 422*4882a593Smuzhiyun * unmap_ring_from_vector() 423*4882a593Smuzhiyun * Unmap rings from vector 424*4882a593Smuzhiyun * reset_queue() 425*4882a593Smuzhiyun * Reset queue 426*4882a593Smuzhiyun * get_fw_version() 427*4882a593Smuzhiyun * Get firmware version 428*4882a593Smuzhiyun * get_mdix_mode() 429*4882a593Smuzhiyun * Get media typr of phy 430*4882a593Smuzhiyun * enable_vlan_filter() 431*4882a593Smuzhiyun * Enable vlan filter 432*4882a593Smuzhiyun * set_vlan_filter() 433*4882a593Smuzhiyun * Set vlan filter config of Ports 434*4882a593Smuzhiyun * set_vf_vlan_filter() 435*4882a593Smuzhiyun * Set vlan filter config of vf 436*4882a593Smuzhiyun * enable_hw_strip_rxvtag() 437*4882a593Smuzhiyun * Enable/disable hardware strip vlan tag of packets received 438*4882a593Smuzhiyun * set_gro_en 439*4882a593Smuzhiyun * Enable/disable HW GRO 440*4882a593Smuzhiyun * add_arfs_entry 441*4882a593Smuzhiyun * Check the 5-tuples of flow, and create flow director rule 442*4882a593Smuzhiyun * get_vf_config 443*4882a593Smuzhiyun * Get the VF configuration setting by the host 444*4882a593Smuzhiyun * set_vf_link_state 445*4882a593Smuzhiyun * Set VF link status 446*4882a593Smuzhiyun * set_vf_spoofchk 447*4882a593Smuzhiyun * Enable/disable spoof check for specified vf 448*4882a593Smuzhiyun * set_vf_trust 449*4882a593Smuzhiyun * Enable/disable trust for specified vf, if the vf being trusted, then 450*4882a593Smuzhiyun * it can enable promisc mode 451*4882a593Smuzhiyun * set_vf_rate 452*4882a593Smuzhiyun * Set the max tx rate of specified vf. 453*4882a593Smuzhiyun * set_vf_mac 454*4882a593Smuzhiyun * Configure the default MAC for specified VF 455*4882a593Smuzhiyun * get_module_eeprom 456*4882a593Smuzhiyun * Get the optical module eeprom info. 457*4882a593Smuzhiyun */ 458*4882a593Smuzhiyun struct hnae3_ae_ops { 459*4882a593Smuzhiyun int (*init_ae_dev)(struct hnae3_ae_dev *ae_dev); 460*4882a593Smuzhiyun void (*uninit_ae_dev)(struct hnae3_ae_dev *ae_dev); 461*4882a593Smuzhiyun void (*flr_prepare)(struct hnae3_ae_dev *ae_dev); 462*4882a593Smuzhiyun void (*flr_done)(struct hnae3_ae_dev *ae_dev); 463*4882a593Smuzhiyun int (*init_client_instance)(struct hnae3_client *client, 464*4882a593Smuzhiyun struct hnae3_ae_dev *ae_dev); 465*4882a593Smuzhiyun void (*uninit_client_instance)(struct hnae3_client *client, 466*4882a593Smuzhiyun struct hnae3_ae_dev *ae_dev); 467*4882a593Smuzhiyun int (*start)(struct hnae3_handle *handle); 468*4882a593Smuzhiyun void (*stop)(struct hnae3_handle *handle); 469*4882a593Smuzhiyun int (*client_start)(struct hnae3_handle *handle); 470*4882a593Smuzhiyun void (*client_stop)(struct hnae3_handle *handle); 471*4882a593Smuzhiyun int (*get_status)(struct hnae3_handle *handle); 472*4882a593Smuzhiyun void (*get_ksettings_an_result)(struct hnae3_handle *handle, 473*4882a593Smuzhiyun u8 *auto_neg, u32 *speed, u8 *duplex); 474*4882a593Smuzhiyun 475*4882a593Smuzhiyun int (*cfg_mac_speed_dup_h)(struct hnae3_handle *handle, int speed, 476*4882a593Smuzhiyun u8 duplex); 477*4882a593Smuzhiyun 478*4882a593Smuzhiyun void (*get_media_type)(struct hnae3_handle *handle, u8 *media_type, 479*4882a593Smuzhiyun u8 *module_type); 480*4882a593Smuzhiyun int (*check_port_speed)(struct hnae3_handle *handle, u32 speed); 481*4882a593Smuzhiyun void (*get_fec)(struct hnae3_handle *handle, u8 *fec_ability, 482*4882a593Smuzhiyun u8 *fec_mode); 483*4882a593Smuzhiyun int (*set_fec)(struct hnae3_handle *handle, u32 fec_mode); 484*4882a593Smuzhiyun void (*adjust_link)(struct hnae3_handle *handle, int speed, int duplex); 485*4882a593Smuzhiyun int (*set_loopback)(struct hnae3_handle *handle, 486*4882a593Smuzhiyun enum hnae3_loop loop_mode, bool en); 487*4882a593Smuzhiyun 488*4882a593Smuzhiyun int (*set_promisc_mode)(struct hnae3_handle *handle, bool en_uc_pmc, 489*4882a593Smuzhiyun bool en_mc_pmc); 490*4882a593Smuzhiyun void (*request_update_promisc_mode)(struct hnae3_handle *handle); 491*4882a593Smuzhiyun int (*set_mtu)(struct hnae3_handle *handle, int new_mtu); 492*4882a593Smuzhiyun 493*4882a593Smuzhiyun void (*get_pauseparam)(struct hnae3_handle *handle, 494*4882a593Smuzhiyun u32 *auto_neg, u32 *rx_en, u32 *tx_en); 495*4882a593Smuzhiyun int (*set_pauseparam)(struct hnae3_handle *handle, 496*4882a593Smuzhiyun u32 auto_neg, u32 rx_en, u32 tx_en); 497*4882a593Smuzhiyun 498*4882a593Smuzhiyun int (*set_autoneg)(struct hnae3_handle *handle, bool enable); 499*4882a593Smuzhiyun int (*get_autoneg)(struct hnae3_handle *handle); 500*4882a593Smuzhiyun int (*restart_autoneg)(struct hnae3_handle *handle); 501*4882a593Smuzhiyun int (*halt_autoneg)(struct hnae3_handle *handle, bool halt); 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun void (*get_coalesce_usecs)(struct hnae3_handle *handle, 504*4882a593Smuzhiyun u32 *tx_usecs, u32 *rx_usecs); 505*4882a593Smuzhiyun void (*get_rx_max_coalesced_frames)(struct hnae3_handle *handle, 506*4882a593Smuzhiyun u32 *tx_frames, u32 *rx_frames); 507*4882a593Smuzhiyun int (*set_coalesce_usecs)(struct hnae3_handle *handle, u32 timeout); 508*4882a593Smuzhiyun int (*set_coalesce_frames)(struct hnae3_handle *handle, 509*4882a593Smuzhiyun u32 coalesce_frames); 510*4882a593Smuzhiyun void (*get_coalesce_range)(struct hnae3_handle *handle, 511*4882a593Smuzhiyun u32 *tx_frames_low, u32 *rx_frames_low, 512*4882a593Smuzhiyun u32 *tx_frames_high, u32 *rx_frames_high, 513*4882a593Smuzhiyun u32 *tx_usecs_low, u32 *rx_usecs_low, 514*4882a593Smuzhiyun u32 *tx_usecs_high, u32 *rx_usecs_high); 515*4882a593Smuzhiyun 516*4882a593Smuzhiyun void (*get_mac_addr)(struct hnae3_handle *handle, u8 *p); 517*4882a593Smuzhiyun int (*set_mac_addr)(struct hnae3_handle *handle, void *p, 518*4882a593Smuzhiyun bool is_first); 519*4882a593Smuzhiyun int (*do_ioctl)(struct hnae3_handle *handle, 520*4882a593Smuzhiyun struct ifreq *ifr, int cmd); 521*4882a593Smuzhiyun int (*add_uc_addr)(struct hnae3_handle *handle, 522*4882a593Smuzhiyun const unsigned char *addr); 523*4882a593Smuzhiyun int (*rm_uc_addr)(struct hnae3_handle *handle, 524*4882a593Smuzhiyun const unsigned char *addr); 525*4882a593Smuzhiyun int (*set_mc_addr)(struct hnae3_handle *handle, void *addr); 526*4882a593Smuzhiyun int (*add_mc_addr)(struct hnae3_handle *handle, 527*4882a593Smuzhiyun const unsigned char *addr); 528*4882a593Smuzhiyun int (*rm_mc_addr)(struct hnae3_handle *handle, 529*4882a593Smuzhiyun const unsigned char *addr); 530*4882a593Smuzhiyun void (*set_tso_stats)(struct hnae3_handle *handle, int enable); 531*4882a593Smuzhiyun void (*update_stats)(struct hnae3_handle *handle, 532*4882a593Smuzhiyun struct net_device_stats *net_stats); 533*4882a593Smuzhiyun void (*get_stats)(struct hnae3_handle *handle, u64 *data); 534*4882a593Smuzhiyun void (*get_mac_stats)(struct hnae3_handle *handle, 535*4882a593Smuzhiyun struct hns3_mac_stats *mac_stats); 536*4882a593Smuzhiyun void (*get_strings)(struct hnae3_handle *handle, 537*4882a593Smuzhiyun u32 stringset, u8 *data); 538*4882a593Smuzhiyun int (*get_sset_count)(struct hnae3_handle *handle, int stringset); 539*4882a593Smuzhiyun 540*4882a593Smuzhiyun void (*get_regs)(struct hnae3_handle *handle, u32 *version, 541*4882a593Smuzhiyun void *data); 542*4882a593Smuzhiyun int (*get_regs_len)(struct hnae3_handle *handle); 543*4882a593Smuzhiyun 544*4882a593Smuzhiyun u32 (*get_rss_key_size)(struct hnae3_handle *handle); 545*4882a593Smuzhiyun u32 (*get_rss_indir_size)(struct hnae3_handle *handle); 546*4882a593Smuzhiyun int (*get_rss)(struct hnae3_handle *handle, u32 *indir, u8 *key, 547*4882a593Smuzhiyun u8 *hfunc); 548*4882a593Smuzhiyun int (*set_rss)(struct hnae3_handle *handle, const u32 *indir, 549*4882a593Smuzhiyun const u8 *key, const u8 hfunc); 550*4882a593Smuzhiyun int (*set_rss_tuple)(struct hnae3_handle *handle, 551*4882a593Smuzhiyun struct ethtool_rxnfc *cmd); 552*4882a593Smuzhiyun int (*get_rss_tuple)(struct hnae3_handle *handle, 553*4882a593Smuzhiyun struct ethtool_rxnfc *cmd); 554*4882a593Smuzhiyun 555*4882a593Smuzhiyun int (*get_tc_size)(struct hnae3_handle *handle); 556*4882a593Smuzhiyun 557*4882a593Smuzhiyun int (*get_vector)(struct hnae3_handle *handle, u16 vector_num, 558*4882a593Smuzhiyun struct hnae3_vector_info *vector_info); 559*4882a593Smuzhiyun int (*put_vector)(struct hnae3_handle *handle, int vector_num); 560*4882a593Smuzhiyun int (*map_ring_to_vector)(struct hnae3_handle *handle, 561*4882a593Smuzhiyun int vector_num, 562*4882a593Smuzhiyun struct hnae3_ring_chain_node *vr_chain); 563*4882a593Smuzhiyun int (*unmap_ring_from_vector)(struct hnae3_handle *handle, 564*4882a593Smuzhiyun int vector_num, 565*4882a593Smuzhiyun struct hnae3_ring_chain_node *vr_chain); 566*4882a593Smuzhiyun 567*4882a593Smuzhiyun int (*reset_queue)(struct hnae3_handle *handle, u16 queue_id); 568*4882a593Smuzhiyun u32 (*get_fw_version)(struct hnae3_handle *handle); 569*4882a593Smuzhiyun void (*get_mdix_mode)(struct hnae3_handle *handle, 570*4882a593Smuzhiyun u8 *tp_mdix_ctrl, u8 *tp_mdix); 571*4882a593Smuzhiyun 572*4882a593Smuzhiyun void (*enable_vlan_filter)(struct hnae3_handle *handle, bool enable); 573*4882a593Smuzhiyun int (*set_vlan_filter)(struct hnae3_handle *handle, __be16 proto, 574*4882a593Smuzhiyun u16 vlan_id, bool is_kill); 575*4882a593Smuzhiyun int (*set_vf_vlan_filter)(struct hnae3_handle *handle, int vfid, 576*4882a593Smuzhiyun u16 vlan, u8 qos, __be16 proto); 577*4882a593Smuzhiyun int (*enable_hw_strip_rxvtag)(struct hnae3_handle *handle, bool enable); 578*4882a593Smuzhiyun void (*reset_event)(struct pci_dev *pdev, struct hnae3_handle *handle); 579*4882a593Smuzhiyun enum hnae3_reset_type (*get_reset_level)(struct hnae3_ae_dev *ae_dev, 580*4882a593Smuzhiyun unsigned long *addr); 581*4882a593Smuzhiyun void (*set_default_reset_request)(struct hnae3_ae_dev *ae_dev, 582*4882a593Smuzhiyun enum hnae3_reset_type rst_type); 583*4882a593Smuzhiyun void (*get_channels)(struct hnae3_handle *handle, 584*4882a593Smuzhiyun struct ethtool_channels *ch); 585*4882a593Smuzhiyun void (*get_tqps_and_rss_info)(struct hnae3_handle *h, 586*4882a593Smuzhiyun u16 *alloc_tqps, u16 *max_rss_size); 587*4882a593Smuzhiyun int (*set_channels)(struct hnae3_handle *handle, u32 new_tqps_num, 588*4882a593Smuzhiyun bool rxfh_configured); 589*4882a593Smuzhiyun void (*get_flowctrl_adv)(struct hnae3_handle *handle, 590*4882a593Smuzhiyun u32 *flowctrl_adv); 591*4882a593Smuzhiyun int (*set_led_id)(struct hnae3_handle *handle, 592*4882a593Smuzhiyun enum ethtool_phys_id_state status); 593*4882a593Smuzhiyun void (*get_link_mode)(struct hnae3_handle *handle, 594*4882a593Smuzhiyun unsigned long *supported, 595*4882a593Smuzhiyun unsigned long *advertising); 596*4882a593Smuzhiyun int (*add_fd_entry)(struct hnae3_handle *handle, 597*4882a593Smuzhiyun struct ethtool_rxnfc *cmd); 598*4882a593Smuzhiyun int (*del_fd_entry)(struct hnae3_handle *handle, 599*4882a593Smuzhiyun struct ethtool_rxnfc *cmd); 600*4882a593Smuzhiyun void (*del_all_fd_entries)(struct hnae3_handle *handle, 601*4882a593Smuzhiyun bool clear_list); 602*4882a593Smuzhiyun int (*get_fd_rule_cnt)(struct hnae3_handle *handle, 603*4882a593Smuzhiyun struct ethtool_rxnfc *cmd); 604*4882a593Smuzhiyun int (*get_fd_rule_info)(struct hnae3_handle *handle, 605*4882a593Smuzhiyun struct ethtool_rxnfc *cmd); 606*4882a593Smuzhiyun int (*get_fd_all_rules)(struct hnae3_handle *handle, 607*4882a593Smuzhiyun struct ethtool_rxnfc *cmd, u32 *rule_locs); 608*4882a593Smuzhiyun void (*enable_fd)(struct hnae3_handle *handle, bool enable); 609*4882a593Smuzhiyun int (*add_arfs_entry)(struct hnae3_handle *handle, u16 queue_id, 610*4882a593Smuzhiyun u16 flow_id, struct flow_keys *fkeys); 611*4882a593Smuzhiyun int (*dbg_run_cmd)(struct hnae3_handle *handle, const char *cmd_buf); 612*4882a593Smuzhiyun pci_ers_result_t (*handle_hw_ras_error)(struct hnae3_ae_dev *ae_dev); 613*4882a593Smuzhiyun bool (*get_hw_reset_stat)(struct hnae3_handle *handle); 614*4882a593Smuzhiyun bool (*ae_dev_resetting)(struct hnae3_handle *handle); 615*4882a593Smuzhiyun unsigned long (*ae_dev_reset_cnt)(struct hnae3_handle *handle); 616*4882a593Smuzhiyun int (*set_gro_en)(struct hnae3_handle *handle, bool enable); 617*4882a593Smuzhiyun u16 (*get_global_queue_id)(struct hnae3_handle *handle, u16 queue_id); 618*4882a593Smuzhiyun void (*set_timer_task)(struct hnae3_handle *handle, bool enable); 619*4882a593Smuzhiyun int (*mac_connect_phy)(struct hnae3_handle *handle); 620*4882a593Smuzhiyun void (*mac_disconnect_phy)(struct hnae3_handle *handle); 621*4882a593Smuzhiyun int (*get_vf_config)(struct hnae3_handle *handle, int vf, 622*4882a593Smuzhiyun struct ifla_vf_info *ivf); 623*4882a593Smuzhiyun int (*set_vf_link_state)(struct hnae3_handle *handle, int vf, 624*4882a593Smuzhiyun int link_state); 625*4882a593Smuzhiyun int (*set_vf_spoofchk)(struct hnae3_handle *handle, int vf, 626*4882a593Smuzhiyun bool enable); 627*4882a593Smuzhiyun int (*set_vf_trust)(struct hnae3_handle *handle, int vf, bool enable); 628*4882a593Smuzhiyun int (*set_vf_rate)(struct hnae3_handle *handle, int vf, 629*4882a593Smuzhiyun int min_tx_rate, int max_tx_rate, bool force); 630*4882a593Smuzhiyun int (*set_vf_mac)(struct hnae3_handle *handle, int vf, u8 *p); 631*4882a593Smuzhiyun int (*get_module_eeprom)(struct hnae3_handle *handle, u32 offset, 632*4882a593Smuzhiyun u32 len, u8 *data); 633*4882a593Smuzhiyun bool (*get_cmdq_stat)(struct hnae3_handle *handle); 634*4882a593Smuzhiyun }; 635*4882a593Smuzhiyun 636*4882a593Smuzhiyun struct hnae3_dcb_ops { 637*4882a593Smuzhiyun /* IEEE 802.1Qaz std */ 638*4882a593Smuzhiyun int (*ieee_getets)(struct hnae3_handle *, struct ieee_ets *); 639*4882a593Smuzhiyun int (*ieee_setets)(struct hnae3_handle *, struct ieee_ets *); 640*4882a593Smuzhiyun int (*ieee_getpfc)(struct hnae3_handle *, struct ieee_pfc *); 641*4882a593Smuzhiyun int (*ieee_setpfc)(struct hnae3_handle *, struct ieee_pfc *); 642*4882a593Smuzhiyun 643*4882a593Smuzhiyun /* DCBX configuration */ 644*4882a593Smuzhiyun u8 (*getdcbx)(struct hnae3_handle *); 645*4882a593Smuzhiyun u8 (*setdcbx)(struct hnae3_handle *, u8); 646*4882a593Smuzhiyun 647*4882a593Smuzhiyun int (*setup_tc)(struct hnae3_handle *, u8, u8 *); 648*4882a593Smuzhiyun }; 649*4882a593Smuzhiyun 650*4882a593Smuzhiyun struct hnae3_ae_algo { 651*4882a593Smuzhiyun const struct hnae3_ae_ops *ops; 652*4882a593Smuzhiyun struct list_head node; 653*4882a593Smuzhiyun const struct pci_device_id *pdev_id_table; 654*4882a593Smuzhiyun }; 655*4882a593Smuzhiyun 656*4882a593Smuzhiyun #define HNAE3_INT_NAME_LEN 32 657*4882a593Smuzhiyun #define HNAE3_ITR_COUNTDOWN_START 100 658*4882a593Smuzhiyun 659*4882a593Smuzhiyun struct hnae3_tc_info { 660*4882a593Smuzhiyun u16 tqp_offset; /* TQP offset from base TQP */ 661*4882a593Smuzhiyun u16 tqp_count; /* Total TQPs */ 662*4882a593Smuzhiyun u8 tc; /* TC index */ 663*4882a593Smuzhiyun bool enable; /* If this TC is enable or not */ 664*4882a593Smuzhiyun }; 665*4882a593Smuzhiyun 666*4882a593Smuzhiyun #define HNAE3_MAX_TC 8 667*4882a593Smuzhiyun #define HNAE3_MAX_USER_PRIO 8 668*4882a593Smuzhiyun struct hnae3_knic_private_info { 669*4882a593Smuzhiyun struct net_device *netdev; /* Set by KNIC client when init instance */ 670*4882a593Smuzhiyun u16 rss_size; /* Allocated RSS queues */ 671*4882a593Smuzhiyun u16 req_rss_size; 672*4882a593Smuzhiyun u16 rx_buf_len; 673*4882a593Smuzhiyun u16 num_tx_desc; 674*4882a593Smuzhiyun u16 num_rx_desc; 675*4882a593Smuzhiyun 676*4882a593Smuzhiyun u8 num_tc; /* Total number of enabled TCs */ 677*4882a593Smuzhiyun u8 prio_tc[HNAE3_MAX_USER_PRIO]; /* TC indexed by prio */ 678*4882a593Smuzhiyun struct hnae3_tc_info tc_info[HNAE3_MAX_TC]; /* Idx of array is HW TC */ 679*4882a593Smuzhiyun 680*4882a593Smuzhiyun u16 num_tqps; /* total number of TQPs in this handle */ 681*4882a593Smuzhiyun struct hnae3_queue **tqp; /* array base of all TQPs in this instance */ 682*4882a593Smuzhiyun const struct hnae3_dcb_ops *dcb_ops; 683*4882a593Smuzhiyun 684*4882a593Smuzhiyun u16 int_rl_setting; 685*4882a593Smuzhiyun enum pkt_hash_types rss_type; 686*4882a593Smuzhiyun }; 687*4882a593Smuzhiyun 688*4882a593Smuzhiyun struct hnae3_roce_private_info { 689*4882a593Smuzhiyun struct net_device *netdev; 690*4882a593Smuzhiyun void __iomem *roce_io_base; 691*4882a593Smuzhiyun int base_vector; 692*4882a593Smuzhiyun int num_vectors; 693*4882a593Smuzhiyun 694*4882a593Smuzhiyun /* The below attributes defined for RoCE client, hnae3 gives 695*4882a593Smuzhiyun * initial values to them, and RoCE client can modify and use 696*4882a593Smuzhiyun * them. 697*4882a593Smuzhiyun */ 698*4882a593Smuzhiyun unsigned long reset_state; 699*4882a593Smuzhiyun unsigned long instance_state; 700*4882a593Smuzhiyun unsigned long state; 701*4882a593Smuzhiyun }; 702*4882a593Smuzhiyun 703*4882a593Smuzhiyun #define HNAE3_SUPPORT_APP_LOOPBACK BIT(0) 704*4882a593Smuzhiyun #define HNAE3_SUPPORT_PHY_LOOPBACK BIT(1) 705*4882a593Smuzhiyun #define HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK BIT(2) 706*4882a593Smuzhiyun #define HNAE3_SUPPORT_VF BIT(3) 707*4882a593Smuzhiyun #define HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK BIT(4) 708*4882a593Smuzhiyun 709*4882a593Smuzhiyun #define HNAE3_USER_UPE BIT(0) /* unicast promisc enabled by user */ 710*4882a593Smuzhiyun #define HNAE3_USER_MPE BIT(1) /* mulitcast promisc enabled by user */ 711*4882a593Smuzhiyun #define HNAE3_BPE BIT(2) /* broadcast promisc enable */ 712*4882a593Smuzhiyun #define HNAE3_OVERFLOW_UPE BIT(3) /* unicast mac vlan overflow */ 713*4882a593Smuzhiyun #define HNAE3_OVERFLOW_MPE BIT(4) /* multicast mac vlan overflow */ 714*4882a593Smuzhiyun #define HNAE3_VLAN_FLTR BIT(5) /* enable vlan filter */ 715*4882a593Smuzhiyun #define HNAE3_UPE (HNAE3_USER_UPE | HNAE3_OVERFLOW_UPE) 716*4882a593Smuzhiyun #define HNAE3_MPE (HNAE3_USER_MPE | HNAE3_OVERFLOW_MPE) 717*4882a593Smuzhiyun 718*4882a593Smuzhiyun struct hnae3_handle { 719*4882a593Smuzhiyun struct hnae3_client *client; 720*4882a593Smuzhiyun struct pci_dev *pdev; 721*4882a593Smuzhiyun void *priv; 722*4882a593Smuzhiyun struct hnae3_ae_algo *ae_algo; /* the class who provides this handle */ 723*4882a593Smuzhiyun u64 flags; /* Indicate the capabilities for this handle */ 724*4882a593Smuzhiyun 725*4882a593Smuzhiyun union { 726*4882a593Smuzhiyun struct net_device *netdev; /* first member */ 727*4882a593Smuzhiyun struct hnae3_knic_private_info kinfo; 728*4882a593Smuzhiyun struct hnae3_roce_private_info rinfo; 729*4882a593Smuzhiyun }; 730*4882a593Smuzhiyun 731*4882a593Smuzhiyun u32 numa_node_mask; /* for multi-chip support */ 732*4882a593Smuzhiyun 733*4882a593Smuzhiyun enum hnae3_port_base_vlan_state port_base_vlan_state; 734*4882a593Smuzhiyun 735*4882a593Smuzhiyun u8 netdev_flags; 736*4882a593Smuzhiyun struct dentry *hnae3_dbgfs; 737*4882a593Smuzhiyun 738*4882a593Smuzhiyun /* Network interface message level enabled bits */ 739*4882a593Smuzhiyun u32 msg_enable; 740*4882a593Smuzhiyun }; 741*4882a593Smuzhiyun 742*4882a593Smuzhiyun #define hnae3_set_field(origin, mask, shift, val) \ 743*4882a593Smuzhiyun do { \ 744*4882a593Smuzhiyun (origin) &= (~(mask)); \ 745*4882a593Smuzhiyun (origin) |= ((val) << (shift)) & (mask); \ 746*4882a593Smuzhiyun } while (0) 747*4882a593Smuzhiyun #define hnae3_get_field(origin, mask, shift) (((origin) & (mask)) >> (shift)) 748*4882a593Smuzhiyun 749*4882a593Smuzhiyun #define hnae3_set_bit(origin, shift, val) \ 750*4882a593Smuzhiyun hnae3_set_field((origin), (0x1 << (shift)), (shift), (val)) 751*4882a593Smuzhiyun #define hnae3_get_bit(origin, shift) \ 752*4882a593Smuzhiyun hnae3_get_field((origin), (0x1 << (shift)), (shift)) 753*4882a593Smuzhiyun 754*4882a593Smuzhiyun int hnae3_register_ae_dev(struct hnae3_ae_dev *ae_dev); 755*4882a593Smuzhiyun void hnae3_unregister_ae_dev(struct hnae3_ae_dev *ae_dev); 756*4882a593Smuzhiyun 757*4882a593Smuzhiyun void hnae3_unregister_ae_algo_prepare(struct hnae3_ae_algo *ae_algo); 758*4882a593Smuzhiyun void hnae3_unregister_ae_algo(struct hnae3_ae_algo *ae_algo); 759*4882a593Smuzhiyun void hnae3_register_ae_algo(struct hnae3_ae_algo *ae_algo); 760*4882a593Smuzhiyun 761*4882a593Smuzhiyun void hnae3_unregister_client(struct hnae3_client *client); 762*4882a593Smuzhiyun int hnae3_register_client(struct hnae3_client *client); 763*4882a593Smuzhiyun 764*4882a593Smuzhiyun void hnae3_set_client_init_flag(struct hnae3_client *client, 765*4882a593Smuzhiyun struct hnae3_ae_dev *ae_dev, 766*4882a593Smuzhiyun unsigned int inited); 767*4882a593Smuzhiyun #endif 768