1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef FS_ENET_FEC_H 3*4882a593Smuzhiyun #define FS_ENET_FEC_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define FEC_MAX_MULTICAST_ADDRS 64 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* Interrupt events/masks. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #define FEC_ENET_HBERR 0x80000000U /* Heartbeat error */ 10*4882a593Smuzhiyun #define FEC_ENET_BABR 0x40000000U /* Babbling receiver */ 11*4882a593Smuzhiyun #define FEC_ENET_BABT 0x20000000U /* Babbling transmitter */ 12*4882a593Smuzhiyun #define FEC_ENET_GRA 0x10000000U /* Graceful stop complete */ 13*4882a593Smuzhiyun #define FEC_ENET_TXF 0x08000000U /* Full frame transmitted */ 14*4882a593Smuzhiyun #define FEC_ENET_TXB 0x04000000U /* A buffer was transmitted */ 15*4882a593Smuzhiyun #define FEC_ENET_RXF 0x02000000U /* Full frame received */ 16*4882a593Smuzhiyun #define FEC_ENET_RXB 0x01000000U /* A buffer was received */ 17*4882a593Smuzhiyun #define FEC_ENET_MII 0x00800000U /* MII interrupt */ 18*4882a593Smuzhiyun #define FEC_ENET_EBERR 0x00400000U /* SDMA bus error */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define FEC_ECNTRL_PINMUX 0x00000004 21*4882a593Smuzhiyun #define FEC_ECNTRL_ETHER_EN 0x00000002 22*4882a593Smuzhiyun #define FEC_ECNTRL_RESET 0x00000001 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* RMII mode enabled only when MII_MODE bit is set too. */ 25*4882a593Smuzhiyun #define FEC_RCNTRL_RMII_MODE (0x00000100 | \ 26*4882a593Smuzhiyun FEC_RCNTRL_MII_MODE | FEC_RCNTRL_FCE) 27*4882a593Smuzhiyun #define FEC_RCNTRL_FCE 0x00000020 28*4882a593Smuzhiyun #define FEC_RCNTRL_BC_REJ 0x00000010 29*4882a593Smuzhiyun #define FEC_RCNTRL_PROM 0x00000008 30*4882a593Smuzhiyun #define FEC_RCNTRL_MII_MODE 0x00000004 31*4882a593Smuzhiyun #define FEC_RCNTRL_DRT 0x00000002 32*4882a593Smuzhiyun #define FEC_RCNTRL_LOOP 0x00000001 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define FEC_TCNTRL_FDEN 0x00000004 35*4882a593Smuzhiyun #define FEC_TCNTRL_HBC 0x00000002 36*4882a593Smuzhiyun #define FEC_TCNTRL_GTS 0x00000001 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* 39*4882a593Smuzhiyun * Delay to wait for FEC reset command to complete (in us) 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun #define FEC_RESET_DELAY 50 42*4882a593Smuzhiyun #endif 43