xref: /OK3568_Linux_fs/kernel/drivers/net/ethernet/freescale/fman/fman.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright 2008-2015 Freescale Semiconductor Inc.
3*4882a593Smuzhiyun  * Copyright 2020 NXP
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Redistribution and use in source and binary forms, with or without
6*4882a593Smuzhiyun  * modification, are permitted provided that the following conditions are met:
7*4882a593Smuzhiyun  *     * Redistributions of source code must retain the above copyright
8*4882a593Smuzhiyun  *       notice, this list of conditions and the following disclaimer.
9*4882a593Smuzhiyun  *     * Redistributions in binary form must reproduce the above copyright
10*4882a593Smuzhiyun  *       notice, this list of conditions and the following disclaimer in the
11*4882a593Smuzhiyun  *       documentation and/or other materials provided with the distribution.
12*4882a593Smuzhiyun  *     * Neither the name of Freescale Semiconductor nor the
13*4882a593Smuzhiyun  *       names of its contributors may be used to endorse or promote products
14*4882a593Smuzhiyun  *       derived from this software without specific prior written permission.
15*4882a593Smuzhiyun  *
16*4882a593Smuzhiyun  *
17*4882a593Smuzhiyun  * ALTERNATIVELY, this software may be distributed under the terms of the
18*4882a593Smuzhiyun  * GNU General Public License ("GPL") as published by the Free Software
19*4882a593Smuzhiyun  * Foundation, either version 2 of that License or (at your option) any
20*4882a593Smuzhiyun  * later version.
21*4882a593Smuzhiyun  *
22*4882a593Smuzhiyun  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
23*4882a593Smuzhiyun  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24*4882a593Smuzhiyun  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25*4882a593Smuzhiyun  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
26*4882a593Smuzhiyun  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27*4882a593Smuzhiyun  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28*4882a593Smuzhiyun  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
29*4882a593Smuzhiyun  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30*4882a593Smuzhiyun  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
31*4882a593Smuzhiyun  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32*4882a593Smuzhiyun  */
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #ifndef __FM_H
35*4882a593Smuzhiyun #define __FM_H
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #include <linux/io.h>
38*4882a593Smuzhiyun #include <linux/interrupt.h>
39*4882a593Smuzhiyun #include <linux/of_irq.h>
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun /* FM Frame descriptor macros  */
42*4882a593Smuzhiyun /* Frame queue Context Override */
43*4882a593Smuzhiyun #define FM_FD_CMD_FCO                   0x80000000
44*4882a593Smuzhiyun #define FM_FD_CMD_RPD                   0x40000000  /* Read Prepended Data */
45*4882a593Smuzhiyun #define FM_FD_CMD_UPD			0x20000000  /* Update Prepended Data */
46*4882a593Smuzhiyun #define FM_FD_CMD_DTC                   0x10000000  /* Do L4 Checksum */
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun /* TX-Port: Unsupported Format */
49*4882a593Smuzhiyun #define FM_FD_ERR_UNSUPPORTED_FORMAT    0x04000000
50*4882a593Smuzhiyun /* TX Port: Length Error */
51*4882a593Smuzhiyun #define FM_FD_ERR_LENGTH                0x02000000
52*4882a593Smuzhiyun #define FM_FD_ERR_DMA                   0x01000000  /* DMA Data error */
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun /* IPR frame (not error) */
55*4882a593Smuzhiyun #define FM_FD_IPR                       0x00000001
56*4882a593Smuzhiyun /* IPR non-consistent-sp */
57*4882a593Smuzhiyun #define FM_FD_ERR_IPR_NCSP              (0x00100000 | FM_FD_IPR)
58*4882a593Smuzhiyun /* IPR error */
59*4882a593Smuzhiyun #define FM_FD_ERR_IPR                   (0x00200000 | FM_FD_IPR)
60*4882a593Smuzhiyun /* IPR timeout */
61*4882a593Smuzhiyun #define FM_FD_ERR_IPR_TO                (0x00300000 | FM_FD_IPR)
62*4882a593Smuzhiyun /* TX Port: Length Error */
63*4882a593Smuzhiyun #define FM_FD_ERR_IPRE                  (FM_FD_ERR_IPR & ~FM_FD_IPR)
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun /* Rx FIFO overflow, FCS error, code error, running disparity error
66*4882a593Smuzhiyun  * (SGMII and TBI modes), FIFO parity error. PHY Sequence error,
67*4882a593Smuzhiyun  * PHY error control character detected.
68*4882a593Smuzhiyun  */
69*4882a593Smuzhiyun #define FM_FD_ERR_PHYSICAL              0x00080000
70*4882a593Smuzhiyun /* Frame too long OR Frame size exceeds max_length_frame  */
71*4882a593Smuzhiyun #define FM_FD_ERR_SIZE                  0x00040000
72*4882a593Smuzhiyun /* classification discard */
73*4882a593Smuzhiyun #define FM_FD_ERR_CLS_DISCARD           0x00020000
74*4882a593Smuzhiyun /* Extract Out of Frame */
75*4882a593Smuzhiyun #define FM_FD_ERR_EXTRACTION            0x00008000
76*4882a593Smuzhiyun /* No Scheme Selected */
77*4882a593Smuzhiyun #define FM_FD_ERR_NO_SCHEME             0x00004000
78*4882a593Smuzhiyun /* Keysize Overflow */
79*4882a593Smuzhiyun #define FM_FD_ERR_KEYSIZE_OVERFLOW      0x00002000
80*4882a593Smuzhiyun /* Frame color is red */
81*4882a593Smuzhiyun #define FM_FD_ERR_COLOR_RED             0x00000800
82*4882a593Smuzhiyun /* Frame color is yellow */
83*4882a593Smuzhiyun #define FM_FD_ERR_COLOR_YELLOW          0x00000400
84*4882a593Smuzhiyun /* Parser Time out Exceed */
85*4882a593Smuzhiyun #define FM_FD_ERR_PRS_TIMEOUT           0x00000080
86*4882a593Smuzhiyun /* Invalid Soft Parser instruction */
87*4882a593Smuzhiyun #define FM_FD_ERR_PRS_ILL_INSTRUCT      0x00000040
88*4882a593Smuzhiyun /* Header error was identified during parsing */
89*4882a593Smuzhiyun #define FM_FD_ERR_PRS_HDR_ERR           0x00000020
90*4882a593Smuzhiyun /* Frame parsed beyind 256 first bytes */
91*4882a593Smuzhiyun #define FM_FD_ERR_BLOCK_LIMIT_EXCEEDED  0x00000008
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun /* non Frame-Manager error */
94*4882a593Smuzhiyun #define FM_FD_RX_STATUS_ERR_NON_FM      0x00400000
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun /* FMan driver defines */
97*4882a593Smuzhiyun #define FMAN_BMI_FIFO_UNITS		0x100
98*4882a593Smuzhiyun #define OFFSET_UNITS			16
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun /* BMan defines */
101*4882a593Smuzhiyun #define BM_MAX_NUM_OF_POOLS		64 /* Buffers pools */
102*4882a593Smuzhiyun #define FMAN_PORT_MAX_EXT_POOLS_NUM	8  /* External BM pools per Rx port */
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun struct fman; /* FMan data */
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun /* Enum for defining port types */
107*4882a593Smuzhiyun enum fman_port_type {
108*4882a593Smuzhiyun 	FMAN_PORT_TYPE_TX = 0,	/* TX Port */
109*4882a593Smuzhiyun 	FMAN_PORT_TYPE_RX,	/* RX Port */
110*4882a593Smuzhiyun };
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun struct fman_rev_info {
113*4882a593Smuzhiyun 	u8 major;			/* Major revision */
114*4882a593Smuzhiyun 	u8 minor;			/* Minor revision */
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun enum fman_exceptions {
118*4882a593Smuzhiyun 	FMAN_EX_DMA_BUS_ERROR = 0,	/* DMA bus error. */
119*4882a593Smuzhiyun 	FMAN_EX_DMA_READ_ECC,		/* Read Buffer ECC error */
120*4882a593Smuzhiyun 	FMAN_EX_DMA_SYSTEM_WRITE_ECC,	/* Write Buffer ECC err on sys side */
121*4882a593Smuzhiyun 	FMAN_EX_DMA_FM_WRITE_ECC,	/* Write Buffer ECC error on FM side */
122*4882a593Smuzhiyun 	FMAN_EX_DMA_SINGLE_PORT_ECC,	/* Single Port ECC error on FM side */
123*4882a593Smuzhiyun 	FMAN_EX_FPM_STALL_ON_TASKS,	/* Stall of tasks on FPM */
124*4882a593Smuzhiyun 	FMAN_EX_FPM_SINGLE_ECC,		/* Single ECC on FPM. */
125*4882a593Smuzhiyun 	FMAN_EX_FPM_DOUBLE_ECC,		/* Double ECC error on FPM ram access */
126*4882a593Smuzhiyun 	FMAN_EX_QMI_SINGLE_ECC,	/* Single ECC on QMI. */
127*4882a593Smuzhiyun 	FMAN_EX_QMI_DOUBLE_ECC,	/* Double bit ECC occurred on QMI */
128*4882a593Smuzhiyun 	FMAN_EX_QMI_DEQ_FROM_UNKNOWN_PORTID,/* DeQ from unknown port id */
129*4882a593Smuzhiyun 	FMAN_EX_BMI_LIST_RAM_ECC,	/* Linked List RAM ECC error */
130*4882a593Smuzhiyun 	FMAN_EX_BMI_STORAGE_PROFILE_ECC,/* storage profile */
131*4882a593Smuzhiyun 	FMAN_EX_BMI_STATISTICS_RAM_ECC,/* Statistics RAM ECC Err Enable */
132*4882a593Smuzhiyun 	FMAN_EX_BMI_DISPATCH_RAM_ECC,	/* Dispatch RAM ECC Error Enable */
133*4882a593Smuzhiyun 	FMAN_EX_IRAM_ECC,		/* Double bit ECC occurred on IRAM */
134*4882a593Smuzhiyun 	FMAN_EX_MURAM_ECC		/* Double bit ECC occurred on MURAM */
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun /* Parse results memory layout */
138*4882a593Smuzhiyun struct fman_prs_result {
139*4882a593Smuzhiyun 	u8 lpid;		/* Logical port id */
140*4882a593Smuzhiyun 	u8 shimr;		/* Shim header result  */
141*4882a593Smuzhiyun 	__be16 l2r;		/* Layer 2 result */
142*4882a593Smuzhiyun 	__be16 l3r;		/* Layer 3 result */
143*4882a593Smuzhiyun 	u8 l4r;		/* Layer 4 result */
144*4882a593Smuzhiyun 	u8 cplan;		/* Classification plan id */
145*4882a593Smuzhiyun 	__be16 nxthdr;		/* Next Header  */
146*4882a593Smuzhiyun 	__be16 cksum;		/* Running-sum */
147*4882a593Smuzhiyun 	/* Flags&fragment-offset field of the last IP-header */
148*4882a593Smuzhiyun 	__be16 flags_frag_off;
149*4882a593Smuzhiyun 	/* Routing type field of a IPV6 routing extension header */
150*4882a593Smuzhiyun 	u8 route_type;
151*4882a593Smuzhiyun 	/* Routing Extension Header Present; last bit is IP valid */
152*4882a593Smuzhiyun 	u8 rhp_ip_valid;
153*4882a593Smuzhiyun 	u8 shim_off[2];		/* Shim offset */
154*4882a593Smuzhiyun 	u8 ip_pid_off;		/* IP PID (last IP-proto) offset */
155*4882a593Smuzhiyun 	u8 eth_off;		/* ETH offset */
156*4882a593Smuzhiyun 	u8 llc_snap_off;	/* LLC_SNAP offset */
157*4882a593Smuzhiyun 	u8 vlan_off[2];		/* VLAN offset */
158*4882a593Smuzhiyun 	u8 etype_off;		/* ETYPE offset */
159*4882a593Smuzhiyun 	u8 pppoe_off;		/* PPP offset */
160*4882a593Smuzhiyun 	u8 mpls_off[2];		/* MPLS offset */
161*4882a593Smuzhiyun 	u8 ip_off[2];		/* IP offset */
162*4882a593Smuzhiyun 	u8 gre_off;		/* GRE offset */
163*4882a593Smuzhiyun 	u8 l4_off;		/* Layer 4 offset */
164*4882a593Smuzhiyun 	u8 nxthdr_off;		/* Parser end point */
165*4882a593Smuzhiyun };
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun /* A structure for defining buffer prefix area content. */
168*4882a593Smuzhiyun struct fman_buffer_prefix_content {
169*4882a593Smuzhiyun 	/* Number of bytes to be left at the beginning of the external
170*4882a593Smuzhiyun 	 * buffer; Note that the private-area will start from the base
171*4882a593Smuzhiyun 	 * of the buffer address.
172*4882a593Smuzhiyun 	 */
173*4882a593Smuzhiyun 	u16 priv_data_size;
174*4882a593Smuzhiyun 	/* true to pass the parse result to/from the FM;
175*4882a593Smuzhiyun 	 * User may use FM_PORT_GetBufferPrsResult() in
176*4882a593Smuzhiyun 	 * order to get the parser-result from a buffer.
177*4882a593Smuzhiyun 	 */
178*4882a593Smuzhiyun 	bool pass_prs_result;
179*4882a593Smuzhiyun 	/* true to pass the timeStamp to/from the FM User */
180*4882a593Smuzhiyun 	bool pass_time_stamp;
181*4882a593Smuzhiyun 	/* true to pass the KG hash result to/from the FM User may
182*4882a593Smuzhiyun 	 * use FM_PORT_GetBufferHashResult() in order to get the
183*4882a593Smuzhiyun 	 * parser-result from a buffer.
184*4882a593Smuzhiyun 	 */
185*4882a593Smuzhiyun 	bool pass_hash_result;
186*4882a593Smuzhiyun 	/* Add all other Internal-Context information: AD,
187*4882a593Smuzhiyun 	 * hash-result, key, etc.
188*4882a593Smuzhiyun 	 */
189*4882a593Smuzhiyun 	u16 data_align;
190*4882a593Smuzhiyun };
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun /* A structure of information about each of the external
193*4882a593Smuzhiyun  * buffer pools used by a port or storage-profile.
194*4882a593Smuzhiyun  */
195*4882a593Smuzhiyun struct fman_ext_pool_params {
196*4882a593Smuzhiyun 	u8 id;		    /* External buffer pool id */
197*4882a593Smuzhiyun 	u16 size;		    /* External buffer pool buffer size */
198*4882a593Smuzhiyun };
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun /* A structure for informing the driver about the external
201*4882a593Smuzhiyun  * buffer pools allocated in the BM and used by a port or a
202*4882a593Smuzhiyun  * storage-profile.
203*4882a593Smuzhiyun  */
204*4882a593Smuzhiyun struct fman_ext_pools {
205*4882a593Smuzhiyun 	u8 num_of_pools_used; /* Number of pools use by this port */
206*4882a593Smuzhiyun 	struct fman_ext_pool_params ext_buf_pool[FMAN_PORT_MAX_EXT_POOLS_NUM];
207*4882a593Smuzhiyun 					/* Parameters for each port */
208*4882a593Smuzhiyun };
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun /* A structure for defining BM pool depletion criteria */
211*4882a593Smuzhiyun struct fman_buf_pool_depletion {
212*4882a593Smuzhiyun 	/* select mode in which pause frames will be sent after a
213*4882a593Smuzhiyun 	 * number of pools (all together!) are depleted
214*4882a593Smuzhiyun 	 */
215*4882a593Smuzhiyun 	bool pools_grp_mode_enable;
216*4882a593Smuzhiyun 	/* the number of depleted pools that will invoke pause
217*4882a593Smuzhiyun 	 * frames transmission.
218*4882a593Smuzhiyun 	 */
219*4882a593Smuzhiyun 	u8 num_of_pools;
220*4882a593Smuzhiyun 	/* For each pool, true if it should be considered for
221*4882a593Smuzhiyun 	 * depletion (Note - this pool must be used by this port!).
222*4882a593Smuzhiyun 	 */
223*4882a593Smuzhiyun 	bool pools_to_consider[BM_MAX_NUM_OF_POOLS];
224*4882a593Smuzhiyun 	/* select mode in which pause frames will be sent
225*4882a593Smuzhiyun 	 * after a single-pool is depleted;
226*4882a593Smuzhiyun 	 */
227*4882a593Smuzhiyun 	bool single_pool_mode_enable;
228*4882a593Smuzhiyun 	/* For each pool, true if it should be considered
229*4882a593Smuzhiyun 	 * for depletion (Note - this pool must be used by this port!)
230*4882a593Smuzhiyun 	 */
231*4882a593Smuzhiyun 	bool pools_to_consider_for_single_mode[BM_MAX_NUM_OF_POOLS];
232*4882a593Smuzhiyun };
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun /* Enum for inter-module interrupts registration */
235*4882a593Smuzhiyun enum fman_event_modules {
236*4882a593Smuzhiyun 	FMAN_MOD_MAC = 0,		/* MAC event */
237*4882a593Smuzhiyun 	FMAN_MOD_FMAN_CTRL,	/* FMAN Controller */
238*4882a593Smuzhiyun 	FMAN_MOD_DUMMY_LAST
239*4882a593Smuzhiyun };
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun /* Enum for interrupts types */
242*4882a593Smuzhiyun enum fman_intr_type {
243*4882a593Smuzhiyun 	FMAN_INTR_TYPE_ERR,
244*4882a593Smuzhiyun 	FMAN_INTR_TYPE_NORMAL
245*4882a593Smuzhiyun };
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun /* Enum for inter-module interrupts registration */
248*4882a593Smuzhiyun enum fman_inter_module_event {
249*4882a593Smuzhiyun 	FMAN_EV_ERR_MAC0 = 0,	/* MAC 0 error event */
250*4882a593Smuzhiyun 	FMAN_EV_ERR_MAC1,		/* MAC 1 error event */
251*4882a593Smuzhiyun 	FMAN_EV_ERR_MAC2,		/* MAC 2 error event */
252*4882a593Smuzhiyun 	FMAN_EV_ERR_MAC3,		/* MAC 3 error event */
253*4882a593Smuzhiyun 	FMAN_EV_ERR_MAC4,		/* MAC 4 error event */
254*4882a593Smuzhiyun 	FMAN_EV_ERR_MAC5,		/* MAC 5 error event */
255*4882a593Smuzhiyun 	FMAN_EV_ERR_MAC6,		/* MAC 6 error event */
256*4882a593Smuzhiyun 	FMAN_EV_ERR_MAC7,		/* MAC 7 error event */
257*4882a593Smuzhiyun 	FMAN_EV_ERR_MAC8,		/* MAC 8 error event */
258*4882a593Smuzhiyun 	FMAN_EV_ERR_MAC9,		/* MAC 9 error event */
259*4882a593Smuzhiyun 	FMAN_EV_MAC0,		/* MAC 0 event (Magic packet detection) */
260*4882a593Smuzhiyun 	FMAN_EV_MAC1,		/* MAC 1 event (Magic packet detection) */
261*4882a593Smuzhiyun 	FMAN_EV_MAC2,		/* MAC 2 (Magic packet detection) */
262*4882a593Smuzhiyun 	FMAN_EV_MAC3,		/* MAC 3 (Magic packet detection) */
263*4882a593Smuzhiyun 	FMAN_EV_MAC4,		/* MAC 4 (Magic packet detection) */
264*4882a593Smuzhiyun 	FMAN_EV_MAC5,		/* MAC 5 (Magic packet detection) */
265*4882a593Smuzhiyun 	FMAN_EV_MAC6,		/* MAC 6 (Magic packet detection) */
266*4882a593Smuzhiyun 	FMAN_EV_MAC7,		/* MAC 7 (Magic packet detection) */
267*4882a593Smuzhiyun 	FMAN_EV_MAC8,		/* MAC 8 event (Magic packet detection) */
268*4882a593Smuzhiyun 	FMAN_EV_MAC9,		/* MAC 9 event (Magic packet detection) */
269*4882a593Smuzhiyun 	FMAN_EV_FMAN_CTRL_0,	/* Fman controller event 0 */
270*4882a593Smuzhiyun 	FMAN_EV_FMAN_CTRL_1,	/* Fman controller event 1 */
271*4882a593Smuzhiyun 	FMAN_EV_FMAN_CTRL_2,	/* Fman controller event 2 */
272*4882a593Smuzhiyun 	FMAN_EV_FMAN_CTRL_3,	/* Fman controller event 3 */
273*4882a593Smuzhiyun 	FMAN_EV_CNT
274*4882a593Smuzhiyun };
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun struct fman_intr_src {
277*4882a593Smuzhiyun 	void (*isr_cb)(void *src_arg);
278*4882a593Smuzhiyun 	void *src_handle;
279*4882a593Smuzhiyun };
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun /** fman_exceptions_cb
282*4882a593Smuzhiyun  * fman         - Pointer to FMan
283*4882a593Smuzhiyun  * exception    - The exception.
284*4882a593Smuzhiyun  *
285*4882a593Smuzhiyun  * Exceptions user callback routine, will be called upon an exception
286*4882a593Smuzhiyun  * passing the exception identification.
287*4882a593Smuzhiyun  *
288*4882a593Smuzhiyun  * Return: irq status
289*4882a593Smuzhiyun  */
290*4882a593Smuzhiyun typedef irqreturn_t (fman_exceptions_cb)(struct fman *fman,
291*4882a593Smuzhiyun 					 enum fman_exceptions exception);
292*4882a593Smuzhiyun /** fman_bus_error_cb
293*4882a593Smuzhiyun  * fman         - Pointer to FMan
294*4882a593Smuzhiyun  * port_id      - Port id
295*4882a593Smuzhiyun  * addr         - Address that caused the error
296*4882a593Smuzhiyun  * tnum         - Owner of error
297*4882a593Smuzhiyun  * liodn        - Logical IO device number
298*4882a593Smuzhiyun  *
299*4882a593Smuzhiyun  * Bus error user callback routine, will be called upon bus error,
300*4882a593Smuzhiyun  * passing parameters describing the errors and the owner.
301*4882a593Smuzhiyun  *
302*4882a593Smuzhiyun  * Return: IRQ status
303*4882a593Smuzhiyun  */
304*4882a593Smuzhiyun typedef irqreturn_t (fman_bus_error_cb)(struct fman *fman, u8 port_id,
305*4882a593Smuzhiyun 					u64 addr, u8 tnum, u16 liodn);
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun /* Structure that holds information received from device tree */
308*4882a593Smuzhiyun struct fman_dts_params {
309*4882a593Smuzhiyun 	void __iomem *base_addr;                /* FMan virtual address */
310*4882a593Smuzhiyun 	struct resource *res;                   /* FMan memory resource */
311*4882a593Smuzhiyun 	u8 id;                                  /* FMan ID */
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 	int err_irq;                            /* FMan Error IRQ */
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 	u16 clk_freq;                           /* FMan clock freq (In Mhz) */
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun 	u32 qman_channel_base;                  /* QMan channels base */
318*4882a593Smuzhiyun 	u32 num_of_qman_channels;               /* Number of QMan channels */
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun 	struct resource muram_res;              /* MURAM resource */
321*4882a593Smuzhiyun };
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun struct fman {
324*4882a593Smuzhiyun 	struct device *dev;
325*4882a593Smuzhiyun 	void __iomem *base_addr;
326*4882a593Smuzhiyun 	struct fman_intr_src intr_mng[FMAN_EV_CNT];
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun 	struct fman_fpm_regs __iomem *fpm_regs;
329*4882a593Smuzhiyun 	struct fman_bmi_regs __iomem *bmi_regs;
330*4882a593Smuzhiyun 	struct fman_qmi_regs __iomem *qmi_regs;
331*4882a593Smuzhiyun 	struct fman_dma_regs __iomem *dma_regs;
332*4882a593Smuzhiyun 	struct fman_hwp_regs __iomem *hwp_regs;
333*4882a593Smuzhiyun 	struct fman_kg_regs __iomem *kg_regs;
334*4882a593Smuzhiyun 	fman_exceptions_cb *exception_cb;
335*4882a593Smuzhiyun 	fman_bus_error_cb *bus_error_cb;
336*4882a593Smuzhiyun 	/* Spinlock for FMan use */
337*4882a593Smuzhiyun 	spinlock_t spinlock;
338*4882a593Smuzhiyun 	struct fman_state_struct *state;
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	struct fman_cfg *cfg;
341*4882a593Smuzhiyun 	struct muram_info *muram;
342*4882a593Smuzhiyun 	struct fman_keygen *keygen;
343*4882a593Smuzhiyun 	/* cam section in muram */
344*4882a593Smuzhiyun 	unsigned long cam_offset;
345*4882a593Smuzhiyun 	size_t cam_size;
346*4882a593Smuzhiyun 	/* Fifo in MURAM */
347*4882a593Smuzhiyun 	unsigned long fifo_offset;
348*4882a593Smuzhiyun 	size_t fifo_size;
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun 	u32 liodn_base[64];
351*4882a593Smuzhiyun 	u32 liodn_offset[64];
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun 	struct fman_dts_params dts_params;
354*4882a593Smuzhiyun };
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun /* Structure for port-FM communication during fman_port_init. */
357*4882a593Smuzhiyun struct fman_port_init_params {
358*4882a593Smuzhiyun 	u8 port_id;			/* port Id */
359*4882a593Smuzhiyun 	enum fman_port_type port_type;	/* Port type */
360*4882a593Smuzhiyun 	u16 port_speed;			/* Port speed */
361*4882a593Smuzhiyun 	u16 liodn_offset;		/* Port's requested resource */
362*4882a593Smuzhiyun 	u8 num_of_tasks;		/* Port's requested resource */
363*4882a593Smuzhiyun 	u8 num_of_extra_tasks;		/* Port's requested resource */
364*4882a593Smuzhiyun 	u8 num_of_open_dmas;		/* Port's requested resource */
365*4882a593Smuzhiyun 	u8 num_of_extra_open_dmas;	/* Port's requested resource */
366*4882a593Smuzhiyun 	u32 size_of_fifo;		/* Port's requested resource */
367*4882a593Smuzhiyun 	u32 extra_size_of_fifo;		/* Port's requested resource */
368*4882a593Smuzhiyun 	u8 deq_pipeline_depth;		/* Port's requested resource */
369*4882a593Smuzhiyun 	u16 max_frame_length;		/* Port's max frame length. */
370*4882a593Smuzhiyun 	u16 liodn_base;
371*4882a593Smuzhiyun 	/* LIODN base for this port, to be used together with LIODN offset. */
372*4882a593Smuzhiyun };
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun void fman_get_revision(struct fman *fman, struct fman_rev_info *rev_info);
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun void fman_register_intr(struct fman *fman, enum fman_event_modules mod,
377*4882a593Smuzhiyun 			u8 mod_id, enum fman_intr_type intr_type,
378*4882a593Smuzhiyun 			void (*f_isr)(void *h_src_arg), void *h_src_arg);
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun void fman_unregister_intr(struct fman *fman, enum fman_event_modules mod,
381*4882a593Smuzhiyun 			  u8 mod_id, enum fman_intr_type intr_type);
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun int fman_set_port_params(struct fman *fman,
384*4882a593Smuzhiyun 			 struct fman_port_init_params *port_params);
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun int fman_reset_mac(struct fman *fman, u8 mac_id);
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun u16 fman_get_clock_freq(struct fman *fman);
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun u32 fman_get_bmi_max_fifo_size(struct fman *fman);
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun int fman_set_mac_max_frame(struct fman *fman, u8 mac_id, u16 mfl);
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun u32 fman_get_qman_channel_id(struct fman *fman, u32 port_id);
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun struct resource *fman_get_mem_region(struct fman *fman);
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun u16 fman_get_max_frm(void);
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun int fman_get_rx_extra_headroom(void);
401*4882a593Smuzhiyun 
402*4882a593Smuzhiyun #ifdef CONFIG_DPAA_ERRATUM_A050385
403*4882a593Smuzhiyun bool fman_has_errata_a050385(void);
404*4882a593Smuzhiyun #endif
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun struct fman *fman_bind(struct device *dev);
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun #endif /* __FM_H */
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