1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2013-2016 Freescale Semiconductor Inc. 4*4882a593Smuzhiyun * Copyright 2016-2018 NXP 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _FSL_DPRTC_CMD_H 8*4882a593Smuzhiyun #define _FSL_DPRTC_CMD_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* Command versioning */ 11*4882a593Smuzhiyun #define DPRTC_CMD_BASE_VERSION 1 12*4882a593Smuzhiyun #define DPRTC_CMD_VERSION_2 2 13*4882a593Smuzhiyun #define DPRTC_CMD_ID_OFFSET 4 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define DPRTC_CMD(id) (((id) << DPRTC_CMD_ID_OFFSET) | DPRTC_CMD_BASE_VERSION) 16*4882a593Smuzhiyun #define DPRTC_CMD_V2(id) (((id) << DPRTC_CMD_ID_OFFSET) | DPRTC_CMD_VERSION_2) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Command IDs */ 19*4882a593Smuzhiyun #define DPRTC_CMDID_CLOSE DPRTC_CMD(0x800) 20*4882a593Smuzhiyun #define DPRTC_CMDID_OPEN DPRTC_CMD(0x810) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define DPRTC_CMDID_SET_IRQ_ENABLE DPRTC_CMD(0x012) 23*4882a593Smuzhiyun #define DPRTC_CMDID_GET_IRQ_ENABLE DPRTC_CMD(0x013) 24*4882a593Smuzhiyun #define DPRTC_CMDID_SET_IRQ_MASK DPRTC_CMD_V2(0x014) 25*4882a593Smuzhiyun #define DPRTC_CMDID_GET_IRQ_MASK DPRTC_CMD(0x015) 26*4882a593Smuzhiyun #define DPRTC_CMDID_GET_IRQ_STATUS DPRTC_CMD(0x016) 27*4882a593Smuzhiyun #define DPRTC_CMDID_CLEAR_IRQ_STATUS DPRTC_CMD(0x017) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #pragma pack(push, 1) 30*4882a593Smuzhiyun struct dprtc_cmd_open { 31*4882a593Smuzhiyun __le32 dprtc_id; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun struct dprtc_cmd_get_irq { 35*4882a593Smuzhiyun __le32 pad; 36*4882a593Smuzhiyun u8 irq_index; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun struct dprtc_cmd_set_irq_enable { 40*4882a593Smuzhiyun u8 en; 41*4882a593Smuzhiyun u8 pad[3]; 42*4882a593Smuzhiyun u8 irq_index; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun struct dprtc_rsp_get_irq_enable { 46*4882a593Smuzhiyun u8 en; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun struct dprtc_cmd_set_irq_mask { 50*4882a593Smuzhiyun __le32 mask; 51*4882a593Smuzhiyun u8 irq_index; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun struct dprtc_rsp_get_irq_mask { 55*4882a593Smuzhiyun __le32 mask; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun struct dprtc_cmd_get_irq_status { 59*4882a593Smuzhiyun __le32 status; 60*4882a593Smuzhiyun u8 irq_index; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun struct dprtc_rsp_get_irq_status { 64*4882a593Smuzhiyun __le32 status; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun struct dprtc_cmd_clear_irq_status { 68*4882a593Smuzhiyun __le32 status; 69*4882a593Smuzhiyun u8 irq_index; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #pragma pack(pop) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #endif /* _FSL_DPRTC_CMD_H */ 75