1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2*4882a593Smuzhiyun /* Copyright 2013-2016 Freescale Semiconductor Inc. 3*4882a593Smuzhiyun * Copyright 2019 NXP 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef _FSL_DPMAC_CMD_H 6*4882a593Smuzhiyun #define _FSL_DPMAC_CMD_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* DPMAC Version */ 9*4882a593Smuzhiyun #define DPMAC_VER_MAJOR 4 10*4882a593Smuzhiyun #define DPMAC_VER_MINOR 4 11*4882a593Smuzhiyun #define DPMAC_CMD_BASE_VERSION 1 12*4882a593Smuzhiyun #define DPMAC_CMD_2ND_VERSION 2 13*4882a593Smuzhiyun #define DPMAC_CMD_ID_OFFSET 4 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define DPMAC_CMD(id) (((id) << DPMAC_CMD_ID_OFFSET) | DPMAC_CMD_BASE_VERSION) 16*4882a593Smuzhiyun #define DPMAC_CMD_V2(id) (((id) << DPMAC_CMD_ID_OFFSET) | DPMAC_CMD_2ND_VERSION) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Command IDs */ 19*4882a593Smuzhiyun #define DPMAC_CMDID_CLOSE DPMAC_CMD(0x800) 20*4882a593Smuzhiyun #define DPMAC_CMDID_OPEN DPMAC_CMD(0x80c) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define DPMAC_CMDID_GET_ATTR DPMAC_CMD(0x004) 23*4882a593Smuzhiyun #define DPMAC_CMDID_SET_LINK_STATE DPMAC_CMD_V2(0x0c3) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define DPMAC_CMDID_GET_COUNTER DPMAC_CMD(0x0c4) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Macros for accessing command fields smaller than 1byte */ 28*4882a593Smuzhiyun #define DPMAC_MASK(field) \ 29*4882a593Smuzhiyun GENMASK(DPMAC_##field##_SHIFT + DPMAC_##field##_SIZE - 1, \ 30*4882a593Smuzhiyun DPMAC_##field##_SHIFT) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define dpmac_set_field(var, field, val) \ 33*4882a593Smuzhiyun ((var) |= (((val) << DPMAC_##field##_SHIFT) & DPMAC_MASK(field))) 34*4882a593Smuzhiyun #define dpmac_get_field(var, field) \ 35*4882a593Smuzhiyun (((var) & DPMAC_MASK(field)) >> DPMAC_##field##_SHIFT) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun struct dpmac_cmd_open { 38*4882a593Smuzhiyun __le32 dpmac_id; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun struct dpmac_rsp_get_attributes { 42*4882a593Smuzhiyun u8 eth_if; 43*4882a593Smuzhiyun u8 link_type; 44*4882a593Smuzhiyun __le16 id; 45*4882a593Smuzhiyun __le32 max_rate; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define DPMAC_STATE_SIZE 1 49*4882a593Smuzhiyun #define DPMAC_STATE_SHIFT 0 50*4882a593Smuzhiyun #define DPMAC_STATE_VALID_SIZE 1 51*4882a593Smuzhiyun #define DPMAC_STATE_VALID_SHIFT 1 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun struct dpmac_cmd_set_link_state { 54*4882a593Smuzhiyun __le64 options; 55*4882a593Smuzhiyun __le32 rate; 56*4882a593Smuzhiyun __le32 pad0; 57*4882a593Smuzhiyun /* from lsb: up:1, state_valid:1 */ 58*4882a593Smuzhiyun u8 state; 59*4882a593Smuzhiyun u8 pad1[7]; 60*4882a593Smuzhiyun __le64 supported; 61*4882a593Smuzhiyun __le64 advertising; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun struct dpmac_cmd_get_counter { 65*4882a593Smuzhiyun u8 id; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun struct dpmac_rsp_get_counter { 69*4882a593Smuzhiyun __le64 pad; 70*4882a593Smuzhiyun __le64 counter; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #endif /* _FSL_DPMAC_CMD_H */ 74