xref: /OK3568_Linux_fs/kernel/drivers/net/ethernet/faraday/ftmac100.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Faraday FTMAC100 10/100 Ethernet
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * (C) Copyright 2009-2011 Faraday Technology
6*4882a593Smuzhiyun  * Po-Yu Chuang <ratbert@faraday-tech.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <linux/dma-mapping.h>
12*4882a593Smuzhiyun #include <linux/etherdevice.h>
13*4882a593Smuzhiyun #include <linux/ethtool.h>
14*4882a593Smuzhiyun #include <linux/init.h>
15*4882a593Smuzhiyun #include <linux/interrupt.h>
16*4882a593Smuzhiyun #include <linux/io.h>
17*4882a593Smuzhiyun #include <linux/mii.h>
18*4882a593Smuzhiyun #include <linux/module.h>
19*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
20*4882a593Smuzhiyun #include <linux/netdevice.h>
21*4882a593Smuzhiyun #include <linux/platform_device.h>
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #include "ftmac100.h"
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #define DRV_NAME	"ftmac100"
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define RX_QUEUE_ENTRIES	128	/* must be power of 2 */
28*4882a593Smuzhiyun #define TX_QUEUE_ENTRIES	16	/* must be power of 2 */
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define MAX_PKT_SIZE		1518
31*4882a593Smuzhiyun #define RX_BUF_SIZE		2044	/* must be smaller than 0x7ff */
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #if MAX_PKT_SIZE > 0x7ff
34*4882a593Smuzhiyun #error invalid MAX_PKT_SIZE
35*4882a593Smuzhiyun #endif
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #if RX_BUF_SIZE > 0x7ff || RX_BUF_SIZE > PAGE_SIZE
38*4882a593Smuzhiyun #error invalid RX_BUF_SIZE
39*4882a593Smuzhiyun #endif
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun /******************************************************************************
42*4882a593Smuzhiyun  * private data
43*4882a593Smuzhiyun  *****************************************************************************/
44*4882a593Smuzhiyun struct ftmac100_descs {
45*4882a593Smuzhiyun 	struct ftmac100_rxdes rxdes[RX_QUEUE_ENTRIES];
46*4882a593Smuzhiyun 	struct ftmac100_txdes txdes[TX_QUEUE_ENTRIES];
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun struct ftmac100 {
50*4882a593Smuzhiyun 	struct resource *res;
51*4882a593Smuzhiyun 	void __iomem *base;
52*4882a593Smuzhiyun 	int irq;
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 	struct ftmac100_descs *descs;
55*4882a593Smuzhiyun 	dma_addr_t descs_dma_addr;
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	unsigned int rx_pointer;
58*4882a593Smuzhiyun 	unsigned int tx_clean_pointer;
59*4882a593Smuzhiyun 	unsigned int tx_pointer;
60*4882a593Smuzhiyun 	unsigned int tx_pending;
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	spinlock_t tx_lock;
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 	struct net_device *netdev;
65*4882a593Smuzhiyun 	struct device *dev;
66*4882a593Smuzhiyun 	struct napi_struct napi;
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun 	struct mii_if_info mii;
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun static int ftmac100_alloc_rx_page(struct ftmac100 *priv,
72*4882a593Smuzhiyun 				  struct ftmac100_rxdes *rxdes, gfp_t gfp);
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun /******************************************************************************
75*4882a593Smuzhiyun  * internal functions (hardware register access)
76*4882a593Smuzhiyun  *****************************************************************************/
77*4882a593Smuzhiyun #define INT_MASK_ALL_ENABLED	(FTMAC100_INT_RPKT_FINISH	| \
78*4882a593Smuzhiyun 				 FTMAC100_INT_NORXBUF		| \
79*4882a593Smuzhiyun 				 FTMAC100_INT_XPKT_OK		| \
80*4882a593Smuzhiyun 				 FTMAC100_INT_XPKT_LOST		| \
81*4882a593Smuzhiyun 				 FTMAC100_INT_RPKT_LOST		| \
82*4882a593Smuzhiyun 				 FTMAC100_INT_AHB_ERR		| \
83*4882a593Smuzhiyun 				 FTMAC100_INT_PHYSTS_CHG)
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun #define INT_MASK_ALL_DISABLED	0
86*4882a593Smuzhiyun 
ftmac100_enable_all_int(struct ftmac100 * priv)87*4882a593Smuzhiyun static void ftmac100_enable_all_int(struct ftmac100 *priv)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun 	iowrite32(INT_MASK_ALL_ENABLED, priv->base + FTMAC100_OFFSET_IMR);
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun 
ftmac100_disable_all_int(struct ftmac100 * priv)92*4882a593Smuzhiyun static void ftmac100_disable_all_int(struct ftmac100 *priv)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun 	iowrite32(INT_MASK_ALL_DISABLED, priv->base + FTMAC100_OFFSET_IMR);
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun 
ftmac100_set_rx_ring_base(struct ftmac100 * priv,dma_addr_t addr)97*4882a593Smuzhiyun static void ftmac100_set_rx_ring_base(struct ftmac100 *priv, dma_addr_t addr)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun 	iowrite32(addr, priv->base + FTMAC100_OFFSET_RXR_BADR);
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun 
ftmac100_set_tx_ring_base(struct ftmac100 * priv,dma_addr_t addr)102*4882a593Smuzhiyun static void ftmac100_set_tx_ring_base(struct ftmac100 *priv, dma_addr_t addr)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun 	iowrite32(addr, priv->base + FTMAC100_OFFSET_TXR_BADR);
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun 
ftmac100_txdma_start_polling(struct ftmac100 * priv)107*4882a593Smuzhiyun static void ftmac100_txdma_start_polling(struct ftmac100 *priv)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun 	iowrite32(1, priv->base + FTMAC100_OFFSET_TXPD);
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun 
ftmac100_reset(struct ftmac100 * priv)112*4882a593Smuzhiyun static int ftmac100_reset(struct ftmac100 *priv)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun 	struct net_device *netdev = priv->netdev;
115*4882a593Smuzhiyun 	int i;
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	/* NOTE: reset clears all registers */
118*4882a593Smuzhiyun 	iowrite32(FTMAC100_MACCR_SW_RST, priv->base + FTMAC100_OFFSET_MACCR);
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	for (i = 0; i < 5; i++) {
121*4882a593Smuzhiyun 		unsigned int maccr;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 		maccr = ioread32(priv->base + FTMAC100_OFFSET_MACCR);
124*4882a593Smuzhiyun 		if (!(maccr & FTMAC100_MACCR_SW_RST)) {
125*4882a593Smuzhiyun 			/*
126*4882a593Smuzhiyun 			 * FTMAC100_MACCR_SW_RST cleared does not indicate
127*4882a593Smuzhiyun 			 * that hardware reset completed (what the f*ck).
128*4882a593Smuzhiyun 			 * We still need to wait for a while.
129*4882a593Smuzhiyun 			 */
130*4882a593Smuzhiyun 			udelay(500);
131*4882a593Smuzhiyun 			return 0;
132*4882a593Smuzhiyun 		}
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 		udelay(1000);
135*4882a593Smuzhiyun 	}
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	netdev_err(netdev, "software reset failed\n");
138*4882a593Smuzhiyun 	return -EIO;
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun 
ftmac100_set_mac(struct ftmac100 * priv,const unsigned char * mac)141*4882a593Smuzhiyun static void ftmac100_set_mac(struct ftmac100 *priv, const unsigned char *mac)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun 	unsigned int maddr = mac[0] << 8 | mac[1];
144*4882a593Smuzhiyun 	unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	iowrite32(maddr, priv->base + FTMAC100_OFFSET_MAC_MADR);
147*4882a593Smuzhiyun 	iowrite32(laddr, priv->base + FTMAC100_OFFSET_MAC_LADR);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun #define MACCR_ENABLE_ALL	(FTMAC100_MACCR_XMT_EN	| \
151*4882a593Smuzhiyun 				 FTMAC100_MACCR_RCV_EN	| \
152*4882a593Smuzhiyun 				 FTMAC100_MACCR_XDMA_EN	| \
153*4882a593Smuzhiyun 				 FTMAC100_MACCR_RDMA_EN	| \
154*4882a593Smuzhiyun 				 FTMAC100_MACCR_CRC_APD	| \
155*4882a593Smuzhiyun 				 FTMAC100_MACCR_FULLDUP	| \
156*4882a593Smuzhiyun 				 FTMAC100_MACCR_RX_RUNT	| \
157*4882a593Smuzhiyun 				 FTMAC100_MACCR_RX_BROADPKT)
158*4882a593Smuzhiyun 
ftmac100_start_hw(struct ftmac100 * priv)159*4882a593Smuzhiyun static int ftmac100_start_hw(struct ftmac100 *priv)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun 	struct net_device *netdev = priv->netdev;
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	if (ftmac100_reset(priv))
164*4882a593Smuzhiyun 		return -EIO;
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun 	/* setup ring buffer base registers */
167*4882a593Smuzhiyun 	ftmac100_set_rx_ring_base(priv,
168*4882a593Smuzhiyun 				  priv->descs_dma_addr +
169*4882a593Smuzhiyun 				  offsetof(struct ftmac100_descs, rxdes));
170*4882a593Smuzhiyun 	ftmac100_set_tx_ring_base(priv,
171*4882a593Smuzhiyun 				  priv->descs_dma_addr +
172*4882a593Smuzhiyun 				  offsetof(struct ftmac100_descs, txdes));
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	iowrite32(FTMAC100_APTC_RXPOLL_CNT(1), priv->base + FTMAC100_OFFSET_APTC);
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun 	ftmac100_set_mac(priv, netdev->dev_addr);
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	iowrite32(MACCR_ENABLE_ALL, priv->base + FTMAC100_OFFSET_MACCR);
179*4882a593Smuzhiyun 	return 0;
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun 
ftmac100_stop_hw(struct ftmac100 * priv)182*4882a593Smuzhiyun static void ftmac100_stop_hw(struct ftmac100 *priv)
183*4882a593Smuzhiyun {
184*4882a593Smuzhiyun 	iowrite32(0, priv->base + FTMAC100_OFFSET_MACCR);
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun /******************************************************************************
188*4882a593Smuzhiyun  * internal functions (receive descriptor)
189*4882a593Smuzhiyun  *****************************************************************************/
ftmac100_rxdes_first_segment(struct ftmac100_rxdes * rxdes)190*4882a593Smuzhiyun static bool ftmac100_rxdes_first_segment(struct ftmac100_rxdes *rxdes)
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun 	return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_FRS);
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun 
ftmac100_rxdes_last_segment(struct ftmac100_rxdes * rxdes)195*4882a593Smuzhiyun static bool ftmac100_rxdes_last_segment(struct ftmac100_rxdes *rxdes)
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun 	return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_LRS);
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun 
ftmac100_rxdes_owned_by_dma(struct ftmac100_rxdes * rxdes)200*4882a593Smuzhiyun static bool ftmac100_rxdes_owned_by_dma(struct ftmac100_rxdes *rxdes)
201*4882a593Smuzhiyun {
202*4882a593Smuzhiyun 	return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_RXDMA_OWN);
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun 
ftmac100_rxdes_set_dma_own(struct ftmac100_rxdes * rxdes)205*4882a593Smuzhiyun static void ftmac100_rxdes_set_dma_own(struct ftmac100_rxdes *rxdes)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun 	/* clear status bits */
208*4882a593Smuzhiyun 	rxdes->rxdes0 = cpu_to_le32(FTMAC100_RXDES0_RXDMA_OWN);
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun 
ftmac100_rxdes_rx_error(struct ftmac100_rxdes * rxdes)211*4882a593Smuzhiyun static bool ftmac100_rxdes_rx_error(struct ftmac100_rxdes *rxdes)
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun 	return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_RX_ERR);
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun 
ftmac100_rxdes_crc_error(struct ftmac100_rxdes * rxdes)216*4882a593Smuzhiyun static bool ftmac100_rxdes_crc_error(struct ftmac100_rxdes *rxdes)
217*4882a593Smuzhiyun {
218*4882a593Smuzhiyun 	return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_CRC_ERR);
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun 
ftmac100_rxdes_frame_too_long(struct ftmac100_rxdes * rxdes)221*4882a593Smuzhiyun static bool ftmac100_rxdes_frame_too_long(struct ftmac100_rxdes *rxdes)
222*4882a593Smuzhiyun {
223*4882a593Smuzhiyun 	return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_FTL);
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun 
ftmac100_rxdes_runt(struct ftmac100_rxdes * rxdes)226*4882a593Smuzhiyun static bool ftmac100_rxdes_runt(struct ftmac100_rxdes *rxdes)
227*4882a593Smuzhiyun {
228*4882a593Smuzhiyun 	return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_RUNT);
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun 
ftmac100_rxdes_odd_nibble(struct ftmac100_rxdes * rxdes)231*4882a593Smuzhiyun static bool ftmac100_rxdes_odd_nibble(struct ftmac100_rxdes *rxdes)
232*4882a593Smuzhiyun {
233*4882a593Smuzhiyun 	return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_RX_ODD_NB);
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun 
ftmac100_rxdes_frame_length(struct ftmac100_rxdes * rxdes)236*4882a593Smuzhiyun static unsigned int ftmac100_rxdes_frame_length(struct ftmac100_rxdes *rxdes)
237*4882a593Smuzhiyun {
238*4882a593Smuzhiyun 	return le32_to_cpu(rxdes->rxdes0) & FTMAC100_RXDES0_RFL;
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun 
ftmac100_rxdes_multicast(struct ftmac100_rxdes * rxdes)241*4882a593Smuzhiyun static bool ftmac100_rxdes_multicast(struct ftmac100_rxdes *rxdes)
242*4882a593Smuzhiyun {
243*4882a593Smuzhiyun 	return rxdes->rxdes0 & cpu_to_le32(FTMAC100_RXDES0_MULTICAST);
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun 
ftmac100_rxdes_set_buffer_size(struct ftmac100_rxdes * rxdes,unsigned int size)246*4882a593Smuzhiyun static void ftmac100_rxdes_set_buffer_size(struct ftmac100_rxdes *rxdes,
247*4882a593Smuzhiyun 					   unsigned int size)
248*4882a593Smuzhiyun {
249*4882a593Smuzhiyun 	rxdes->rxdes1 &= cpu_to_le32(FTMAC100_RXDES1_EDORR);
250*4882a593Smuzhiyun 	rxdes->rxdes1 |= cpu_to_le32(FTMAC100_RXDES1_RXBUF_SIZE(size));
251*4882a593Smuzhiyun }
252*4882a593Smuzhiyun 
ftmac100_rxdes_set_end_of_ring(struct ftmac100_rxdes * rxdes)253*4882a593Smuzhiyun static void ftmac100_rxdes_set_end_of_ring(struct ftmac100_rxdes *rxdes)
254*4882a593Smuzhiyun {
255*4882a593Smuzhiyun 	rxdes->rxdes1 |= cpu_to_le32(FTMAC100_RXDES1_EDORR);
256*4882a593Smuzhiyun }
257*4882a593Smuzhiyun 
ftmac100_rxdes_set_dma_addr(struct ftmac100_rxdes * rxdes,dma_addr_t addr)258*4882a593Smuzhiyun static void ftmac100_rxdes_set_dma_addr(struct ftmac100_rxdes *rxdes,
259*4882a593Smuzhiyun 					dma_addr_t addr)
260*4882a593Smuzhiyun {
261*4882a593Smuzhiyun 	rxdes->rxdes2 = cpu_to_le32(addr);
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun 
ftmac100_rxdes_get_dma_addr(struct ftmac100_rxdes * rxdes)264*4882a593Smuzhiyun static dma_addr_t ftmac100_rxdes_get_dma_addr(struct ftmac100_rxdes *rxdes)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun 	return le32_to_cpu(rxdes->rxdes2);
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun /*
270*4882a593Smuzhiyun  * rxdes3 is not used by hardware. We use it to keep track of page.
271*4882a593Smuzhiyun  * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
272*4882a593Smuzhiyun  */
ftmac100_rxdes_set_page(struct ftmac100_rxdes * rxdes,struct page * page)273*4882a593Smuzhiyun static void ftmac100_rxdes_set_page(struct ftmac100_rxdes *rxdes, struct page *page)
274*4882a593Smuzhiyun {
275*4882a593Smuzhiyun 	rxdes->rxdes3 = (unsigned int)page;
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun 
ftmac100_rxdes_get_page(struct ftmac100_rxdes * rxdes)278*4882a593Smuzhiyun static struct page *ftmac100_rxdes_get_page(struct ftmac100_rxdes *rxdes)
279*4882a593Smuzhiyun {
280*4882a593Smuzhiyun 	return (struct page *)rxdes->rxdes3;
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun /******************************************************************************
284*4882a593Smuzhiyun  * internal functions (receive)
285*4882a593Smuzhiyun  *****************************************************************************/
ftmac100_next_rx_pointer(int pointer)286*4882a593Smuzhiyun static int ftmac100_next_rx_pointer(int pointer)
287*4882a593Smuzhiyun {
288*4882a593Smuzhiyun 	return (pointer + 1) & (RX_QUEUE_ENTRIES - 1);
289*4882a593Smuzhiyun }
290*4882a593Smuzhiyun 
ftmac100_rx_pointer_advance(struct ftmac100 * priv)291*4882a593Smuzhiyun static void ftmac100_rx_pointer_advance(struct ftmac100 *priv)
292*4882a593Smuzhiyun {
293*4882a593Smuzhiyun 	priv->rx_pointer = ftmac100_next_rx_pointer(priv->rx_pointer);
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun 
ftmac100_current_rxdes(struct ftmac100 * priv)296*4882a593Smuzhiyun static struct ftmac100_rxdes *ftmac100_current_rxdes(struct ftmac100 *priv)
297*4882a593Smuzhiyun {
298*4882a593Smuzhiyun 	return &priv->descs->rxdes[priv->rx_pointer];
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun static struct ftmac100_rxdes *
ftmac100_rx_locate_first_segment(struct ftmac100 * priv)302*4882a593Smuzhiyun ftmac100_rx_locate_first_segment(struct ftmac100 *priv)
303*4882a593Smuzhiyun {
304*4882a593Smuzhiyun 	struct ftmac100_rxdes *rxdes = ftmac100_current_rxdes(priv);
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 	while (!ftmac100_rxdes_owned_by_dma(rxdes)) {
307*4882a593Smuzhiyun 		if (ftmac100_rxdes_first_segment(rxdes))
308*4882a593Smuzhiyun 			return rxdes;
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun 		ftmac100_rxdes_set_dma_own(rxdes);
311*4882a593Smuzhiyun 		ftmac100_rx_pointer_advance(priv);
312*4882a593Smuzhiyun 		rxdes = ftmac100_current_rxdes(priv);
313*4882a593Smuzhiyun 	}
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 	return NULL;
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun 
ftmac100_rx_packet_error(struct ftmac100 * priv,struct ftmac100_rxdes * rxdes)318*4882a593Smuzhiyun static bool ftmac100_rx_packet_error(struct ftmac100 *priv,
319*4882a593Smuzhiyun 				     struct ftmac100_rxdes *rxdes)
320*4882a593Smuzhiyun {
321*4882a593Smuzhiyun 	struct net_device *netdev = priv->netdev;
322*4882a593Smuzhiyun 	bool error = false;
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun 	if (unlikely(ftmac100_rxdes_rx_error(rxdes))) {
325*4882a593Smuzhiyun 		if (net_ratelimit())
326*4882a593Smuzhiyun 			netdev_info(netdev, "rx err\n");
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun 		netdev->stats.rx_errors++;
329*4882a593Smuzhiyun 		error = true;
330*4882a593Smuzhiyun 	}
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 	if (unlikely(ftmac100_rxdes_crc_error(rxdes))) {
333*4882a593Smuzhiyun 		if (net_ratelimit())
334*4882a593Smuzhiyun 			netdev_info(netdev, "rx crc err\n");
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 		netdev->stats.rx_crc_errors++;
337*4882a593Smuzhiyun 		error = true;
338*4882a593Smuzhiyun 	}
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	if (unlikely(ftmac100_rxdes_frame_too_long(rxdes))) {
341*4882a593Smuzhiyun 		if (net_ratelimit())
342*4882a593Smuzhiyun 			netdev_info(netdev, "rx frame too long\n");
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun 		netdev->stats.rx_length_errors++;
345*4882a593Smuzhiyun 		error = true;
346*4882a593Smuzhiyun 	} else if (unlikely(ftmac100_rxdes_runt(rxdes))) {
347*4882a593Smuzhiyun 		if (net_ratelimit())
348*4882a593Smuzhiyun 			netdev_info(netdev, "rx runt\n");
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun 		netdev->stats.rx_length_errors++;
351*4882a593Smuzhiyun 		error = true;
352*4882a593Smuzhiyun 	} else if (unlikely(ftmac100_rxdes_odd_nibble(rxdes))) {
353*4882a593Smuzhiyun 		if (net_ratelimit())
354*4882a593Smuzhiyun 			netdev_info(netdev, "rx odd nibble\n");
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun 		netdev->stats.rx_length_errors++;
357*4882a593Smuzhiyun 		error = true;
358*4882a593Smuzhiyun 	}
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 	return error;
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun 
ftmac100_rx_drop_packet(struct ftmac100 * priv)363*4882a593Smuzhiyun static void ftmac100_rx_drop_packet(struct ftmac100 *priv)
364*4882a593Smuzhiyun {
365*4882a593Smuzhiyun 	struct net_device *netdev = priv->netdev;
366*4882a593Smuzhiyun 	struct ftmac100_rxdes *rxdes = ftmac100_current_rxdes(priv);
367*4882a593Smuzhiyun 	bool done = false;
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun 	if (net_ratelimit())
370*4882a593Smuzhiyun 		netdev_dbg(netdev, "drop packet %p\n", rxdes);
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun 	do {
373*4882a593Smuzhiyun 		if (ftmac100_rxdes_last_segment(rxdes))
374*4882a593Smuzhiyun 			done = true;
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun 		ftmac100_rxdes_set_dma_own(rxdes);
377*4882a593Smuzhiyun 		ftmac100_rx_pointer_advance(priv);
378*4882a593Smuzhiyun 		rxdes = ftmac100_current_rxdes(priv);
379*4882a593Smuzhiyun 	} while (!done && !ftmac100_rxdes_owned_by_dma(rxdes));
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun 	netdev->stats.rx_dropped++;
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun 
ftmac100_rx_packet(struct ftmac100 * priv,int * processed)384*4882a593Smuzhiyun static bool ftmac100_rx_packet(struct ftmac100 *priv, int *processed)
385*4882a593Smuzhiyun {
386*4882a593Smuzhiyun 	struct net_device *netdev = priv->netdev;
387*4882a593Smuzhiyun 	struct ftmac100_rxdes *rxdes;
388*4882a593Smuzhiyun 	struct sk_buff *skb;
389*4882a593Smuzhiyun 	struct page *page;
390*4882a593Smuzhiyun 	dma_addr_t map;
391*4882a593Smuzhiyun 	int length;
392*4882a593Smuzhiyun 	bool ret;
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun 	rxdes = ftmac100_rx_locate_first_segment(priv);
395*4882a593Smuzhiyun 	if (!rxdes)
396*4882a593Smuzhiyun 		return false;
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 	if (unlikely(ftmac100_rx_packet_error(priv, rxdes))) {
399*4882a593Smuzhiyun 		ftmac100_rx_drop_packet(priv);
400*4882a593Smuzhiyun 		return true;
401*4882a593Smuzhiyun 	}
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun 	/*
404*4882a593Smuzhiyun 	 * It is impossible to get multi-segment packets
405*4882a593Smuzhiyun 	 * because we always provide big enough receive buffers.
406*4882a593Smuzhiyun 	 */
407*4882a593Smuzhiyun 	ret = ftmac100_rxdes_last_segment(rxdes);
408*4882a593Smuzhiyun 	BUG_ON(!ret);
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	/* start processing */
411*4882a593Smuzhiyun 	skb = netdev_alloc_skb_ip_align(netdev, 128);
412*4882a593Smuzhiyun 	if (unlikely(!skb)) {
413*4882a593Smuzhiyun 		if (net_ratelimit())
414*4882a593Smuzhiyun 			netdev_err(netdev, "rx skb alloc failed\n");
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun 		ftmac100_rx_drop_packet(priv);
417*4882a593Smuzhiyun 		return true;
418*4882a593Smuzhiyun 	}
419*4882a593Smuzhiyun 
420*4882a593Smuzhiyun 	if (unlikely(ftmac100_rxdes_multicast(rxdes)))
421*4882a593Smuzhiyun 		netdev->stats.multicast++;
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun 	map = ftmac100_rxdes_get_dma_addr(rxdes);
424*4882a593Smuzhiyun 	dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
425*4882a593Smuzhiyun 
426*4882a593Smuzhiyun 	length = ftmac100_rxdes_frame_length(rxdes);
427*4882a593Smuzhiyun 	page = ftmac100_rxdes_get_page(rxdes);
428*4882a593Smuzhiyun 	skb_fill_page_desc(skb, 0, page, 0, length);
429*4882a593Smuzhiyun 	skb->len += length;
430*4882a593Smuzhiyun 	skb->data_len += length;
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun 	if (length > 128) {
433*4882a593Smuzhiyun 		skb->truesize += PAGE_SIZE;
434*4882a593Smuzhiyun 		/* We pull the minimum amount into linear part */
435*4882a593Smuzhiyun 		__pskb_pull_tail(skb, ETH_HLEN);
436*4882a593Smuzhiyun 	} else {
437*4882a593Smuzhiyun 		/* Small frames are copied into linear part to free one page */
438*4882a593Smuzhiyun 		__pskb_pull_tail(skb, length);
439*4882a593Smuzhiyun 	}
440*4882a593Smuzhiyun 	ftmac100_alloc_rx_page(priv, rxdes, GFP_ATOMIC);
441*4882a593Smuzhiyun 
442*4882a593Smuzhiyun 	ftmac100_rx_pointer_advance(priv);
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun 	skb->protocol = eth_type_trans(skb, netdev);
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun 	netdev->stats.rx_packets++;
447*4882a593Smuzhiyun 	netdev->stats.rx_bytes += skb->len;
448*4882a593Smuzhiyun 
449*4882a593Smuzhiyun 	/* push packet to protocol stack */
450*4882a593Smuzhiyun 	netif_receive_skb(skb);
451*4882a593Smuzhiyun 
452*4882a593Smuzhiyun 	(*processed)++;
453*4882a593Smuzhiyun 	return true;
454*4882a593Smuzhiyun }
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun /******************************************************************************
457*4882a593Smuzhiyun  * internal functions (transmit descriptor)
458*4882a593Smuzhiyun  *****************************************************************************/
ftmac100_txdes_reset(struct ftmac100_txdes * txdes)459*4882a593Smuzhiyun static void ftmac100_txdes_reset(struct ftmac100_txdes *txdes)
460*4882a593Smuzhiyun {
461*4882a593Smuzhiyun 	/* clear all except end of ring bit */
462*4882a593Smuzhiyun 	txdes->txdes0 = 0;
463*4882a593Smuzhiyun 	txdes->txdes1 &= cpu_to_le32(FTMAC100_TXDES1_EDOTR);
464*4882a593Smuzhiyun 	txdes->txdes2 = 0;
465*4882a593Smuzhiyun 	txdes->txdes3 = 0;
466*4882a593Smuzhiyun }
467*4882a593Smuzhiyun 
ftmac100_txdes_owned_by_dma(struct ftmac100_txdes * txdes)468*4882a593Smuzhiyun static bool ftmac100_txdes_owned_by_dma(struct ftmac100_txdes *txdes)
469*4882a593Smuzhiyun {
470*4882a593Smuzhiyun 	return txdes->txdes0 & cpu_to_le32(FTMAC100_TXDES0_TXDMA_OWN);
471*4882a593Smuzhiyun }
472*4882a593Smuzhiyun 
ftmac100_txdes_set_dma_own(struct ftmac100_txdes * txdes)473*4882a593Smuzhiyun static void ftmac100_txdes_set_dma_own(struct ftmac100_txdes *txdes)
474*4882a593Smuzhiyun {
475*4882a593Smuzhiyun 	/*
476*4882a593Smuzhiyun 	 * Make sure dma own bit will not be set before any other
477*4882a593Smuzhiyun 	 * descriptor fields.
478*4882a593Smuzhiyun 	 */
479*4882a593Smuzhiyun 	wmb();
480*4882a593Smuzhiyun 	txdes->txdes0 |= cpu_to_le32(FTMAC100_TXDES0_TXDMA_OWN);
481*4882a593Smuzhiyun }
482*4882a593Smuzhiyun 
ftmac100_txdes_excessive_collision(struct ftmac100_txdes * txdes)483*4882a593Smuzhiyun static bool ftmac100_txdes_excessive_collision(struct ftmac100_txdes *txdes)
484*4882a593Smuzhiyun {
485*4882a593Smuzhiyun 	return txdes->txdes0 & cpu_to_le32(FTMAC100_TXDES0_TXPKT_EXSCOL);
486*4882a593Smuzhiyun }
487*4882a593Smuzhiyun 
ftmac100_txdes_late_collision(struct ftmac100_txdes * txdes)488*4882a593Smuzhiyun static bool ftmac100_txdes_late_collision(struct ftmac100_txdes *txdes)
489*4882a593Smuzhiyun {
490*4882a593Smuzhiyun 	return txdes->txdes0 & cpu_to_le32(FTMAC100_TXDES0_TXPKT_LATECOL);
491*4882a593Smuzhiyun }
492*4882a593Smuzhiyun 
ftmac100_txdes_set_end_of_ring(struct ftmac100_txdes * txdes)493*4882a593Smuzhiyun static void ftmac100_txdes_set_end_of_ring(struct ftmac100_txdes *txdes)
494*4882a593Smuzhiyun {
495*4882a593Smuzhiyun 	txdes->txdes1 |= cpu_to_le32(FTMAC100_TXDES1_EDOTR);
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun 
ftmac100_txdes_set_first_segment(struct ftmac100_txdes * txdes)498*4882a593Smuzhiyun static void ftmac100_txdes_set_first_segment(struct ftmac100_txdes *txdes)
499*4882a593Smuzhiyun {
500*4882a593Smuzhiyun 	txdes->txdes1 |= cpu_to_le32(FTMAC100_TXDES1_FTS);
501*4882a593Smuzhiyun }
502*4882a593Smuzhiyun 
ftmac100_txdes_set_last_segment(struct ftmac100_txdes * txdes)503*4882a593Smuzhiyun static void ftmac100_txdes_set_last_segment(struct ftmac100_txdes *txdes)
504*4882a593Smuzhiyun {
505*4882a593Smuzhiyun 	txdes->txdes1 |= cpu_to_le32(FTMAC100_TXDES1_LTS);
506*4882a593Smuzhiyun }
507*4882a593Smuzhiyun 
ftmac100_txdes_set_txint(struct ftmac100_txdes * txdes)508*4882a593Smuzhiyun static void ftmac100_txdes_set_txint(struct ftmac100_txdes *txdes)
509*4882a593Smuzhiyun {
510*4882a593Smuzhiyun 	txdes->txdes1 |= cpu_to_le32(FTMAC100_TXDES1_TXIC);
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun 
ftmac100_txdes_set_buffer_size(struct ftmac100_txdes * txdes,unsigned int len)513*4882a593Smuzhiyun static void ftmac100_txdes_set_buffer_size(struct ftmac100_txdes *txdes,
514*4882a593Smuzhiyun 					   unsigned int len)
515*4882a593Smuzhiyun {
516*4882a593Smuzhiyun 	txdes->txdes1 |= cpu_to_le32(FTMAC100_TXDES1_TXBUF_SIZE(len));
517*4882a593Smuzhiyun }
518*4882a593Smuzhiyun 
ftmac100_txdes_set_dma_addr(struct ftmac100_txdes * txdes,dma_addr_t addr)519*4882a593Smuzhiyun static void ftmac100_txdes_set_dma_addr(struct ftmac100_txdes *txdes,
520*4882a593Smuzhiyun 					dma_addr_t addr)
521*4882a593Smuzhiyun {
522*4882a593Smuzhiyun 	txdes->txdes2 = cpu_to_le32(addr);
523*4882a593Smuzhiyun }
524*4882a593Smuzhiyun 
ftmac100_txdes_get_dma_addr(struct ftmac100_txdes * txdes)525*4882a593Smuzhiyun static dma_addr_t ftmac100_txdes_get_dma_addr(struct ftmac100_txdes *txdes)
526*4882a593Smuzhiyun {
527*4882a593Smuzhiyun 	return le32_to_cpu(txdes->txdes2);
528*4882a593Smuzhiyun }
529*4882a593Smuzhiyun 
530*4882a593Smuzhiyun /*
531*4882a593Smuzhiyun  * txdes3 is not used by hardware. We use it to keep track of socket buffer.
532*4882a593Smuzhiyun  * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
533*4882a593Smuzhiyun  */
ftmac100_txdes_set_skb(struct ftmac100_txdes * txdes,struct sk_buff * skb)534*4882a593Smuzhiyun static void ftmac100_txdes_set_skb(struct ftmac100_txdes *txdes, struct sk_buff *skb)
535*4882a593Smuzhiyun {
536*4882a593Smuzhiyun 	txdes->txdes3 = (unsigned int)skb;
537*4882a593Smuzhiyun }
538*4882a593Smuzhiyun 
ftmac100_txdes_get_skb(struct ftmac100_txdes * txdes)539*4882a593Smuzhiyun static struct sk_buff *ftmac100_txdes_get_skb(struct ftmac100_txdes *txdes)
540*4882a593Smuzhiyun {
541*4882a593Smuzhiyun 	return (struct sk_buff *)txdes->txdes3;
542*4882a593Smuzhiyun }
543*4882a593Smuzhiyun 
544*4882a593Smuzhiyun /******************************************************************************
545*4882a593Smuzhiyun  * internal functions (transmit)
546*4882a593Smuzhiyun  *****************************************************************************/
ftmac100_next_tx_pointer(int pointer)547*4882a593Smuzhiyun static int ftmac100_next_tx_pointer(int pointer)
548*4882a593Smuzhiyun {
549*4882a593Smuzhiyun 	return (pointer + 1) & (TX_QUEUE_ENTRIES - 1);
550*4882a593Smuzhiyun }
551*4882a593Smuzhiyun 
ftmac100_tx_pointer_advance(struct ftmac100 * priv)552*4882a593Smuzhiyun static void ftmac100_tx_pointer_advance(struct ftmac100 *priv)
553*4882a593Smuzhiyun {
554*4882a593Smuzhiyun 	priv->tx_pointer = ftmac100_next_tx_pointer(priv->tx_pointer);
555*4882a593Smuzhiyun }
556*4882a593Smuzhiyun 
ftmac100_tx_clean_pointer_advance(struct ftmac100 * priv)557*4882a593Smuzhiyun static void ftmac100_tx_clean_pointer_advance(struct ftmac100 *priv)
558*4882a593Smuzhiyun {
559*4882a593Smuzhiyun 	priv->tx_clean_pointer = ftmac100_next_tx_pointer(priv->tx_clean_pointer);
560*4882a593Smuzhiyun }
561*4882a593Smuzhiyun 
ftmac100_current_txdes(struct ftmac100 * priv)562*4882a593Smuzhiyun static struct ftmac100_txdes *ftmac100_current_txdes(struct ftmac100 *priv)
563*4882a593Smuzhiyun {
564*4882a593Smuzhiyun 	return &priv->descs->txdes[priv->tx_pointer];
565*4882a593Smuzhiyun }
566*4882a593Smuzhiyun 
ftmac100_current_clean_txdes(struct ftmac100 * priv)567*4882a593Smuzhiyun static struct ftmac100_txdes *ftmac100_current_clean_txdes(struct ftmac100 *priv)
568*4882a593Smuzhiyun {
569*4882a593Smuzhiyun 	return &priv->descs->txdes[priv->tx_clean_pointer];
570*4882a593Smuzhiyun }
571*4882a593Smuzhiyun 
ftmac100_tx_complete_packet(struct ftmac100 * priv)572*4882a593Smuzhiyun static bool ftmac100_tx_complete_packet(struct ftmac100 *priv)
573*4882a593Smuzhiyun {
574*4882a593Smuzhiyun 	struct net_device *netdev = priv->netdev;
575*4882a593Smuzhiyun 	struct ftmac100_txdes *txdes;
576*4882a593Smuzhiyun 	struct sk_buff *skb;
577*4882a593Smuzhiyun 	dma_addr_t map;
578*4882a593Smuzhiyun 
579*4882a593Smuzhiyun 	if (priv->tx_pending == 0)
580*4882a593Smuzhiyun 		return false;
581*4882a593Smuzhiyun 
582*4882a593Smuzhiyun 	txdes = ftmac100_current_clean_txdes(priv);
583*4882a593Smuzhiyun 
584*4882a593Smuzhiyun 	if (ftmac100_txdes_owned_by_dma(txdes))
585*4882a593Smuzhiyun 		return false;
586*4882a593Smuzhiyun 
587*4882a593Smuzhiyun 	skb = ftmac100_txdes_get_skb(txdes);
588*4882a593Smuzhiyun 	map = ftmac100_txdes_get_dma_addr(txdes);
589*4882a593Smuzhiyun 
590*4882a593Smuzhiyun 	if (unlikely(ftmac100_txdes_excessive_collision(txdes) ||
591*4882a593Smuzhiyun 		     ftmac100_txdes_late_collision(txdes))) {
592*4882a593Smuzhiyun 		/*
593*4882a593Smuzhiyun 		 * packet transmitted to ethernet lost due to late collision
594*4882a593Smuzhiyun 		 * or excessive collision
595*4882a593Smuzhiyun 		 */
596*4882a593Smuzhiyun 		netdev->stats.tx_aborted_errors++;
597*4882a593Smuzhiyun 	} else {
598*4882a593Smuzhiyun 		netdev->stats.tx_packets++;
599*4882a593Smuzhiyun 		netdev->stats.tx_bytes += skb->len;
600*4882a593Smuzhiyun 	}
601*4882a593Smuzhiyun 
602*4882a593Smuzhiyun 	dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
603*4882a593Smuzhiyun 	dev_kfree_skb(skb);
604*4882a593Smuzhiyun 
605*4882a593Smuzhiyun 	ftmac100_txdes_reset(txdes);
606*4882a593Smuzhiyun 
607*4882a593Smuzhiyun 	ftmac100_tx_clean_pointer_advance(priv);
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun 	spin_lock(&priv->tx_lock);
610*4882a593Smuzhiyun 	priv->tx_pending--;
611*4882a593Smuzhiyun 	spin_unlock(&priv->tx_lock);
612*4882a593Smuzhiyun 	netif_wake_queue(netdev);
613*4882a593Smuzhiyun 
614*4882a593Smuzhiyun 	return true;
615*4882a593Smuzhiyun }
616*4882a593Smuzhiyun 
ftmac100_tx_complete(struct ftmac100 * priv)617*4882a593Smuzhiyun static void ftmac100_tx_complete(struct ftmac100 *priv)
618*4882a593Smuzhiyun {
619*4882a593Smuzhiyun 	while (ftmac100_tx_complete_packet(priv))
620*4882a593Smuzhiyun 		;
621*4882a593Smuzhiyun }
622*4882a593Smuzhiyun 
ftmac100_xmit(struct ftmac100 * priv,struct sk_buff * skb,dma_addr_t map)623*4882a593Smuzhiyun static netdev_tx_t ftmac100_xmit(struct ftmac100 *priv, struct sk_buff *skb,
624*4882a593Smuzhiyun 				 dma_addr_t map)
625*4882a593Smuzhiyun {
626*4882a593Smuzhiyun 	struct net_device *netdev = priv->netdev;
627*4882a593Smuzhiyun 	struct ftmac100_txdes *txdes;
628*4882a593Smuzhiyun 	unsigned int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len;
629*4882a593Smuzhiyun 
630*4882a593Smuzhiyun 	txdes = ftmac100_current_txdes(priv);
631*4882a593Smuzhiyun 	ftmac100_tx_pointer_advance(priv);
632*4882a593Smuzhiyun 
633*4882a593Smuzhiyun 	/* setup TX descriptor */
634*4882a593Smuzhiyun 	ftmac100_txdes_set_skb(txdes, skb);
635*4882a593Smuzhiyun 	ftmac100_txdes_set_dma_addr(txdes, map);
636*4882a593Smuzhiyun 
637*4882a593Smuzhiyun 	ftmac100_txdes_set_first_segment(txdes);
638*4882a593Smuzhiyun 	ftmac100_txdes_set_last_segment(txdes);
639*4882a593Smuzhiyun 	ftmac100_txdes_set_txint(txdes);
640*4882a593Smuzhiyun 	ftmac100_txdes_set_buffer_size(txdes, len);
641*4882a593Smuzhiyun 
642*4882a593Smuzhiyun 	spin_lock(&priv->tx_lock);
643*4882a593Smuzhiyun 	priv->tx_pending++;
644*4882a593Smuzhiyun 	if (priv->tx_pending == TX_QUEUE_ENTRIES)
645*4882a593Smuzhiyun 		netif_stop_queue(netdev);
646*4882a593Smuzhiyun 
647*4882a593Smuzhiyun 	/* start transmit */
648*4882a593Smuzhiyun 	ftmac100_txdes_set_dma_own(txdes);
649*4882a593Smuzhiyun 	spin_unlock(&priv->tx_lock);
650*4882a593Smuzhiyun 
651*4882a593Smuzhiyun 	ftmac100_txdma_start_polling(priv);
652*4882a593Smuzhiyun 	return NETDEV_TX_OK;
653*4882a593Smuzhiyun }
654*4882a593Smuzhiyun 
655*4882a593Smuzhiyun /******************************************************************************
656*4882a593Smuzhiyun  * internal functions (buffer)
657*4882a593Smuzhiyun  *****************************************************************************/
ftmac100_alloc_rx_page(struct ftmac100 * priv,struct ftmac100_rxdes * rxdes,gfp_t gfp)658*4882a593Smuzhiyun static int ftmac100_alloc_rx_page(struct ftmac100 *priv,
659*4882a593Smuzhiyun 				  struct ftmac100_rxdes *rxdes, gfp_t gfp)
660*4882a593Smuzhiyun {
661*4882a593Smuzhiyun 	struct net_device *netdev = priv->netdev;
662*4882a593Smuzhiyun 	struct page *page;
663*4882a593Smuzhiyun 	dma_addr_t map;
664*4882a593Smuzhiyun 
665*4882a593Smuzhiyun 	page = alloc_page(gfp);
666*4882a593Smuzhiyun 	if (!page) {
667*4882a593Smuzhiyun 		if (net_ratelimit())
668*4882a593Smuzhiyun 			netdev_err(netdev, "failed to allocate rx page\n");
669*4882a593Smuzhiyun 		return -ENOMEM;
670*4882a593Smuzhiyun 	}
671*4882a593Smuzhiyun 
672*4882a593Smuzhiyun 	map = dma_map_page(priv->dev, page, 0, RX_BUF_SIZE, DMA_FROM_DEVICE);
673*4882a593Smuzhiyun 	if (unlikely(dma_mapping_error(priv->dev, map))) {
674*4882a593Smuzhiyun 		if (net_ratelimit())
675*4882a593Smuzhiyun 			netdev_err(netdev, "failed to map rx page\n");
676*4882a593Smuzhiyun 		__free_page(page);
677*4882a593Smuzhiyun 		return -ENOMEM;
678*4882a593Smuzhiyun 	}
679*4882a593Smuzhiyun 
680*4882a593Smuzhiyun 	ftmac100_rxdes_set_page(rxdes, page);
681*4882a593Smuzhiyun 	ftmac100_rxdes_set_dma_addr(rxdes, map);
682*4882a593Smuzhiyun 	ftmac100_rxdes_set_buffer_size(rxdes, RX_BUF_SIZE);
683*4882a593Smuzhiyun 	ftmac100_rxdes_set_dma_own(rxdes);
684*4882a593Smuzhiyun 	return 0;
685*4882a593Smuzhiyun }
686*4882a593Smuzhiyun 
ftmac100_free_buffers(struct ftmac100 * priv)687*4882a593Smuzhiyun static void ftmac100_free_buffers(struct ftmac100 *priv)
688*4882a593Smuzhiyun {
689*4882a593Smuzhiyun 	int i;
690*4882a593Smuzhiyun 
691*4882a593Smuzhiyun 	for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
692*4882a593Smuzhiyun 		struct ftmac100_rxdes *rxdes = &priv->descs->rxdes[i];
693*4882a593Smuzhiyun 		struct page *page = ftmac100_rxdes_get_page(rxdes);
694*4882a593Smuzhiyun 		dma_addr_t map = ftmac100_rxdes_get_dma_addr(rxdes);
695*4882a593Smuzhiyun 
696*4882a593Smuzhiyun 		if (!page)
697*4882a593Smuzhiyun 			continue;
698*4882a593Smuzhiyun 
699*4882a593Smuzhiyun 		dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
700*4882a593Smuzhiyun 		__free_page(page);
701*4882a593Smuzhiyun 	}
702*4882a593Smuzhiyun 
703*4882a593Smuzhiyun 	for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
704*4882a593Smuzhiyun 		struct ftmac100_txdes *txdes = &priv->descs->txdes[i];
705*4882a593Smuzhiyun 		struct sk_buff *skb = ftmac100_txdes_get_skb(txdes);
706*4882a593Smuzhiyun 		dma_addr_t map = ftmac100_txdes_get_dma_addr(txdes);
707*4882a593Smuzhiyun 
708*4882a593Smuzhiyun 		if (!skb)
709*4882a593Smuzhiyun 			continue;
710*4882a593Smuzhiyun 
711*4882a593Smuzhiyun 		dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
712*4882a593Smuzhiyun 		dev_kfree_skb(skb);
713*4882a593Smuzhiyun 	}
714*4882a593Smuzhiyun 
715*4882a593Smuzhiyun 	dma_free_coherent(priv->dev, sizeof(struct ftmac100_descs),
716*4882a593Smuzhiyun 			  priv->descs, priv->descs_dma_addr);
717*4882a593Smuzhiyun }
718*4882a593Smuzhiyun 
ftmac100_alloc_buffers(struct ftmac100 * priv)719*4882a593Smuzhiyun static int ftmac100_alloc_buffers(struct ftmac100 *priv)
720*4882a593Smuzhiyun {
721*4882a593Smuzhiyun 	int i;
722*4882a593Smuzhiyun 
723*4882a593Smuzhiyun 	priv->descs = dma_alloc_coherent(priv->dev,
724*4882a593Smuzhiyun 					 sizeof(struct ftmac100_descs),
725*4882a593Smuzhiyun 					 &priv->descs_dma_addr, GFP_KERNEL);
726*4882a593Smuzhiyun 	if (!priv->descs)
727*4882a593Smuzhiyun 		return -ENOMEM;
728*4882a593Smuzhiyun 
729*4882a593Smuzhiyun 	/* initialize RX ring */
730*4882a593Smuzhiyun 	ftmac100_rxdes_set_end_of_ring(&priv->descs->rxdes[RX_QUEUE_ENTRIES - 1]);
731*4882a593Smuzhiyun 
732*4882a593Smuzhiyun 	for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
733*4882a593Smuzhiyun 		struct ftmac100_rxdes *rxdes = &priv->descs->rxdes[i];
734*4882a593Smuzhiyun 
735*4882a593Smuzhiyun 		if (ftmac100_alloc_rx_page(priv, rxdes, GFP_KERNEL))
736*4882a593Smuzhiyun 			goto err;
737*4882a593Smuzhiyun 	}
738*4882a593Smuzhiyun 
739*4882a593Smuzhiyun 	/* initialize TX ring */
740*4882a593Smuzhiyun 	ftmac100_txdes_set_end_of_ring(&priv->descs->txdes[TX_QUEUE_ENTRIES - 1]);
741*4882a593Smuzhiyun 	return 0;
742*4882a593Smuzhiyun 
743*4882a593Smuzhiyun err:
744*4882a593Smuzhiyun 	ftmac100_free_buffers(priv);
745*4882a593Smuzhiyun 	return -ENOMEM;
746*4882a593Smuzhiyun }
747*4882a593Smuzhiyun 
748*4882a593Smuzhiyun /******************************************************************************
749*4882a593Smuzhiyun  * struct mii_if_info functions
750*4882a593Smuzhiyun  *****************************************************************************/
ftmac100_mdio_read(struct net_device * netdev,int phy_id,int reg)751*4882a593Smuzhiyun static int ftmac100_mdio_read(struct net_device *netdev, int phy_id, int reg)
752*4882a593Smuzhiyun {
753*4882a593Smuzhiyun 	struct ftmac100 *priv = netdev_priv(netdev);
754*4882a593Smuzhiyun 	unsigned int phycr;
755*4882a593Smuzhiyun 	int i;
756*4882a593Smuzhiyun 
757*4882a593Smuzhiyun 	phycr = FTMAC100_PHYCR_PHYAD(phy_id) |
758*4882a593Smuzhiyun 		FTMAC100_PHYCR_REGAD(reg) |
759*4882a593Smuzhiyun 		FTMAC100_PHYCR_MIIRD;
760*4882a593Smuzhiyun 
761*4882a593Smuzhiyun 	iowrite32(phycr, priv->base + FTMAC100_OFFSET_PHYCR);
762*4882a593Smuzhiyun 
763*4882a593Smuzhiyun 	for (i = 0; i < 10; i++) {
764*4882a593Smuzhiyun 		phycr = ioread32(priv->base + FTMAC100_OFFSET_PHYCR);
765*4882a593Smuzhiyun 
766*4882a593Smuzhiyun 		if ((phycr & FTMAC100_PHYCR_MIIRD) == 0)
767*4882a593Smuzhiyun 			return phycr & FTMAC100_PHYCR_MIIRDATA;
768*4882a593Smuzhiyun 
769*4882a593Smuzhiyun 		udelay(100);
770*4882a593Smuzhiyun 	}
771*4882a593Smuzhiyun 
772*4882a593Smuzhiyun 	netdev_err(netdev, "mdio read timed out\n");
773*4882a593Smuzhiyun 	return 0;
774*4882a593Smuzhiyun }
775*4882a593Smuzhiyun 
ftmac100_mdio_write(struct net_device * netdev,int phy_id,int reg,int data)776*4882a593Smuzhiyun static void ftmac100_mdio_write(struct net_device *netdev, int phy_id, int reg,
777*4882a593Smuzhiyun 				int data)
778*4882a593Smuzhiyun {
779*4882a593Smuzhiyun 	struct ftmac100 *priv = netdev_priv(netdev);
780*4882a593Smuzhiyun 	unsigned int phycr;
781*4882a593Smuzhiyun 	int i;
782*4882a593Smuzhiyun 
783*4882a593Smuzhiyun 	phycr = FTMAC100_PHYCR_PHYAD(phy_id) |
784*4882a593Smuzhiyun 		FTMAC100_PHYCR_REGAD(reg) |
785*4882a593Smuzhiyun 		FTMAC100_PHYCR_MIIWR;
786*4882a593Smuzhiyun 
787*4882a593Smuzhiyun 	data = FTMAC100_PHYWDATA_MIIWDATA(data);
788*4882a593Smuzhiyun 
789*4882a593Smuzhiyun 	iowrite32(data, priv->base + FTMAC100_OFFSET_PHYWDATA);
790*4882a593Smuzhiyun 	iowrite32(phycr, priv->base + FTMAC100_OFFSET_PHYCR);
791*4882a593Smuzhiyun 
792*4882a593Smuzhiyun 	for (i = 0; i < 10; i++) {
793*4882a593Smuzhiyun 		phycr = ioread32(priv->base + FTMAC100_OFFSET_PHYCR);
794*4882a593Smuzhiyun 
795*4882a593Smuzhiyun 		if ((phycr & FTMAC100_PHYCR_MIIWR) == 0)
796*4882a593Smuzhiyun 			return;
797*4882a593Smuzhiyun 
798*4882a593Smuzhiyun 		udelay(100);
799*4882a593Smuzhiyun 	}
800*4882a593Smuzhiyun 
801*4882a593Smuzhiyun 	netdev_err(netdev, "mdio write timed out\n");
802*4882a593Smuzhiyun }
803*4882a593Smuzhiyun 
804*4882a593Smuzhiyun /******************************************************************************
805*4882a593Smuzhiyun  * struct ethtool_ops functions
806*4882a593Smuzhiyun  *****************************************************************************/
ftmac100_get_drvinfo(struct net_device * netdev,struct ethtool_drvinfo * info)807*4882a593Smuzhiyun static void ftmac100_get_drvinfo(struct net_device *netdev,
808*4882a593Smuzhiyun 				 struct ethtool_drvinfo *info)
809*4882a593Smuzhiyun {
810*4882a593Smuzhiyun 	strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
811*4882a593Smuzhiyun 	strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info));
812*4882a593Smuzhiyun }
813*4882a593Smuzhiyun 
ftmac100_get_link_ksettings(struct net_device * netdev,struct ethtool_link_ksettings * cmd)814*4882a593Smuzhiyun static int ftmac100_get_link_ksettings(struct net_device *netdev,
815*4882a593Smuzhiyun 				       struct ethtool_link_ksettings *cmd)
816*4882a593Smuzhiyun {
817*4882a593Smuzhiyun 	struct ftmac100 *priv = netdev_priv(netdev);
818*4882a593Smuzhiyun 
819*4882a593Smuzhiyun 	mii_ethtool_get_link_ksettings(&priv->mii, cmd);
820*4882a593Smuzhiyun 
821*4882a593Smuzhiyun 	return 0;
822*4882a593Smuzhiyun }
823*4882a593Smuzhiyun 
ftmac100_set_link_ksettings(struct net_device * netdev,const struct ethtool_link_ksettings * cmd)824*4882a593Smuzhiyun static int ftmac100_set_link_ksettings(struct net_device *netdev,
825*4882a593Smuzhiyun 				       const struct ethtool_link_ksettings *cmd)
826*4882a593Smuzhiyun {
827*4882a593Smuzhiyun 	struct ftmac100 *priv = netdev_priv(netdev);
828*4882a593Smuzhiyun 	return mii_ethtool_set_link_ksettings(&priv->mii, cmd);
829*4882a593Smuzhiyun }
830*4882a593Smuzhiyun 
ftmac100_nway_reset(struct net_device * netdev)831*4882a593Smuzhiyun static int ftmac100_nway_reset(struct net_device *netdev)
832*4882a593Smuzhiyun {
833*4882a593Smuzhiyun 	struct ftmac100 *priv = netdev_priv(netdev);
834*4882a593Smuzhiyun 	return mii_nway_restart(&priv->mii);
835*4882a593Smuzhiyun }
836*4882a593Smuzhiyun 
ftmac100_get_link(struct net_device * netdev)837*4882a593Smuzhiyun static u32 ftmac100_get_link(struct net_device *netdev)
838*4882a593Smuzhiyun {
839*4882a593Smuzhiyun 	struct ftmac100 *priv = netdev_priv(netdev);
840*4882a593Smuzhiyun 	return mii_link_ok(&priv->mii);
841*4882a593Smuzhiyun }
842*4882a593Smuzhiyun 
843*4882a593Smuzhiyun static const struct ethtool_ops ftmac100_ethtool_ops = {
844*4882a593Smuzhiyun 	.get_drvinfo		= ftmac100_get_drvinfo,
845*4882a593Smuzhiyun 	.nway_reset		= ftmac100_nway_reset,
846*4882a593Smuzhiyun 	.get_link		= ftmac100_get_link,
847*4882a593Smuzhiyun 	.get_link_ksettings	= ftmac100_get_link_ksettings,
848*4882a593Smuzhiyun 	.set_link_ksettings	= ftmac100_set_link_ksettings,
849*4882a593Smuzhiyun };
850*4882a593Smuzhiyun 
851*4882a593Smuzhiyun /******************************************************************************
852*4882a593Smuzhiyun  * interrupt handler
853*4882a593Smuzhiyun  *****************************************************************************/
ftmac100_interrupt(int irq,void * dev_id)854*4882a593Smuzhiyun static irqreturn_t ftmac100_interrupt(int irq, void *dev_id)
855*4882a593Smuzhiyun {
856*4882a593Smuzhiyun 	struct net_device *netdev = dev_id;
857*4882a593Smuzhiyun 	struct ftmac100 *priv = netdev_priv(netdev);
858*4882a593Smuzhiyun 
859*4882a593Smuzhiyun 	/* Disable interrupts for polling */
860*4882a593Smuzhiyun 	ftmac100_disable_all_int(priv);
861*4882a593Smuzhiyun 	if (likely(netif_running(netdev)))
862*4882a593Smuzhiyun 		napi_schedule(&priv->napi);
863*4882a593Smuzhiyun 
864*4882a593Smuzhiyun 	return IRQ_HANDLED;
865*4882a593Smuzhiyun }
866*4882a593Smuzhiyun 
867*4882a593Smuzhiyun /******************************************************************************
868*4882a593Smuzhiyun  * struct napi_struct functions
869*4882a593Smuzhiyun  *****************************************************************************/
ftmac100_poll(struct napi_struct * napi,int budget)870*4882a593Smuzhiyun static int ftmac100_poll(struct napi_struct *napi, int budget)
871*4882a593Smuzhiyun {
872*4882a593Smuzhiyun 	struct ftmac100 *priv = container_of(napi, struct ftmac100, napi);
873*4882a593Smuzhiyun 	struct net_device *netdev = priv->netdev;
874*4882a593Smuzhiyun 	unsigned int status;
875*4882a593Smuzhiyun 	bool completed = true;
876*4882a593Smuzhiyun 	int rx = 0;
877*4882a593Smuzhiyun 
878*4882a593Smuzhiyun 	status = ioread32(priv->base + FTMAC100_OFFSET_ISR);
879*4882a593Smuzhiyun 
880*4882a593Smuzhiyun 	if (status & (FTMAC100_INT_RPKT_FINISH | FTMAC100_INT_NORXBUF)) {
881*4882a593Smuzhiyun 		/*
882*4882a593Smuzhiyun 		 * FTMAC100_INT_RPKT_FINISH:
883*4882a593Smuzhiyun 		 *	RX DMA has received packets into RX buffer successfully
884*4882a593Smuzhiyun 		 *
885*4882a593Smuzhiyun 		 * FTMAC100_INT_NORXBUF:
886*4882a593Smuzhiyun 		 *	RX buffer unavailable
887*4882a593Smuzhiyun 		 */
888*4882a593Smuzhiyun 		bool retry;
889*4882a593Smuzhiyun 
890*4882a593Smuzhiyun 		do {
891*4882a593Smuzhiyun 			retry = ftmac100_rx_packet(priv, &rx);
892*4882a593Smuzhiyun 		} while (retry && rx < budget);
893*4882a593Smuzhiyun 
894*4882a593Smuzhiyun 		if (retry && rx == budget)
895*4882a593Smuzhiyun 			completed = false;
896*4882a593Smuzhiyun 	}
897*4882a593Smuzhiyun 
898*4882a593Smuzhiyun 	if (status & (FTMAC100_INT_XPKT_OK | FTMAC100_INT_XPKT_LOST)) {
899*4882a593Smuzhiyun 		/*
900*4882a593Smuzhiyun 		 * FTMAC100_INT_XPKT_OK:
901*4882a593Smuzhiyun 		 *	packet transmitted to ethernet successfully
902*4882a593Smuzhiyun 		 *
903*4882a593Smuzhiyun 		 * FTMAC100_INT_XPKT_LOST:
904*4882a593Smuzhiyun 		 *	packet transmitted to ethernet lost due to late
905*4882a593Smuzhiyun 		 *	collision or excessive collision
906*4882a593Smuzhiyun 		 */
907*4882a593Smuzhiyun 		ftmac100_tx_complete(priv);
908*4882a593Smuzhiyun 	}
909*4882a593Smuzhiyun 
910*4882a593Smuzhiyun 	if (status & (FTMAC100_INT_NORXBUF | FTMAC100_INT_RPKT_LOST |
911*4882a593Smuzhiyun 		      FTMAC100_INT_AHB_ERR | FTMAC100_INT_PHYSTS_CHG)) {
912*4882a593Smuzhiyun 		if (net_ratelimit())
913*4882a593Smuzhiyun 			netdev_info(netdev, "[ISR] = 0x%x: %s%s%s%s\n", status,
914*4882a593Smuzhiyun 				    status & FTMAC100_INT_NORXBUF ? "NORXBUF " : "",
915*4882a593Smuzhiyun 				    status & FTMAC100_INT_RPKT_LOST ? "RPKT_LOST " : "",
916*4882a593Smuzhiyun 				    status & FTMAC100_INT_AHB_ERR ? "AHB_ERR " : "",
917*4882a593Smuzhiyun 				    status & FTMAC100_INT_PHYSTS_CHG ? "PHYSTS_CHG" : "");
918*4882a593Smuzhiyun 
919*4882a593Smuzhiyun 		if (status & FTMAC100_INT_NORXBUF) {
920*4882a593Smuzhiyun 			/* RX buffer unavailable */
921*4882a593Smuzhiyun 			netdev->stats.rx_over_errors++;
922*4882a593Smuzhiyun 		}
923*4882a593Smuzhiyun 
924*4882a593Smuzhiyun 		if (status & FTMAC100_INT_RPKT_LOST) {
925*4882a593Smuzhiyun 			/* received packet lost due to RX FIFO full */
926*4882a593Smuzhiyun 			netdev->stats.rx_fifo_errors++;
927*4882a593Smuzhiyun 		}
928*4882a593Smuzhiyun 
929*4882a593Smuzhiyun 		if (status & FTMAC100_INT_PHYSTS_CHG) {
930*4882a593Smuzhiyun 			/* PHY link status change */
931*4882a593Smuzhiyun 			mii_check_link(&priv->mii);
932*4882a593Smuzhiyun 		}
933*4882a593Smuzhiyun 	}
934*4882a593Smuzhiyun 
935*4882a593Smuzhiyun 	if (completed) {
936*4882a593Smuzhiyun 		/* stop polling */
937*4882a593Smuzhiyun 		napi_complete(napi);
938*4882a593Smuzhiyun 		ftmac100_enable_all_int(priv);
939*4882a593Smuzhiyun 	}
940*4882a593Smuzhiyun 
941*4882a593Smuzhiyun 	return rx;
942*4882a593Smuzhiyun }
943*4882a593Smuzhiyun 
944*4882a593Smuzhiyun /******************************************************************************
945*4882a593Smuzhiyun  * struct net_device_ops functions
946*4882a593Smuzhiyun  *****************************************************************************/
ftmac100_open(struct net_device * netdev)947*4882a593Smuzhiyun static int ftmac100_open(struct net_device *netdev)
948*4882a593Smuzhiyun {
949*4882a593Smuzhiyun 	struct ftmac100 *priv = netdev_priv(netdev);
950*4882a593Smuzhiyun 	int err;
951*4882a593Smuzhiyun 
952*4882a593Smuzhiyun 	err = ftmac100_alloc_buffers(priv);
953*4882a593Smuzhiyun 	if (err) {
954*4882a593Smuzhiyun 		netdev_err(netdev, "failed to allocate buffers\n");
955*4882a593Smuzhiyun 		goto err_alloc;
956*4882a593Smuzhiyun 	}
957*4882a593Smuzhiyun 
958*4882a593Smuzhiyun 	err = request_irq(priv->irq, ftmac100_interrupt, 0, netdev->name, netdev);
959*4882a593Smuzhiyun 	if (err) {
960*4882a593Smuzhiyun 		netdev_err(netdev, "failed to request irq %d\n", priv->irq);
961*4882a593Smuzhiyun 		goto err_irq;
962*4882a593Smuzhiyun 	}
963*4882a593Smuzhiyun 
964*4882a593Smuzhiyun 	priv->rx_pointer = 0;
965*4882a593Smuzhiyun 	priv->tx_clean_pointer = 0;
966*4882a593Smuzhiyun 	priv->tx_pointer = 0;
967*4882a593Smuzhiyun 	priv->tx_pending = 0;
968*4882a593Smuzhiyun 
969*4882a593Smuzhiyun 	err = ftmac100_start_hw(priv);
970*4882a593Smuzhiyun 	if (err)
971*4882a593Smuzhiyun 		goto err_hw;
972*4882a593Smuzhiyun 
973*4882a593Smuzhiyun 	napi_enable(&priv->napi);
974*4882a593Smuzhiyun 	netif_start_queue(netdev);
975*4882a593Smuzhiyun 
976*4882a593Smuzhiyun 	ftmac100_enable_all_int(priv);
977*4882a593Smuzhiyun 
978*4882a593Smuzhiyun 	return 0;
979*4882a593Smuzhiyun 
980*4882a593Smuzhiyun err_hw:
981*4882a593Smuzhiyun 	free_irq(priv->irq, netdev);
982*4882a593Smuzhiyun err_irq:
983*4882a593Smuzhiyun 	ftmac100_free_buffers(priv);
984*4882a593Smuzhiyun err_alloc:
985*4882a593Smuzhiyun 	return err;
986*4882a593Smuzhiyun }
987*4882a593Smuzhiyun 
ftmac100_stop(struct net_device * netdev)988*4882a593Smuzhiyun static int ftmac100_stop(struct net_device *netdev)
989*4882a593Smuzhiyun {
990*4882a593Smuzhiyun 	struct ftmac100 *priv = netdev_priv(netdev);
991*4882a593Smuzhiyun 
992*4882a593Smuzhiyun 	ftmac100_disable_all_int(priv);
993*4882a593Smuzhiyun 	netif_stop_queue(netdev);
994*4882a593Smuzhiyun 	napi_disable(&priv->napi);
995*4882a593Smuzhiyun 	ftmac100_stop_hw(priv);
996*4882a593Smuzhiyun 	free_irq(priv->irq, netdev);
997*4882a593Smuzhiyun 	ftmac100_free_buffers(priv);
998*4882a593Smuzhiyun 
999*4882a593Smuzhiyun 	return 0;
1000*4882a593Smuzhiyun }
1001*4882a593Smuzhiyun 
1002*4882a593Smuzhiyun static netdev_tx_t
ftmac100_hard_start_xmit(struct sk_buff * skb,struct net_device * netdev)1003*4882a593Smuzhiyun ftmac100_hard_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1004*4882a593Smuzhiyun {
1005*4882a593Smuzhiyun 	struct ftmac100 *priv = netdev_priv(netdev);
1006*4882a593Smuzhiyun 	dma_addr_t map;
1007*4882a593Smuzhiyun 
1008*4882a593Smuzhiyun 	if (unlikely(skb->len > MAX_PKT_SIZE)) {
1009*4882a593Smuzhiyun 		if (net_ratelimit())
1010*4882a593Smuzhiyun 			netdev_dbg(netdev, "tx packet too big\n");
1011*4882a593Smuzhiyun 
1012*4882a593Smuzhiyun 		netdev->stats.tx_dropped++;
1013*4882a593Smuzhiyun 		dev_kfree_skb(skb);
1014*4882a593Smuzhiyun 		return NETDEV_TX_OK;
1015*4882a593Smuzhiyun 	}
1016*4882a593Smuzhiyun 
1017*4882a593Smuzhiyun 	map = dma_map_single(priv->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
1018*4882a593Smuzhiyun 	if (unlikely(dma_mapping_error(priv->dev, map))) {
1019*4882a593Smuzhiyun 		/* drop packet */
1020*4882a593Smuzhiyun 		if (net_ratelimit())
1021*4882a593Smuzhiyun 			netdev_err(netdev, "map socket buffer failed\n");
1022*4882a593Smuzhiyun 
1023*4882a593Smuzhiyun 		netdev->stats.tx_dropped++;
1024*4882a593Smuzhiyun 		dev_kfree_skb(skb);
1025*4882a593Smuzhiyun 		return NETDEV_TX_OK;
1026*4882a593Smuzhiyun 	}
1027*4882a593Smuzhiyun 
1028*4882a593Smuzhiyun 	return ftmac100_xmit(priv, skb, map);
1029*4882a593Smuzhiyun }
1030*4882a593Smuzhiyun 
1031*4882a593Smuzhiyun /* optional */
ftmac100_do_ioctl(struct net_device * netdev,struct ifreq * ifr,int cmd)1032*4882a593Smuzhiyun static int ftmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1033*4882a593Smuzhiyun {
1034*4882a593Smuzhiyun 	struct ftmac100 *priv = netdev_priv(netdev);
1035*4882a593Smuzhiyun 	struct mii_ioctl_data *data = if_mii(ifr);
1036*4882a593Smuzhiyun 
1037*4882a593Smuzhiyun 	return generic_mii_ioctl(&priv->mii, data, cmd, NULL);
1038*4882a593Smuzhiyun }
1039*4882a593Smuzhiyun 
1040*4882a593Smuzhiyun static const struct net_device_ops ftmac100_netdev_ops = {
1041*4882a593Smuzhiyun 	.ndo_open		= ftmac100_open,
1042*4882a593Smuzhiyun 	.ndo_stop		= ftmac100_stop,
1043*4882a593Smuzhiyun 	.ndo_start_xmit		= ftmac100_hard_start_xmit,
1044*4882a593Smuzhiyun 	.ndo_set_mac_address	= eth_mac_addr,
1045*4882a593Smuzhiyun 	.ndo_validate_addr	= eth_validate_addr,
1046*4882a593Smuzhiyun 	.ndo_do_ioctl		= ftmac100_do_ioctl,
1047*4882a593Smuzhiyun };
1048*4882a593Smuzhiyun 
1049*4882a593Smuzhiyun /******************************************************************************
1050*4882a593Smuzhiyun  * struct platform_driver functions
1051*4882a593Smuzhiyun  *****************************************************************************/
ftmac100_probe(struct platform_device * pdev)1052*4882a593Smuzhiyun static int ftmac100_probe(struct platform_device *pdev)
1053*4882a593Smuzhiyun {
1054*4882a593Smuzhiyun 	struct resource *res;
1055*4882a593Smuzhiyun 	int irq;
1056*4882a593Smuzhiyun 	struct net_device *netdev;
1057*4882a593Smuzhiyun 	struct ftmac100 *priv;
1058*4882a593Smuzhiyun 	int err;
1059*4882a593Smuzhiyun 
1060*4882a593Smuzhiyun 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1061*4882a593Smuzhiyun 	if (!res)
1062*4882a593Smuzhiyun 		return -ENXIO;
1063*4882a593Smuzhiyun 
1064*4882a593Smuzhiyun 	irq = platform_get_irq(pdev, 0);
1065*4882a593Smuzhiyun 	if (irq < 0)
1066*4882a593Smuzhiyun 		return irq;
1067*4882a593Smuzhiyun 
1068*4882a593Smuzhiyun 	/* setup net_device */
1069*4882a593Smuzhiyun 	netdev = alloc_etherdev(sizeof(*priv));
1070*4882a593Smuzhiyun 	if (!netdev) {
1071*4882a593Smuzhiyun 		err = -ENOMEM;
1072*4882a593Smuzhiyun 		goto err_alloc_etherdev;
1073*4882a593Smuzhiyun 	}
1074*4882a593Smuzhiyun 
1075*4882a593Smuzhiyun 	SET_NETDEV_DEV(netdev, &pdev->dev);
1076*4882a593Smuzhiyun 	netdev->ethtool_ops = &ftmac100_ethtool_ops;
1077*4882a593Smuzhiyun 	netdev->netdev_ops = &ftmac100_netdev_ops;
1078*4882a593Smuzhiyun 
1079*4882a593Smuzhiyun 	platform_set_drvdata(pdev, netdev);
1080*4882a593Smuzhiyun 
1081*4882a593Smuzhiyun 	/* setup private data */
1082*4882a593Smuzhiyun 	priv = netdev_priv(netdev);
1083*4882a593Smuzhiyun 	priv->netdev = netdev;
1084*4882a593Smuzhiyun 	priv->dev = &pdev->dev;
1085*4882a593Smuzhiyun 
1086*4882a593Smuzhiyun 	spin_lock_init(&priv->tx_lock);
1087*4882a593Smuzhiyun 
1088*4882a593Smuzhiyun 	/* initialize NAPI */
1089*4882a593Smuzhiyun 	netif_napi_add(netdev, &priv->napi, ftmac100_poll, 64);
1090*4882a593Smuzhiyun 
1091*4882a593Smuzhiyun 	/* map io memory */
1092*4882a593Smuzhiyun 	priv->res = request_mem_region(res->start, resource_size(res),
1093*4882a593Smuzhiyun 				       dev_name(&pdev->dev));
1094*4882a593Smuzhiyun 	if (!priv->res) {
1095*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Could not reserve memory region\n");
1096*4882a593Smuzhiyun 		err = -ENOMEM;
1097*4882a593Smuzhiyun 		goto err_req_mem;
1098*4882a593Smuzhiyun 	}
1099*4882a593Smuzhiyun 
1100*4882a593Smuzhiyun 	priv->base = ioremap(res->start, resource_size(res));
1101*4882a593Smuzhiyun 	if (!priv->base) {
1102*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
1103*4882a593Smuzhiyun 		err = -EIO;
1104*4882a593Smuzhiyun 		goto err_ioremap;
1105*4882a593Smuzhiyun 	}
1106*4882a593Smuzhiyun 
1107*4882a593Smuzhiyun 	priv->irq = irq;
1108*4882a593Smuzhiyun 
1109*4882a593Smuzhiyun 	/* initialize struct mii_if_info */
1110*4882a593Smuzhiyun 	priv->mii.phy_id	= 0;
1111*4882a593Smuzhiyun 	priv->mii.phy_id_mask	= 0x1f;
1112*4882a593Smuzhiyun 	priv->mii.reg_num_mask	= 0x1f;
1113*4882a593Smuzhiyun 	priv->mii.dev		= netdev;
1114*4882a593Smuzhiyun 	priv->mii.mdio_read	= ftmac100_mdio_read;
1115*4882a593Smuzhiyun 	priv->mii.mdio_write	= ftmac100_mdio_write;
1116*4882a593Smuzhiyun 
1117*4882a593Smuzhiyun 	/* register network device */
1118*4882a593Smuzhiyun 	err = register_netdev(netdev);
1119*4882a593Smuzhiyun 	if (err) {
1120*4882a593Smuzhiyun 		dev_err(&pdev->dev, "Failed to register netdev\n");
1121*4882a593Smuzhiyun 		goto err_register_netdev;
1122*4882a593Smuzhiyun 	}
1123*4882a593Smuzhiyun 
1124*4882a593Smuzhiyun 	netdev_info(netdev, "irq %d, mapped at %p\n", priv->irq, priv->base);
1125*4882a593Smuzhiyun 
1126*4882a593Smuzhiyun 	if (!is_valid_ether_addr(netdev->dev_addr)) {
1127*4882a593Smuzhiyun 		eth_hw_addr_random(netdev);
1128*4882a593Smuzhiyun 		netdev_info(netdev, "generated random MAC address %pM\n",
1129*4882a593Smuzhiyun 			    netdev->dev_addr);
1130*4882a593Smuzhiyun 	}
1131*4882a593Smuzhiyun 
1132*4882a593Smuzhiyun 	return 0;
1133*4882a593Smuzhiyun 
1134*4882a593Smuzhiyun err_register_netdev:
1135*4882a593Smuzhiyun 	iounmap(priv->base);
1136*4882a593Smuzhiyun err_ioremap:
1137*4882a593Smuzhiyun 	release_resource(priv->res);
1138*4882a593Smuzhiyun err_req_mem:
1139*4882a593Smuzhiyun 	netif_napi_del(&priv->napi);
1140*4882a593Smuzhiyun 	free_netdev(netdev);
1141*4882a593Smuzhiyun err_alloc_etherdev:
1142*4882a593Smuzhiyun 	return err;
1143*4882a593Smuzhiyun }
1144*4882a593Smuzhiyun 
ftmac100_remove(struct platform_device * pdev)1145*4882a593Smuzhiyun static int ftmac100_remove(struct platform_device *pdev)
1146*4882a593Smuzhiyun {
1147*4882a593Smuzhiyun 	struct net_device *netdev;
1148*4882a593Smuzhiyun 	struct ftmac100 *priv;
1149*4882a593Smuzhiyun 
1150*4882a593Smuzhiyun 	netdev = platform_get_drvdata(pdev);
1151*4882a593Smuzhiyun 	priv = netdev_priv(netdev);
1152*4882a593Smuzhiyun 
1153*4882a593Smuzhiyun 	unregister_netdev(netdev);
1154*4882a593Smuzhiyun 
1155*4882a593Smuzhiyun 	iounmap(priv->base);
1156*4882a593Smuzhiyun 	release_resource(priv->res);
1157*4882a593Smuzhiyun 
1158*4882a593Smuzhiyun 	netif_napi_del(&priv->napi);
1159*4882a593Smuzhiyun 	free_netdev(netdev);
1160*4882a593Smuzhiyun 	return 0;
1161*4882a593Smuzhiyun }
1162*4882a593Smuzhiyun 
1163*4882a593Smuzhiyun static const struct of_device_id ftmac100_of_ids[] = {
1164*4882a593Smuzhiyun 	{ .compatible = "andestech,atmac100" },
1165*4882a593Smuzhiyun 	{ }
1166*4882a593Smuzhiyun };
1167*4882a593Smuzhiyun 
1168*4882a593Smuzhiyun static struct platform_driver ftmac100_driver = {
1169*4882a593Smuzhiyun 	.probe		= ftmac100_probe,
1170*4882a593Smuzhiyun 	.remove		= ftmac100_remove,
1171*4882a593Smuzhiyun 	.driver		= {
1172*4882a593Smuzhiyun 		.name	= DRV_NAME,
1173*4882a593Smuzhiyun 		.of_match_table = ftmac100_of_ids
1174*4882a593Smuzhiyun 	},
1175*4882a593Smuzhiyun };
1176*4882a593Smuzhiyun 
1177*4882a593Smuzhiyun /******************************************************************************
1178*4882a593Smuzhiyun  * initialization / finalization
1179*4882a593Smuzhiyun  *****************************************************************************/
ftmac100_init(void)1180*4882a593Smuzhiyun static int __init ftmac100_init(void)
1181*4882a593Smuzhiyun {
1182*4882a593Smuzhiyun 	return platform_driver_register(&ftmac100_driver);
1183*4882a593Smuzhiyun }
1184*4882a593Smuzhiyun 
ftmac100_exit(void)1185*4882a593Smuzhiyun static void __exit ftmac100_exit(void)
1186*4882a593Smuzhiyun {
1187*4882a593Smuzhiyun 	platform_driver_unregister(&ftmac100_driver);
1188*4882a593Smuzhiyun }
1189*4882a593Smuzhiyun 
1190*4882a593Smuzhiyun module_init(ftmac100_init);
1191*4882a593Smuzhiyun module_exit(ftmac100_exit);
1192*4882a593Smuzhiyun 
1193*4882a593Smuzhiyun MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
1194*4882a593Smuzhiyun MODULE_DESCRIPTION("FTMAC100 driver");
1195*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1196*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ftmac100_of_ids);
1197