xref: /OK3568_Linux_fs/kernel/drivers/net/ethernet/emulex/benet/be.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2005 - 2016 Broadcom
4*4882a593Smuzhiyun  * All rights reserved.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Contact Information:
7*4882a593Smuzhiyun  * linux-drivers@emulex.com
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * Emulex
10*4882a593Smuzhiyun  * 3333 Susan Street
11*4882a593Smuzhiyun  * Costa Mesa, CA 92626
12*4882a593Smuzhiyun  */
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #ifndef BE_H
15*4882a593Smuzhiyun #define BE_H
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include <linux/pci.h>
18*4882a593Smuzhiyun #include <linux/etherdevice.h>
19*4882a593Smuzhiyun #include <linux/delay.h>
20*4882a593Smuzhiyun #include <net/tcp.h>
21*4882a593Smuzhiyun #include <net/ip.h>
22*4882a593Smuzhiyun #include <net/ipv6.h>
23*4882a593Smuzhiyun #include <linux/if_vlan.h>
24*4882a593Smuzhiyun #include <linux/workqueue.h>
25*4882a593Smuzhiyun #include <linux/interrupt.h>
26*4882a593Smuzhiyun #include <linux/firmware.h>
27*4882a593Smuzhiyun #include <linux/slab.h>
28*4882a593Smuzhiyun #include <linux/u64_stats_sync.h>
29*4882a593Smuzhiyun #include <linux/cpumask.h>
30*4882a593Smuzhiyun #include <linux/hwmon.h>
31*4882a593Smuzhiyun #include <linux/hwmon-sysfs.h>
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #include "be_hw.h"
34*4882a593Smuzhiyun #include "be_roce.h"
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define DRV_NAME		"be2net"
37*4882a593Smuzhiyun #define BE_NAME			"Emulex BladeEngine2"
38*4882a593Smuzhiyun #define BE3_NAME		"Emulex BladeEngine3"
39*4882a593Smuzhiyun #define OC_NAME			"Emulex OneConnect"
40*4882a593Smuzhiyun #define OC_NAME_BE		OC_NAME	"(be3)"
41*4882a593Smuzhiyun #define OC_NAME_LANCER		OC_NAME "(Lancer)"
42*4882a593Smuzhiyun #define OC_NAME_SH		OC_NAME "(Skyhawk)"
43*4882a593Smuzhiyun #define DRV_DESC		"Emulex OneConnect NIC Driver"
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun #define BE_VENDOR_ID 		0x19a2
46*4882a593Smuzhiyun #define EMULEX_VENDOR_ID	0x10df
47*4882a593Smuzhiyun #define BE_DEVICE_ID1		0x211
48*4882a593Smuzhiyun #define BE_DEVICE_ID2		0x221
49*4882a593Smuzhiyun #define OC_DEVICE_ID1		0x700	/* Device Id for BE2 cards */
50*4882a593Smuzhiyun #define OC_DEVICE_ID2		0x710	/* Device Id for BE3 cards */
51*4882a593Smuzhiyun #define OC_DEVICE_ID3		0xe220	/* Device id for Lancer cards */
52*4882a593Smuzhiyun #define OC_DEVICE_ID4           0xe228   /* Device id for VF in Lancer */
53*4882a593Smuzhiyun #define OC_DEVICE_ID5		0x720	/* Device Id for Skyhawk cards */
54*4882a593Smuzhiyun #define OC_DEVICE_ID6		0x728   /* Device id for VF in SkyHawk */
55*4882a593Smuzhiyun #define OC_SUBSYS_DEVICE_ID1	0xE602
56*4882a593Smuzhiyun #define OC_SUBSYS_DEVICE_ID2	0xE642
57*4882a593Smuzhiyun #define OC_SUBSYS_DEVICE_ID3	0xE612
58*4882a593Smuzhiyun #define OC_SUBSYS_DEVICE_ID4	0xE652
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun /* Number of bytes of an RX frame that are copied to skb->data */
61*4882a593Smuzhiyun #define BE_HDR_LEN		((u16) 64)
62*4882a593Smuzhiyun /* allocate extra space to allow tunneling decapsulation without head reallocation */
63*4882a593Smuzhiyun #define BE_RX_SKB_ALLOC_SIZE	256
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun #define BE_MAX_JUMBO_FRAME_SIZE	9018
66*4882a593Smuzhiyun #define BE_MIN_MTU		256
67*4882a593Smuzhiyun #define BE_MAX_MTU              (BE_MAX_JUMBO_FRAME_SIZE -	\
68*4882a593Smuzhiyun 				 (ETH_HLEN + ETH_FCS_LEN))
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun /* Accommodate for QnQ configurations where VLAN insertion is enabled in HW */
71*4882a593Smuzhiyun #define BE_MAX_GSO_SIZE		(65535 - 2 * VLAN_HLEN)
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun #define BE_NUM_VLANS_SUPPORTED	64
74*4882a593Smuzhiyun #define BE_MAX_EQD		128u
75*4882a593Smuzhiyun #define	BE_MAX_TX_FRAG_COUNT	30
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun #define EVNT_Q_LEN		1024
78*4882a593Smuzhiyun #define TX_Q_LEN		2048
79*4882a593Smuzhiyun #define TX_CQ_LEN		1024
80*4882a593Smuzhiyun #define RX_Q_LEN		1024	/* Does not support any other value */
81*4882a593Smuzhiyun #define RX_CQ_LEN		1024
82*4882a593Smuzhiyun #define MCC_Q_LEN		128	/* total size not to exceed 8 pages */
83*4882a593Smuzhiyun #define MCC_CQ_LEN		256
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun #define BE2_MAX_RSS_QS		4
86*4882a593Smuzhiyun #define BE3_MAX_RSS_QS		16
87*4882a593Smuzhiyun #define BE3_MAX_TX_QS		16
88*4882a593Smuzhiyun #define BE3_MAX_EVT_QS		16
89*4882a593Smuzhiyun #define BE3_SRIOV_MAX_EVT_QS	8
90*4882a593Smuzhiyun #define SH_VF_MAX_NIC_EQS	3	/* Skyhawk VFs can have a max of 4 EQs
91*4882a593Smuzhiyun 					 * and at least 1 is granted to either
92*4882a593Smuzhiyun 					 * SURF/DPDK
93*4882a593Smuzhiyun 					 */
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun #define MAX_PORT_RSS_TABLES	15
96*4882a593Smuzhiyun #define MAX_NIC_FUNCS		16
97*4882a593Smuzhiyun #define MAX_RX_QS		32
98*4882a593Smuzhiyun #define MAX_EVT_QS		32
99*4882a593Smuzhiyun #define MAX_TX_QS		32
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun #define MAX_ROCE_EQS		5
102*4882a593Smuzhiyun #define MAX_MSIX_VECTORS	32
103*4882a593Smuzhiyun #define MIN_MSIX_VECTORS	1
104*4882a593Smuzhiyun #define BE_NAPI_WEIGHT		64
105*4882a593Smuzhiyun #define MAX_RX_POST		BE_NAPI_WEIGHT /* Frags posted at a time */
106*4882a593Smuzhiyun #define RX_FRAGS_REFILL_WM	(RX_Q_LEN - MAX_RX_POST)
107*4882a593Smuzhiyun #define MAX_NUM_POST_ERX_DB	255u
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun #define MAX_VFS			30 /* Max VFs supported by BE3 FW */
110*4882a593Smuzhiyun #define FW_VER_LEN		32
111*4882a593Smuzhiyun #define	CNTL_SERIAL_NUM_WORDS	8  /* Controller serial number words */
112*4882a593Smuzhiyun #define	CNTL_SERIAL_NUM_WORD_SZ	(sizeof(u16)) /* Byte-sz of serial num word */
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun #define	RSS_INDIR_TABLE_LEN	128
115*4882a593Smuzhiyun #define RSS_HASH_KEY_LEN	40
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun #define BE_UNKNOWN_PHY_STATE	0xFF
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun struct be_dma_mem {
120*4882a593Smuzhiyun 	void *va;
121*4882a593Smuzhiyun 	dma_addr_t dma;
122*4882a593Smuzhiyun 	u32 size;
123*4882a593Smuzhiyun };
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun struct be_queue_info {
126*4882a593Smuzhiyun 	u32 len;
127*4882a593Smuzhiyun 	u32 entry_size;	/* Size of an element in the queue */
128*4882a593Smuzhiyun 	u32 tail, head;
129*4882a593Smuzhiyun 	atomic_t used;	/* Number of valid elements in the queue */
130*4882a593Smuzhiyun 	u32 id;
131*4882a593Smuzhiyun 	struct be_dma_mem dma_mem;
132*4882a593Smuzhiyun 	bool created;
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun 
MODULO(u32 val,u32 limit)135*4882a593Smuzhiyun static inline u32 MODULO(u32 val, u32 limit)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun 	BUG_ON(limit & (limit - 1));
138*4882a593Smuzhiyun 	return val & (limit - 1);
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun 
index_adv(u32 * index,u32 val,u32 limit)141*4882a593Smuzhiyun static inline void index_adv(u32 *index, u32 val, u32 limit)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun 	*index = MODULO((*index + val), limit);
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun 
index_inc(u32 * index,u32 limit)146*4882a593Smuzhiyun static inline void index_inc(u32 *index, u32 limit)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun 	*index = MODULO((*index + 1), limit);
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun 
queue_head_node(struct be_queue_info * q)151*4882a593Smuzhiyun static inline void *queue_head_node(struct be_queue_info *q)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun 	return q->dma_mem.va + q->head * q->entry_size;
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun 
queue_tail_node(struct be_queue_info * q)156*4882a593Smuzhiyun static inline void *queue_tail_node(struct be_queue_info *q)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun 	return q->dma_mem.va + q->tail * q->entry_size;
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun 
queue_index_node(struct be_queue_info * q,u16 index)161*4882a593Smuzhiyun static inline void *queue_index_node(struct be_queue_info *q, u16 index)
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun 	return q->dma_mem.va + index * q->entry_size;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun 
queue_head_inc(struct be_queue_info * q)166*4882a593Smuzhiyun static inline void queue_head_inc(struct be_queue_info *q)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun 	index_inc(&q->head, q->len);
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun 
index_dec(u32 * index,u32 limit)171*4882a593Smuzhiyun static inline void index_dec(u32 *index, u32 limit)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun 	*index = MODULO((*index - 1), limit);
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun 
queue_tail_inc(struct be_queue_info * q)176*4882a593Smuzhiyun static inline void queue_tail_inc(struct be_queue_info *q)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun 	index_inc(&q->tail, q->len);
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun struct be_eq_obj {
182*4882a593Smuzhiyun 	struct be_queue_info q;
183*4882a593Smuzhiyun 	char desc[32];
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	struct be_adapter *adapter;
186*4882a593Smuzhiyun 	struct napi_struct napi;
187*4882a593Smuzhiyun 	u8 idx;			/* array index */
188*4882a593Smuzhiyun 	u8 msix_idx;
189*4882a593Smuzhiyun 	u16 spurious_intr;
190*4882a593Smuzhiyun 	cpumask_var_t  affinity_mask;
191*4882a593Smuzhiyun } ____cacheline_aligned_in_smp;
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun struct be_aic_obj {		/* Adaptive interrupt coalescing (AIC) info */
194*4882a593Smuzhiyun 	u32 min_eqd;		/* in usecs */
195*4882a593Smuzhiyun 	u32 max_eqd;		/* in usecs */
196*4882a593Smuzhiyun 	u32 prev_eqd;		/* in usecs */
197*4882a593Smuzhiyun 	u32 et_eqd;		/* configured val when aic is off */
198*4882a593Smuzhiyun 	ulong jiffies;
199*4882a593Smuzhiyun 	u64 rx_pkts_prev;	/* Used to calculate RX pps */
200*4882a593Smuzhiyun 	u64 tx_reqs_prev;	/* Used to calculate TX pps */
201*4882a593Smuzhiyun };
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun struct be_mcc_obj {
204*4882a593Smuzhiyun 	struct be_queue_info q;
205*4882a593Smuzhiyun 	struct be_queue_info cq;
206*4882a593Smuzhiyun 	bool rearm_cq;
207*4882a593Smuzhiyun };
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun struct be_tx_stats {
210*4882a593Smuzhiyun 	u64 tx_bytes;
211*4882a593Smuzhiyun 	u64 tx_pkts;
212*4882a593Smuzhiyun 	u64 tx_vxlan_offload_pkts;
213*4882a593Smuzhiyun 	u64 tx_reqs;
214*4882a593Smuzhiyun 	u64 tx_compl;
215*4882a593Smuzhiyun 	u32 tx_stops;
216*4882a593Smuzhiyun 	u32 tx_drv_drops;	/* pkts dropped by driver */
217*4882a593Smuzhiyun 	/* the error counters are described in be_ethtool.c */
218*4882a593Smuzhiyun 	u32 tx_hdr_parse_err;
219*4882a593Smuzhiyun 	u32 tx_dma_err;
220*4882a593Smuzhiyun 	u32 tx_tso_err;
221*4882a593Smuzhiyun 	u32 tx_spoof_check_err;
222*4882a593Smuzhiyun 	u32 tx_qinq_err;
223*4882a593Smuzhiyun 	u32 tx_internal_parity_err;
224*4882a593Smuzhiyun 	u32 tx_sge_err;
225*4882a593Smuzhiyun 	struct u64_stats_sync sync;
226*4882a593Smuzhiyun 	struct u64_stats_sync sync_compl;
227*4882a593Smuzhiyun };
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun /* Structure to hold some data of interest obtained from a TX CQE */
230*4882a593Smuzhiyun struct be_tx_compl_info {
231*4882a593Smuzhiyun 	u8 status;		/* Completion status */
232*4882a593Smuzhiyun 	u16 end_index;		/* Completed TXQ Index */
233*4882a593Smuzhiyun };
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun struct be_tx_obj {
236*4882a593Smuzhiyun 	u32 db_offset;
237*4882a593Smuzhiyun 	struct be_tx_compl_info txcp;
238*4882a593Smuzhiyun 	struct be_queue_info q;
239*4882a593Smuzhiyun 	struct be_queue_info cq;
240*4882a593Smuzhiyun 	/* Remember the skbs that were transmitted */
241*4882a593Smuzhiyun 	struct sk_buff *sent_skb_list[TX_Q_LEN];
242*4882a593Smuzhiyun 	struct be_tx_stats stats;
243*4882a593Smuzhiyun 	u16 pend_wrb_cnt;	/* Number of WRBs yet to be given to HW */
244*4882a593Smuzhiyun 	u16 last_req_wrb_cnt;	/* wrb cnt of the last req in the Q */
245*4882a593Smuzhiyun 	u16 last_req_hdr;	/* index of the last req's hdr-wrb */
246*4882a593Smuzhiyun } ____cacheline_aligned_in_smp;
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun /* Struct to remember the pages posted for rx frags */
249*4882a593Smuzhiyun struct be_rx_page_info {
250*4882a593Smuzhiyun 	struct page *page;
251*4882a593Smuzhiyun 	/* set to page-addr for last frag of the page & frag-addr otherwise */
252*4882a593Smuzhiyun 	DEFINE_DMA_UNMAP_ADDR(bus);
253*4882a593Smuzhiyun 	u16 page_offset;
254*4882a593Smuzhiyun 	bool last_frag;		/* last frag of the page */
255*4882a593Smuzhiyun };
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun struct be_rx_stats {
258*4882a593Smuzhiyun 	u64 rx_bytes;
259*4882a593Smuzhiyun 	u64 rx_pkts;
260*4882a593Smuzhiyun 	u64 rx_vxlan_offload_pkts;
261*4882a593Smuzhiyun 	u32 rx_drops_no_skbs;	/* skb allocation errors */
262*4882a593Smuzhiyun 	u32 rx_drops_no_frags;	/* HW has no fetched frags */
263*4882a593Smuzhiyun 	u32 rx_post_fail;	/* page post alloc failures */
264*4882a593Smuzhiyun 	u32 rx_compl;
265*4882a593Smuzhiyun 	u32 rx_mcast_pkts;
266*4882a593Smuzhiyun 	u32 rx_compl_err;	/* completions with err set */
267*4882a593Smuzhiyun 	struct u64_stats_sync sync;
268*4882a593Smuzhiyun };
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun struct be_rx_compl_info {
271*4882a593Smuzhiyun 	u32 rss_hash;
272*4882a593Smuzhiyun 	u16 vlan_tag;
273*4882a593Smuzhiyun 	u16 pkt_size;
274*4882a593Smuzhiyun 	u16 port;
275*4882a593Smuzhiyun 	u8 vlanf;
276*4882a593Smuzhiyun 	u8 num_rcvd;
277*4882a593Smuzhiyun 	u8 err;
278*4882a593Smuzhiyun 	u8 ipf;
279*4882a593Smuzhiyun 	u8 tcpf;
280*4882a593Smuzhiyun 	u8 udpf;
281*4882a593Smuzhiyun 	u8 ip_csum;
282*4882a593Smuzhiyun 	u8 l4_csum;
283*4882a593Smuzhiyun 	u8 ipv6;
284*4882a593Smuzhiyun 	u8 qnq;
285*4882a593Smuzhiyun 	u8 pkt_type;
286*4882a593Smuzhiyun 	u8 ip_frag;
287*4882a593Smuzhiyun 	u8 tunneled;
288*4882a593Smuzhiyun };
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun struct be_rx_obj {
291*4882a593Smuzhiyun 	struct be_adapter *adapter;
292*4882a593Smuzhiyun 	struct be_queue_info q;
293*4882a593Smuzhiyun 	struct be_queue_info cq;
294*4882a593Smuzhiyun 	struct be_rx_compl_info rxcp;
295*4882a593Smuzhiyun 	struct be_rx_page_info page_info_tbl[RX_Q_LEN];
296*4882a593Smuzhiyun 	struct be_rx_stats stats;
297*4882a593Smuzhiyun 	u8 rss_id;
298*4882a593Smuzhiyun 	bool rx_post_starved;	/* Zero rx frags have been posted to BE */
299*4882a593Smuzhiyun } ____cacheline_aligned_in_smp;
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun struct be_drv_stats {
302*4882a593Smuzhiyun 	u32 eth_red_drops;
303*4882a593Smuzhiyun 	u32 dma_map_errors;
304*4882a593Smuzhiyun 	u32 rx_drops_no_pbuf;
305*4882a593Smuzhiyun 	u32 rx_drops_no_txpb;
306*4882a593Smuzhiyun 	u32 rx_drops_no_erx_descr;
307*4882a593Smuzhiyun 	u32 rx_drops_no_tpre_descr;
308*4882a593Smuzhiyun 	u32 rx_drops_too_many_frags;
309*4882a593Smuzhiyun 	u32 forwarded_packets;
310*4882a593Smuzhiyun 	u32 rx_drops_mtu;
311*4882a593Smuzhiyun 	u32 rx_crc_errors;
312*4882a593Smuzhiyun 	u32 rx_alignment_symbol_errors;
313*4882a593Smuzhiyun 	u32 rx_pause_frames;
314*4882a593Smuzhiyun 	u32 rx_priority_pause_frames;
315*4882a593Smuzhiyun 	u32 rx_control_frames;
316*4882a593Smuzhiyun 	u32 rx_in_range_errors;
317*4882a593Smuzhiyun 	u32 rx_out_range_errors;
318*4882a593Smuzhiyun 	u32 rx_frame_too_long;
319*4882a593Smuzhiyun 	u32 rx_address_filtered;
320*4882a593Smuzhiyun 	u32 rx_dropped_too_small;
321*4882a593Smuzhiyun 	u32 rx_dropped_too_short;
322*4882a593Smuzhiyun 	u32 rx_dropped_header_too_small;
323*4882a593Smuzhiyun 	u32 rx_dropped_tcp_length;
324*4882a593Smuzhiyun 	u32 rx_dropped_runt;
325*4882a593Smuzhiyun 	u32 rx_ip_checksum_errs;
326*4882a593Smuzhiyun 	u32 rx_tcp_checksum_errs;
327*4882a593Smuzhiyun 	u32 rx_udp_checksum_errs;
328*4882a593Smuzhiyun 	u32 tx_pauseframes;
329*4882a593Smuzhiyun 	u32 tx_priority_pauseframes;
330*4882a593Smuzhiyun 	u32 tx_controlframes;
331*4882a593Smuzhiyun 	u32 rxpp_fifo_overflow_drop;
332*4882a593Smuzhiyun 	u32 rx_input_fifo_overflow_drop;
333*4882a593Smuzhiyun 	u32 pmem_fifo_overflow_drop;
334*4882a593Smuzhiyun 	u32 jabber_events;
335*4882a593Smuzhiyun 	u32 rx_roce_bytes_lsd;
336*4882a593Smuzhiyun 	u32 rx_roce_bytes_msd;
337*4882a593Smuzhiyun 	u32 rx_roce_frames;
338*4882a593Smuzhiyun 	u32 roce_drops_payload_len;
339*4882a593Smuzhiyun 	u32 roce_drops_crc;
340*4882a593Smuzhiyun };
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun /* A vlan-id of 0xFFFF must be used to clear transparent vlan-tagging */
343*4882a593Smuzhiyun #define BE_RESET_VLAN_TAG_ID	0xFFFF
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun struct be_vf_cfg {
346*4882a593Smuzhiyun 	unsigned char mac_addr[ETH_ALEN];
347*4882a593Smuzhiyun 	int if_handle;
348*4882a593Smuzhiyun 	int pmac_id;
349*4882a593Smuzhiyun 	u16 vlan_tag;
350*4882a593Smuzhiyun 	u32 tx_rate;
351*4882a593Smuzhiyun 	u32 plink_tracking;
352*4882a593Smuzhiyun 	u32 privileges;
353*4882a593Smuzhiyun 	bool spoofchk;
354*4882a593Smuzhiyun };
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun enum vf_state {
357*4882a593Smuzhiyun 	ENABLED = 0,
358*4882a593Smuzhiyun 	ASSIGNED = 1
359*4882a593Smuzhiyun };
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun #define BE_FLAGS_LINK_STATUS_INIT		BIT(1)
362*4882a593Smuzhiyun #define BE_FLAGS_SRIOV_ENABLED			BIT(2)
363*4882a593Smuzhiyun #define BE_FLAGS_WORKER_SCHEDULED		BIT(3)
364*4882a593Smuzhiyun #define BE_FLAGS_NAPI_ENABLED			BIT(6)
365*4882a593Smuzhiyun #define BE_FLAGS_QNQ_ASYNC_EVT_RCVD		BIT(7)
366*4882a593Smuzhiyun #define BE_FLAGS_VXLAN_OFFLOADS			BIT(8)
367*4882a593Smuzhiyun #define BE_FLAGS_SETUP_DONE			BIT(9)
368*4882a593Smuzhiyun #define BE_FLAGS_PHY_MISCONFIGURED		BIT(10)
369*4882a593Smuzhiyun #define BE_FLAGS_ERR_DETECTION_SCHEDULED	BIT(11)
370*4882a593Smuzhiyun #define BE_FLAGS_OS2BMC				BIT(12)
371*4882a593Smuzhiyun #define BE_FLAGS_TRY_RECOVERY			BIT(13)
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun #define BE_UC_PMAC_COUNT			30
374*4882a593Smuzhiyun #define BE_VF_UC_PMAC_COUNT			2
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun #define MAX_ERR_RECOVERY_RETRY_COUNT		3
377*4882a593Smuzhiyun #define ERR_DETECTION_DELAY			1000
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun /* Ethtool set_dump flags */
380*4882a593Smuzhiyun #define LANCER_INITIATE_FW_DUMP			0x1
381*4882a593Smuzhiyun #define LANCER_DELETE_FW_DUMP			0x2
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun struct phy_info {
384*4882a593Smuzhiyun /* From SFF-8472 spec */
385*4882a593Smuzhiyun #define SFP_VENDOR_NAME_LEN			17
386*4882a593Smuzhiyun 	u8 transceiver;
387*4882a593Smuzhiyun 	u8 autoneg;
388*4882a593Smuzhiyun 	u8 fc_autoneg;
389*4882a593Smuzhiyun 	u8 port_type;
390*4882a593Smuzhiyun 	u16 phy_type;
391*4882a593Smuzhiyun 	u16 interface_type;
392*4882a593Smuzhiyun 	u32 misc_params;
393*4882a593Smuzhiyun 	u16 auto_speeds_supported;
394*4882a593Smuzhiyun 	u16 fixed_speeds_supported;
395*4882a593Smuzhiyun 	int link_speed;
396*4882a593Smuzhiyun 	u32 advertising;
397*4882a593Smuzhiyun 	u32 supported;
398*4882a593Smuzhiyun 	u8 cable_type;
399*4882a593Smuzhiyun 	u8 vendor_name[SFP_VENDOR_NAME_LEN];
400*4882a593Smuzhiyun 	u8 vendor_pn[SFP_VENDOR_NAME_LEN];
401*4882a593Smuzhiyun };
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun struct be_resources {
404*4882a593Smuzhiyun 	u16 max_vfs;		/* Total VFs "really" supported by FW/HW */
405*4882a593Smuzhiyun 	u16 max_mcast_mac;
406*4882a593Smuzhiyun 	u16 max_tx_qs;
407*4882a593Smuzhiyun 	u16 max_rss_qs;
408*4882a593Smuzhiyun 	u16 max_rx_qs;
409*4882a593Smuzhiyun 	u16 max_cq_count;
410*4882a593Smuzhiyun 	u16 max_uc_mac;		/* Max UC MACs programmable */
411*4882a593Smuzhiyun 	u16 max_vlans;		/* Number of vlans supported */
412*4882a593Smuzhiyun 	u16 max_iface_count;
413*4882a593Smuzhiyun 	u16 max_mcc_count;
414*4882a593Smuzhiyun 	u16 max_evt_qs;
415*4882a593Smuzhiyun 	u16 max_nic_evt_qs;	/* NIC's share of evt qs */
416*4882a593Smuzhiyun 	u32 if_cap_flags;
417*4882a593Smuzhiyun 	u32 vf_if_cap_flags;	/* VF if capability flags */
418*4882a593Smuzhiyun 	u32 flags;
419*4882a593Smuzhiyun 	/* Calculated PF Pool's share of RSS Tables. This is not enforced by
420*4882a593Smuzhiyun 	 * the FW, but is a self-imposed driver limitation.
421*4882a593Smuzhiyun 	 */
422*4882a593Smuzhiyun 	u16 max_rss_tables;
423*4882a593Smuzhiyun };
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun /* These are port-wide values */
426*4882a593Smuzhiyun struct be_port_resources {
427*4882a593Smuzhiyun 	u16 max_vfs;
428*4882a593Smuzhiyun 	u16 nic_pfs;
429*4882a593Smuzhiyun };
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun #define be_is_os2bmc_enabled(adapter) (adapter->flags & BE_FLAGS_OS2BMC)
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun struct rss_info {
434*4882a593Smuzhiyun 	u8 rsstable[RSS_INDIR_TABLE_LEN];
435*4882a593Smuzhiyun 	u8 rss_queue[RSS_INDIR_TABLE_LEN];
436*4882a593Smuzhiyun 	u8 rss_hkey[RSS_HASH_KEY_LEN];
437*4882a593Smuzhiyun 	u64 rss_flags;
438*4882a593Smuzhiyun };
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun #define BE_INVALID_DIE_TEMP	0xFF
441*4882a593Smuzhiyun struct be_hwmon {
442*4882a593Smuzhiyun 	struct device *hwmon_dev;
443*4882a593Smuzhiyun 	u8 be_on_die_temp;  /* Unit: millidegree Celsius */
444*4882a593Smuzhiyun };
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun /* Macros to read/write the 'features' word of be_wrb_params structure.
447*4882a593Smuzhiyun  */
448*4882a593Smuzhiyun #define	BE_WRB_F_BIT(name)			BE_WRB_F_##name##_BIT
449*4882a593Smuzhiyun #define	BE_WRB_F_MASK(name)			BIT_MASK(BE_WRB_F_##name##_BIT)
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun #define	BE_WRB_F_GET(word, name)	\
452*4882a593Smuzhiyun 	(((word) & (BE_WRB_F_MASK(name))) >> BE_WRB_F_BIT(name))
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun #define	BE_WRB_F_SET(word, name, val)	\
455*4882a593Smuzhiyun 	((word) |= (((val) << BE_WRB_F_BIT(name)) & BE_WRB_F_MASK(name)))
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun /* Feature/offload bits */
458*4882a593Smuzhiyun enum {
459*4882a593Smuzhiyun 	BE_WRB_F_CRC_BIT,		/* Ethernet CRC */
460*4882a593Smuzhiyun 	BE_WRB_F_IPCS_BIT,		/* IP csum */
461*4882a593Smuzhiyun 	BE_WRB_F_TCPCS_BIT,		/* TCP csum */
462*4882a593Smuzhiyun 	BE_WRB_F_UDPCS_BIT,		/* UDP csum */
463*4882a593Smuzhiyun 	BE_WRB_F_LSO_BIT,		/* LSO */
464*4882a593Smuzhiyun 	BE_WRB_F_LSO6_BIT,		/* LSO6 */
465*4882a593Smuzhiyun 	BE_WRB_F_VLAN_BIT,		/* VLAN */
466*4882a593Smuzhiyun 	BE_WRB_F_VLAN_SKIP_HW_BIT,	/* Skip VLAN tag (workaround) */
467*4882a593Smuzhiyun 	BE_WRB_F_OS2BMC_BIT		/* Send packet to the management ring */
468*4882a593Smuzhiyun };
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun /* The structure below provides a HW-agnostic abstraction of WRB params
471*4882a593Smuzhiyun  * retrieved from a TX skb. This is in turn passed to chip specific routines
472*4882a593Smuzhiyun  * during transmit, to set the corresponding params in the WRB.
473*4882a593Smuzhiyun  */
474*4882a593Smuzhiyun struct be_wrb_params {
475*4882a593Smuzhiyun 	u32 features;	/* Feature bits */
476*4882a593Smuzhiyun 	u16 vlan_tag;	/* VLAN tag */
477*4882a593Smuzhiyun 	u16 lso_mss;	/* MSS for LSO */
478*4882a593Smuzhiyun };
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun struct be_eth_addr {
481*4882a593Smuzhiyun 	unsigned char mac[ETH_ALEN];
482*4882a593Smuzhiyun };
483*4882a593Smuzhiyun 
484*4882a593Smuzhiyun #define BE_SEC	1000			/* in msec */
485*4882a593Smuzhiyun #define BE_MIN	(60 * BE_SEC)		/* in msec */
486*4882a593Smuzhiyun #define BE_HOUR	(60 * BE_MIN)		/* in msec */
487*4882a593Smuzhiyun 
488*4882a593Smuzhiyun #define ERR_RECOVERY_MAX_RETRY_COUNT		3
489*4882a593Smuzhiyun #define ERR_RECOVERY_DETECTION_DELAY		BE_SEC
490*4882a593Smuzhiyun #define ERR_RECOVERY_RETRY_DELAY		(30 * BE_SEC)
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun /* UE-detection-duration in BEx/Skyhawk:
493*4882a593Smuzhiyun  * All PFs must wait for this duration after they detect UE before reading
494*4882a593Smuzhiyun  * SLIPORT_SEMAPHORE register. At the end of this duration, the Firmware
495*4882a593Smuzhiyun  * guarantees that the SLIPORT_SEMAPHORE register is updated to indicate
496*4882a593Smuzhiyun  * if the UE is recoverable.
497*4882a593Smuzhiyun  */
498*4882a593Smuzhiyun #define ERR_RECOVERY_UE_DETECT_DURATION			BE_SEC
499*4882a593Smuzhiyun 
500*4882a593Smuzhiyun /* Initial idle time (in msec) to elapse after driver load,
501*4882a593Smuzhiyun  * before UE recovery is allowed.
502*4882a593Smuzhiyun  */
503*4882a593Smuzhiyun #define ERR_IDLE_HR			24
504*4882a593Smuzhiyun #define ERR_RECOVERY_IDLE_TIME		(ERR_IDLE_HR * BE_HOUR)
505*4882a593Smuzhiyun 
506*4882a593Smuzhiyun /* Time interval (in msec) after which UE recovery can be repeated */
507*4882a593Smuzhiyun #define ERR_INTERVAL_HR			72
508*4882a593Smuzhiyun #define ERR_RECOVERY_INTERVAL		(ERR_INTERVAL_HR * BE_HOUR)
509*4882a593Smuzhiyun 
510*4882a593Smuzhiyun /* BEx/SH UE recovery state machine */
511*4882a593Smuzhiyun enum {
512*4882a593Smuzhiyun 	ERR_RECOVERY_ST_NONE = 0,		/* No Recovery */
513*4882a593Smuzhiyun 	ERR_RECOVERY_ST_DETECT = 1,		/* UE detection duration */
514*4882a593Smuzhiyun 	ERR_RECOVERY_ST_RESET = 2,		/* Reset Phase (PF0 only) */
515*4882a593Smuzhiyun 	ERR_RECOVERY_ST_PRE_POLL = 3,		/* Pre-Poll Phase (all PFs) */
516*4882a593Smuzhiyun 	ERR_RECOVERY_ST_REINIT = 4		/* Re-initialize Phase */
517*4882a593Smuzhiyun };
518*4882a593Smuzhiyun 
519*4882a593Smuzhiyun struct be_error_recovery {
520*4882a593Smuzhiyun 	union {
521*4882a593Smuzhiyun 		u8 recovery_retries;	/* used for Lancer		*/
522*4882a593Smuzhiyun 		u8 recovery_state;	/* used for BEx and Skyhawk	*/
523*4882a593Smuzhiyun 	};
524*4882a593Smuzhiyun 
525*4882a593Smuzhiyun 	/* BEx/Skyhawk error recovery variables */
526*4882a593Smuzhiyun 	bool recovery_supported;
527*4882a593Smuzhiyun 	u16 ue_to_reset_time;		/* Time after UE, to soft reset
528*4882a593Smuzhiyun 					 * the chip - PF0 only
529*4882a593Smuzhiyun 					 */
530*4882a593Smuzhiyun 	u16 ue_to_poll_time;		/* Time after UE, to Restart Polling
531*4882a593Smuzhiyun 					 * of SLIPORT_SEMAPHORE reg
532*4882a593Smuzhiyun 					 */
533*4882a593Smuzhiyun 	u16 last_err_code;
534*4882a593Smuzhiyun 	unsigned long probe_time;
535*4882a593Smuzhiyun 	unsigned long last_recovery_time;
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun 	/* Common to both Lancer & BEx/SH error recovery */
538*4882a593Smuzhiyun 	u32 resched_delay;
539*4882a593Smuzhiyun 	struct delayed_work err_detection_work;
540*4882a593Smuzhiyun };
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun /* Ethtool priv_flags */
543*4882a593Smuzhiyun #define	BE_DISABLE_TPE_RECOVERY	0x1
544*4882a593Smuzhiyun 
545*4882a593Smuzhiyun struct be_vxlan_port {
546*4882a593Smuzhiyun 	struct list_head list;
547*4882a593Smuzhiyun 	__be16 port;		/* VxLAN UDP dst port */
548*4882a593Smuzhiyun 	int port_aliases;	/* alias count */
549*4882a593Smuzhiyun };
550*4882a593Smuzhiyun 
551*4882a593Smuzhiyun struct be_adapter {
552*4882a593Smuzhiyun 	struct pci_dev *pdev;
553*4882a593Smuzhiyun 	struct net_device *netdev;
554*4882a593Smuzhiyun 
555*4882a593Smuzhiyun 	u8 __iomem *csr;	/* CSR BAR used only for BE2/3 */
556*4882a593Smuzhiyun 	u8 __iomem *db;		/* Door Bell */
557*4882a593Smuzhiyun 	u8 __iomem *pcicfg;	/* On SH,BEx only. Shadow of PCI config space */
558*4882a593Smuzhiyun 
559*4882a593Smuzhiyun 	struct mutex mbox_lock; /* For serializing mbox cmds to BE card */
560*4882a593Smuzhiyun 	struct be_dma_mem mbox_mem;
561*4882a593Smuzhiyun 	/* Mbox mem is adjusted to align to 16 bytes. The allocated addr
562*4882a593Smuzhiyun 	 * is stored for freeing purpose */
563*4882a593Smuzhiyun 	struct be_dma_mem mbox_mem_alloced;
564*4882a593Smuzhiyun 
565*4882a593Smuzhiyun 	struct be_mcc_obj mcc_obj;
566*4882a593Smuzhiyun 	struct mutex mcc_lock;	/* For serializing mcc cmds to BE card */
567*4882a593Smuzhiyun 	spinlock_t mcc_cq_lock;
568*4882a593Smuzhiyun 
569*4882a593Smuzhiyun 	u16 cfg_num_rx_irqs;		/* configured via set-channels */
570*4882a593Smuzhiyun 	u16 cfg_num_tx_irqs;		/* configured via set-channels */
571*4882a593Smuzhiyun 	u16 num_evt_qs;
572*4882a593Smuzhiyun 	u16 num_msix_vec;
573*4882a593Smuzhiyun 	struct be_eq_obj eq_obj[MAX_EVT_QS];
574*4882a593Smuzhiyun 	struct msix_entry msix_entries[MAX_MSIX_VECTORS];
575*4882a593Smuzhiyun 	bool isr_registered;
576*4882a593Smuzhiyun 
577*4882a593Smuzhiyun 	/* TX Rings */
578*4882a593Smuzhiyun 	u16 num_tx_qs;
579*4882a593Smuzhiyun 	struct be_tx_obj tx_obj[MAX_TX_QS];
580*4882a593Smuzhiyun 
581*4882a593Smuzhiyun 	/* Rx rings */
582*4882a593Smuzhiyun 	u16 num_rx_qs;
583*4882a593Smuzhiyun 	u16 num_rss_qs;
584*4882a593Smuzhiyun 	u16 need_def_rxq;
585*4882a593Smuzhiyun 	struct be_rx_obj rx_obj[MAX_RX_QS];
586*4882a593Smuzhiyun 	u32 big_page_size;	/* Compounded page size shared by rx wrbs */
587*4882a593Smuzhiyun 
588*4882a593Smuzhiyun 	struct be_drv_stats drv_stats;
589*4882a593Smuzhiyun 	struct be_aic_obj aic_obj[MAX_EVT_QS];
590*4882a593Smuzhiyun 	bool aic_enabled;
591*4882a593Smuzhiyun 	u8 vlan_prio_bmap;	/* Available Priority BitMap */
592*4882a593Smuzhiyun 	u16 recommended_prio_bits;/* Recommended Priority bits in vlan tag */
593*4882a593Smuzhiyun 	struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */
594*4882a593Smuzhiyun 
595*4882a593Smuzhiyun 	struct be_dma_mem stats_cmd;
596*4882a593Smuzhiyun 	/* Work queue used to perform periodic tasks like getting statistics */
597*4882a593Smuzhiyun 	struct delayed_work work;
598*4882a593Smuzhiyun 	u16 work_counter;
599*4882a593Smuzhiyun 
600*4882a593Smuzhiyun 	u8 recovery_retries;
601*4882a593Smuzhiyun 	u8 err_flags;
602*4882a593Smuzhiyun 	bool pcicfg_mapped;	/* pcicfg obtained via pci_iomap() */
603*4882a593Smuzhiyun 	u32 flags;
604*4882a593Smuzhiyun 	u32 cmd_privileges;
605*4882a593Smuzhiyun 	/* Ethtool knobs and info */
606*4882a593Smuzhiyun 	char fw_ver[FW_VER_LEN];
607*4882a593Smuzhiyun 	char fw_on_flash[FW_VER_LEN];
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun 	/* IFACE filtering fields */
610*4882a593Smuzhiyun 	int if_handle;		/* Used to configure filtering */
611*4882a593Smuzhiyun 	u32 if_flags;		/* Interface filtering flags */
612*4882a593Smuzhiyun 	u32 *pmac_id;		/* MAC addr handle used by BE card */
613*4882a593Smuzhiyun 	struct be_eth_addr *uc_list;/* list of uc-addrs programmed (not perm) */
614*4882a593Smuzhiyun 	u32 uc_macs;		/* Count of secondary UC MAC programmed */
615*4882a593Smuzhiyun 	struct be_eth_addr *mc_list;/* list of mcast addrs programmed */
616*4882a593Smuzhiyun 	u32 mc_count;
617*4882a593Smuzhiyun 	unsigned long vids[BITS_TO_LONGS(VLAN_N_VID)];
618*4882a593Smuzhiyun 	u16 vlans_added;
619*4882a593Smuzhiyun 	bool update_uc_list;
620*4882a593Smuzhiyun 	bool update_mc_list;
621*4882a593Smuzhiyun 	struct mutex rx_filter_lock;/* For protecting vids[] & mc/uc_list[] */
622*4882a593Smuzhiyun 
623*4882a593Smuzhiyun 	u32 beacon_state;	/* for set_phys_id */
624*4882a593Smuzhiyun 
625*4882a593Smuzhiyun 	u32 port_num;
626*4882a593Smuzhiyun 	char port_name;
627*4882a593Smuzhiyun 	u8 mc_type;
628*4882a593Smuzhiyun 	u32 function_mode;
629*4882a593Smuzhiyun 	u32 function_caps;
630*4882a593Smuzhiyun 	u32 rx_fc;		/* Rx flow control */
631*4882a593Smuzhiyun 	u32 tx_fc;		/* Tx flow control */
632*4882a593Smuzhiyun 	bool stats_cmd_sent;
633*4882a593Smuzhiyun 	struct {
634*4882a593Smuzhiyun 		u32 size;
635*4882a593Smuzhiyun 		u32 total_size;
636*4882a593Smuzhiyun 		u64 io_addr;
637*4882a593Smuzhiyun 	} roce_db;
638*4882a593Smuzhiyun 	u32 num_msix_roce_vec;
639*4882a593Smuzhiyun 	struct ocrdma_dev *ocrdma_dev;
640*4882a593Smuzhiyun 	struct list_head entry;
641*4882a593Smuzhiyun 
642*4882a593Smuzhiyun 	u32 flash_status;
643*4882a593Smuzhiyun 	struct completion et_cmd_compl;
644*4882a593Smuzhiyun 
645*4882a593Smuzhiyun 	struct be_resources pool_res;	/* resources available for the port */
646*4882a593Smuzhiyun 	struct be_resources res;	/* resources available for the func */
647*4882a593Smuzhiyun 	u16 num_vfs;			/* Number of VFs provisioned by PF */
648*4882a593Smuzhiyun 	u8 pf_num;			/* Numbering used by FW, starts at 0 */
649*4882a593Smuzhiyun 	u8 vf_num;			/* Numbering used by FW, starts at 1 */
650*4882a593Smuzhiyun 	u8 virtfn;
651*4882a593Smuzhiyun 	struct be_vf_cfg *vf_cfg;
652*4882a593Smuzhiyun 	bool be3_native;
653*4882a593Smuzhiyun 	u32 sli_family;
654*4882a593Smuzhiyun 	u8 hba_port_num;
655*4882a593Smuzhiyun 	u16 pvid;
656*4882a593Smuzhiyun 	__be16 vxlan_port;		/* offloaded vxlan port num */
657*4882a593Smuzhiyun 	struct phy_info phy;
658*4882a593Smuzhiyun 	u8 wol_cap;
659*4882a593Smuzhiyun 	bool wol_en;
660*4882a593Smuzhiyun 	u16 asic_rev;
661*4882a593Smuzhiyun 	u16 qnq_vid;
662*4882a593Smuzhiyun 	u32 msg_enable;
663*4882a593Smuzhiyun 	int be_get_temp_freq;
664*4882a593Smuzhiyun 	struct be_hwmon hwmon_info;
665*4882a593Smuzhiyun 	struct rss_info rss_info;
666*4882a593Smuzhiyun 	/* Filters for packets that need to be sent to BMC */
667*4882a593Smuzhiyun 	u32 bmc_filt_mask;
668*4882a593Smuzhiyun 	u32 fat_dump_len;
669*4882a593Smuzhiyun 	u16 serial_num[CNTL_SERIAL_NUM_WORDS];
670*4882a593Smuzhiyun 	u8 phy_state; /* state of sfp optics (functional, faulted, etc.,) */
671*4882a593Smuzhiyun 	u8 dev_mac[ETH_ALEN];
672*4882a593Smuzhiyun 	u32 priv_flags; /* ethtool get/set_priv_flags() */
673*4882a593Smuzhiyun 	struct be_error_recovery error_recovery;
674*4882a593Smuzhiyun };
675*4882a593Smuzhiyun 
676*4882a593Smuzhiyun /* Used for defered FW config cmds. Add fields to this struct as reqd */
677*4882a593Smuzhiyun struct be_cmd_work {
678*4882a593Smuzhiyun 	struct work_struct work;
679*4882a593Smuzhiyun 	struct be_adapter *adapter;
680*4882a593Smuzhiyun };
681*4882a593Smuzhiyun 
682*4882a593Smuzhiyun #define be_physfn(adapter)		(!adapter->virtfn)
683*4882a593Smuzhiyun #define be_virtfn(adapter)		(adapter->virtfn)
684*4882a593Smuzhiyun #define sriov_enabled(adapter)		(adapter->flags &	\
685*4882a593Smuzhiyun 					 BE_FLAGS_SRIOV_ENABLED)
686*4882a593Smuzhiyun 
687*4882a593Smuzhiyun #define for_all_vfs(adapter, vf_cfg, i)					\
688*4882a593Smuzhiyun 	for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs;	\
689*4882a593Smuzhiyun 		i++, vf_cfg++)
690*4882a593Smuzhiyun 
691*4882a593Smuzhiyun #define ON				1
692*4882a593Smuzhiyun #define OFF				0
693*4882a593Smuzhiyun 
694*4882a593Smuzhiyun #define be_max_vlans(adapter)		(adapter->res.max_vlans)
695*4882a593Smuzhiyun #define be_max_uc(adapter)		(adapter->res.max_uc_mac)
696*4882a593Smuzhiyun #define be_max_mc(adapter)		(adapter->res.max_mcast_mac)
697*4882a593Smuzhiyun #define be_max_vfs(adapter)		(adapter->pool_res.max_vfs)
698*4882a593Smuzhiyun #define be_max_rss(adapter)		(adapter->res.max_rss_qs)
699*4882a593Smuzhiyun #define be_max_txqs(adapter)		(adapter->res.max_tx_qs)
700*4882a593Smuzhiyun #define be_max_prio_txqs(adapter)	(adapter->res.max_prio_tx_qs)
701*4882a593Smuzhiyun #define be_max_rxqs(adapter)		(adapter->res.max_rx_qs)
702*4882a593Smuzhiyun /* Max number of EQs available for the function (NIC + RoCE (if enabled)) */
703*4882a593Smuzhiyun #define be_max_func_eqs(adapter)	(adapter->res.max_evt_qs)
704*4882a593Smuzhiyun /* Max number of EQs available avaialble only for NIC */
705*4882a593Smuzhiyun #define be_max_nic_eqs(adapter)		(adapter->res.max_nic_evt_qs)
706*4882a593Smuzhiyun #define be_if_cap_flags(adapter)	(adapter->res.if_cap_flags)
707*4882a593Smuzhiyun #define be_max_pf_pool_rss_tables(adapter)	\
708*4882a593Smuzhiyun 				(adapter->pool_res.max_rss_tables)
709*4882a593Smuzhiyun /* Max irqs avaialble for NIC */
710*4882a593Smuzhiyun #define be_max_irqs(adapter)		\
711*4882a593Smuzhiyun 			(min_t(u16, be_max_nic_eqs(adapter), num_online_cpus()))
712*4882a593Smuzhiyun 
713*4882a593Smuzhiyun /* Max irqs *needed* for RX queues */
be_max_rx_irqs(struct be_adapter * adapter)714*4882a593Smuzhiyun static inline u16 be_max_rx_irqs(struct be_adapter *adapter)
715*4882a593Smuzhiyun {
716*4882a593Smuzhiyun 	/* If no RSS, need atleast one irq for def-RXQ */
717*4882a593Smuzhiyun 	u16 num = max_t(u16, be_max_rss(adapter), 1);
718*4882a593Smuzhiyun 
719*4882a593Smuzhiyun 	return min_t(u16, num, be_max_irqs(adapter));
720*4882a593Smuzhiyun }
721*4882a593Smuzhiyun 
722*4882a593Smuzhiyun /* Max irqs *needed* for TX queues */
be_max_tx_irqs(struct be_adapter * adapter)723*4882a593Smuzhiyun static inline u16 be_max_tx_irqs(struct be_adapter *adapter)
724*4882a593Smuzhiyun {
725*4882a593Smuzhiyun 	return min_t(u16, be_max_txqs(adapter), be_max_irqs(adapter));
726*4882a593Smuzhiyun }
727*4882a593Smuzhiyun 
728*4882a593Smuzhiyun /* Max irqs *needed* for combined queues */
be_max_qp_irqs(struct be_adapter * adapter)729*4882a593Smuzhiyun static inline u16 be_max_qp_irqs(struct be_adapter *adapter)
730*4882a593Smuzhiyun {
731*4882a593Smuzhiyun 	return min(be_max_tx_irqs(adapter), be_max_rx_irqs(adapter));
732*4882a593Smuzhiyun }
733*4882a593Smuzhiyun 
734*4882a593Smuzhiyun /* Max irqs *needed* for RX and TX queues together */
be_max_any_irqs(struct be_adapter * adapter)735*4882a593Smuzhiyun static inline u16 be_max_any_irqs(struct be_adapter *adapter)
736*4882a593Smuzhiyun {
737*4882a593Smuzhiyun 	return max(be_max_tx_irqs(adapter), be_max_rx_irqs(adapter));
738*4882a593Smuzhiyun }
739*4882a593Smuzhiyun 
740*4882a593Smuzhiyun /* Is BE in pvid_tagging mode */
741*4882a593Smuzhiyun #define be_pvid_tagging_enabled(adapter)	(adapter->pvid)
742*4882a593Smuzhiyun 
743*4882a593Smuzhiyun /* Is BE in QNQ multi-channel mode */
744*4882a593Smuzhiyun #define be_is_qnq_mode(adapter)		(adapter->function_mode & QNQ_MODE)
745*4882a593Smuzhiyun 
746*4882a593Smuzhiyun #ifdef CONFIG_BE2NET_LANCER
747*4882a593Smuzhiyun #define lancer_chip(adapter)	(adapter->pdev->device == OC_DEVICE_ID3 || \
748*4882a593Smuzhiyun 				 adapter->pdev->device == OC_DEVICE_ID4)
749*4882a593Smuzhiyun #else
750*4882a593Smuzhiyun #define lancer_chip(adapter)	(0)
751*4882a593Smuzhiyun #endif /* CONFIG_BE2NET_LANCER */
752*4882a593Smuzhiyun 
753*4882a593Smuzhiyun #ifdef CONFIG_BE2NET_SKYHAWK
754*4882a593Smuzhiyun #define skyhawk_chip(adapter)	(adapter->pdev->device == OC_DEVICE_ID5 || \
755*4882a593Smuzhiyun 				 adapter->pdev->device == OC_DEVICE_ID6)
756*4882a593Smuzhiyun #else
757*4882a593Smuzhiyun #define skyhawk_chip(adapter)	(0)
758*4882a593Smuzhiyun #endif /* CONFIG_BE2NET_SKYHAWK */
759*4882a593Smuzhiyun 
760*4882a593Smuzhiyun #ifdef CONFIG_BE2NET_BE3
761*4882a593Smuzhiyun #define BE3_chip(adapter)	(adapter->pdev->device == BE_DEVICE_ID2 || \
762*4882a593Smuzhiyun 				 adapter->pdev->device == OC_DEVICE_ID2)
763*4882a593Smuzhiyun #else
764*4882a593Smuzhiyun #define BE3_chip(adapter)	(0)
765*4882a593Smuzhiyun #endif /* CONFIG_BE2NET_BE3 */
766*4882a593Smuzhiyun 
767*4882a593Smuzhiyun #ifdef CONFIG_BE2NET_BE2
768*4882a593Smuzhiyun #define BE2_chip(adapter)	(adapter->pdev->device == BE_DEVICE_ID1 || \
769*4882a593Smuzhiyun 				 adapter->pdev->device == OC_DEVICE_ID1)
770*4882a593Smuzhiyun #else
771*4882a593Smuzhiyun #define BE2_chip(adapter)	(0)
772*4882a593Smuzhiyun #endif /* CONFIG_BE2NET_BE2 */
773*4882a593Smuzhiyun 
774*4882a593Smuzhiyun #define BEx_chip(adapter)	(BE3_chip(adapter) || BE2_chip(adapter))
775*4882a593Smuzhiyun 
776*4882a593Smuzhiyun #define be_roce_supported(adapter)	(skyhawk_chip(adapter) && \
777*4882a593Smuzhiyun 					(adapter->function_mode & RDMA_ENABLED))
778*4882a593Smuzhiyun 
779*4882a593Smuzhiyun extern const struct ethtool_ops be_ethtool_ops;
780*4882a593Smuzhiyun 
781*4882a593Smuzhiyun #define msix_enabled(adapter)		(adapter->num_msix_vec > 0)
782*4882a593Smuzhiyun #define num_irqs(adapter)		(msix_enabled(adapter) ?	\
783*4882a593Smuzhiyun 						adapter->num_msix_vec : 1)
784*4882a593Smuzhiyun #define tx_stats(txo)			(&(txo)->stats)
785*4882a593Smuzhiyun #define rx_stats(rxo)			(&(rxo)->stats)
786*4882a593Smuzhiyun 
787*4882a593Smuzhiyun /* The default RXQ is the last RXQ */
788*4882a593Smuzhiyun #define default_rxo(adpt)		(&adpt->rx_obj[adpt->num_rx_qs - 1])
789*4882a593Smuzhiyun 
790*4882a593Smuzhiyun #define for_all_rx_queues(adapter, rxo, i)				\
791*4882a593Smuzhiyun 	for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs;	\
792*4882a593Smuzhiyun 		i++, rxo++)
793*4882a593Smuzhiyun 
794*4882a593Smuzhiyun #define for_all_rss_queues(adapter, rxo, i)				\
795*4882a593Smuzhiyun 	for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rss_qs;	\
796*4882a593Smuzhiyun 		i++, rxo++)
797*4882a593Smuzhiyun 
798*4882a593Smuzhiyun #define for_all_tx_queues(adapter, txo, i)				\
799*4882a593Smuzhiyun 	for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs;	\
800*4882a593Smuzhiyun 		i++, txo++)
801*4882a593Smuzhiyun 
802*4882a593Smuzhiyun #define for_all_evt_queues(adapter, eqo, i)				\
803*4882a593Smuzhiyun 	for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \
804*4882a593Smuzhiyun 		i++, eqo++)
805*4882a593Smuzhiyun 
806*4882a593Smuzhiyun #define for_all_rx_queues_on_eq(adapter, eqo, rxo, i)			\
807*4882a593Smuzhiyun 	for (i = eqo->idx, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs;\
808*4882a593Smuzhiyun 		 i += adapter->num_evt_qs, rxo += adapter->num_evt_qs)
809*4882a593Smuzhiyun 
810*4882a593Smuzhiyun #define for_all_tx_queues_on_eq(adapter, eqo, txo, i)			\
811*4882a593Smuzhiyun 	for (i = eqo->idx, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs;\
812*4882a593Smuzhiyun 		i += adapter->num_evt_qs, txo += adapter->num_evt_qs)
813*4882a593Smuzhiyun 
814*4882a593Smuzhiyun #define is_mcc_eqo(eqo)			(eqo->idx == 0)
815*4882a593Smuzhiyun #define mcc_eqo(adapter)		(&adapter->eq_obj[0])
816*4882a593Smuzhiyun 
817*4882a593Smuzhiyun #define PAGE_SHIFT_4K		12
818*4882a593Smuzhiyun #define PAGE_SIZE_4K		(1 << PAGE_SHIFT_4K)
819*4882a593Smuzhiyun 
820*4882a593Smuzhiyun /* Returns number of pages spanned by the data starting at the given addr */
821*4882a593Smuzhiyun #define PAGES_4K_SPANNED(_address, size) 				\
822*4882a593Smuzhiyun 		((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + 	\
823*4882a593Smuzhiyun 			(size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
824*4882a593Smuzhiyun 
825*4882a593Smuzhiyun /* Returns bit offset within a DWORD of a bitfield */
826*4882a593Smuzhiyun #define AMAP_BIT_OFFSET(_struct, field)  				\
827*4882a593Smuzhiyun 		(((size_t)&(((_struct *)0)->field))%32)
828*4882a593Smuzhiyun 
829*4882a593Smuzhiyun /* Returns the bit mask of the field that is NOT shifted into location. */
amap_mask(u32 bitsize)830*4882a593Smuzhiyun static inline u32 amap_mask(u32 bitsize)
831*4882a593Smuzhiyun {
832*4882a593Smuzhiyun 	return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
833*4882a593Smuzhiyun }
834*4882a593Smuzhiyun 
835*4882a593Smuzhiyun static inline void
amap_set(void * ptr,u32 dw_offset,u32 mask,u32 offset,u32 value)836*4882a593Smuzhiyun amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
837*4882a593Smuzhiyun {
838*4882a593Smuzhiyun 	u32 *dw = (u32 *) ptr + dw_offset;
839*4882a593Smuzhiyun 	*dw &= ~(mask << offset);
840*4882a593Smuzhiyun 	*dw |= (mask & value) << offset;
841*4882a593Smuzhiyun }
842*4882a593Smuzhiyun 
843*4882a593Smuzhiyun #define AMAP_SET_BITS(_struct, field, ptr, val)				\
844*4882a593Smuzhiyun 		amap_set(ptr,						\
845*4882a593Smuzhiyun 			offsetof(_struct, field)/32,			\
846*4882a593Smuzhiyun 			amap_mask(sizeof(((_struct *)0)->field)),	\
847*4882a593Smuzhiyun 			AMAP_BIT_OFFSET(_struct, field),		\
848*4882a593Smuzhiyun 			val)
849*4882a593Smuzhiyun 
amap_get(void * ptr,u32 dw_offset,u32 mask,u32 offset)850*4882a593Smuzhiyun static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
851*4882a593Smuzhiyun {
852*4882a593Smuzhiyun 	u32 *dw = (u32 *) ptr;
853*4882a593Smuzhiyun 	return mask & (*(dw + dw_offset) >> offset);
854*4882a593Smuzhiyun }
855*4882a593Smuzhiyun 
856*4882a593Smuzhiyun #define AMAP_GET_BITS(_struct, field, ptr)				\
857*4882a593Smuzhiyun 		amap_get(ptr,						\
858*4882a593Smuzhiyun 			offsetof(_struct, field)/32,			\
859*4882a593Smuzhiyun 			amap_mask(sizeof(((_struct *)0)->field)),	\
860*4882a593Smuzhiyun 			AMAP_BIT_OFFSET(_struct, field))
861*4882a593Smuzhiyun 
862*4882a593Smuzhiyun #define GET_RX_COMPL_V0_BITS(field, ptr)				\
863*4882a593Smuzhiyun 		AMAP_GET_BITS(struct amap_eth_rx_compl_v0, field, ptr)
864*4882a593Smuzhiyun 
865*4882a593Smuzhiyun #define GET_RX_COMPL_V1_BITS(field, ptr)				\
866*4882a593Smuzhiyun 		AMAP_GET_BITS(struct amap_eth_rx_compl_v1, field, ptr)
867*4882a593Smuzhiyun 
868*4882a593Smuzhiyun #define GET_TX_COMPL_BITS(field, ptr)					\
869*4882a593Smuzhiyun 		AMAP_GET_BITS(struct amap_eth_tx_compl, field, ptr)
870*4882a593Smuzhiyun 
871*4882a593Smuzhiyun #define SET_TX_WRB_HDR_BITS(field, ptr, val)				\
872*4882a593Smuzhiyun 		AMAP_SET_BITS(struct amap_eth_hdr_wrb, field, ptr, val)
873*4882a593Smuzhiyun 
874*4882a593Smuzhiyun #define be_dws_cpu_to_le(wrb, len)	swap_dws(wrb, len)
875*4882a593Smuzhiyun #define be_dws_le_to_cpu(wrb, len)	swap_dws(wrb, len)
swap_dws(void * wrb,int len)876*4882a593Smuzhiyun static inline void swap_dws(void *wrb, int len)
877*4882a593Smuzhiyun {
878*4882a593Smuzhiyun #ifdef __BIG_ENDIAN
879*4882a593Smuzhiyun 	u32 *dw = wrb;
880*4882a593Smuzhiyun 	BUG_ON(len % 4);
881*4882a593Smuzhiyun 	do {
882*4882a593Smuzhiyun 		*dw = cpu_to_le32(*dw);
883*4882a593Smuzhiyun 		dw++;
884*4882a593Smuzhiyun 		len -= 4;
885*4882a593Smuzhiyun 	} while (len);
886*4882a593Smuzhiyun #endif				/* __BIG_ENDIAN */
887*4882a593Smuzhiyun }
888*4882a593Smuzhiyun 
889*4882a593Smuzhiyun #define be_cmd_status(status)		(status > 0 ? -EIO : status)
890*4882a593Smuzhiyun 
is_tcp_pkt(struct sk_buff * skb)891*4882a593Smuzhiyun static inline u8 is_tcp_pkt(struct sk_buff *skb)
892*4882a593Smuzhiyun {
893*4882a593Smuzhiyun 	u8 val = 0;
894*4882a593Smuzhiyun 
895*4882a593Smuzhiyun 	if (ip_hdr(skb)->version == 4)
896*4882a593Smuzhiyun 		val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
897*4882a593Smuzhiyun 	else if (ip_hdr(skb)->version == 6)
898*4882a593Smuzhiyun 		val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
899*4882a593Smuzhiyun 
900*4882a593Smuzhiyun 	return val;
901*4882a593Smuzhiyun }
902*4882a593Smuzhiyun 
is_udp_pkt(struct sk_buff * skb)903*4882a593Smuzhiyun static inline u8 is_udp_pkt(struct sk_buff *skb)
904*4882a593Smuzhiyun {
905*4882a593Smuzhiyun 	u8 val = 0;
906*4882a593Smuzhiyun 
907*4882a593Smuzhiyun 	if (ip_hdr(skb)->version == 4)
908*4882a593Smuzhiyun 		val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
909*4882a593Smuzhiyun 	else if (ip_hdr(skb)->version == 6)
910*4882a593Smuzhiyun 		val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
911*4882a593Smuzhiyun 
912*4882a593Smuzhiyun 	return val;
913*4882a593Smuzhiyun }
914*4882a593Smuzhiyun 
is_ipv4_pkt(struct sk_buff * skb)915*4882a593Smuzhiyun static inline bool is_ipv4_pkt(struct sk_buff *skb)
916*4882a593Smuzhiyun {
917*4882a593Smuzhiyun 	return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
918*4882a593Smuzhiyun }
919*4882a593Smuzhiyun 
is_ipv6_ext_hdr(struct sk_buff * skb)920*4882a593Smuzhiyun static inline bool is_ipv6_ext_hdr(struct sk_buff *skb)
921*4882a593Smuzhiyun {
922*4882a593Smuzhiyun 	if (ip_hdr(skb)->version == 6)
923*4882a593Smuzhiyun 		return ipv6_ext_hdr(ipv6_hdr(skb)->nexthdr);
924*4882a593Smuzhiyun 	else
925*4882a593Smuzhiyun 		return false;
926*4882a593Smuzhiyun }
927*4882a593Smuzhiyun 
928*4882a593Smuzhiyun #define be_error_recovering(adapter)	\
929*4882a593Smuzhiyun 		(adapter->flags & BE_FLAGS_TRY_RECOVERY)
930*4882a593Smuzhiyun 
931*4882a593Smuzhiyun #define BE_ERROR_EEH		1
932*4882a593Smuzhiyun #define BE_ERROR_UE		BIT(1)
933*4882a593Smuzhiyun #define BE_ERROR_FW		BIT(2)
934*4882a593Smuzhiyun #define BE_ERROR_TX		BIT(3)
935*4882a593Smuzhiyun #define BE_ERROR_HW		(BE_ERROR_EEH | BE_ERROR_UE | BE_ERROR_TX)
936*4882a593Smuzhiyun #define BE_ERROR_ANY		(BE_ERROR_EEH | BE_ERROR_UE | BE_ERROR_FW | \
937*4882a593Smuzhiyun 				 BE_ERROR_TX)
938*4882a593Smuzhiyun #define BE_CLEAR_ALL		0xFF
939*4882a593Smuzhiyun 
be_check_error(struct be_adapter * adapter,u32 err_type)940*4882a593Smuzhiyun static inline u8 be_check_error(struct be_adapter *adapter, u32 err_type)
941*4882a593Smuzhiyun {
942*4882a593Smuzhiyun 	return (adapter->err_flags & err_type);
943*4882a593Smuzhiyun }
944*4882a593Smuzhiyun 
be_set_error(struct be_adapter * adapter,int err_type)945*4882a593Smuzhiyun static inline void be_set_error(struct be_adapter *adapter, int err_type)
946*4882a593Smuzhiyun {
947*4882a593Smuzhiyun 	struct net_device *netdev = adapter->netdev;
948*4882a593Smuzhiyun 
949*4882a593Smuzhiyun 	adapter->err_flags |= err_type;
950*4882a593Smuzhiyun 	netif_carrier_off(netdev);
951*4882a593Smuzhiyun 
952*4882a593Smuzhiyun 	dev_info(&adapter->pdev->dev, "%s: Link down\n", netdev->name);
953*4882a593Smuzhiyun }
954*4882a593Smuzhiyun 
be_clear_error(struct be_adapter * adapter,int err_type)955*4882a593Smuzhiyun static inline void  be_clear_error(struct be_adapter *adapter, int err_type)
956*4882a593Smuzhiyun {
957*4882a593Smuzhiyun 	adapter->err_flags &= ~err_type;
958*4882a593Smuzhiyun }
959*4882a593Smuzhiyun 
be_multi_rxq(const struct be_adapter * adapter)960*4882a593Smuzhiyun static inline bool be_multi_rxq(const struct be_adapter *adapter)
961*4882a593Smuzhiyun {
962*4882a593Smuzhiyun 	return adapter->num_rx_qs > 1;
963*4882a593Smuzhiyun }
964*4882a593Smuzhiyun 
965*4882a593Smuzhiyun void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
966*4882a593Smuzhiyun 		  u16 num_popped);
967*4882a593Smuzhiyun void be_link_status_update(struct be_adapter *adapter, u8 link_status);
968*4882a593Smuzhiyun void be_parse_stats(struct be_adapter *adapter);
969*4882a593Smuzhiyun int be_load_fw(struct be_adapter *adapter, u8 *func);
970*4882a593Smuzhiyun bool be_is_wol_supported(struct be_adapter *adapter);
971*4882a593Smuzhiyun bool be_pause_supported(struct be_adapter *adapter);
972*4882a593Smuzhiyun u32 be_get_fw_log_level(struct be_adapter *adapter);
973*4882a593Smuzhiyun int be_update_queues(struct be_adapter *adapter);
974*4882a593Smuzhiyun int be_poll(struct napi_struct *napi, int budget);
975*4882a593Smuzhiyun void be_eqd_update(struct be_adapter *adapter, bool force_update);
976*4882a593Smuzhiyun 
977*4882a593Smuzhiyun /*
978*4882a593Smuzhiyun  * internal function to initialize-cleanup roce device.
979*4882a593Smuzhiyun  */
980*4882a593Smuzhiyun void be_roce_dev_add(struct be_adapter *);
981*4882a593Smuzhiyun void be_roce_dev_remove(struct be_adapter *);
982*4882a593Smuzhiyun 
983*4882a593Smuzhiyun /*
984*4882a593Smuzhiyun  * internal function to open-close roce device during ifup-ifdown.
985*4882a593Smuzhiyun  */
986*4882a593Smuzhiyun void be_roce_dev_shutdown(struct be_adapter *);
987*4882a593Smuzhiyun 
988*4882a593Smuzhiyun #endif				/* BE_H */
989