xref: /OK3568_Linux_fs/kernel/drivers/net/ethernet/cisco/enic/vnic_intr.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.
3*4882a593Smuzhiyun  * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * This program is free software; you may redistribute it and/or modify
6*4882a593Smuzhiyun  * it under the terms of the GNU General Public License as published by
7*4882a593Smuzhiyun  * the Free Software Foundation; version 2 of the License.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
10*4882a593Smuzhiyun  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
11*4882a593Smuzhiyun  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
12*4882a593Smuzhiyun  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
13*4882a593Smuzhiyun  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
14*4882a593Smuzhiyun  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
15*4882a593Smuzhiyun  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
16*4882a593Smuzhiyun  * SOFTWARE.
17*4882a593Smuzhiyun  *
18*4882a593Smuzhiyun  */
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #ifndef _VNIC_INTR_H_
21*4882a593Smuzhiyun #define _VNIC_INTR_H_
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #include <linux/pci.h>
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #include "vnic_dev.h"
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define VNIC_INTR_TIMER_TYPE_ABS	0
28*4882a593Smuzhiyun #define VNIC_INTR_TIMER_TYPE_QUIET	1
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun /* Interrupt control */
31*4882a593Smuzhiyun struct vnic_intr_ctrl {
32*4882a593Smuzhiyun 	u32 coalescing_timer;		/* 0x00 */
33*4882a593Smuzhiyun 	u32 pad0;
34*4882a593Smuzhiyun 	u32 coalescing_value;		/* 0x08 */
35*4882a593Smuzhiyun 	u32 pad1;
36*4882a593Smuzhiyun 	u32 coalescing_type;		/* 0x10 */
37*4882a593Smuzhiyun 	u32 pad2;
38*4882a593Smuzhiyun 	u32 mask_on_assertion;		/* 0x18 */
39*4882a593Smuzhiyun 	u32 pad3;
40*4882a593Smuzhiyun 	u32 mask;			/* 0x20 */
41*4882a593Smuzhiyun 	u32 pad4;
42*4882a593Smuzhiyun 	u32 int_credits;		/* 0x28 */
43*4882a593Smuzhiyun 	u32 pad5;
44*4882a593Smuzhiyun 	u32 int_credit_return;		/* 0x30 */
45*4882a593Smuzhiyun 	u32 pad6;
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun struct vnic_intr {
49*4882a593Smuzhiyun 	unsigned int index;
50*4882a593Smuzhiyun 	struct vnic_dev *vdev;
51*4882a593Smuzhiyun 	struct vnic_intr_ctrl __iomem *ctrl;		/* memory-mapped */
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun 
vnic_intr_unmask(struct vnic_intr * intr)54*4882a593Smuzhiyun static inline void vnic_intr_unmask(struct vnic_intr *intr)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun 	iowrite32(0, &intr->ctrl->mask);
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun 
vnic_intr_mask(struct vnic_intr * intr)59*4882a593Smuzhiyun static inline void vnic_intr_mask(struct vnic_intr *intr)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun 	iowrite32(1, &intr->ctrl->mask);
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun 
vnic_intr_masked(struct vnic_intr * intr)64*4882a593Smuzhiyun static inline int vnic_intr_masked(struct vnic_intr *intr)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun 	return ioread32(&intr->ctrl->mask);
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun 
vnic_intr_return_credits(struct vnic_intr * intr,unsigned int credits,int unmask,int reset_timer)69*4882a593Smuzhiyun static inline void vnic_intr_return_credits(struct vnic_intr *intr,
70*4882a593Smuzhiyun 	unsigned int credits, int unmask, int reset_timer)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun #define VNIC_INTR_UNMASK_SHIFT		16
73*4882a593Smuzhiyun #define VNIC_INTR_RESET_TIMER_SHIFT	17
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun 	u32 int_credit_return = (credits & 0xffff) |
76*4882a593Smuzhiyun 		(unmask ? (1 << VNIC_INTR_UNMASK_SHIFT) : 0) |
77*4882a593Smuzhiyun 		(reset_timer ? (1 << VNIC_INTR_RESET_TIMER_SHIFT) : 0);
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	iowrite32(int_credit_return, &intr->ctrl->int_credit_return);
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun 
vnic_intr_credits(struct vnic_intr * intr)82*4882a593Smuzhiyun static inline unsigned int vnic_intr_credits(struct vnic_intr *intr)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun 	return ioread32(&intr->ctrl->int_credits);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun 
vnic_intr_return_all_credits(struct vnic_intr * intr)87*4882a593Smuzhiyun static inline void vnic_intr_return_all_credits(struct vnic_intr *intr)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun 	unsigned int credits = vnic_intr_credits(intr);
90*4882a593Smuzhiyun 	int unmask = 1;
91*4882a593Smuzhiyun 	int reset_timer = 1;
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	vnic_intr_return_credits(intr, credits, unmask, reset_timer);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun 
vnic_intr_legacy_pba(u32 __iomem * legacy_pba)96*4882a593Smuzhiyun static inline u32 vnic_intr_legacy_pba(u32 __iomem *legacy_pba)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun 	/* read PBA without clearing */
99*4882a593Smuzhiyun 	return ioread32(legacy_pba);
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun void vnic_intr_free(struct vnic_intr *intr);
103*4882a593Smuzhiyun int vnic_intr_alloc(struct vnic_dev *vdev, struct vnic_intr *intr,
104*4882a593Smuzhiyun 	unsigned int index);
105*4882a593Smuzhiyun void vnic_intr_init(struct vnic_intr *intr, u32 coalescing_timer,
106*4882a593Smuzhiyun 	unsigned int coalescing_type, unsigned int mask_on_assertion);
107*4882a593Smuzhiyun void vnic_intr_coalescing_timer_set(struct vnic_intr *intr,
108*4882a593Smuzhiyun 	u32 coalescing_timer);
109*4882a593Smuzhiyun void vnic_intr_clean(struct vnic_intr *intr);
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun #endif /* _VNIC_INTR_H_ */
112