1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
3*4882a593Smuzhiyun * Copyright 2007 Nuova Systems, Inc. All rights reserved.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * This program is free software; you may redistribute it and/or modify
6*4882a593Smuzhiyun * it under the terms of the GNU General Public License as published by
7*4882a593Smuzhiyun * the Free Software Foundation; version 2 of the License.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
10*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
11*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
12*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
13*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
14*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
15*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
16*4882a593Smuzhiyun * SOFTWARE.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun */
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <linux/kernel.h>
21*4882a593Smuzhiyun #include <linux/errno.h>
22*4882a593Smuzhiyun #include <linux/types.h>
23*4882a593Smuzhiyun #include <linux/pci.h>
24*4882a593Smuzhiyun #include <linux/netdevice.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #include "wq_enet_desc.h"
27*4882a593Smuzhiyun #include "rq_enet_desc.h"
28*4882a593Smuzhiyun #include "cq_enet_desc.h"
29*4882a593Smuzhiyun #include "vnic_resource.h"
30*4882a593Smuzhiyun #include "vnic_enet.h"
31*4882a593Smuzhiyun #include "vnic_dev.h"
32*4882a593Smuzhiyun #include "vnic_wq.h"
33*4882a593Smuzhiyun #include "vnic_rq.h"
34*4882a593Smuzhiyun #include "vnic_cq.h"
35*4882a593Smuzhiyun #include "vnic_intr.h"
36*4882a593Smuzhiyun #include "vnic_stats.h"
37*4882a593Smuzhiyun #include "vnic_nic.h"
38*4882a593Smuzhiyun #include "vnic_rss.h"
39*4882a593Smuzhiyun #include "enic_res.h"
40*4882a593Smuzhiyun #include "enic.h"
41*4882a593Smuzhiyun
enic_get_vnic_config(struct enic * enic)42*4882a593Smuzhiyun int enic_get_vnic_config(struct enic *enic)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun struct vnic_enet_config *c = &enic->config;
45*4882a593Smuzhiyun int err;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun err = vnic_dev_get_mac_addr(enic->vdev, enic->mac_addr);
48*4882a593Smuzhiyun if (err) {
49*4882a593Smuzhiyun dev_err(enic_get_dev(enic),
50*4882a593Smuzhiyun "Error getting MAC addr, %d\n", err);
51*4882a593Smuzhiyun return err;
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #define GET_CONFIG(m) \
55*4882a593Smuzhiyun do { \
56*4882a593Smuzhiyun err = vnic_dev_spec(enic->vdev, \
57*4882a593Smuzhiyun offsetof(struct vnic_enet_config, m), \
58*4882a593Smuzhiyun sizeof(c->m), &c->m); \
59*4882a593Smuzhiyun if (err) { \
60*4882a593Smuzhiyun dev_err(enic_get_dev(enic), \
61*4882a593Smuzhiyun "Error getting %s, %d\n", #m, err); \
62*4882a593Smuzhiyun return err; \
63*4882a593Smuzhiyun } \
64*4882a593Smuzhiyun } while (0)
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun GET_CONFIG(flags);
67*4882a593Smuzhiyun GET_CONFIG(wq_desc_count);
68*4882a593Smuzhiyun GET_CONFIG(rq_desc_count);
69*4882a593Smuzhiyun GET_CONFIG(mtu);
70*4882a593Smuzhiyun GET_CONFIG(intr_timer_type);
71*4882a593Smuzhiyun GET_CONFIG(intr_mode);
72*4882a593Smuzhiyun GET_CONFIG(intr_timer_usec);
73*4882a593Smuzhiyun GET_CONFIG(loop_tag);
74*4882a593Smuzhiyun GET_CONFIG(num_arfs);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun c->wq_desc_count =
77*4882a593Smuzhiyun min_t(u32, ENIC_MAX_WQ_DESCS,
78*4882a593Smuzhiyun max_t(u32, ENIC_MIN_WQ_DESCS,
79*4882a593Smuzhiyun c->wq_desc_count));
80*4882a593Smuzhiyun c->wq_desc_count &= 0xffffffe0; /* must be aligned to groups of 32 */
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun c->rq_desc_count =
83*4882a593Smuzhiyun min_t(u32, ENIC_MAX_RQ_DESCS,
84*4882a593Smuzhiyun max_t(u32, ENIC_MIN_RQ_DESCS,
85*4882a593Smuzhiyun c->rq_desc_count));
86*4882a593Smuzhiyun c->rq_desc_count &= 0xffffffe0; /* must be aligned to groups of 32 */
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun if (c->mtu == 0)
89*4882a593Smuzhiyun c->mtu = 1500;
90*4882a593Smuzhiyun c->mtu = min_t(u16, ENIC_MAX_MTU,
91*4882a593Smuzhiyun max_t(u16, ENIC_MIN_MTU,
92*4882a593Smuzhiyun c->mtu));
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun c->intr_timer_usec = min_t(u32, c->intr_timer_usec,
95*4882a593Smuzhiyun vnic_dev_get_intr_coal_timer_max(enic->vdev));
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun dev_info(enic_get_dev(enic),
98*4882a593Smuzhiyun "vNIC MAC addr %pM wq/rq %d/%d mtu %d\n",
99*4882a593Smuzhiyun enic->mac_addr, c->wq_desc_count, c->rq_desc_count, c->mtu);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun dev_info(enic_get_dev(enic), "vNIC csum tx/rx %s/%s "
102*4882a593Smuzhiyun "tso/lro %s/%s rss %s intr mode %s type %s timer %d usec "
103*4882a593Smuzhiyun "loopback tag 0x%04x\n",
104*4882a593Smuzhiyun ENIC_SETTING(enic, TXCSUM) ? "yes" : "no",
105*4882a593Smuzhiyun ENIC_SETTING(enic, RXCSUM) ? "yes" : "no",
106*4882a593Smuzhiyun ENIC_SETTING(enic, TSO) ? "yes" : "no",
107*4882a593Smuzhiyun ENIC_SETTING(enic, LRO) ? "yes" : "no",
108*4882a593Smuzhiyun ENIC_SETTING(enic, RSS) ? "yes" : "no",
109*4882a593Smuzhiyun c->intr_mode == VENET_INTR_MODE_INTX ? "INTx" :
110*4882a593Smuzhiyun c->intr_mode == VENET_INTR_MODE_MSI ? "MSI" :
111*4882a593Smuzhiyun c->intr_mode == VENET_INTR_MODE_ANY ? "any" :
112*4882a593Smuzhiyun "unknown",
113*4882a593Smuzhiyun c->intr_timer_type == VENET_INTR_TYPE_MIN ? "min" :
114*4882a593Smuzhiyun c->intr_timer_type == VENET_INTR_TYPE_IDLE ? "idle" :
115*4882a593Smuzhiyun "unknown",
116*4882a593Smuzhiyun c->intr_timer_usec,
117*4882a593Smuzhiyun c->loop_tag);
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun return 0;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
enic_add_vlan(struct enic * enic,u16 vlanid)122*4882a593Smuzhiyun int enic_add_vlan(struct enic *enic, u16 vlanid)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun u64 a0 = vlanid, a1 = 0;
125*4882a593Smuzhiyun int wait = 1000;
126*4882a593Smuzhiyun int err;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun err = vnic_dev_cmd(enic->vdev, CMD_VLAN_ADD, &a0, &a1, wait);
129*4882a593Smuzhiyun if (err)
130*4882a593Smuzhiyun dev_err(enic_get_dev(enic), "Can't add vlan id, %d\n", err);
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun return err;
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
enic_del_vlan(struct enic * enic,u16 vlanid)135*4882a593Smuzhiyun int enic_del_vlan(struct enic *enic, u16 vlanid)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun u64 a0 = vlanid, a1 = 0;
138*4882a593Smuzhiyun int wait = 1000;
139*4882a593Smuzhiyun int err;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun err = vnic_dev_cmd(enic->vdev, CMD_VLAN_DEL, &a0, &a1, wait);
142*4882a593Smuzhiyun if (err)
143*4882a593Smuzhiyun dev_err(enic_get_dev(enic), "Can't delete vlan id, %d\n", err);
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun return err;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
enic_set_nic_cfg(struct enic * enic,u8 rss_default_cpu,u8 rss_hash_type,u8 rss_hash_bits,u8 rss_base_cpu,u8 rss_enable,u8 tso_ipid_split_en,u8 ig_vlan_strip_en)148*4882a593Smuzhiyun int enic_set_nic_cfg(struct enic *enic, u8 rss_default_cpu, u8 rss_hash_type,
149*4882a593Smuzhiyun u8 rss_hash_bits, u8 rss_base_cpu, u8 rss_enable, u8 tso_ipid_split_en,
150*4882a593Smuzhiyun u8 ig_vlan_strip_en)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun enum vnic_devcmd_cmd cmd = CMD_NIC_CFG;
153*4882a593Smuzhiyun u64 a0, a1;
154*4882a593Smuzhiyun u32 nic_cfg;
155*4882a593Smuzhiyun int wait = 1000;
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun vnic_set_nic_cfg(&nic_cfg, rss_default_cpu,
158*4882a593Smuzhiyun rss_hash_type, rss_hash_bits, rss_base_cpu,
159*4882a593Smuzhiyun rss_enable, tso_ipid_split_en, ig_vlan_strip_en);
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun a0 = nic_cfg;
162*4882a593Smuzhiyun a1 = 0;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun if (rss_hash_type & (NIC_CFG_RSS_HASH_TYPE_UDP_IPV4 |
165*4882a593Smuzhiyun NIC_CFG_RSS_HASH_TYPE_UDP_IPV6))
166*4882a593Smuzhiyun cmd = CMD_NIC_CFG_CHK;
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun return vnic_dev_cmd(enic->vdev, cmd, &a0, &a1, wait);
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun
enic_set_rss_key(struct enic * enic,dma_addr_t key_pa,u64 len)171*4882a593Smuzhiyun int enic_set_rss_key(struct enic *enic, dma_addr_t key_pa, u64 len)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun u64 a0 = (u64)key_pa, a1 = len;
174*4882a593Smuzhiyun int wait = 1000;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun return vnic_dev_cmd(enic->vdev, CMD_RSS_KEY, &a0, &a1, wait);
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun
enic_set_rss_cpu(struct enic * enic,dma_addr_t cpu_pa,u64 len)179*4882a593Smuzhiyun int enic_set_rss_cpu(struct enic *enic, dma_addr_t cpu_pa, u64 len)
180*4882a593Smuzhiyun {
181*4882a593Smuzhiyun u64 a0 = (u64)cpu_pa, a1 = len;
182*4882a593Smuzhiyun int wait = 1000;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun return vnic_dev_cmd(enic->vdev, CMD_RSS_CPU, &a0, &a1, wait);
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
enic_free_vnic_resources(struct enic * enic)187*4882a593Smuzhiyun void enic_free_vnic_resources(struct enic *enic)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun unsigned int i;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun for (i = 0; i < enic->wq_count; i++)
192*4882a593Smuzhiyun vnic_wq_free(&enic->wq[i]);
193*4882a593Smuzhiyun for (i = 0; i < enic->rq_count; i++)
194*4882a593Smuzhiyun vnic_rq_free(&enic->rq[i]);
195*4882a593Smuzhiyun for (i = 0; i < enic->cq_count; i++)
196*4882a593Smuzhiyun vnic_cq_free(&enic->cq[i]);
197*4882a593Smuzhiyun for (i = 0; i < enic->intr_count; i++)
198*4882a593Smuzhiyun vnic_intr_free(&enic->intr[i]);
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun
enic_get_res_counts(struct enic * enic)201*4882a593Smuzhiyun void enic_get_res_counts(struct enic *enic)
202*4882a593Smuzhiyun {
203*4882a593Smuzhiyun enic->wq_count = vnic_dev_get_res_count(enic->vdev, RES_TYPE_WQ);
204*4882a593Smuzhiyun enic->rq_count = vnic_dev_get_res_count(enic->vdev, RES_TYPE_RQ);
205*4882a593Smuzhiyun enic->cq_count = vnic_dev_get_res_count(enic->vdev, RES_TYPE_CQ);
206*4882a593Smuzhiyun enic->intr_count = vnic_dev_get_res_count(enic->vdev,
207*4882a593Smuzhiyun RES_TYPE_INTR_CTRL);
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun dev_info(enic_get_dev(enic),
210*4882a593Smuzhiyun "vNIC resources avail: wq %d rq %d cq %d intr %d\n",
211*4882a593Smuzhiyun enic->wq_count, enic->rq_count,
212*4882a593Smuzhiyun enic->cq_count, enic->intr_count);
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun
enic_init_vnic_resources(struct enic * enic)215*4882a593Smuzhiyun void enic_init_vnic_resources(struct enic *enic)
216*4882a593Smuzhiyun {
217*4882a593Smuzhiyun enum vnic_dev_intr_mode intr_mode;
218*4882a593Smuzhiyun unsigned int mask_on_assertion;
219*4882a593Smuzhiyun unsigned int interrupt_offset;
220*4882a593Smuzhiyun unsigned int error_interrupt_enable;
221*4882a593Smuzhiyun unsigned int error_interrupt_offset;
222*4882a593Smuzhiyun unsigned int cq_index;
223*4882a593Smuzhiyun unsigned int i;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun intr_mode = vnic_dev_get_intr_mode(enic->vdev);
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun /* Init RQ/WQ resources.
228*4882a593Smuzhiyun *
229*4882a593Smuzhiyun * RQ[0 - n-1] point to CQ[0 - n-1]
230*4882a593Smuzhiyun * WQ[0 - m-1] point to CQ[n - n+m-1]
231*4882a593Smuzhiyun *
232*4882a593Smuzhiyun * Error interrupt is not enabled for MSI.
233*4882a593Smuzhiyun */
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun switch (intr_mode) {
236*4882a593Smuzhiyun case VNIC_DEV_INTR_MODE_INTX:
237*4882a593Smuzhiyun case VNIC_DEV_INTR_MODE_MSIX:
238*4882a593Smuzhiyun error_interrupt_enable = 1;
239*4882a593Smuzhiyun error_interrupt_offset = enic->intr_count - 2;
240*4882a593Smuzhiyun break;
241*4882a593Smuzhiyun default:
242*4882a593Smuzhiyun error_interrupt_enable = 0;
243*4882a593Smuzhiyun error_interrupt_offset = 0;
244*4882a593Smuzhiyun break;
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun for (i = 0; i < enic->rq_count; i++) {
248*4882a593Smuzhiyun cq_index = i;
249*4882a593Smuzhiyun vnic_rq_init(&enic->rq[i],
250*4882a593Smuzhiyun cq_index,
251*4882a593Smuzhiyun error_interrupt_enable,
252*4882a593Smuzhiyun error_interrupt_offset);
253*4882a593Smuzhiyun }
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun for (i = 0; i < enic->wq_count; i++) {
256*4882a593Smuzhiyun cq_index = enic->rq_count + i;
257*4882a593Smuzhiyun vnic_wq_init(&enic->wq[i],
258*4882a593Smuzhiyun cq_index,
259*4882a593Smuzhiyun error_interrupt_enable,
260*4882a593Smuzhiyun error_interrupt_offset);
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun /* Init CQ resources
264*4882a593Smuzhiyun *
265*4882a593Smuzhiyun * CQ[0 - n+m-1] point to INTR[0] for INTx, MSI
266*4882a593Smuzhiyun * CQ[0 - n+m-1] point to INTR[0 - n+m-1] for MSI-X
267*4882a593Smuzhiyun */
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun for (i = 0; i < enic->cq_count; i++) {
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun switch (intr_mode) {
272*4882a593Smuzhiyun case VNIC_DEV_INTR_MODE_MSIX:
273*4882a593Smuzhiyun interrupt_offset = i;
274*4882a593Smuzhiyun break;
275*4882a593Smuzhiyun default:
276*4882a593Smuzhiyun interrupt_offset = 0;
277*4882a593Smuzhiyun break;
278*4882a593Smuzhiyun }
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun vnic_cq_init(&enic->cq[i],
281*4882a593Smuzhiyun 0 /* flow_control_enable */,
282*4882a593Smuzhiyun 1 /* color_enable */,
283*4882a593Smuzhiyun 0 /* cq_head */,
284*4882a593Smuzhiyun 0 /* cq_tail */,
285*4882a593Smuzhiyun 1 /* cq_tail_color */,
286*4882a593Smuzhiyun 1 /* interrupt_enable */,
287*4882a593Smuzhiyun 1 /* cq_entry_enable */,
288*4882a593Smuzhiyun 0 /* cq_message_enable */,
289*4882a593Smuzhiyun interrupt_offset,
290*4882a593Smuzhiyun 0 /* cq_message_addr */);
291*4882a593Smuzhiyun }
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun /* Init INTR resources
294*4882a593Smuzhiyun *
295*4882a593Smuzhiyun * mask_on_assertion is not used for INTx due to the level-
296*4882a593Smuzhiyun * triggered nature of INTx
297*4882a593Smuzhiyun */
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun switch (intr_mode) {
300*4882a593Smuzhiyun case VNIC_DEV_INTR_MODE_MSI:
301*4882a593Smuzhiyun case VNIC_DEV_INTR_MODE_MSIX:
302*4882a593Smuzhiyun mask_on_assertion = 1;
303*4882a593Smuzhiyun break;
304*4882a593Smuzhiyun default:
305*4882a593Smuzhiyun mask_on_assertion = 0;
306*4882a593Smuzhiyun break;
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun for (i = 0; i < enic->intr_count; i++) {
310*4882a593Smuzhiyun vnic_intr_init(&enic->intr[i],
311*4882a593Smuzhiyun enic->config.intr_timer_usec,
312*4882a593Smuzhiyun enic->config.intr_timer_type,
313*4882a593Smuzhiyun mask_on_assertion);
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun }
316*4882a593Smuzhiyun
enic_alloc_vnic_resources(struct enic * enic)317*4882a593Smuzhiyun int enic_alloc_vnic_resources(struct enic *enic)
318*4882a593Smuzhiyun {
319*4882a593Smuzhiyun enum vnic_dev_intr_mode intr_mode;
320*4882a593Smuzhiyun unsigned int i;
321*4882a593Smuzhiyun int err;
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun intr_mode = vnic_dev_get_intr_mode(enic->vdev);
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun dev_info(enic_get_dev(enic), "vNIC resources used: "
326*4882a593Smuzhiyun "wq %d rq %d cq %d intr %d intr mode %s\n",
327*4882a593Smuzhiyun enic->wq_count, enic->rq_count,
328*4882a593Smuzhiyun enic->cq_count, enic->intr_count,
329*4882a593Smuzhiyun intr_mode == VNIC_DEV_INTR_MODE_INTX ? "legacy PCI INTx" :
330*4882a593Smuzhiyun intr_mode == VNIC_DEV_INTR_MODE_MSI ? "MSI" :
331*4882a593Smuzhiyun intr_mode == VNIC_DEV_INTR_MODE_MSIX ? "MSI-X" :
332*4882a593Smuzhiyun "unknown");
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun /* Allocate queue resources
335*4882a593Smuzhiyun */
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun for (i = 0; i < enic->wq_count; i++) {
338*4882a593Smuzhiyun err = vnic_wq_alloc(enic->vdev, &enic->wq[i], i,
339*4882a593Smuzhiyun enic->config.wq_desc_count,
340*4882a593Smuzhiyun sizeof(struct wq_enet_desc));
341*4882a593Smuzhiyun if (err)
342*4882a593Smuzhiyun goto err_out_cleanup;
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun for (i = 0; i < enic->rq_count; i++) {
346*4882a593Smuzhiyun err = vnic_rq_alloc(enic->vdev, &enic->rq[i], i,
347*4882a593Smuzhiyun enic->config.rq_desc_count,
348*4882a593Smuzhiyun sizeof(struct rq_enet_desc));
349*4882a593Smuzhiyun if (err)
350*4882a593Smuzhiyun goto err_out_cleanup;
351*4882a593Smuzhiyun }
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun for (i = 0; i < enic->cq_count; i++) {
354*4882a593Smuzhiyun if (i < enic->rq_count)
355*4882a593Smuzhiyun err = vnic_cq_alloc(enic->vdev, &enic->cq[i], i,
356*4882a593Smuzhiyun enic->config.rq_desc_count,
357*4882a593Smuzhiyun sizeof(struct cq_enet_rq_desc));
358*4882a593Smuzhiyun else
359*4882a593Smuzhiyun err = vnic_cq_alloc(enic->vdev, &enic->cq[i], i,
360*4882a593Smuzhiyun enic->config.wq_desc_count,
361*4882a593Smuzhiyun sizeof(struct cq_enet_wq_desc));
362*4882a593Smuzhiyun if (err)
363*4882a593Smuzhiyun goto err_out_cleanup;
364*4882a593Smuzhiyun }
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun for (i = 0; i < enic->intr_count; i++) {
367*4882a593Smuzhiyun err = vnic_intr_alloc(enic->vdev, &enic->intr[i], i);
368*4882a593Smuzhiyun if (err)
369*4882a593Smuzhiyun goto err_out_cleanup;
370*4882a593Smuzhiyun }
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun /* Hook remaining resource
373*4882a593Smuzhiyun */
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun enic->legacy_pba = vnic_dev_get_res(enic->vdev,
376*4882a593Smuzhiyun RES_TYPE_INTR_PBA_LEGACY, 0);
377*4882a593Smuzhiyun if (!enic->legacy_pba && intr_mode == VNIC_DEV_INTR_MODE_INTX) {
378*4882a593Smuzhiyun dev_err(enic_get_dev(enic),
379*4882a593Smuzhiyun "Failed to hook legacy pba resource\n");
380*4882a593Smuzhiyun err = -ENODEV;
381*4882a593Smuzhiyun goto err_out_cleanup;
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun return 0;
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun err_out_cleanup:
387*4882a593Smuzhiyun enic_free_vnic_resources(enic);
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun return err;
390*4882a593Smuzhiyun }
391