1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
3*4882a593Smuzhiyun * Copyright 2007 Nuova Systems, Inc. All rights reserved.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * This program is free software; you may redistribute it and/or modify
6*4882a593Smuzhiyun * it under the terms of the GNU General Public License as published by
7*4882a593Smuzhiyun * the Free Software Foundation; version 2 of the License.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
10*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
11*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
12*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
13*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
14*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
15*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
16*4882a593Smuzhiyun * SOFTWARE.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun */
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #ifndef _ENIC_H_
21*4882a593Smuzhiyun #define _ENIC_H_
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include "vnic_enet.h"
24*4882a593Smuzhiyun #include "vnic_dev.h"
25*4882a593Smuzhiyun #include "vnic_wq.h"
26*4882a593Smuzhiyun #include "vnic_rq.h"
27*4882a593Smuzhiyun #include "vnic_cq.h"
28*4882a593Smuzhiyun #include "vnic_intr.h"
29*4882a593Smuzhiyun #include "vnic_stats.h"
30*4882a593Smuzhiyun #include "vnic_nic.h"
31*4882a593Smuzhiyun #include "vnic_rss.h"
32*4882a593Smuzhiyun #include <linux/irq.h>
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define DRV_NAME "enic"
35*4882a593Smuzhiyun #define DRV_DESCRIPTION "Cisco VIC Ethernet NIC Driver"
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define ENIC_BARS_MAX 6
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define ENIC_WQ_MAX 8
40*4882a593Smuzhiyun #define ENIC_RQ_MAX 8
41*4882a593Smuzhiyun #define ENIC_CQ_MAX (ENIC_WQ_MAX + ENIC_RQ_MAX)
42*4882a593Smuzhiyun #define ENIC_INTR_MAX (ENIC_CQ_MAX + 2)
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define ENIC_WQ_NAPI_BUDGET 256
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun #define ENIC_AIC_LARGE_PKT_DIFF 3
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun struct enic_msix_entry {
49*4882a593Smuzhiyun int requested;
50*4882a593Smuzhiyun char devname[IFNAMSIZ + 8];
51*4882a593Smuzhiyun irqreturn_t (*isr)(int, void *);
52*4882a593Smuzhiyun void *devid;
53*4882a593Smuzhiyun cpumask_var_t affinity_mask;
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* Store only the lower range. Higher range is given by fw. */
57*4882a593Smuzhiyun struct enic_intr_mod_range {
58*4882a593Smuzhiyun u32 small_pkt_range_start;
59*4882a593Smuzhiyun u32 large_pkt_range_start;
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun struct enic_intr_mod_table {
63*4882a593Smuzhiyun u32 rx_rate;
64*4882a593Smuzhiyun u32 range_percent;
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #define ENIC_MAX_LINK_SPEEDS 3
68*4882a593Smuzhiyun #define ENIC_LINK_SPEED_10G 10000
69*4882a593Smuzhiyun #define ENIC_LINK_SPEED_4G 4000
70*4882a593Smuzhiyun #define ENIC_LINK_40G_INDEX 2
71*4882a593Smuzhiyun #define ENIC_LINK_10G_INDEX 1
72*4882a593Smuzhiyun #define ENIC_LINK_4G_INDEX 0
73*4882a593Smuzhiyun #define ENIC_RX_COALESCE_RANGE_END 125
74*4882a593Smuzhiyun #define ENIC_AIC_TS_BREAK 100
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun struct enic_rx_coal {
77*4882a593Smuzhiyun u32 small_pkt_range_start;
78*4882a593Smuzhiyun u32 large_pkt_range_start;
79*4882a593Smuzhiyun u32 range_end;
80*4882a593Smuzhiyun u32 use_adaptive_rx_coalesce;
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /* priv_flags */
84*4882a593Smuzhiyun #define ENIC_SRIOV_ENABLED (1 << 0)
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /* enic port profile set flags */
87*4882a593Smuzhiyun #define ENIC_PORT_REQUEST_APPLIED (1 << 0)
88*4882a593Smuzhiyun #define ENIC_SET_REQUEST (1 << 1)
89*4882a593Smuzhiyun #define ENIC_SET_NAME (1 << 2)
90*4882a593Smuzhiyun #define ENIC_SET_INSTANCE (1 << 3)
91*4882a593Smuzhiyun #define ENIC_SET_HOST (1 << 4)
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun struct enic_port_profile {
94*4882a593Smuzhiyun u32 set;
95*4882a593Smuzhiyun u8 request;
96*4882a593Smuzhiyun char name[PORT_PROFILE_MAX];
97*4882a593Smuzhiyun u8 instance_uuid[PORT_UUID_MAX];
98*4882a593Smuzhiyun u8 host_uuid[PORT_UUID_MAX];
99*4882a593Smuzhiyun u8 vf_mac[ETH_ALEN];
100*4882a593Smuzhiyun u8 mac_addr[ETH_ALEN];
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /* enic_rfs_fltr_node - rfs filter node in hash table
104*4882a593Smuzhiyun * @@keys: IPv4 5 tuple
105*4882a593Smuzhiyun * @flow_id: flow_id of clsf filter provided by kernel
106*4882a593Smuzhiyun * @fltr_id: filter id of clsf filter returned by adaptor
107*4882a593Smuzhiyun * @rq_id: desired rq index
108*4882a593Smuzhiyun * @node: hlist_node
109*4882a593Smuzhiyun */
110*4882a593Smuzhiyun struct enic_rfs_fltr_node {
111*4882a593Smuzhiyun struct flow_keys keys;
112*4882a593Smuzhiyun u32 flow_id;
113*4882a593Smuzhiyun u16 fltr_id;
114*4882a593Smuzhiyun u16 rq_id;
115*4882a593Smuzhiyun struct hlist_node node;
116*4882a593Smuzhiyun };
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun /* enic_rfs_flw_tbl - rfs flow table
119*4882a593Smuzhiyun * @max: Maximum number of filters vNIC supports
120*4882a593Smuzhiyun * @free: Number of free filters available
121*4882a593Smuzhiyun * @toclean: hash table index to clean next
122*4882a593Smuzhiyun * @ht_head: hash table list head
123*4882a593Smuzhiyun * @lock: spin lock
124*4882a593Smuzhiyun * @rfs_may_expire: timer function for enic_rps_may_expire_flow
125*4882a593Smuzhiyun */
126*4882a593Smuzhiyun struct enic_rfs_flw_tbl {
127*4882a593Smuzhiyun u16 max;
128*4882a593Smuzhiyun int free;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun #define ENIC_RFS_FLW_BITSHIFT (10)
131*4882a593Smuzhiyun #define ENIC_RFS_FLW_MASK ((1 << ENIC_RFS_FLW_BITSHIFT) - 1)
132*4882a593Smuzhiyun u16 toclean:ENIC_RFS_FLW_BITSHIFT;
133*4882a593Smuzhiyun struct hlist_head ht_head[1 << ENIC_RFS_FLW_BITSHIFT];
134*4882a593Smuzhiyun spinlock_t lock;
135*4882a593Smuzhiyun struct timer_list rfs_may_expire;
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun struct vxlan_offload {
139*4882a593Smuzhiyun u16 vxlan_udp_port_number;
140*4882a593Smuzhiyun u8 patch_level;
141*4882a593Smuzhiyun u8 flags;
142*4882a593Smuzhiyun };
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun /* Per-instance private data structure */
145*4882a593Smuzhiyun struct enic {
146*4882a593Smuzhiyun struct net_device *netdev;
147*4882a593Smuzhiyun struct pci_dev *pdev;
148*4882a593Smuzhiyun struct vnic_enet_config config;
149*4882a593Smuzhiyun struct vnic_dev_bar bar[ENIC_BARS_MAX];
150*4882a593Smuzhiyun struct vnic_dev *vdev;
151*4882a593Smuzhiyun struct timer_list notify_timer;
152*4882a593Smuzhiyun struct work_struct reset;
153*4882a593Smuzhiyun struct work_struct tx_hang_reset;
154*4882a593Smuzhiyun struct work_struct change_mtu_work;
155*4882a593Smuzhiyun struct msix_entry msix_entry[ENIC_INTR_MAX];
156*4882a593Smuzhiyun struct enic_msix_entry msix[ENIC_INTR_MAX];
157*4882a593Smuzhiyun u32 msg_enable;
158*4882a593Smuzhiyun spinlock_t devcmd_lock;
159*4882a593Smuzhiyun u8 mac_addr[ETH_ALEN];
160*4882a593Smuzhiyun unsigned int flags;
161*4882a593Smuzhiyun unsigned int priv_flags;
162*4882a593Smuzhiyun unsigned int mc_count;
163*4882a593Smuzhiyun unsigned int uc_count;
164*4882a593Smuzhiyun u32 port_mtu;
165*4882a593Smuzhiyun struct enic_rx_coal rx_coalesce_setting;
166*4882a593Smuzhiyun u32 rx_coalesce_usecs;
167*4882a593Smuzhiyun u32 tx_coalesce_usecs;
168*4882a593Smuzhiyun #ifdef CONFIG_PCI_IOV
169*4882a593Smuzhiyun u16 num_vfs;
170*4882a593Smuzhiyun #endif
171*4882a593Smuzhiyun spinlock_t enic_api_lock;
172*4882a593Smuzhiyun bool enic_api_busy;
173*4882a593Smuzhiyun struct enic_port_profile *pp;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun /* work queue cache line section */
176*4882a593Smuzhiyun ____cacheline_aligned struct vnic_wq wq[ENIC_WQ_MAX];
177*4882a593Smuzhiyun spinlock_t wq_lock[ENIC_WQ_MAX];
178*4882a593Smuzhiyun unsigned int wq_count;
179*4882a593Smuzhiyun u16 loop_enable;
180*4882a593Smuzhiyun u16 loop_tag;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun /* receive queue cache line section */
183*4882a593Smuzhiyun ____cacheline_aligned struct vnic_rq rq[ENIC_RQ_MAX];
184*4882a593Smuzhiyun unsigned int rq_count;
185*4882a593Smuzhiyun struct vxlan_offload vxlan;
186*4882a593Smuzhiyun u64 rq_truncated_pkts;
187*4882a593Smuzhiyun u64 rq_bad_fcs;
188*4882a593Smuzhiyun struct napi_struct napi[ENIC_RQ_MAX + ENIC_WQ_MAX];
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun /* interrupt resource cache line section */
191*4882a593Smuzhiyun ____cacheline_aligned struct vnic_intr intr[ENIC_INTR_MAX];
192*4882a593Smuzhiyun unsigned int intr_count;
193*4882a593Smuzhiyun u32 __iomem *legacy_pba; /* memory-mapped */
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun /* completion queue cache line section */
196*4882a593Smuzhiyun ____cacheline_aligned struct vnic_cq cq[ENIC_CQ_MAX];
197*4882a593Smuzhiyun unsigned int cq_count;
198*4882a593Smuzhiyun struct enic_rfs_flw_tbl rfs_h;
199*4882a593Smuzhiyun u32 rx_copybreak;
200*4882a593Smuzhiyun u8 rss_key[ENIC_RSS_LEN];
201*4882a593Smuzhiyun struct vnic_gen_stats gen_stats;
202*4882a593Smuzhiyun };
203*4882a593Smuzhiyun
vnic_get_netdev(struct vnic_dev * vdev)204*4882a593Smuzhiyun static inline struct net_device *vnic_get_netdev(struct vnic_dev *vdev)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun struct enic *enic = vdev->priv;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun return enic->netdev;
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun /* wrappers function for kernel log
212*4882a593Smuzhiyun */
213*4882a593Smuzhiyun #define vdev_err(vdev, fmt, ...) \
214*4882a593Smuzhiyun dev_err(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__)
215*4882a593Smuzhiyun #define vdev_warn(vdev, fmt, ...) \
216*4882a593Smuzhiyun dev_warn(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__)
217*4882a593Smuzhiyun #define vdev_info(vdev, fmt, ...) \
218*4882a593Smuzhiyun dev_info(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__)
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun #define vdev_neterr(vdev, fmt, ...) \
221*4882a593Smuzhiyun netdev_err(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__)
222*4882a593Smuzhiyun #define vdev_netwarn(vdev, fmt, ...) \
223*4882a593Smuzhiyun netdev_warn(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__)
224*4882a593Smuzhiyun #define vdev_netinfo(vdev, fmt, ...) \
225*4882a593Smuzhiyun netdev_info(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__)
226*4882a593Smuzhiyun
enic_get_dev(struct enic * enic)227*4882a593Smuzhiyun static inline struct device *enic_get_dev(struct enic *enic)
228*4882a593Smuzhiyun {
229*4882a593Smuzhiyun return &(enic->pdev->dev);
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun
enic_cq_rq(struct enic * enic,unsigned int rq)232*4882a593Smuzhiyun static inline unsigned int enic_cq_rq(struct enic *enic, unsigned int rq)
233*4882a593Smuzhiyun {
234*4882a593Smuzhiyun return rq;
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
enic_cq_wq(struct enic * enic,unsigned int wq)237*4882a593Smuzhiyun static inline unsigned int enic_cq_wq(struct enic *enic, unsigned int wq)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun return enic->rq_count + wq;
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun
enic_legacy_io_intr(void)242*4882a593Smuzhiyun static inline unsigned int enic_legacy_io_intr(void)
243*4882a593Smuzhiyun {
244*4882a593Smuzhiyun return 0;
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun
enic_legacy_err_intr(void)247*4882a593Smuzhiyun static inline unsigned int enic_legacy_err_intr(void)
248*4882a593Smuzhiyun {
249*4882a593Smuzhiyun return 1;
250*4882a593Smuzhiyun }
251*4882a593Smuzhiyun
enic_legacy_notify_intr(void)252*4882a593Smuzhiyun static inline unsigned int enic_legacy_notify_intr(void)
253*4882a593Smuzhiyun {
254*4882a593Smuzhiyun return 2;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
enic_msix_rq_intr(struct enic * enic,unsigned int rq)257*4882a593Smuzhiyun static inline unsigned int enic_msix_rq_intr(struct enic *enic,
258*4882a593Smuzhiyun unsigned int rq)
259*4882a593Smuzhiyun {
260*4882a593Smuzhiyun return enic->cq[enic_cq_rq(enic, rq)].interrupt_offset;
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun
enic_msix_wq_intr(struct enic * enic,unsigned int wq)263*4882a593Smuzhiyun static inline unsigned int enic_msix_wq_intr(struct enic *enic,
264*4882a593Smuzhiyun unsigned int wq)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun return enic->cq[enic_cq_wq(enic, wq)].interrupt_offset;
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun
enic_msix_err_intr(struct enic * enic)269*4882a593Smuzhiyun static inline unsigned int enic_msix_err_intr(struct enic *enic)
270*4882a593Smuzhiyun {
271*4882a593Smuzhiyun return enic->rq_count + enic->wq_count;
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun
enic_msix_notify_intr(struct enic * enic)274*4882a593Smuzhiyun static inline unsigned int enic_msix_notify_intr(struct enic *enic)
275*4882a593Smuzhiyun {
276*4882a593Smuzhiyun return enic->rq_count + enic->wq_count + 1;
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun
enic_is_err_intr(struct enic * enic,int intr)279*4882a593Smuzhiyun static inline bool enic_is_err_intr(struct enic *enic, int intr)
280*4882a593Smuzhiyun {
281*4882a593Smuzhiyun switch (vnic_dev_get_intr_mode(enic->vdev)) {
282*4882a593Smuzhiyun case VNIC_DEV_INTR_MODE_INTX:
283*4882a593Smuzhiyun return intr == enic_legacy_err_intr();
284*4882a593Smuzhiyun case VNIC_DEV_INTR_MODE_MSIX:
285*4882a593Smuzhiyun return intr == enic_msix_err_intr(enic);
286*4882a593Smuzhiyun case VNIC_DEV_INTR_MODE_MSI:
287*4882a593Smuzhiyun default:
288*4882a593Smuzhiyun return false;
289*4882a593Smuzhiyun }
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun
enic_is_notify_intr(struct enic * enic,int intr)292*4882a593Smuzhiyun static inline bool enic_is_notify_intr(struct enic *enic, int intr)
293*4882a593Smuzhiyun {
294*4882a593Smuzhiyun switch (vnic_dev_get_intr_mode(enic->vdev)) {
295*4882a593Smuzhiyun case VNIC_DEV_INTR_MODE_INTX:
296*4882a593Smuzhiyun return intr == enic_legacy_notify_intr();
297*4882a593Smuzhiyun case VNIC_DEV_INTR_MODE_MSIX:
298*4882a593Smuzhiyun return intr == enic_msix_notify_intr(enic);
299*4882a593Smuzhiyun case VNIC_DEV_INTR_MODE_MSI:
300*4882a593Smuzhiyun default:
301*4882a593Smuzhiyun return false;
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun
enic_dma_map_check(struct enic * enic,dma_addr_t dma_addr)305*4882a593Smuzhiyun static inline int enic_dma_map_check(struct enic *enic, dma_addr_t dma_addr)
306*4882a593Smuzhiyun {
307*4882a593Smuzhiyun if (unlikely(pci_dma_mapping_error(enic->pdev, dma_addr))) {
308*4882a593Smuzhiyun net_warn_ratelimited("%s: PCI dma mapping failed!\n",
309*4882a593Smuzhiyun enic->netdev->name);
310*4882a593Smuzhiyun enic->gen_stats.dma_map_error++;
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun return -ENOMEM;
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun return 0;
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun void enic_reset_addr_lists(struct enic *enic);
319*4882a593Smuzhiyun int enic_sriov_enabled(struct enic *enic);
320*4882a593Smuzhiyun int enic_is_valid_vf(struct enic *enic, int vf);
321*4882a593Smuzhiyun int enic_is_dynamic(struct enic *enic);
322*4882a593Smuzhiyun void enic_set_ethtool_ops(struct net_device *netdev);
323*4882a593Smuzhiyun int __enic_set_rsskey(struct enic *enic);
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun #endif /* _ENIC_H_ */
326