1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet 3*4882a593Smuzhiyun * driver for Linux. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This software is available to you under a choice of one of two 8*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU 9*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file 10*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the 11*4882a593Smuzhiyun * OpenIB.org BSD license below: 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or 14*4882a593Smuzhiyun * without modification, are permitted provided that the following 15*4882a593Smuzhiyun * conditions are met: 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * - Redistributions of source code must retain the above 18*4882a593Smuzhiyun * copyright notice, this list of conditions and the following 19*4882a593Smuzhiyun * disclaimer. 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above 22*4882a593Smuzhiyun * copyright notice, this list of conditions and the following 23*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials 24*4882a593Smuzhiyun * provided with the distribution. 25*4882a593Smuzhiyun * 26*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 29*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 30*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 31*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33*4882a593Smuzhiyun * SOFTWARE. 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #ifndef __T4VF_DEFS_H__ 37*4882a593Smuzhiyun #define __T4VF_DEFS_H__ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #include "../cxgb4/t4_regs.h" 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* 42*4882a593Smuzhiyun * The VF Register Map. 43*4882a593Smuzhiyun * 44*4882a593Smuzhiyun * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local 45*4882a593Smuzhiyun * bus module (PL) and CPU Interface Module (CIM) components are mapped via 46*4882a593Smuzhiyun * the Slice to Module Map Table (see below) in the Physical Function Register 47*4882a593Smuzhiyun * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base 48*4882a593Smuzhiyun * and Offset registers in the PF Register Map. The MBDATA base address is 49*4882a593Smuzhiyun * quite constrained as it determines the Mailbox Data addresses for both PFs 50*4882a593Smuzhiyun * and VFs, and therefore must fit in both the VF and PF Register Maps without 51*4882a593Smuzhiyun * overlapping other registers. 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun #define T4VF_SGE_BASE_ADDR 0x0000 54*4882a593Smuzhiyun #define T4VF_MPS_BASE_ADDR 0x0100 55*4882a593Smuzhiyun #define T4VF_PL_BASE_ADDR 0x0200 56*4882a593Smuzhiyun #define T4VF_MBDATA_BASE_ADDR 0x0240 57*4882a593Smuzhiyun #define T6VF_MBDATA_BASE_ADDR 0x0280 58*4882a593Smuzhiyun #define T4VF_CIM_BASE_ADDR 0x0300 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define T4VF_REGMAP_START 0x0000 61*4882a593Smuzhiyun #define T4VF_REGMAP_SIZE 0x0400 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* 64*4882a593Smuzhiyun * There's no hardware limitation which requires that the addresses of the 65*4882a593Smuzhiyun * Mailbox Data in the fixed CIM PF map and the programmable VF map must 66*4882a593Smuzhiyun * match. However, it's a useful convention ... 67*4882a593Smuzhiyun */ 68*4882a593Smuzhiyun #if T4VF_MBDATA_BASE_ADDR != CIM_PF_MAILBOX_DATA_A 69*4882a593Smuzhiyun #error T4VF_MBDATA_BASE_ADDR must match CIM_PF_MAILBOX_DATA_A! 70*4882a593Smuzhiyun #endif 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* 73*4882a593Smuzhiyun * Virtual Function "Slice to Module Map Table" definitions. 74*4882a593Smuzhiyun * 75*4882a593Smuzhiyun * This table allows us to map subsets of the various module register sets 76*4882a593Smuzhiyun * into the T4VF Register Map. Each table entry identifies the index of the 77*4882a593Smuzhiyun * module whose registers are being mapped, the offset within the module's 78*4882a593Smuzhiyun * register set that the mapping should start at, the limit of the mapping, 79*4882a593Smuzhiyun * and the offset within the T4VF Register Map to which the module's registers 80*4882a593Smuzhiyun * are being mapped. All addresses and qualtities are in terms of 32-bit 81*4882a593Smuzhiyun * words. The "limit" value is also in terms of 32-bit words and is equal to 82*4882a593Smuzhiyun * the last address mapped in the T4VF Register Map 1 (i.e. it's a "<=" 83*4882a593Smuzhiyun * relation rather than a "<"). 84*4882a593Smuzhiyun */ 85*4882a593Smuzhiyun #define T4VF_MOD_MAP(module, index, first, last) \ 86*4882a593Smuzhiyun T4VF_MOD_MAP_##module##_INDEX = (index), \ 87*4882a593Smuzhiyun T4VF_MOD_MAP_##module##_FIRST = (first), \ 88*4882a593Smuzhiyun T4VF_MOD_MAP_##module##_LAST = (last), \ 89*4882a593Smuzhiyun T4VF_MOD_MAP_##module##_OFFSET = ((first)/4), \ 90*4882a593Smuzhiyun T4VF_MOD_MAP_##module##_BASE = \ 91*4882a593Smuzhiyun (T4VF_##module##_BASE_ADDR/4 + (first)/4), \ 92*4882a593Smuzhiyun T4VF_MOD_MAP_##module##_LIMIT = \ 93*4882a593Smuzhiyun (T4VF_##module##_BASE_ADDR/4 + (last)/4), 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define SGE_VF_KDOORBELL 0x0 96*4882a593Smuzhiyun #define SGE_VF_GTS 0x4 97*4882a593Smuzhiyun #define MPS_VF_CTL 0x0 98*4882a593Smuzhiyun #define MPS_VF_STAT_RX_VF_ERR_FRAMES_H 0xfc 99*4882a593Smuzhiyun #define PL_VF_WHOAMI 0x0 100*4882a593Smuzhiyun #define CIM_VF_EXT_MAILBOX_CTRL 0x0 101*4882a593Smuzhiyun #define CIM_VF_EXT_MAILBOX_STATUS 0x4 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun enum { 104*4882a593Smuzhiyun T4VF_MOD_MAP(SGE, 2, SGE_VF_KDOORBELL, SGE_VF_GTS) 105*4882a593Smuzhiyun T4VF_MOD_MAP(MPS, 0, MPS_VF_CTL, MPS_VF_STAT_RX_VF_ERR_FRAMES_H) 106*4882a593Smuzhiyun T4VF_MOD_MAP(PL, 3, PL_VF_WHOAMI, PL_VF_WHOAMI) 107*4882a593Smuzhiyun T4VF_MOD_MAP(CIM, 1, CIM_VF_EXT_MAILBOX_CTRL, CIM_VF_EXT_MAILBOX_STATUS) 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* 111*4882a593Smuzhiyun * There isn't a Slice to Module Map Table entry for the Mailbox Data 112*4882a593Smuzhiyun * registers, but it's convenient to use similar names as above. There are 8 113*4882a593Smuzhiyun * little-endian 64-bit Mailbox Data registers. Note that the "instances" 114*4882a593Smuzhiyun * value below is in terms of 32-bit words which matches the "word" addressing 115*4882a593Smuzhiyun * space we use above for the Slice to Module Map Space. 116*4882a593Smuzhiyun */ 117*4882a593Smuzhiyun #define NUM_CIM_VF_MAILBOX_DATA_INSTANCES 16 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define T4VF_MBDATA_FIRST 0 120*4882a593Smuzhiyun #define T4VF_MBDATA_LAST ((NUM_CIM_VF_MAILBOX_DATA_INSTANCES-1)*4) 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #endif /* __T4T4VF_DEFS_H__ */ 123