1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This file is part of the Chelsio T4/T5/T6 Ethernet driver for Linux. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (c) 2017 Chelsio Communications, Inc. All rights reserved. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This software is available to you under a choice of one of two 7*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU 8*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file 9*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the 10*4882a593Smuzhiyun * OpenIB.org BSD license below: 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or 13*4882a593Smuzhiyun * without modification, are permitted provided that the following 14*4882a593Smuzhiyun * conditions are met: 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * - Redistributions of source code must retain the above 17*4882a593Smuzhiyun * copyright notice, this list of conditions and the following 18*4882a593Smuzhiyun * disclaimer. 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above 21*4882a593Smuzhiyun * copyright notice, this list of conditions and the following 22*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials 23*4882a593Smuzhiyun * provided with the distribution. 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32*4882a593Smuzhiyun * SOFTWARE. 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #ifndef __T4_TCB_H 36*4882a593Smuzhiyun #define __T4_TCB_H 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define TCB_L2T_IX_W 0 39*4882a593Smuzhiyun #define TCB_L2T_IX_S 12 40*4882a593Smuzhiyun #define TCB_L2T_IX_M 0xfffULL 41*4882a593Smuzhiyun #define TCB_L2T_IX_V(x) ((x) << TCB_L2T_IX_S) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define TCB_T_FLAGS_W 1 44*4882a593Smuzhiyun #define TCB_T_FLAGS_S 0 45*4882a593Smuzhiyun #define TCB_T_FLAGS_M 0xffffffffffffffffULL 46*4882a593Smuzhiyun #define TCB_T_FLAGS_V(x) ((__u64)(x) << TCB_T_FLAGS_S) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define TCB_FIELD_COOKIE_TFLAG 1 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define TCB_SMAC_SEL_W 0 51*4882a593Smuzhiyun #define TCB_SMAC_SEL_S 24 52*4882a593Smuzhiyun #define TCB_SMAC_SEL_M 0xffULL 53*4882a593Smuzhiyun #define TCB_SMAC_SEL_V(x) ((x) << TCB_SMAC_SEL_S) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define TCB_T_FLAGS_W 1 56*4882a593Smuzhiyun #define TCB_T_FLAGS_S 0 57*4882a593Smuzhiyun #define TCB_T_FLAGS_M 0xffffffffffffffffULL 58*4882a593Smuzhiyun #define TCB_T_FLAGS_V(x) ((__u64)(x) << TCB_T_FLAGS_S) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define TF_DROP_S 22 61*4882a593Smuzhiyun #define TF_DIRECT_STEER_S 23 62*4882a593Smuzhiyun #define TF_LPBK_S 59 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define TF_CCTRL_ECE_S 60 65*4882a593Smuzhiyun #define TF_CCTRL_CWR_S 61 66*4882a593Smuzhiyun #define TF_CCTRL_RFR_S 62 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define TCB_RSS_INFO_W 3 69*4882a593Smuzhiyun #define TCB_RSS_INFO_S 0 70*4882a593Smuzhiyun #define TCB_RSS_INFO_M 0x3ffULL 71*4882a593Smuzhiyun #define TCB_RSS_INFO_V(x) ((x) << TCB_RSS_INFO_S) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define TCB_T_STATE_W 3 74*4882a593Smuzhiyun #define TCB_T_STATE_S 16 75*4882a593Smuzhiyun #define TCB_T_STATE_M 0xfULL 76*4882a593Smuzhiyun #define TCB_T_STATE_V(x) ((x) << TCB_T_STATE_S) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define TCB_TIMESTAMP_W 5 79*4882a593Smuzhiyun #define TCB_TIMESTAMP_S 0 80*4882a593Smuzhiyun #define TCB_TIMESTAMP_M 0xffffffffULL 81*4882a593Smuzhiyun #define TCB_TIMESTAMP_V(x) ((x) << TCB_TIMESTAMP_S) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define TCB_RTT_TS_RECENT_AGE_W 6 84*4882a593Smuzhiyun #define TCB_RTT_TS_RECENT_AGE_S 0 85*4882a593Smuzhiyun #define TCB_RTT_TS_RECENT_AGE_M 0xffffffffULL 86*4882a593Smuzhiyun #define TCB_RTT_TS_RECENT_AGE_V(x) ((x) << TCB_RTT_TS_RECENT_AGE_S) 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #define TCB_T_RTSEQ_RECENT_W 7 89*4882a593Smuzhiyun #define TCB_T_RTSEQ_RECENT_S 0 90*4882a593Smuzhiyun #define TCB_T_RTSEQ_RECENT_M 0xffffffffULL 91*4882a593Smuzhiyun #define TCB_T_RTSEQ_RECENT_V(x) ((x) << TCB_T_RTSEQ_RECENT_S) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define TCB_TX_MAX_W 9 94*4882a593Smuzhiyun #define TCB_TX_MAX_S 0 95*4882a593Smuzhiyun #define TCB_TX_MAX_M 0xffffffffULL 96*4882a593Smuzhiyun #define TCB_TX_MAX_V(x) ((x) << TCB_TX_MAX_S) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define TCB_SND_UNA_RAW_W 10 99*4882a593Smuzhiyun #define TCB_SND_UNA_RAW_S 0 100*4882a593Smuzhiyun #define TCB_SND_UNA_RAW_M 0xfffffffULL 101*4882a593Smuzhiyun #define TCB_SND_UNA_RAW_V(x) ((x) << TCB_SND_UNA_RAW_S) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define TCB_SND_NXT_RAW_W 10 104*4882a593Smuzhiyun #define TCB_SND_NXT_RAW_S 28 105*4882a593Smuzhiyun #define TCB_SND_NXT_RAW_M 0xfffffffULL 106*4882a593Smuzhiyun #define TCB_SND_NXT_RAW_V(x) ((x) << TCB_SND_NXT_RAW_S) 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define TCB_SND_MAX_RAW_W 11 109*4882a593Smuzhiyun #define TCB_SND_MAX_RAW_S 24 110*4882a593Smuzhiyun #define TCB_SND_MAX_RAW_M 0xfffffffULL 111*4882a593Smuzhiyun #define TCB_SND_MAX_RAW_V(x) ((x) << TCB_SND_MAX_RAW_S) 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define TCB_RCV_NXT_W 16 114*4882a593Smuzhiyun #define TCB_RCV_NXT_S 10 115*4882a593Smuzhiyun #define TCB_RCV_NXT_M 0xffffffffULL 116*4882a593Smuzhiyun #define TCB_RCV_NXT_V(x) ((x) << TCB_RCV_NXT_S) 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define TCB_RCV_WND_W 17 119*4882a593Smuzhiyun #define TCB_RCV_WND_S 10 120*4882a593Smuzhiyun #define TCB_RCV_WND_M 0xffffffULL 121*4882a593Smuzhiyun #define TCB_RCV_WND_V(x) ((x) << TCB_RCV_WND_S) 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #define TCB_RX_FRAG2_PTR_RAW_W 27 124*4882a593Smuzhiyun #define TCB_RX_FRAG3_LEN_RAW_W 29 125*4882a593Smuzhiyun #define TCB_RX_FRAG3_START_IDX_OFFSET_RAW_W 30 126*4882a593Smuzhiyun #define TCB_PDU_HDR_LEN_W 31 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #define TCB_RQ_START_W 30 129*4882a593Smuzhiyun #define TCB_RQ_START_S 0 130*4882a593Smuzhiyun #define TCB_RQ_START_M 0x3ffffffULL 131*4882a593Smuzhiyun #define TCB_RQ_START_V(x) ((x) << TCB_RQ_START_S) 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #define TF_RX_PDU_OUT_S 49 134*4882a593Smuzhiyun #define TF_RX_PDU_OUT_V(x) ((__u64)(x) << TF_RX_PDU_OUT_S) 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #define TF_CORE_BYPASS_S 63 137*4882a593Smuzhiyun #define TF_CORE_BYPASS_V(x) ((__u64)(x) << TF_CORE_BYPASS_S) 138*4882a593Smuzhiyun #define TF_CORE_BYPASS_F TF_CORE_BYPASS_V(1) 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun #define TF_NON_OFFLOAD_S 1 141*4882a593Smuzhiyun #define TF_NON_OFFLOAD_V(x) ((x) << TF_NON_OFFLOAD_S) 142*4882a593Smuzhiyun #define TF_NON_OFFLOAD_F TF_NON_OFFLOAD_V(1) 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #endif /* __T4_TCB_H */ 145