xref: /OK3568_Linux_fs/kernel/drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * This file is part of the Chelsio T4 Ethernet driver for Linux.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * This software is available to you under a choice of one of two
7*4882a593Smuzhiyun  * licenses.  You may choose to be licensed under the terms of the GNU
8*4882a593Smuzhiyun  * General Public License (GPL) Version 2, available from the file
9*4882a593Smuzhiyun  * COPYING in the main directory of this source tree, or the
10*4882a593Smuzhiyun  * OpenIB.org BSD license below:
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  *     Redistribution and use in source and binary forms, with or
13*4882a593Smuzhiyun  *     without modification, are permitted provided that the following
14*4882a593Smuzhiyun  *     conditions are met:
15*4882a593Smuzhiyun  *
16*4882a593Smuzhiyun  *      - Redistributions of source code must retain the above
17*4882a593Smuzhiyun  *        copyright notice, this list of conditions and the following
18*4882a593Smuzhiyun  *        disclaimer.
19*4882a593Smuzhiyun  *
20*4882a593Smuzhiyun  *      - Redistributions in binary form must reproduce the above
21*4882a593Smuzhiyun  *        copyright notice, this list of conditions and the following
22*4882a593Smuzhiyun  *        disclaimer in the documentation and/or other materials
23*4882a593Smuzhiyun  *        provided with the distribution.
24*4882a593Smuzhiyun  *
25*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26*4882a593Smuzhiyun  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27*4882a593Smuzhiyun  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28*4882a593Smuzhiyun  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29*4882a593Smuzhiyun  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30*4882a593Smuzhiyun  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31*4882a593Smuzhiyun  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32*4882a593Smuzhiyun  * SOFTWARE.
33*4882a593Smuzhiyun  */
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun #ifndef __CXGB4_ULD_H
36*4882a593Smuzhiyun #define __CXGB4_ULD_H
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #include <linux/cache.h>
39*4882a593Smuzhiyun #include <linux/spinlock.h>
40*4882a593Smuzhiyun #include <linux/skbuff.h>
41*4882a593Smuzhiyun #include <linux/inetdevice.h>
42*4882a593Smuzhiyun #include <linux/atomic.h>
43*4882a593Smuzhiyun #include <net/tls.h>
44*4882a593Smuzhiyun #include "cxgb4.h"
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun #define MAX_ULD_QSETS 16
47*4882a593Smuzhiyun #define MAX_ULD_NPORTS 4
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun /* ulp_mem_io + ulptx_idata + payload + padding */
50*4882a593Smuzhiyun #define MAX_IMM_ULPTX_WR_LEN (32 + 8 + 256 + 8)
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun /* CPL message priority levels */
53*4882a593Smuzhiyun enum {
54*4882a593Smuzhiyun 	CPL_PRIORITY_DATA     = 0,  /* data messages */
55*4882a593Smuzhiyun 	CPL_PRIORITY_SETUP    = 1,  /* connection setup messages */
56*4882a593Smuzhiyun 	CPL_PRIORITY_TEARDOWN = 0,  /* connection teardown messages */
57*4882a593Smuzhiyun 	CPL_PRIORITY_LISTEN   = 1,  /* listen start/stop messages */
58*4882a593Smuzhiyun 	CPL_PRIORITY_ACK      = 1,  /* RX ACK messages */
59*4882a593Smuzhiyun 	CPL_PRIORITY_CONTROL  = 1   /* control messages */
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun #define INIT_TP_WR(w, tid) do { \
63*4882a593Smuzhiyun 	(w)->wr.wr_hi = htonl(FW_WR_OP_V(FW_TP_WR) | \
64*4882a593Smuzhiyun 			      FW_WR_IMMDLEN_V(sizeof(*w) - sizeof(w->wr))); \
65*4882a593Smuzhiyun 	(w)->wr.wr_mid = htonl(FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*w), 16)) | \
66*4882a593Smuzhiyun 			       FW_WR_FLOWID_V(tid)); \
67*4882a593Smuzhiyun 	(w)->wr.wr_lo = cpu_to_be64(0); \
68*4882a593Smuzhiyun } while (0)
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun #define INIT_TP_WR_CPL(w, cpl, tid) do { \
71*4882a593Smuzhiyun 	INIT_TP_WR(w, tid); \
72*4882a593Smuzhiyun 	OPCODE_TID(w) = htonl(MK_OPCODE_TID(cpl, tid)); \
73*4882a593Smuzhiyun } while (0)
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun #define INIT_ULPTX_WR(w, wrlen, atomic, tid) do { \
76*4882a593Smuzhiyun 	(w)->wr.wr_hi = htonl(FW_WR_OP_V(FW_ULPTX_WR) | \
77*4882a593Smuzhiyun 			      FW_WR_ATOMIC_V(atomic)); \
78*4882a593Smuzhiyun 	(w)->wr.wr_mid = htonl(FW_WR_LEN16_V(DIV_ROUND_UP(wrlen, 16)) | \
79*4882a593Smuzhiyun 			       FW_WR_FLOWID_V(tid)); \
80*4882a593Smuzhiyun 	(w)->wr.wr_lo = cpu_to_be64(0); \
81*4882a593Smuzhiyun } while (0)
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun /* Special asynchronous notification message */
84*4882a593Smuzhiyun #define CXGB4_MSG_AN ((void *)1)
85*4882a593Smuzhiyun #define TX_ULD(uld)(((uld) != CXGB4_ULD_CRYPTO) ? CXGB4_TX_OFLD :\
86*4882a593Smuzhiyun 		      CXGB4_TX_CRYPTO)
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun struct serv_entry {
89*4882a593Smuzhiyun 	void *data;
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun union aopen_entry {
93*4882a593Smuzhiyun 	void *data;
94*4882a593Smuzhiyun 	union aopen_entry *next;
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun struct eotid_entry {
98*4882a593Smuzhiyun 	void *data;
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun /*
102*4882a593Smuzhiyun  * Holds the size, base address, free list start, etc of the TID, server TID,
103*4882a593Smuzhiyun  * and active-open TID tables.  The tables themselves are allocated dynamically.
104*4882a593Smuzhiyun  */
105*4882a593Smuzhiyun struct tid_info {
106*4882a593Smuzhiyun 	void **tid_tab;
107*4882a593Smuzhiyun 	unsigned int tid_base;
108*4882a593Smuzhiyun 	unsigned int ntids;
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	struct serv_entry *stid_tab;
111*4882a593Smuzhiyun 	unsigned long *stid_bmap;
112*4882a593Smuzhiyun 	unsigned int nstids;
113*4882a593Smuzhiyun 	unsigned int stid_base;
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	unsigned int nhash;
116*4882a593Smuzhiyun 	unsigned int hash_base;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	union aopen_entry *atid_tab;
119*4882a593Smuzhiyun 	unsigned int natids;
120*4882a593Smuzhiyun 	unsigned int atid_base;
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	struct filter_entry *hpftid_tab;
123*4882a593Smuzhiyun 	unsigned long *hpftid_bmap;
124*4882a593Smuzhiyun 	unsigned int nhpftids;
125*4882a593Smuzhiyun 	unsigned int hpftid_base;
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 	struct filter_entry *ftid_tab;
128*4882a593Smuzhiyun 	unsigned long *ftid_bmap;
129*4882a593Smuzhiyun 	unsigned int nftids;
130*4882a593Smuzhiyun 	unsigned int ftid_base;
131*4882a593Smuzhiyun 	unsigned int aftid_base;
132*4882a593Smuzhiyun 	unsigned int aftid_end;
133*4882a593Smuzhiyun 	/* Server filter region */
134*4882a593Smuzhiyun 	unsigned int sftid_base;
135*4882a593Smuzhiyun 	unsigned int nsftids;
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	spinlock_t atid_lock ____cacheline_aligned_in_smp;
138*4882a593Smuzhiyun 	union aopen_entry *afree;
139*4882a593Smuzhiyun 	unsigned int atids_in_use;
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	spinlock_t stid_lock;
142*4882a593Smuzhiyun 	unsigned int stids_in_use;
143*4882a593Smuzhiyun 	unsigned int v6_stids_in_use;
144*4882a593Smuzhiyun 	unsigned int sftids_in_use;
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	/* ETHOFLD range */
147*4882a593Smuzhiyun 	struct eotid_entry *eotid_tab;
148*4882a593Smuzhiyun 	unsigned long *eotid_bmap;
149*4882a593Smuzhiyun 	unsigned int eotid_base;
150*4882a593Smuzhiyun 	unsigned int neotids;
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	/* TIDs in the TCAM */
153*4882a593Smuzhiyun 	atomic_t tids_in_use;
154*4882a593Smuzhiyun 	/* TIDs in the HASH */
155*4882a593Smuzhiyun 	atomic_t hash_tids_in_use;
156*4882a593Smuzhiyun 	atomic_t conns_in_use;
157*4882a593Smuzhiyun 	/* ETHOFLD TIDs used for rate limiting */
158*4882a593Smuzhiyun 	atomic_t eotids_in_use;
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	/* lock for setting/clearing filter bitmap */
161*4882a593Smuzhiyun 	spinlock_t ftid_lock;
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	unsigned int tc_hash_tids_max_prio;
164*4882a593Smuzhiyun };
165*4882a593Smuzhiyun 
lookup_tid(const struct tid_info * t,unsigned int tid)166*4882a593Smuzhiyun static inline void *lookup_tid(const struct tid_info *t, unsigned int tid)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun 	tid -= t->tid_base;
169*4882a593Smuzhiyun 	return tid < t->ntids ? t->tid_tab[tid] : NULL;
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun 
tid_out_of_range(const struct tid_info * t,unsigned int tid)172*4882a593Smuzhiyun static inline bool tid_out_of_range(const struct tid_info *t, unsigned int tid)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun 	return ((tid - t->tid_base) >= t->ntids);
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun 
lookup_atid(const struct tid_info * t,unsigned int atid)177*4882a593Smuzhiyun static inline void *lookup_atid(const struct tid_info *t, unsigned int atid)
178*4882a593Smuzhiyun {
179*4882a593Smuzhiyun 	return atid < t->natids ? t->atid_tab[atid].data : NULL;
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun 
lookup_stid(const struct tid_info * t,unsigned int stid)182*4882a593Smuzhiyun static inline void *lookup_stid(const struct tid_info *t, unsigned int stid)
183*4882a593Smuzhiyun {
184*4882a593Smuzhiyun 	/* Is it a server filter TID? */
185*4882a593Smuzhiyun 	if (t->nsftids && (stid >= t->sftid_base)) {
186*4882a593Smuzhiyun 		stid -= t->sftid_base;
187*4882a593Smuzhiyun 		stid += t->nstids;
188*4882a593Smuzhiyun 	} else {
189*4882a593Smuzhiyun 		stid -= t->stid_base;
190*4882a593Smuzhiyun 	}
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	return stid < (t->nstids + t->nsftids) ? t->stid_tab[stid].data : NULL;
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun 
cxgb4_insert_tid(struct tid_info * t,void * data,unsigned int tid,unsigned short family)195*4882a593Smuzhiyun static inline void cxgb4_insert_tid(struct tid_info *t, void *data,
196*4882a593Smuzhiyun 				    unsigned int tid, unsigned short family)
197*4882a593Smuzhiyun {
198*4882a593Smuzhiyun 	t->tid_tab[tid - t->tid_base] = data;
199*4882a593Smuzhiyun 	if (t->hash_base && (tid >= t->hash_base)) {
200*4882a593Smuzhiyun 		if (family == AF_INET6)
201*4882a593Smuzhiyun 			atomic_add(2, &t->hash_tids_in_use);
202*4882a593Smuzhiyun 		else
203*4882a593Smuzhiyun 			atomic_inc(&t->hash_tids_in_use);
204*4882a593Smuzhiyun 	} else {
205*4882a593Smuzhiyun 		if (family == AF_INET6)
206*4882a593Smuzhiyun 			atomic_add(2, &t->tids_in_use);
207*4882a593Smuzhiyun 		else
208*4882a593Smuzhiyun 			atomic_inc(&t->tids_in_use);
209*4882a593Smuzhiyun 	}
210*4882a593Smuzhiyun 	atomic_inc(&t->conns_in_use);
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun 
cxgb4_lookup_eotid(struct tid_info * t,u32 eotid)213*4882a593Smuzhiyun static inline struct eotid_entry *cxgb4_lookup_eotid(struct tid_info *t,
214*4882a593Smuzhiyun 						     u32 eotid)
215*4882a593Smuzhiyun {
216*4882a593Smuzhiyun 	return eotid < t->neotids ? &t->eotid_tab[eotid] : NULL;
217*4882a593Smuzhiyun }
218*4882a593Smuzhiyun 
cxgb4_get_free_eotid(struct tid_info * t)219*4882a593Smuzhiyun static inline int cxgb4_get_free_eotid(struct tid_info *t)
220*4882a593Smuzhiyun {
221*4882a593Smuzhiyun 	int eotid;
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	eotid = find_first_zero_bit(t->eotid_bmap, t->neotids);
224*4882a593Smuzhiyun 	if (eotid >= t->neotids)
225*4882a593Smuzhiyun 		eotid = -1;
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 	return eotid;
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun 
cxgb4_alloc_eotid(struct tid_info * t,u32 eotid,void * data)230*4882a593Smuzhiyun static inline void cxgb4_alloc_eotid(struct tid_info *t, u32 eotid, void *data)
231*4882a593Smuzhiyun {
232*4882a593Smuzhiyun 	set_bit(eotid, t->eotid_bmap);
233*4882a593Smuzhiyun 	t->eotid_tab[eotid].data = data;
234*4882a593Smuzhiyun 	atomic_inc(&t->eotids_in_use);
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun 
cxgb4_free_eotid(struct tid_info * t,u32 eotid)237*4882a593Smuzhiyun static inline void cxgb4_free_eotid(struct tid_info *t, u32 eotid)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun 	clear_bit(eotid, t->eotid_bmap);
240*4882a593Smuzhiyun 	t->eotid_tab[eotid].data = NULL;
241*4882a593Smuzhiyun 	atomic_dec(&t->eotids_in_use);
242*4882a593Smuzhiyun }
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun int cxgb4_alloc_atid(struct tid_info *t, void *data);
245*4882a593Smuzhiyun int cxgb4_alloc_stid(struct tid_info *t, int family, void *data);
246*4882a593Smuzhiyun int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data);
247*4882a593Smuzhiyun void cxgb4_free_atid(struct tid_info *t, unsigned int atid);
248*4882a593Smuzhiyun void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family);
249*4882a593Smuzhiyun void cxgb4_remove_tid(struct tid_info *t, unsigned int qid, unsigned int tid,
250*4882a593Smuzhiyun 		      unsigned short family);
251*4882a593Smuzhiyun struct in6_addr;
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
254*4882a593Smuzhiyun 			__be32 sip, __be16 sport, __be16 vlan,
255*4882a593Smuzhiyun 			unsigned int queue);
256*4882a593Smuzhiyun int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
257*4882a593Smuzhiyun 			 const struct in6_addr *sip, __be16 sport,
258*4882a593Smuzhiyun 			 unsigned int queue);
259*4882a593Smuzhiyun int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
260*4882a593Smuzhiyun 			unsigned int queue, bool ipv6);
261*4882a593Smuzhiyun int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
262*4882a593Smuzhiyun 			       __be32 sip, __be16 sport, __be16 vlan,
263*4882a593Smuzhiyun 			       unsigned int queue,
264*4882a593Smuzhiyun 			       unsigned char port, unsigned char mask);
265*4882a593Smuzhiyun int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
266*4882a593Smuzhiyun 			       unsigned int queue, bool ipv6);
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun /* Filter operation context to allow callers of cxgb4_set_filter() and
269*4882a593Smuzhiyun  * cxgb4_del_filter() to wait for an asynchronous completion.
270*4882a593Smuzhiyun  */
271*4882a593Smuzhiyun struct filter_ctx {
272*4882a593Smuzhiyun 	struct completion completion;	/* completion rendezvous */
273*4882a593Smuzhiyun 	void *closure;			/* caller's opaque information */
274*4882a593Smuzhiyun 	int result;			/* result of operation */
275*4882a593Smuzhiyun 	u32 tid;			/* to store tid */
276*4882a593Smuzhiyun };
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun struct chcr_ktls {
279*4882a593Smuzhiyun 	refcount_t ktls_refcount;
280*4882a593Smuzhiyun };
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun struct ch_filter_specification;
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun int cxgb4_get_free_ftid(struct net_device *dev, u8 family, bool hash_en,
285*4882a593Smuzhiyun 			u32 tc_prio);
286*4882a593Smuzhiyun int __cxgb4_set_filter(struct net_device *dev, int filter_id,
287*4882a593Smuzhiyun 		       struct ch_filter_specification *fs,
288*4882a593Smuzhiyun 		       struct filter_ctx *ctx);
289*4882a593Smuzhiyun int __cxgb4_del_filter(struct net_device *dev, int filter_id,
290*4882a593Smuzhiyun 		       struct ch_filter_specification *fs,
291*4882a593Smuzhiyun 		       struct filter_ctx *ctx);
292*4882a593Smuzhiyun int cxgb4_set_filter(struct net_device *dev, int filter_id,
293*4882a593Smuzhiyun 		     struct ch_filter_specification *fs);
294*4882a593Smuzhiyun int cxgb4_del_filter(struct net_device *dev, int filter_id,
295*4882a593Smuzhiyun 		     struct ch_filter_specification *fs);
296*4882a593Smuzhiyun int cxgb4_get_filter_counters(struct net_device *dev, unsigned int fidx,
297*4882a593Smuzhiyun 			      u64 *hitcnt, u64 *bytecnt, bool hash);
298*4882a593Smuzhiyun 
set_wr_txq(struct sk_buff * skb,int prio,int queue)299*4882a593Smuzhiyun static inline void set_wr_txq(struct sk_buff *skb, int prio, int queue)
300*4882a593Smuzhiyun {
301*4882a593Smuzhiyun 	skb_set_queue_mapping(skb, (queue << 1) | prio);
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun enum cxgb4_uld {
305*4882a593Smuzhiyun 	CXGB4_ULD_INIT,
306*4882a593Smuzhiyun 	CXGB4_ULD_RDMA,
307*4882a593Smuzhiyun 	CXGB4_ULD_ISCSI,
308*4882a593Smuzhiyun 	CXGB4_ULD_ISCSIT,
309*4882a593Smuzhiyun 	CXGB4_ULD_CRYPTO,
310*4882a593Smuzhiyun 	CXGB4_ULD_IPSEC,
311*4882a593Smuzhiyun 	CXGB4_ULD_TLS,
312*4882a593Smuzhiyun 	CXGB4_ULD_KTLS,
313*4882a593Smuzhiyun 	CXGB4_ULD_MAX
314*4882a593Smuzhiyun };
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun enum cxgb4_tx_uld {
317*4882a593Smuzhiyun 	CXGB4_TX_OFLD,
318*4882a593Smuzhiyun 	CXGB4_TX_CRYPTO,
319*4882a593Smuzhiyun 	CXGB4_TX_MAX
320*4882a593Smuzhiyun };
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun enum cxgb4_txq_type {
323*4882a593Smuzhiyun 	CXGB4_TXQ_ETH,
324*4882a593Smuzhiyun 	CXGB4_TXQ_ULD,
325*4882a593Smuzhiyun 	CXGB4_TXQ_CTRL,
326*4882a593Smuzhiyun 	CXGB4_TXQ_MAX
327*4882a593Smuzhiyun };
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun enum cxgb4_state {
330*4882a593Smuzhiyun 	CXGB4_STATE_UP,
331*4882a593Smuzhiyun 	CXGB4_STATE_START_RECOVERY,
332*4882a593Smuzhiyun 	CXGB4_STATE_DOWN,
333*4882a593Smuzhiyun 	CXGB4_STATE_DETACH,
334*4882a593Smuzhiyun 	CXGB4_STATE_FATAL_ERROR
335*4882a593Smuzhiyun };
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun enum cxgb4_control {
338*4882a593Smuzhiyun 	CXGB4_CONTROL_DB_FULL,
339*4882a593Smuzhiyun 	CXGB4_CONTROL_DB_EMPTY,
340*4882a593Smuzhiyun 	CXGB4_CONTROL_DB_DROP,
341*4882a593Smuzhiyun };
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun struct adapter;
344*4882a593Smuzhiyun struct pci_dev;
345*4882a593Smuzhiyun struct l2t_data;
346*4882a593Smuzhiyun struct net_device;
347*4882a593Smuzhiyun struct pkt_gl;
348*4882a593Smuzhiyun struct tp_tcp_stats;
349*4882a593Smuzhiyun struct t4_lro_mgr;
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun struct cxgb4_range {
352*4882a593Smuzhiyun 	unsigned int start;
353*4882a593Smuzhiyun 	unsigned int size;
354*4882a593Smuzhiyun };
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun struct cxgb4_virt_res {                      /* virtualized HW resources */
357*4882a593Smuzhiyun 	struct cxgb4_range ddp;
358*4882a593Smuzhiyun 	struct cxgb4_range iscsi;
359*4882a593Smuzhiyun 	struct cxgb4_range stag;
360*4882a593Smuzhiyun 	struct cxgb4_range rq;
361*4882a593Smuzhiyun 	struct cxgb4_range srq;
362*4882a593Smuzhiyun 	struct cxgb4_range pbl;
363*4882a593Smuzhiyun 	struct cxgb4_range qp;
364*4882a593Smuzhiyun 	struct cxgb4_range cq;
365*4882a593Smuzhiyun 	struct cxgb4_range ocq;
366*4882a593Smuzhiyun 	struct cxgb4_range key;
367*4882a593Smuzhiyun 	unsigned int ncrypto_fc;
368*4882a593Smuzhiyun 	struct cxgb4_range ppod_edram;
369*4882a593Smuzhiyun };
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_CHELSIO_TLS_DEVICE)
372*4882a593Smuzhiyun struct ch_ktls_port_stats_debug {
373*4882a593Smuzhiyun 	atomic64_t ktls_tx_connection_open;
374*4882a593Smuzhiyun 	atomic64_t ktls_tx_connection_fail;
375*4882a593Smuzhiyun 	atomic64_t ktls_tx_connection_close;
376*4882a593Smuzhiyun 	atomic64_t ktls_tx_encrypted_packets;
377*4882a593Smuzhiyun 	atomic64_t ktls_tx_encrypted_bytes;
378*4882a593Smuzhiyun 	atomic64_t ktls_tx_ctx;
379*4882a593Smuzhiyun 	atomic64_t ktls_tx_ooo;
380*4882a593Smuzhiyun 	atomic64_t ktls_tx_skip_no_sync_data;
381*4882a593Smuzhiyun 	atomic64_t ktls_tx_drop_no_sync_data;
382*4882a593Smuzhiyun 	atomic64_t ktls_tx_drop_bypass_req;
383*4882a593Smuzhiyun };
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun struct ch_ktls_stats_debug {
386*4882a593Smuzhiyun 	struct ch_ktls_port_stats_debug ktls_port[MAX_ULD_NPORTS];
387*4882a593Smuzhiyun 	atomic64_t ktls_tx_send_records;
388*4882a593Smuzhiyun 	atomic64_t ktls_tx_end_pkts;
389*4882a593Smuzhiyun 	atomic64_t ktls_tx_start_pkts;
390*4882a593Smuzhiyun 	atomic64_t ktls_tx_middle_pkts;
391*4882a593Smuzhiyun 	atomic64_t ktls_tx_retransmit_pkts;
392*4882a593Smuzhiyun 	atomic64_t ktls_tx_complete_pkts;
393*4882a593Smuzhiyun 	atomic64_t ktls_tx_trimmed_pkts;
394*4882a593Smuzhiyun 	atomic64_t ktls_tx_fallback;
395*4882a593Smuzhiyun };
396*4882a593Smuzhiyun #endif
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun struct chcr_stats_debug {
399*4882a593Smuzhiyun 	atomic_t cipher_rqst;
400*4882a593Smuzhiyun 	atomic_t digest_rqst;
401*4882a593Smuzhiyun 	atomic_t aead_rqst;
402*4882a593Smuzhiyun 	atomic_t complete;
403*4882a593Smuzhiyun 	atomic_t error;
404*4882a593Smuzhiyun 	atomic_t fallback;
405*4882a593Smuzhiyun 	atomic_t tls_pdu_tx;
406*4882a593Smuzhiyun 	atomic_t tls_pdu_rx;
407*4882a593Smuzhiyun 	atomic_t tls_key;
408*4882a593Smuzhiyun };
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_CHELSIO_IPSEC_INLINE)
411*4882a593Smuzhiyun struct ch_ipsec_stats_debug {
412*4882a593Smuzhiyun 	atomic_t ipsec_cnt;
413*4882a593Smuzhiyun };
414*4882a593Smuzhiyun #endif
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun #define OCQ_WIN_OFFSET(pdev, vres) \
417*4882a593Smuzhiyun 	(pci_resource_len((pdev), 2) - roundup_pow_of_two((vres)->ocq.size))
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun /*
420*4882a593Smuzhiyun  * Block of information the LLD provides to ULDs attaching to a device.
421*4882a593Smuzhiyun  */
422*4882a593Smuzhiyun struct cxgb4_lld_info {
423*4882a593Smuzhiyun 	struct pci_dev *pdev;                /* associated PCI device */
424*4882a593Smuzhiyun 	struct l2t_data *l2t;                /* L2 table */
425*4882a593Smuzhiyun 	struct tid_info *tids;               /* TID table */
426*4882a593Smuzhiyun 	struct net_device **ports;           /* device ports */
427*4882a593Smuzhiyun 	const struct cxgb4_virt_res *vr;     /* assorted HW resources */
428*4882a593Smuzhiyun 	const unsigned short *mtus;          /* MTU table */
429*4882a593Smuzhiyun 	const unsigned short *rxq_ids;       /* the ULD's Rx queue ids */
430*4882a593Smuzhiyun 	const unsigned short *ciq_ids;       /* the ULD's concentrator IQ ids */
431*4882a593Smuzhiyun 	unsigned short nrxq;                 /* # of Rx queues */
432*4882a593Smuzhiyun 	unsigned short ntxq;                 /* # of Tx queues */
433*4882a593Smuzhiyun 	unsigned short nciq;		     /* # of concentrator IQ */
434*4882a593Smuzhiyun 	unsigned char nchan:4;               /* # of channels */
435*4882a593Smuzhiyun 	unsigned char nports:4;              /* # of ports */
436*4882a593Smuzhiyun 	unsigned char wr_cred;               /* WR 16-byte credits */
437*4882a593Smuzhiyun 	unsigned char adapter_type;          /* type of adapter */
438*4882a593Smuzhiyun 	unsigned char fw_api_ver;            /* FW API version */
439*4882a593Smuzhiyun 	unsigned char crypto;                /* crypto support */
440*4882a593Smuzhiyun 	unsigned int fw_vers;                /* FW version */
441*4882a593Smuzhiyun 	unsigned int iscsi_iolen;            /* iSCSI max I/O length */
442*4882a593Smuzhiyun 	unsigned int cclk_ps;                /* Core clock period in psec */
443*4882a593Smuzhiyun 	unsigned short udb_density;          /* # of user DB/page */
444*4882a593Smuzhiyun 	unsigned short ucq_density;          /* # of user CQs/page */
445*4882a593Smuzhiyun 	unsigned int sge_host_page_size;     /* SGE host page size */
446*4882a593Smuzhiyun 	unsigned short filt_mode;            /* filter optional components */
447*4882a593Smuzhiyun 	unsigned short tx_modq[NCHAN];       /* maps each tx channel to a */
448*4882a593Smuzhiyun 					     /* scheduler queue */
449*4882a593Smuzhiyun 	void __iomem *gts_reg;               /* address of GTS register */
450*4882a593Smuzhiyun 	void __iomem *db_reg;                /* address of kernel doorbell */
451*4882a593Smuzhiyun 	int dbfifo_int_thresh;		     /* doorbell fifo int threshold */
452*4882a593Smuzhiyun 	unsigned int sge_ingpadboundary;     /* SGE ingress padding boundary */
453*4882a593Smuzhiyun 	unsigned int sge_egrstatuspagesize;  /* SGE egress status page size */
454*4882a593Smuzhiyun 	unsigned int sge_pktshift;           /* Padding between CPL and */
455*4882a593Smuzhiyun 					     /*	packet data */
456*4882a593Smuzhiyun 	unsigned int pf;		     /* Physical Function we're using */
457*4882a593Smuzhiyun 	bool enable_fw_ofld_conn;            /* Enable connection through fw */
458*4882a593Smuzhiyun 					     /* WR */
459*4882a593Smuzhiyun 	unsigned int max_ordird_qp;          /* Max ORD/IRD depth per RDMA QP */
460*4882a593Smuzhiyun 	unsigned int max_ird_adapter;        /* Max IRD memory per adapter */
461*4882a593Smuzhiyun 	bool ulptx_memwrite_dsgl;            /* use of T5 DSGL allowed */
462*4882a593Smuzhiyun 	unsigned int iscsi_tagmask;	     /* iscsi ddp tag mask */
463*4882a593Smuzhiyun 	unsigned int iscsi_pgsz_order;	     /* iscsi ddp page size orders */
464*4882a593Smuzhiyun 	unsigned int iscsi_llimit;	     /* chip's iscsi region llimit */
465*4882a593Smuzhiyun 	unsigned int ulp_crypto;             /* crypto lookaside support */
466*4882a593Smuzhiyun 	void **iscsi_ppm;		     /* iscsi page pod manager */
467*4882a593Smuzhiyun 	int nodeid;			     /* device numa node id */
468*4882a593Smuzhiyun 	bool fr_nsmr_tpte_wr_support;	     /* FW supports FR_NSMR_TPTE_WR */
469*4882a593Smuzhiyun 	bool write_w_imm_support;         /* FW supports WRITE_WITH_IMMEDIATE */
470*4882a593Smuzhiyun 	bool write_cmpl_support;             /* FW supports WRITE_CMPL WR */
471*4882a593Smuzhiyun };
472*4882a593Smuzhiyun 
473*4882a593Smuzhiyun struct cxgb4_uld_info {
474*4882a593Smuzhiyun 	char name[IFNAMSIZ];
475*4882a593Smuzhiyun 	void *handle;
476*4882a593Smuzhiyun 	unsigned int nrxq;
477*4882a593Smuzhiyun 	unsigned int rxq_size;
478*4882a593Smuzhiyun 	unsigned int ntxq;
479*4882a593Smuzhiyun 	bool ciq;
480*4882a593Smuzhiyun 	bool lro;
481*4882a593Smuzhiyun 	void *(*add)(const struct cxgb4_lld_info *p);
482*4882a593Smuzhiyun 	int (*rx_handler)(void *handle, const __be64 *rsp,
483*4882a593Smuzhiyun 			  const struct pkt_gl *gl);
484*4882a593Smuzhiyun 	int (*state_change)(void *handle, enum cxgb4_state new_state);
485*4882a593Smuzhiyun 	int (*control)(void *handle, enum cxgb4_control control, ...);
486*4882a593Smuzhiyun 	int (*lro_rx_handler)(void *handle, const __be64 *rsp,
487*4882a593Smuzhiyun 			      const struct pkt_gl *gl,
488*4882a593Smuzhiyun 			      struct t4_lro_mgr *lro_mgr,
489*4882a593Smuzhiyun 			      struct napi_struct *napi);
490*4882a593Smuzhiyun 	void (*lro_flush)(struct t4_lro_mgr *);
491*4882a593Smuzhiyun 	int (*tx_handler)(struct sk_buff *skb, struct net_device *dev);
492*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_CHELSIO_TLS_DEVICE)
493*4882a593Smuzhiyun 	const struct tlsdev_ops *tlsdev_ops;
494*4882a593Smuzhiyun #endif
495*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_XFRM_OFFLOAD)
496*4882a593Smuzhiyun 	const struct xfrmdev_ops *xfrmdev_ops;
497*4882a593Smuzhiyun #endif
498*4882a593Smuzhiyun };
499*4882a593Smuzhiyun 
cxgb4_is_ktls_skb(struct sk_buff * skb)500*4882a593Smuzhiyun static inline bool cxgb4_is_ktls_skb(struct sk_buff *skb)
501*4882a593Smuzhiyun {
502*4882a593Smuzhiyun 	return skb->sk && tls_is_sk_tx_device_offloaded(skb->sk);
503*4882a593Smuzhiyun }
504*4882a593Smuzhiyun 
505*4882a593Smuzhiyun void cxgb4_uld_enable(struct adapter *adap);
506*4882a593Smuzhiyun void cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p);
507*4882a593Smuzhiyun int cxgb4_unregister_uld(enum cxgb4_uld type);
508*4882a593Smuzhiyun int cxgb4_ofld_send(struct net_device *dev, struct sk_buff *skb);
509*4882a593Smuzhiyun int cxgb4_immdata_send(struct net_device *dev, unsigned int idx,
510*4882a593Smuzhiyun 		       const void *src, unsigned int len);
511*4882a593Smuzhiyun int cxgb4_crypto_send(struct net_device *dev, struct sk_buff *skb);
512*4882a593Smuzhiyun unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo);
513*4882a593Smuzhiyun unsigned int cxgb4_port_chan(const struct net_device *dev);
514*4882a593Smuzhiyun unsigned int cxgb4_port_e2cchan(const struct net_device *dev);
515*4882a593Smuzhiyun unsigned int cxgb4_port_viid(const struct net_device *dev);
516*4882a593Smuzhiyun unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid);
517*4882a593Smuzhiyun unsigned int cxgb4_port_idx(const struct net_device *dev);
518*4882a593Smuzhiyun unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
519*4882a593Smuzhiyun 			    unsigned int *idx);
520*4882a593Smuzhiyun unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
521*4882a593Smuzhiyun 				    unsigned short header_size,
522*4882a593Smuzhiyun 				    unsigned short data_size_max,
523*4882a593Smuzhiyun 				    unsigned short data_size_align,
524*4882a593Smuzhiyun 				    unsigned int *mtu_idxp);
525*4882a593Smuzhiyun void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
526*4882a593Smuzhiyun 			 struct tp_tcp_stats *v6);
527*4882a593Smuzhiyun void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
528*4882a593Smuzhiyun 		      const unsigned int *pgsz_order);
529*4882a593Smuzhiyun struct sk_buff *cxgb4_pktgl_to_skb(const struct pkt_gl *gl,
530*4882a593Smuzhiyun 				   unsigned int skb_len, unsigned int pull_len);
531*4882a593Smuzhiyun int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx, u16 size);
532*4882a593Smuzhiyun int cxgb4_flush_eq_cache(struct net_device *dev);
533*4882a593Smuzhiyun int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte);
534*4882a593Smuzhiyun u64 cxgb4_read_sge_timestamp(struct net_device *dev);
535*4882a593Smuzhiyun 
536*4882a593Smuzhiyun enum cxgb4_bar2_qtype { CXGB4_BAR2_QTYPE_EGRESS, CXGB4_BAR2_QTYPE_INGRESS };
537*4882a593Smuzhiyun int cxgb4_bar2_sge_qregs(struct net_device *dev,
538*4882a593Smuzhiyun 			 unsigned int qid,
539*4882a593Smuzhiyun 			 enum cxgb4_bar2_qtype qtype,
540*4882a593Smuzhiyun 			 int user,
541*4882a593Smuzhiyun 			 u64 *pbar2_qoffset,
542*4882a593Smuzhiyun 			 unsigned int *pbar2_qid);
543*4882a593Smuzhiyun 
544*4882a593Smuzhiyun #endif  /* !__CXGB4_ULD_H */
545