xref: /OK3568_Linux_fs/kernel/drivers/net/ethernet/chelsio/cxgb4/cxgb4_dcb.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  Copyright (C) 2013-2014 Chelsio Communications.  All rights reserved.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *  Written by Anish Bhatt (anish@chelsio.com)
6*4882a593Smuzhiyun  *	       Casey Leedom (leedom@chelsio.com)
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include "cxgb4.h"
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun /* DCBx version control
12*4882a593Smuzhiyun  */
13*4882a593Smuzhiyun const char * const dcb_ver_array[] = {
14*4882a593Smuzhiyun 	"Unknown",
15*4882a593Smuzhiyun 	"DCBx-CIN",
16*4882a593Smuzhiyun 	"DCBx-CEE 1.01",
17*4882a593Smuzhiyun 	"DCBx-IEEE",
18*4882a593Smuzhiyun 	"", "", "",
19*4882a593Smuzhiyun 	"Auto Negotiated"
20*4882a593Smuzhiyun };
21*4882a593Smuzhiyun 
cxgb4_dcb_state_synced(enum cxgb4_dcb_state state)22*4882a593Smuzhiyun static inline bool cxgb4_dcb_state_synced(enum cxgb4_dcb_state state)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun 	if (state == CXGB4_DCB_STATE_FW_ALLSYNCED ||
25*4882a593Smuzhiyun 	    state == CXGB4_DCB_STATE_HOST)
26*4882a593Smuzhiyun 		return true;
27*4882a593Smuzhiyun 	else
28*4882a593Smuzhiyun 		return false;
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun /* Initialize a port's Data Center Bridging state.
32*4882a593Smuzhiyun  */
cxgb4_dcb_state_init(struct net_device * dev)33*4882a593Smuzhiyun void cxgb4_dcb_state_init(struct net_device *dev)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
36*4882a593Smuzhiyun 	struct port_dcb_info *dcb = &pi->dcb;
37*4882a593Smuzhiyun 	int version_temp = dcb->dcb_version;
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun 	memset(dcb, 0, sizeof(struct port_dcb_info));
40*4882a593Smuzhiyun 	dcb->state = CXGB4_DCB_STATE_START;
41*4882a593Smuzhiyun 	if (version_temp)
42*4882a593Smuzhiyun 		dcb->dcb_version = version_temp;
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun 	netdev_dbg(dev, "%s: Initializing DCB state for port[%d]\n",
45*4882a593Smuzhiyun 		    __func__, pi->port_id);
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun 
cxgb4_dcb_version_init(struct net_device * dev)48*4882a593Smuzhiyun void cxgb4_dcb_version_init(struct net_device *dev)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
51*4882a593Smuzhiyun 	struct port_dcb_info *dcb = &pi->dcb;
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun 	/* Any writes here are only done on kernels that exlicitly need
54*4882a593Smuzhiyun 	 * a specific version, say < 2.6.38 which only support CEE
55*4882a593Smuzhiyun 	 */
56*4882a593Smuzhiyun 	dcb->dcb_version = FW_PORT_DCB_VER_AUTO;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun 
cxgb4_dcb_cleanup_apps(struct net_device * dev)59*4882a593Smuzhiyun static void cxgb4_dcb_cleanup_apps(struct net_device *dev)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
62*4882a593Smuzhiyun 	struct adapter *adap = pi->adapter;
63*4882a593Smuzhiyun 	struct port_dcb_info *dcb = &pi->dcb;
64*4882a593Smuzhiyun 	struct dcb_app app;
65*4882a593Smuzhiyun 	int i, err;
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	/* zero priority implies remove */
68*4882a593Smuzhiyun 	app.priority = 0;
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 	for (i = 0; i < CXGB4_MAX_DCBX_APP_SUPPORTED; i++) {
71*4882a593Smuzhiyun 		/* Check if app list is exhausted */
72*4882a593Smuzhiyun 		if (!dcb->app_priority[i].protocolid)
73*4882a593Smuzhiyun 			break;
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun 		app.protocol = dcb->app_priority[i].protocolid;
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 		if (dcb->dcb_version == FW_PORT_DCB_VER_IEEE) {
78*4882a593Smuzhiyun 			app.priority = dcb->app_priority[i].user_prio_map;
79*4882a593Smuzhiyun 			app.selector = dcb->app_priority[i].sel_field + 1;
80*4882a593Smuzhiyun 			err = dcb_ieee_delapp(dev, &app);
81*4882a593Smuzhiyun 		} else {
82*4882a593Smuzhiyun 			app.selector = !!(dcb->app_priority[i].sel_field);
83*4882a593Smuzhiyun 			err = dcb_setapp(dev, &app);
84*4882a593Smuzhiyun 		}
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 		if (err) {
87*4882a593Smuzhiyun 			dev_err(adap->pdev_dev,
88*4882a593Smuzhiyun 				"Failed DCB Clear %s Application Priority: sel=%d, prot=%d, , err=%d\n",
89*4882a593Smuzhiyun 				dcb_ver_array[dcb->dcb_version], app.selector,
90*4882a593Smuzhiyun 				app.protocol, -err);
91*4882a593Smuzhiyun 			break;
92*4882a593Smuzhiyun 		}
93*4882a593Smuzhiyun 	}
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun /* Reset a port's Data Center Bridging state.  Typically used after a
97*4882a593Smuzhiyun  * Link Down event.
98*4882a593Smuzhiyun  */
cxgb4_dcb_reset(struct net_device * dev)99*4882a593Smuzhiyun void cxgb4_dcb_reset(struct net_device *dev)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun 	cxgb4_dcb_cleanup_apps(dev);
102*4882a593Smuzhiyun 	cxgb4_dcb_state_init(dev);
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun /* update the dcb port support, if version is IEEE then set it to
106*4882a593Smuzhiyun  * FW_PORT_DCB_VER_IEEE and if DCB_CAP_DCBX_VER_CEE is already set then
107*4882a593Smuzhiyun  * clear that. and if it is set to CEE then set dcb supported to
108*4882a593Smuzhiyun  * DCB_CAP_DCBX_VER_CEE & if DCB_CAP_DCBX_VER_IEEE is set, clear it
109*4882a593Smuzhiyun  */
cxgb4_dcb_update_support(struct port_dcb_info * dcb)110*4882a593Smuzhiyun static inline void cxgb4_dcb_update_support(struct port_dcb_info *dcb)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun 	if (dcb->dcb_version == FW_PORT_DCB_VER_IEEE) {
113*4882a593Smuzhiyun 		if (dcb->supported & DCB_CAP_DCBX_VER_CEE)
114*4882a593Smuzhiyun 			dcb->supported &= ~DCB_CAP_DCBX_VER_CEE;
115*4882a593Smuzhiyun 		dcb->supported |= DCB_CAP_DCBX_VER_IEEE;
116*4882a593Smuzhiyun 	} else if (dcb->dcb_version == FW_PORT_DCB_VER_CEE1D01) {
117*4882a593Smuzhiyun 		if (dcb->supported & DCB_CAP_DCBX_VER_IEEE)
118*4882a593Smuzhiyun 			dcb->supported &= ~DCB_CAP_DCBX_VER_IEEE;
119*4882a593Smuzhiyun 		dcb->supported |= DCB_CAP_DCBX_VER_CEE;
120*4882a593Smuzhiyun 	}
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun /* Finite State machine for Data Center Bridging.
124*4882a593Smuzhiyun  */
cxgb4_dcb_state_fsm(struct net_device * dev,enum cxgb4_dcb_state_input transition_to)125*4882a593Smuzhiyun void cxgb4_dcb_state_fsm(struct net_device *dev,
126*4882a593Smuzhiyun 			 enum cxgb4_dcb_state_input transition_to)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
129*4882a593Smuzhiyun 	struct port_dcb_info *dcb = &pi->dcb;
130*4882a593Smuzhiyun 	struct adapter *adap = pi->adapter;
131*4882a593Smuzhiyun 	enum cxgb4_dcb_state current_state = dcb->state;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	netdev_dbg(dev, "%s: State change from %d to %d for %s\n",
134*4882a593Smuzhiyun 		    __func__, dcb->state, transition_to, dev->name);
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	switch (current_state) {
137*4882a593Smuzhiyun 	case CXGB4_DCB_STATE_START: {
138*4882a593Smuzhiyun 		switch (transition_to) {
139*4882a593Smuzhiyun 		case CXGB4_DCB_INPUT_FW_DISABLED: {
140*4882a593Smuzhiyun 			/* we're going to use Host DCB */
141*4882a593Smuzhiyun 			dcb->state = CXGB4_DCB_STATE_HOST;
142*4882a593Smuzhiyun 			dcb->supported = CXGB4_DCBX_HOST_SUPPORT;
143*4882a593Smuzhiyun 			break;
144*4882a593Smuzhiyun 		}
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 		case CXGB4_DCB_INPUT_FW_ENABLED: {
147*4882a593Smuzhiyun 			/* we're going to use Firmware DCB */
148*4882a593Smuzhiyun 			dcb->state = CXGB4_DCB_STATE_FW_INCOMPLETE;
149*4882a593Smuzhiyun 			dcb->supported = DCB_CAP_DCBX_LLD_MANAGED;
150*4882a593Smuzhiyun 			if (dcb->dcb_version == FW_PORT_DCB_VER_IEEE)
151*4882a593Smuzhiyun 				dcb->supported |= DCB_CAP_DCBX_VER_IEEE;
152*4882a593Smuzhiyun 			else
153*4882a593Smuzhiyun 				dcb->supported |= DCB_CAP_DCBX_VER_CEE;
154*4882a593Smuzhiyun 			break;
155*4882a593Smuzhiyun 		}
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 		case CXGB4_DCB_INPUT_FW_INCOMPLETE: {
158*4882a593Smuzhiyun 			/* expected transition */
159*4882a593Smuzhiyun 			break;
160*4882a593Smuzhiyun 		}
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 		case CXGB4_DCB_INPUT_FW_ALLSYNCED: {
163*4882a593Smuzhiyun 			dcb->state = CXGB4_DCB_STATE_FW_ALLSYNCED;
164*4882a593Smuzhiyun 			break;
165*4882a593Smuzhiyun 		}
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 		default:
168*4882a593Smuzhiyun 			goto bad_state_input;
169*4882a593Smuzhiyun 		}
170*4882a593Smuzhiyun 		break;
171*4882a593Smuzhiyun 	}
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	case CXGB4_DCB_STATE_FW_INCOMPLETE: {
174*4882a593Smuzhiyun 		if (transition_to != CXGB4_DCB_INPUT_FW_DISABLED) {
175*4882a593Smuzhiyun 			/* during this CXGB4_DCB_STATE_FW_INCOMPLETE state,
176*4882a593Smuzhiyun 			 * check if the dcb version is changed (there can be
177*4882a593Smuzhiyun 			 * mismatch in default config & the negotiated switch
178*4882a593Smuzhiyun 			 * configuration at FW, so update the dcb support
179*4882a593Smuzhiyun 			 * accordingly.
180*4882a593Smuzhiyun 			 */
181*4882a593Smuzhiyun 			cxgb4_dcb_update_support(dcb);
182*4882a593Smuzhiyun 		}
183*4882a593Smuzhiyun 		switch (transition_to) {
184*4882a593Smuzhiyun 		case CXGB4_DCB_INPUT_FW_ENABLED: {
185*4882a593Smuzhiyun 			/* we're alreaady in firmware DCB mode */
186*4882a593Smuzhiyun 			break;
187*4882a593Smuzhiyun 		}
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 		case CXGB4_DCB_INPUT_FW_INCOMPLETE: {
190*4882a593Smuzhiyun 			/* we're already incomplete */
191*4882a593Smuzhiyun 			break;
192*4882a593Smuzhiyun 		}
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 		case CXGB4_DCB_INPUT_FW_ALLSYNCED: {
195*4882a593Smuzhiyun 			dcb->state = CXGB4_DCB_STATE_FW_ALLSYNCED;
196*4882a593Smuzhiyun 			dcb->enabled = 1;
197*4882a593Smuzhiyun 			linkwatch_fire_event(dev);
198*4882a593Smuzhiyun 			break;
199*4882a593Smuzhiyun 		}
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 		default:
202*4882a593Smuzhiyun 			goto bad_state_input;
203*4882a593Smuzhiyun 		}
204*4882a593Smuzhiyun 		break;
205*4882a593Smuzhiyun 	}
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	case CXGB4_DCB_STATE_FW_ALLSYNCED: {
208*4882a593Smuzhiyun 		switch (transition_to) {
209*4882a593Smuzhiyun 		case CXGB4_DCB_INPUT_FW_ENABLED: {
210*4882a593Smuzhiyun 			/* we're alreaady in firmware DCB mode */
211*4882a593Smuzhiyun 			break;
212*4882a593Smuzhiyun 		}
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 		case CXGB4_DCB_INPUT_FW_INCOMPLETE: {
215*4882a593Smuzhiyun 			/* We were successfully running with firmware DCB but
216*4882a593Smuzhiyun 			 * now it's telling us that it's in an "incomplete
217*4882a593Smuzhiyun 			 * state.  We need to reset back to a ground state
218*4882a593Smuzhiyun 			 * of incomplete.
219*4882a593Smuzhiyun 			 */
220*4882a593Smuzhiyun 			cxgb4_dcb_reset(dev);
221*4882a593Smuzhiyun 			dcb->state = CXGB4_DCB_STATE_FW_INCOMPLETE;
222*4882a593Smuzhiyun 			dcb->supported = CXGB4_DCBX_FW_SUPPORT;
223*4882a593Smuzhiyun 			linkwatch_fire_event(dev);
224*4882a593Smuzhiyun 			break;
225*4882a593Smuzhiyun 		}
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 		case CXGB4_DCB_INPUT_FW_ALLSYNCED: {
228*4882a593Smuzhiyun 			/* we're already all sync'ed
229*4882a593Smuzhiyun 			 * this is only applicable for IEEE or
230*4882a593Smuzhiyun 			 * when another VI already completed negotiaton
231*4882a593Smuzhiyun 			 */
232*4882a593Smuzhiyun 			dcb->enabled = 1;
233*4882a593Smuzhiyun 			linkwatch_fire_event(dev);
234*4882a593Smuzhiyun 			break;
235*4882a593Smuzhiyun 		}
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 		default:
238*4882a593Smuzhiyun 			goto bad_state_input;
239*4882a593Smuzhiyun 		}
240*4882a593Smuzhiyun 		break;
241*4882a593Smuzhiyun 	}
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	case CXGB4_DCB_STATE_HOST: {
244*4882a593Smuzhiyun 		switch (transition_to) {
245*4882a593Smuzhiyun 		case CXGB4_DCB_INPUT_FW_DISABLED: {
246*4882a593Smuzhiyun 			/* we're alreaady in Host DCB mode */
247*4882a593Smuzhiyun 			break;
248*4882a593Smuzhiyun 		}
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 		default:
251*4882a593Smuzhiyun 			goto bad_state_input;
252*4882a593Smuzhiyun 		}
253*4882a593Smuzhiyun 		break;
254*4882a593Smuzhiyun 	}
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	default:
257*4882a593Smuzhiyun 		goto bad_state_transition;
258*4882a593Smuzhiyun 	}
259*4882a593Smuzhiyun 	return;
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun bad_state_input:
262*4882a593Smuzhiyun 	dev_err(adap->pdev_dev, "cxgb4_dcb_state_fsm: illegal input symbol %d\n",
263*4882a593Smuzhiyun 		transition_to);
264*4882a593Smuzhiyun 	return;
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun bad_state_transition:
267*4882a593Smuzhiyun 	dev_err(adap->pdev_dev, "cxgb4_dcb_state_fsm: bad state transition, state = %d, input = %d\n",
268*4882a593Smuzhiyun 		current_state, transition_to);
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun /* Handle a DCB/DCBX update message from the firmware.
272*4882a593Smuzhiyun  */
cxgb4_dcb_handle_fw_update(struct adapter * adap,const struct fw_port_cmd * pcmd)273*4882a593Smuzhiyun void cxgb4_dcb_handle_fw_update(struct adapter *adap,
274*4882a593Smuzhiyun 				const struct fw_port_cmd *pcmd)
275*4882a593Smuzhiyun {
276*4882a593Smuzhiyun 	const union fw_port_dcb *fwdcb = &pcmd->u.dcb;
277*4882a593Smuzhiyun 	int port = FW_PORT_CMD_PORTID_G(be32_to_cpu(pcmd->op_to_portid));
278*4882a593Smuzhiyun 	struct net_device *dev = adap->port[adap->chan_map[port]];
279*4882a593Smuzhiyun 	struct port_info *pi = netdev_priv(dev);
280*4882a593Smuzhiyun 	struct port_dcb_info *dcb = &pi->dcb;
281*4882a593Smuzhiyun 	int dcb_type = pcmd->u.dcb.pgid.type;
282*4882a593Smuzhiyun 	int dcb_running_version;
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 	/* Handle Firmware DCB Control messages separately since they drive
285*4882a593Smuzhiyun 	 * our state machine.
286*4882a593Smuzhiyun 	 */
287*4882a593Smuzhiyun 	if (dcb_type == FW_PORT_DCB_TYPE_CONTROL) {
288*4882a593Smuzhiyun 		enum cxgb4_dcb_state_input input =
289*4882a593Smuzhiyun 			((pcmd->u.dcb.control.all_syncd_pkd &
290*4882a593Smuzhiyun 			  FW_PORT_CMD_ALL_SYNCD_F)
291*4882a593Smuzhiyun 			 ? CXGB4_DCB_INPUT_FW_ALLSYNCED
292*4882a593Smuzhiyun 			 : CXGB4_DCB_INPUT_FW_INCOMPLETE);
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun 		if (dcb->dcb_version != FW_PORT_DCB_VER_UNKNOWN) {
295*4882a593Smuzhiyun 			dcb_running_version = FW_PORT_CMD_DCB_VERSION_G(
296*4882a593Smuzhiyun 				be16_to_cpu(
297*4882a593Smuzhiyun 				pcmd->u.dcb.control.dcb_version_to_app_state));
298*4882a593Smuzhiyun 			if (dcb_running_version == FW_PORT_DCB_VER_CEE1D01 ||
299*4882a593Smuzhiyun 			    dcb_running_version == FW_PORT_DCB_VER_IEEE) {
300*4882a593Smuzhiyun 				dcb->dcb_version = dcb_running_version;
301*4882a593Smuzhiyun 				dev_warn(adap->pdev_dev, "Interface %s is running %s\n",
302*4882a593Smuzhiyun 					 dev->name,
303*4882a593Smuzhiyun 					 dcb_ver_array[dcb->dcb_version]);
304*4882a593Smuzhiyun 			} else {
305*4882a593Smuzhiyun 				dev_warn(adap->pdev_dev,
306*4882a593Smuzhiyun 					 "Something screwed up, requested firmware for %s, but firmware returned %s instead\n",
307*4882a593Smuzhiyun 					 dcb_ver_array[dcb->dcb_version],
308*4882a593Smuzhiyun 					 dcb_ver_array[dcb_running_version]);
309*4882a593Smuzhiyun 				dcb->dcb_version = FW_PORT_DCB_VER_UNKNOWN;
310*4882a593Smuzhiyun 			}
311*4882a593Smuzhiyun 		}
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 		cxgb4_dcb_state_fsm(dev, input);
314*4882a593Smuzhiyun 		return;
315*4882a593Smuzhiyun 	}
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun 	/* It's weird, and almost certainly an error, to get Firmware DCB
318*4882a593Smuzhiyun 	 * messages when we either haven't been told whether we're going to be
319*4882a593Smuzhiyun 	 * doing Host or Firmware DCB; and even worse when we've been told
320*4882a593Smuzhiyun 	 * that we're doing Host DCB!
321*4882a593Smuzhiyun 	 */
322*4882a593Smuzhiyun 	if (dcb->state == CXGB4_DCB_STATE_START ||
323*4882a593Smuzhiyun 	    dcb->state == CXGB4_DCB_STATE_HOST) {
324*4882a593Smuzhiyun 		dev_err(adap->pdev_dev, "Receiving Firmware DCB messages in State %d\n",
325*4882a593Smuzhiyun 			dcb->state);
326*4882a593Smuzhiyun 		return;
327*4882a593Smuzhiyun 	}
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 	/* Now handle the general Firmware DCB update messages ...
330*4882a593Smuzhiyun 	 */
331*4882a593Smuzhiyun 	switch (dcb_type) {
332*4882a593Smuzhiyun 	case FW_PORT_DCB_TYPE_PGID:
333*4882a593Smuzhiyun 		dcb->pgid = be32_to_cpu(fwdcb->pgid.pgid);
334*4882a593Smuzhiyun 		dcb->msgs |= CXGB4_DCB_FW_PGID;
335*4882a593Smuzhiyun 		break;
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun 	case FW_PORT_DCB_TYPE_PGRATE:
338*4882a593Smuzhiyun 		dcb->pg_num_tcs_supported = fwdcb->pgrate.num_tcs_supported;
339*4882a593Smuzhiyun 		memcpy(dcb->pgrate, &fwdcb->pgrate.pgrate,
340*4882a593Smuzhiyun 		       sizeof(dcb->pgrate));
341*4882a593Smuzhiyun 		memcpy(dcb->tsa, &fwdcb->pgrate.tsa,
342*4882a593Smuzhiyun 		       sizeof(dcb->tsa));
343*4882a593Smuzhiyun 		dcb->msgs |= CXGB4_DCB_FW_PGRATE;
344*4882a593Smuzhiyun 		if (dcb->msgs & CXGB4_DCB_FW_PGID)
345*4882a593Smuzhiyun 			IEEE_FAUX_SYNC(dev, dcb);
346*4882a593Smuzhiyun 		break;
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun 	case FW_PORT_DCB_TYPE_PRIORATE:
349*4882a593Smuzhiyun 		memcpy(dcb->priorate, &fwdcb->priorate.strict_priorate,
350*4882a593Smuzhiyun 		       sizeof(dcb->priorate));
351*4882a593Smuzhiyun 		dcb->msgs |= CXGB4_DCB_FW_PRIORATE;
352*4882a593Smuzhiyun 		break;
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun 	case FW_PORT_DCB_TYPE_PFC:
355*4882a593Smuzhiyun 		dcb->pfcen = fwdcb->pfc.pfcen;
356*4882a593Smuzhiyun 		dcb->pfc_num_tcs_supported = fwdcb->pfc.max_pfc_tcs;
357*4882a593Smuzhiyun 		dcb->msgs |= CXGB4_DCB_FW_PFC;
358*4882a593Smuzhiyun 		IEEE_FAUX_SYNC(dev, dcb);
359*4882a593Smuzhiyun 		break;
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun 	case FW_PORT_DCB_TYPE_APP_ID: {
362*4882a593Smuzhiyun 		const struct fw_port_app_priority *fwap = &fwdcb->app_priority;
363*4882a593Smuzhiyun 		int idx = fwap->idx;
364*4882a593Smuzhiyun 		struct app_priority *ap = &dcb->app_priority[idx];
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun 		struct dcb_app app = {
367*4882a593Smuzhiyun 			.protocol = be16_to_cpu(fwap->protocolid),
368*4882a593Smuzhiyun 		};
369*4882a593Smuzhiyun 		int err;
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun 		/* Convert from firmware format to relevant format
372*4882a593Smuzhiyun 		 * when using app selector
373*4882a593Smuzhiyun 		 */
374*4882a593Smuzhiyun 		if (dcb->dcb_version == FW_PORT_DCB_VER_IEEE) {
375*4882a593Smuzhiyun 			app.selector = (fwap->sel_field + 1);
376*4882a593Smuzhiyun 			app.priority = ffs(fwap->user_prio_map) - 1;
377*4882a593Smuzhiyun 			err = dcb_ieee_setapp(dev, &app);
378*4882a593Smuzhiyun 			IEEE_FAUX_SYNC(dev, dcb);
379*4882a593Smuzhiyun 		} else {
380*4882a593Smuzhiyun 			/* Default is CEE */
381*4882a593Smuzhiyun 			app.selector = !!(fwap->sel_field);
382*4882a593Smuzhiyun 			app.priority = fwap->user_prio_map;
383*4882a593Smuzhiyun 			err = dcb_setapp(dev, &app);
384*4882a593Smuzhiyun 		}
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun 		if (err)
387*4882a593Smuzhiyun 			dev_err(adap->pdev_dev,
388*4882a593Smuzhiyun 				"Failed DCB Set Application Priority: sel=%d, prot=%d, prio=%d, err=%d\n",
389*4882a593Smuzhiyun 				app.selector, app.protocol, app.priority, -err);
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun 		ap->user_prio_map = fwap->user_prio_map;
392*4882a593Smuzhiyun 		ap->sel_field = fwap->sel_field;
393*4882a593Smuzhiyun 		ap->protocolid = be16_to_cpu(fwap->protocolid);
394*4882a593Smuzhiyun 		dcb->msgs |= CXGB4_DCB_FW_APP_ID;
395*4882a593Smuzhiyun 		break;
396*4882a593Smuzhiyun 	}
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 	default:
399*4882a593Smuzhiyun 		dev_err(adap->pdev_dev, "Unknown DCB update type received %x\n",
400*4882a593Smuzhiyun 			dcb_type);
401*4882a593Smuzhiyun 		break;
402*4882a593Smuzhiyun 	}
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun 
405*4882a593Smuzhiyun /* Data Center Bridging netlink operations.
406*4882a593Smuzhiyun  */
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun 
409*4882a593Smuzhiyun /* Get current DCB enabled/disabled state.
410*4882a593Smuzhiyun  */
cxgb4_getstate(struct net_device * dev)411*4882a593Smuzhiyun static u8 cxgb4_getstate(struct net_device *dev)
412*4882a593Smuzhiyun {
413*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun 	return pi->dcb.enabled;
416*4882a593Smuzhiyun }
417*4882a593Smuzhiyun 
418*4882a593Smuzhiyun /* Set DCB enabled/disabled.
419*4882a593Smuzhiyun  */
cxgb4_setstate(struct net_device * dev,u8 enabled)420*4882a593Smuzhiyun static u8 cxgb4_setstate(struct net_device *dev, u8 enabled)
421*4882a593Smuzhiyun {
422*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun 	/* If DCBx is host-managed, dcb is enabled by outside lldp agents */
425*4882a593Smuzhiyun 	if (pi->dcb.state == CXGB4_DCB_STATE_HOST) {
426*4882a593Smuzhiyun 		pi->dcb.enabled = enabled;
427*4882a593Smuzhiyun 		return 0;
428*4882a593Smuzhiyun 	}
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun 	/* Firmware doesn't provide any mechanism to control the DCB state.
431*4882a593Smuzhiyun 	 */
432*4882a593Smuzhiyun 	if (enabled != (pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED))
433*4882a593Smuzhiyun 		return 1;
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun 	return 0;
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun 
cxgb4_getpgtccfg(struct net_device * dev,int tc,u8 * prio_type,u8 * pgid,u8 * bw_per,u8 * up_tc_map,int local)438*4882a593Smuzhiyun static void cxgb4_getpgtccfg(struct net_device *dev, int tc,
439*4882a593Smuzhiyun 			     u8 *prio_type, u8 *pgid, u8 *bw_per,
440*4882a593Smuzhiyun 			     u8 *up_tc_map, int local)
441*4882a593Smuzhiyun {
442*4882a593Smuzhiyun 	struct fw_port_cmd pcmd;
443*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
444*4882a593Smuzhiyun 	struct adapter *adap = pi->adapter;
445*4882a593Smuzhiyun 	int err;
446*4882a593Smuzhiyun 
447*4882a593Smuzhiyun 	*prio_type = *pgid = *bw_per = *up_tc_map = 0;
448*4882a593Smuzhiyun 
449*4882a593Smuzhiyun 	if (local)
450*4882a593Smuzhiyun 		INIT_PORT_DCB_READ_LOCAL_CMD(pcmd, pi->port_id);
451*4882a593Smuzhiyun 	else
452*4882a593Smuzhiyun 		INIT_PORT_DCB_READ_PEER_CMD(pcmd, pi->port_id);
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun 	pcmd.u.dcb.pgid.type = FW_PORT_DCB_TYPE_PGID;
455*4882a593Smuzhiyun 	err = t4_wr_mbox(adap, adap->mbox, &pcmd, sizeof(pcmd), &pcmd);
456*4882a593Smuzhiyun 	if (err != FW_PORT_DCB_CFG_SUCCESS) {
457*4882a593Smuzhiyun 		dev_err(adap->pdev_dev, "DCB read PGID failed with %d\n", -err);
458*4882a593Smuzhiyun 		return;
459*4882a593Smuzhiyun 	}
460*4882a593Smuzhiyun 	*pgid = (be32_to_cpu(pcmd.u.dcb.pgid.pgid) >> (tc * 4)) & 0xf;
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun 	if (local)
463*4882a593Smuzhiyun 		INIT_PORT_DCB_READ_LOCAL_CMD(pcmd, pi->port_id);
464*4882a593Smuzhiyun 	else
465*4882a593Smuzhiyun 		INIT_PORT_DCB_READ_PEER_CMD(pcmd, pi->port_id);
466*4882a593Smuzhiyun 	pcmd.u.dcb.pgrate.type = FW_PORT_DCB_TYPE_PGRATE;
467*4882a593Smuzhiyun 	err = t4_wr_mbox(adap, adap->mbox, &pcmd, sizeof(pcmd), &pcmd);
468*4882a593Smuzhiyun 	if (err != FW_PORT_DCB_CFG_SUCCESS) {
469*4882a593Smuzhiyun 		dev_err(adap->pdev_dev, "DCB read PGRATE failed with %d\n",
470*4882a593Smuzhiyun 			-err);
471*4882a593Smuzhiyun 		return;
472*4882a593Smuzhiyun 	}
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun 	*bw_per = pcmd.u.dcb.pgrate.pgrate[*pgid];
475*4882a593Smuzhiyun 	*up_tc_map = (1 << tc);
476*4882a593Smuzhiyun 
477*4882a593Smuzhiyun 	/* prio_type is link strict */
478*4882a593Smuzhiyun 	if (*pgid != 0xF)
479*4882a593Smuzhiyun 		*prio_type = 0x2;
480*4882a593Smuzhiyun }
481*4882a593Smuzhiyun 
cxgb4_getpgtccfg_tx(struct net_device * dev,int tc,u8 * prio_type,u8 * pgid,u8 * bw_per,u8 * up_tc_map)482*4882a593Smuzhiyun static void cxgb4_getpgtccfg_tx(struct net_device *dev, int tc,
483*4882a593Smuzhiyun 				u8 *prio_type, u8 *pgid, u8 *bw_per,
484*4882a593Smuzhiyun 				u8 *up_tc_map)
485*4882a593Smuzhiyun {
486*4882a593Smuzhiyun 	/* tc 0 is written at MSB position */
487*4882a593Smuzhiyun 	return cxgb4_getpgtccfg(dev, (7 - tc), prio_type, pgid, bw_per,
488*4882a593Smuzhiyun 				up_tc_map, 1);
489*4882a593Smuzhiyun }
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun 
cxgb4_getpgtccfg_rx(struct net_device * dev,int tc,u8 * prio_type,u8 * pgid,u8 * bw_per,u8 * up_tc_map)492*4882a593Smuzhiyun static void cxgb4_getpgtccfg_rx(struct net_device *dev, int tc,
493*4882a593Smuzhiyun 				u8 *prio_type, u8 *pgid, u8 *bw_per,
494*4882a593Smuzhiyun 				u8 *up_tc_map)
495*4882a593Smuzhiyun {
496*4882a593Smuzhiyun 	/* tc 0 is written at MSB position */
497*4882a593Smuzhiyun 	return cxgb4_getpgtccfg(dev, (7 - tc), prio_type, pgid, bw_per,
498*4882a593Smuzhiyun 				up_tc_map, 0);
499*4882a593Smuzhiyun }
500*4882a593Smuzhiyun 
cxgb4_setpgtccfg_tx(struct net_device * dev,int tc,u8 prio_type,u8 pgid,u8 bw_per,u8 up_tc_map)501*4882a593Smuzhiyun static void cxgb4_setpgtccfg_tx(struct net_device *dev, int tc,
502*4882a593Smuzhiyun 				u8 prio_type, u8 pgid, u8 bw_per,
503*4882a593Smuzhiyun 				u8 up_tc_map)
504*4882a593Smuzhiyun {
505*4882a593Smuzhiyun 	struct fw_port_cmd pcmd;
506*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
507*4882a593Smuzhiyun 	struct adapter *adap = pi->adapter;
508*4882a593Smuzhiyun 	int fw_tc = 7 - tc;
509*4882a593Smuzhiyun 	u32 _pgid;
510*4882a593Smuzhiyun 	int err;
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun 	if (pgid == DCB_ATTR_VALUE_UNDEFINED)
513*4882a593Smuzhiyun 		return;
514*4882a593Smuzhiyun 	if (bw_per == DCB_ATTR_VALUE_UNDEFINED)
515*4882a593Smuzhiyun 		return;
516*4882a593Smuzhiyun 
517*4882a593Smuzhiyun 	INIT_PORT_DCB_READ_LOCAL_CMD(pcmd, pi->port_id);
518*4882a593Smuzhiyun 	pcmd.u.dcb.pgid.type = FW_PORT_DCB_TYPE_PGID;
519*4882a593Smuzhiyun 
520*4882a593Smuzhiyun 	err = t4_wr_mbox(adap, adap->mbox, &pcmd, sizeof(pcmd), &pcmd);
521*4882a593Smuzhiyun 	if (err != FW_PORT_DCB_CFG_SUCCESS) {
522*4882a593Smuzhiyun 		dev_err(adap->pdev_dev, "DCB read PGID failed with %d\n", -err);
523*4882a593Smuzhiyun 		return;
524*4882a593Smuzhiyun 	}
525*4882a593Smuzhiyun 
526*4882a593Smuzhiyun 	_pgid = be32_to_cpu(pcmd.u.dcb.pgid.pgid);
527*4882a593Smuzhiyun 	_pgid &= ~(0xF << (fw_tc * 4));
528*4882a593Smuzhiyun 	_pgid |= pgid << (fw_tc * 4);
529*4882a593Smuzhiyun 	pcmd.u.dcb.pgid.pgid = cpu_to_be32(_pgid);
530*4882a593Smuzhiyun 
531*4882a593Smuzhiyun 	INIT_PORT_DCB_WRITE_CMD(pcmd, pi->port_id);
532*4882a593Smuzhiyun 
533*4882a593Smuzhiyun 	err = t4_wr_mbox(adap, adap->mbox, &pcmd, sizeof(pcmd), &pcmd);
534*4882a593Smuzhiyun 	if (err != FW_PORT_DCB_CFG_SUCCESS) {
535*4882a593Smuzhiyun 		dev_err(adap->pdev_dev, "DCB write PGID failed with %d\n",
536*4882a593Smuzhiyun 			-err);
537*4882a593Smuzhiyun 		return;
538*4882a593Smuzhiyun 	}
539*4882a593Smuzhiyun 
540*4882a593Smuzhiyun 	memset(&pcmd, 0, sizeof(struct fw_port_cmd));
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun 	INIT_PORT_DCB_READ_LOCAL_CMD(pcmd, pi->port_id);
543*4882a593Smuzhiyun 	pcmd.u.dcb.pgrate.type = FW_PORT_DCB_TYPE_PGRATE;
544*4882a593Smuzhiyun 
545*4882a593Smuzhiyun 	err = t4_wr_mbox(adap, adap->mbox, &pcmd, sizeof(pcmd), &pcmd);
546*4882a593Smuzhiyun 	if (err != FW_PORT_DCB_CFG_SUCCESS) {
547*4882a593Smuzhiyun 		dev_err(adap->pdev_dev, "DCB read PGRATE failed with %d\n",
548*4882a593Smuzhiyun 			-err);
549*4882a593Smuzhiyun 		return;
550*4882a593Smuzhiyun 	}
551*4882a593Smuzhiyun 
552*4882a593Smuzhiyun 	pcmd.u.dcb.pgrate.pgrate[pgid] = bw_per;
553*4882a593Smuzhiyun 
554*4882a593Smuzhiyun 	INIT_PORT_DCB_WRITE_CMD(pcmd, pi->port_id);
555*4882a593Smuzhiyun 	if (pi->dcb.state == CXGB4_DCB_STATE_HOST)
556*4882a593Smuzhiyun 		pcmd.op_to_portid |= cpu_to_be32(FW_PORT_CMD_APPLY_F);
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun 	err = t4_wr_mbox(adap, adap->mbox, &pcmd, sizeof(pcmd), &pcmd);
559*4882a593Smuzhiyun 	if (err != FW_PORT_DCB_CFG_SUCCESS)
560*4882a593Smuzhiyun 		dev_err(adap->pdev_dev, "DCB write PGRATE failed with %d\n",
561*4882a593Smuzhiyun 			-err);
562*4882a593Smuzhiyun }
563*4882a593Smuzhiyun 
cxgb4_getpgbwgcfg(struct net_device * dev,int pgid,u8 * bw_per,int local)564*4882a593Smuzhiyun static void cxgb4_getpgbwgcfg(struct net_device *dev, int pgid, u8 *bw_per,
565*4882a593Smuzhiyun 			      int local)
566*4882a593Smuzhiyun {
567*4882a593Smuzhiyun 	struct fw_port_cmd pcmd;
568*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
569*4882a593Smuzhiyun 	struct adapter *adap = pi->adapter;
570*4882a593Smuzhiyun 	int err;
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun 	if (local)
573*4882a593Smuzhiyun 		INIT_PORT_DCB_READ_LOCAL_CMD(pcmd, pi->port_id);
574*4882a593Smuzhiyun 	else
575*4882a593Smuzhiyun 		INIT_PORT_DCB_READ_PEER_CMD(pcmd, pi->port_id);
576*4882a593Smuzhiyun 
577*4882a593Smuzhiyun 	pcmd.u.dcb.pgrate.type = FW_PORT_DCB_TYPE_PGRATE;
578*4882a593Smuzhiyun 	err = t4_wr_mbox(adap, adap->mbox, &pcmd, sizeof(pcmd), &pcmd);
579*4882a593Smuzhiyun 	if (err != FW_PORT_DCB_CFG_SUCCESS) {
580*4882a593Smuzhiyun 		dev_err(adap->pdev_dev, "DCB read PGRATE failed with %d\n",
581*4882a593Smuzhiyun 			-err);
582*4882a593Smuzhiyun 		return;
583*4882a593Smuzhiyun 	}
584*4882a593Smuzhiyun 
585*4882a593Smuzhiyun 	*bw_per = pcmd.u.dcb.pgrate.pgrate[pgid];
586*4882a593Smuzhiyun }
587*4882a593Smuzhiyun 
cxgb4_getpgbwgcfg_tx(struct net_device * dev,int pgid,u8 * bw_per)588*4882a593Smuzhiyun static void cxgb4_getpgbwgcfg_tx(struct net_device *dev, int pgid, u8 *bw_per)
589*4882a593Smuzhiyun {
590*4882a593Smuzhiyun 	return cxgb4_getpgbwgcfg(dev, pgid, bw_per, 1);
591*4882a593Smuzhiyun }
592*4882a593Smuzhiyun 
cxgb4_getpgbwgcfg_rx(struct net_device * dev,int pgid,u8 * bw_per)593*4882a593Smuzhiyun static void cxgb4_getpgbwgcfg_rx(struct net_device *dev, int pgid, u8 *bw_per)
594*4882a593Smuzhiyun {
595*4882a593Smuzhiyun 	return cxgb4_getpgbwgcfg(dev, pgid, bw_per, 0);
596*4882a593Smuzhiyun }
597*4882a593Smuzhiyun 
cxgb4_setpgbwgcfg_tx(struct net_device * dev,int pgid,u8 bw_per)598*4882a593Smuzhiyun static void cxgb4_setpgbwgcfg_tx(struct net_device *dev, int pgid,
599*4882a593Smuzhiyun 				 u8 bw_per)
600*4882a593Smuzhiyun {
601*4882a593Smuzhiyun 	struct fw_port_cmd pcmd;
602*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
603*4882a593Smuzhiyun 	struct adapter *adap = pi->adapter;
604*4882a593Smuzhiyun 	int err;
605*4882a593Smuzhiyun 
606*4882a593Smuzhiyun 	INIT_PORT_DCB_READ_LOCAL_CMD(pcmd, pi->port_id);
607*4882a593Smuzhiyun 	pcmd.u.dcb.pgrate.type = FW_PORT_DCB_TYPE_PGRATE;
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun 	err = t4_wr_mbox(adap, adap->mbox, &pcmd, sizeof(pcmd), &pcmd);
610*4882a593Smuzhiyun 	if (err != FW_PORT_DCB_CFG_SUCCESS) {
611*4882a593Smuzhiyun 		dev_err(adap->pdev_dev, "DCB read PGRATE failed with %d\n",
612*4882a593Smuzhiyun 			-err);
613*4882a593Smuzhiyun 		return;
614*4882a593Smuzhiyun 	}
615*4882a593Smuzhiyun 
616*4882a593Smuzhiyun 	pcmd.u.dcb.pgrate.pgrate[pgid] = bw_per;
617*4882a593Smuzhiyun 
618*4882a593Smuzhiyun 	INIT_PORT_DCB_WRITE_CMD(pcmd, pi->port_id);
619*4882a593Smuzhiyun 	if (pi->dcb.state == CXGB4_DCB_STATE_HOST)
620*4882a593Smuzhiyun 		pcmd.op_to_portid |= cpu_to_be32(FW_PORT_CMD_APPLY_F);
621*4882a593Smuzhiyun 
622*4882a593Smuzhiyun 	err = t4_wr_mbox(adap, adap->mbox, &pcmd, sizeof(pcmd), &pcmd);
623*4882a593Smuzhiyun 
624*4882a593Smuzhiyun 	if (err != FW_PORT_DCB_CFG_SUCCESS)
625*4882a593Smuzhiyun 		dev_err(adap->pdev_dev, "DCB write PGRATE failed with %d\n",
626*4882a593Smuzhiyun 			-err);
627*4882a593Smuzhiyun }
628*4882a593Smuzhiyun 
629*4882a593Smuzhiyun /* Return whether the specified Traffic Class Priority has Priority Pause
630*4882a593Smuzhiyun  * Frames enabled.
631*4882a593Smuzhiyun  */
cxgb4_getpfccfg(struct net_device * dev,int priority,u8 * pfccfg)632*4882a593Smuzhiyun static void cxgb4_getpfccfg(struct net_device *dev, int priority, u8 *pfccfg)
633*4882a593Smuzhiyun {
634*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
635*4882a593Smuzhiyun 	struct port_dcb_info *dcb = &pi->dcb;
636*4882a593Smuzhiyun 
637*4882a593Smuzhiyun 	if (!cxgb4_dcb_state_synced(dcb->state) ||
638*4882a593Smuzhiyun 	    priority >= CXGB4_MAX_PRIORITY)
639*4882a593Smuzhiyun 		*pfccfg = 0;
640*4882a593Smuzhiyun 	else
641*4882a593Smuzhiyun 		*pfccfg = (pi->dcb.pfcen >> (7 - priority)) & 1;
642*4882a593Smuzhiyun }
643*4882a593Smuzhiyun 
644*4882a593Smuzhiyun /* Enable/disable Priority Pause Frames for the specified Traffic Class
645*4882a593Smuzhiyun  * Priority.
646*4882a593Smuzhiyun  */
cxgb4_setpfccfg(struct net_device * dev,int priority,u8 pfccfg)647*4882a593Smuzhiyun static void cxgb4_setpfccfg(struct net_device *dev, int priority, u8 pfccfg)
648*4882a593Smuzhiyun {
649*4882a593Smuzhiyun 	struct fw_port_cmd pcmd;
650*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
651*4882a593Smuzhiyun 	struct adapter *adap = pi->adapter;
652*4882a593Smuzhiyun 	int err;
653*4882a593Smuzhiyun 
654*4882a593Smuzhiyun 	if (!cxgb4_dcb_state_synced(pi->dcb.state) ||
655*4882a593Smuzhiyun 	    priority >= CXGB4_MAX_PRIORITY)
656*4882a593Smuzhiyun 		return;
657*4882a593Smuzhiyun 
658*4882a593Smuzhiyun 	INIT_PORT_DCB_WRITE_CMD(pcmd, pi->port_id);
659*4882a593Smuzhiyun 	if (pi->dcb.state == CXGB4_DCB_STATE_HOST)
660*4882a593Smuzhiyun 		pcmd.op_to_portid |= cpu_to_be32(FW_PORT_CMD_APPLY_F);
661*4882a593Smuzhiyun 
662*4882a593Smuzhiyun 	pcmd.u.dcb.pfc.type = FW_PORT_DCB_TYPE_PFC;
663*4882a593Smuzhiyun 	pcmd.u.dcb.pfc.pfcen = pi->dcb.pfcen;
664*4882a593Smuzhiyun 
665*4882a593Smuzhiyun 	if (pfccfg)
666*4882a593Smuzhiyun 		pcmd.u.dcb.pfc.pfcen |= (1 << (7 - priority));
667*4882a593Smuzhiyun 	else
668*4882a593Smuzhiyun 		pcmd.u.dcb.pfc.pfcen &= (~(1 << (7 - priority)));
669*4882a593Smuzhiyun 
670*4882a593Smuzhiyun 	err = t4_wr_mbox(adap, adap->mbox, &pcmd, sizeof(pcmd), &pcmd);
671*4882a593Smuzhiyun 	if (err != FW_PORT_DCB_CFG_SUCCESS) {
672*4882a593Smuzhiyun 		dev_err(adap->pdev_dev, "DCB PFC write failed with %d\n", -err);
673*4882a593Smuzhiyun 		return;
674*4882a593Smuzhiyun 	}
675*4882a593Smuzhiyun 
676*4882a593Smuzhiyun 	pi->dcb.pfcen = pcmd.u.dcb.pfc.pfcen;
677*4882a593Smuzhiyun }
678*4882a593Smuzhiyun 
cxgb4_setall(struct net_device * dev)679*4882a593Smuzhiyun static u8 cxgb4_setall(struct net_device *dev)
680*4882a593Smuzhiyun {
681*4882a593Smuzhiyun 	return 0;
682*4882a593Smuzhiyun }
683*4882a593Smuzhiyun 
684*4882a593Smuzhiyun /* Return DCB capabilities.
685*4882a593Smuzhiyun  */
cxgb4_getcap(struct net_device * dev,int cap_id,u8 * caps)686*4882a593Smuzhiyun static u8 cxgb4_getcap(struct net_device *dev, int cap_id, u8 *caps)
687*4882a593Smuzhiyun {
688*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
689*4882a593Smuzhiyun 
690*4882a593Smuzhiyun 	switch (cap_id) {
691*4882a593Smuzhiyun 	case DCB_CAP_ATTR_PG:
692*4882a593Smuzhiyun 	case DCB_CAP_ATTR_PFC:
693*4882a593Smuzhiyun 		*caps = true;
694*4882a593Smuzhiyun 		break;
695*4882a593Smuzhiyun 
696*4882a593Smuzhiyun 	case DCB_CAP_ATTR_PG_TCS:
697*4882a593Smuzhiyun 		/* 8 priorities for PG represented by bitmap */
698*4882a593Smuzhiyun 		*caps = 0x80;
699*4882a593Smuzhiyun 		break;
700*4882a593Smuzhiyun 
701*4882a593Smuzhiyun 	case DCB_CAP_ATTR_PFC_TCS:
702*4882a593Smuzhiyun 		/* 8 priorities for PFC represented by bitmap */
703*4882a593Smuzhiyun 		*caps = 0x80;
704*4882a593Smuzhiyun 		break;
705*4882a593Smuzhiyun 
706*4882a593Smuzhiyun 	case DCB_CAP_ATTR_GSP:
707*4882a593Smuzhiyun 		*caps = true;
708*4882a593Smuzhiyun 		break;
709*4882a593Smuzhiyun 
710*4882a593Smuzhiyun 	case DCB_CAP_ATTR_UP2TC:
711*4882a593Smuzhiyun 	case DCB_CAP_ATTR_BCN:
712*4882a593Smuzhiyun 		*caps = false;
713*4882a593Smuzhiyun 		break;
714*4882a593Smuzhiyun 
715*4882a593Smuzhiyun 	case DCB_CAP_ATTR_DCBX:
716*4882a593Smuzhiyun 		*caps = pi->dcb.supported;
717*4882a593Smuzhiyun 		break;
718*4882a593Smuzhiyun 
719*4882a593Smuzhiyun 	default:
720*4882a593Smuzhiyun 		*caps = false;
721*4882a593Smuzhiyun 	}
722*4882a593Smuzhiyun 
723*4882a593Smuzhiyun 	return 0;
724*4882a593Smuzhiyun }
725*4882a593Smuzhiyun 
726*4882a593Smuzhiyun /* Return the number of Traffic Classes for the indicated Traffic Class ID.
727*4882a593Smuzhiyun  */
cxgb4_getnumtcs(struct net_device * dev,int tcs_id,u8 * num)728*4882a593Smuzhiyun static int cxgb4_getnumtcs(struct net_device *dev, int tcs_id, u8 *num)
729*4882a593Smuzhiyun {
730*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
731*4882a593Smuzhiyun 
732*4882a593Smuzhiyun 	switch (tcs_id) {
733*4882a593Smuzhiyun 	case DCB_NUMTCS_ATTR_PG:
734*4882a593Smuzhiyun 		if (pi->dcb.msgs & CXGB4_DCB_FW_PGRATE)
735*4882a593Smuzhiyun 			*num = pi->dcb.pg_num_tcs_supported;
736*4882a593Smuzhiyun 		else
737*4882a593Smuzhiyun 			*num = 0x8;
738*4882a593Smuzhiyun 		break;
739*4882a593Smuzhiyun 
740*4882a593Smuzhiyun 	case DCB_NUMTCS_ATTR_PFC:
741*4882a593Smuzhiyun 		*num = 0x8;
742*4882a593Smuzhiyun 		break;
743*4882a593Smuzhiyun 
744*4882a593Smuzhiyun 	default:
745*4882a593Smuzhiyun 		return -EINVAL;
746*4882a593Smuzhiyun 	}
747*4882a593Smuzhiyun 
748*4882a593Smuzhiyun 	return 0;
749*4882a593Smuzhiyun }
750*4882a593Smuzhiyun 
751*4882a593Smuzhiyun /* Set the number of Traffic Classes supported for the indicated Traffic Class
752*4882a593Smuzhiyun  * ID.
753*4882a593Smuzhiyun  */
cxgb4_setnumtcs(struct net_device * dev,int tcs_id,u8 num)754*4882a593Smuzhiyun static int cxgb4_setnumtcs(struct net_device *dev, int tcs_id, u8 num)
755*4882a593Smuzhiyun {
756*4882a593Smuzhiyun 	/* Setting the number of Traffic Classes isn't supported.
757*4882a593Smuzhiyun 	 */
758*4882a593Smuzhiyun 	return -ENOSYS;
759*4882a593Smuzhiyun }
760*4882a593Smuzhiyun 
761*4882a593Smuzhiyun /* Return whether Priority Flow Control is enabled.  */
cxgb4_getpfcstate(struct net_device * dev)762*4882a593Smuzhiyun static u8 cxgb4_getpfcstate(struct net_device *dev)
763*4882a593Smuzhiyun {
764*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
765*4882a593Smuzhiyun 
766*4882a593Smuzhiyun 	if (!cxgb4_dcb_state_synced(pi->dcb.state))
767*4882a593Smuzhiyun 		return false;
768*4882a593Smuzhiyun 
769*4882a593Smuzhiyun 	return pi->dcb.pfcen != 0;
770*4882a593Smuzhiyun }
771*4882a593Smuzhiyun 
772*4882a593Smuzhiyun /* Enable/disable Priority Flow Control. */
cxgb4_setpfcstate(struct net_device * dev,u8 state)773*4882a593Smuzhiyun static void cxgb4_setpfcstate(struct net_device *dev, u8 state)
774*4882a593Smuzhiyun {
775*4882a593Smuzhiyun 	/* We can't enable/disable Priority Flow Control but we also can't
776*4882a593Smuzhiyun 	 * return an error ...
777*4882a593Smuzhiyun 	 */
778*4882a593Smuzhiyun }
779*4882a593Smuzhiyun 
780*4882a593Smuzhiyun /* Return the Application User Priority Map associated with the specified
781*4882a593Smuzhiyun  * Application ID.
782*4882a593Smuzhiyun  */
__cxgb4_getapp(struct net_device * dev,u8 app_idtype,u16 app_id,int peer)783*4882a593Smuzhiyun static int __cxgb4_getapp(struct net_device *dev, u8 app_idtype, u16 app_id,
784*4882a593Smuzhiyun 			  int peer)
785*4882a593Smuzhiyun {
786*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
787*4882a593Smuzhiyun 	struct adapter *adap = pi->adapter;
788*4882a593Smuzhiyun 	int i;
789*4882a593Smuzhiyun 
790*4882a593Smuzhiyun 	if (!cxgb4_dcb_state_synced(pi->dcb.state))
791*4882a593Smuzhiyun 		return 0;
792*4882a593Smuzhiyun 
793*4882a593Smuzhiyun 	for (i = 0; i < CXGB4_MAX_DCBX_APP_SUPPORTED; i++) {
794*4882a593Smuzhiyun 		struct fw_port_cmd pcmd;
795*4882a593Smuzhiyun 		int err;
796*4882a593Smuzhiyun 
797*4882a593Smuzhiyun 		if (peer)
798*4882a593Smuzhiyun 			INIT_PORT_DCB_READ_PEER_CMD(pcmd, pi->port_id);
799*4882a593Smuzhiyun 		else
800*4882a593Smuzhiyun 			INIT_PORT_DCB_READ_LOCAL_CMD(pcmd, pi->port_id);
801*4882a593Smuzhiyun 
802*4882a593Smuzhiyun 		pcmd.u.dcb.app_priority.type = FW_PORT_DCB_TYPE_APP_ID;
803*4882a593Smuzhiyun 		pcmd.u.dcb.app_priority.idx = i;
804*4882a593Smuzhiyun 
805*4882a593Smuzhiyun 		err = t4_wr_mbox(adap, adap->mbox, &pcmd, sizeof(pcmd), &pcmd);
806*4882a593Smuzhiyun 		if (err != FW_PORT_DCB_CFG_SUCCESS) {
807*4882a593Smuzhiyun 			dev_err(adap->pdev_dev, "DCB APP read failed with %d\n",
808*4882a593Smuzhiyun 				-err);
809*4882a593Smuzhiyun 			return err;
810*4882a593Smuzhiyun 		}
811*4882a593Smuzhiyun 		if (be16_to_cpu(pcmd.u.dcb.app_priority.protocolid) == app_id)
812*4882a593Smuzhiyun 			if (pcmd.u.dcb.app_priority.sel_field == app_idtype)
813*4882a593Smuzhiyun 				return pcmd.u.dcb.app_priority.user_prio_map;
814*4882a593Smuzhiyun 
815*4882a593Smuzhiyun 		/* exhausted app list */
816*4882a593Smuzhiyun 		if (!pcmd.u.dcb.app_priority.protocolid)
817*4882a593Smuzhiyun 			break;
818*4882a593Smuzhiyun 	}
819*4882a593Smuzhiyun 
820*4882a593Smuzhiyun 	return -EEXIST;
821*4882a593Smuzhiyun }
822*4882a593Smuzhiyun 
823*4882a593Smuzhiyun /* Return the Application User Priority Map associated with the specified
824*4882a593Smuzhiyun  * Application ID.
825*4882a593Smuzhiyun  */
cxgb4_getapp(struct net_device * dev,u8 app_idtype,u16 app_id)826*4882a593Smuzhiyun static int cxgb4_getapp(struct net_device *dev, u8 app_idtype, u16 app_id)
827*4882a593Smuzhiyun {
828*4882a593Smuzhiyun 	/* Convert app_idtype to firmware format before querying */
829*4882a593Smuzhiyun 	return __cxgb4_getapp(dev, app_idtype == DCB_APP_IDTYPE_ETHTYPE ?
830*4882a593Smuzhiyun 			      app_idtype : 3, app_id, 0);
831*4882a593Smuzhiyun }
832*4882a593Smuzhiyun 
833*4882a593Smuzhiyun /* Write a new Application User Priority Map for the specified Application ID
834*4882a593Smuzhiyun  */
__cxgb4_setapp(struct net_device * dev,u8 app_idtype,u16 app_id,u8 app_prio)835*4882a593Smuzhiyun static int __cxgb4_setapp(struct net_device *dev, u8 app_idtype, u16 app_id,
836*4882a593Smuzhiyun 			  u8 app_prio)
837*4882a593Smuzhiyun {
838*4882a593Smuzhiyun 	struct fw_port_cmd pcmd;
839*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
840*4882a593Smuzhiyun 	struct adapter *adap = pi->adapter;
841*4882a593Smuzhiyun 	int i, err;
842*4882a593Smuzhiyun 
843*4882a593Smuzhiyun 
844*4882a593Smuzhiyun 	if (!cxgb4_dcb_state_synced(pi->dcb.state))
845*4882a593Smuzhiyun 		return -EINVAL;
846*4882a593Smuzhiyun 
847*4882a593Smuzhiyun 	/* DCB info gets thrown away on link up */
848*4882a593Smuzhiyun 	if (!netif_carrier_ok(dev))
849*4882a593Smuzhiyun 		return -ENOLINK;
850*4882a593Smuzhiyun 
851*4882a593Smuzhiyun 	for (i = 0; i < CXGB4_MAX_DCBX_APP_SUPPORTED; i++) {
852*4882a593Smuzhiyun 		INIT_PORT_DCB_READ_LOCAL_CMD(pcmd, pi->port_id);
853*4882a593Smuzhiyun 		pcmd.u.dcb.app_priority.type = FW_PORT_DCB_TYPE_APP_ID;
854*4882a593Smuzhiyun 		pcmd.u.dcb.app_priority.idx = i;
855*4882a593Smuzhiyun 		err = t4_wr_mbox(adap, adap->mbox, &pcmd, sizeof(pcmd), &pcmd);
856*4882a593Smuzhiyun 
857*4882a593Smuzhiyun 		if (err != FW_PORT_DCB_CFG_SUCCESS) {
858*4882a593Smuzhiyun 			dev_err(adap->pdev_dev, "DCB app table read failed with %d\n",
859*4882a593Smuzhiyun 				-err);
860*4882a593Smuzhiyun 			return err;
861*4882a593Smuzhiyun 		}
862*4882a593Smuzhiyun 		if (be16_to_cpu(pcmd.u.dcb.app_priority.protocolid) == app_id) {
863*4882a593Smuzhiyun 			/* overwrite existing app table */
864*4882a593Smuzhiyun 			pcmd.u.dcb.app_priority.protocolid = 0;
865*4882a593Smuzhiyun 			break;
866*4882a593Smuzhiyun 		}
867*4882a593Smuzhiyun 		/* find first empty slot */
868*4882a593Smuzhiyun 		if (!pcmd.u.dcb.app_priority.protocolid)
869*4882a593Smuzhiyun 			break;
870*4882a593Smuzhiyun 	}
871*4882a593Smuzhiyun 
872*4882a593Smuzhiyun 	if (i == CXGB4_MAX_DCBX_APP_SUPPORTED) {
873*4882a593Smuzhiyun 		/* no empty slots available */
874*4882a593Smuzhiyun 		dev_err(adap->pdev_dev, "DCB app table full\n");
875*4882a593Smuzhiyun 		return -EBUSY;
876*4882a593Smuzhiyun 	}
877*4882a593Smuzhiyun 
878*4882a593Smuzhiyun 	/* write out new app table entry */
879*4882a593Smuzhiyun 	INIT_PORT_DCB_WRITE_CMD(pcmd, pi->port_id);
880*4882a593Smuzhiyun 	if (pi->dcb.state == CXGB4_DCB_STATE_HOST)
881*4882a593Smuzhiyun 		pcmd.op_to_portid |= cpu_to_be32(FW_PORT_CMD_APPLY_F);
882*4882a593Smuzhiyun 
883*4882a593Smuzhiyun 	pcmd.u.dcb.app_priority.type = FW_PORT_DCB_TYPE_APP_ID;
884*4882a593Smuzhiyun 	pcmd.u.dcb.app_priority.protocolid = cpu_to_be16(app_id);
885*4882a593Smuzhiyun 	pcmd.u.dcb.app_priority.sel_field = app_idtype;
886*4882a593Smuzhiyun 	pcmd.u.dcb.app_priority.user_prio_map = app_prio;
887*4882a593Smuzhiyun 	pcmd.u.dcb.app_priority.idx = i;
888*4882a593Smuzhiyun 
889*4882a593Smuzhiyun 	err = t4_wr_mbox(adap, adap->mbox, &pcmd, sizeof(pcmd), &pcmd);
890*4882a593Smuzhiyun 	if (err != FW_PORT_DCB_CFG_SUCCESS) {
891*4882a593Smuzhiyun 		dev_err(adap->pdev_dev, "DCB app table write failed with %d\n",
892*4882a593Smuzhiyun 			-err);
893*4882a593Smuzhiyun 		return err;
894*4882a593Smuzhiyun 	}
895*4882a593Smuzhiyun 
896*4882a593Smuzhiyun 	return 0;
897*4882a593Smuzhiyun }
898*4882a593Smuzhiyun 
899*4882a593Smuzhiyun /* Priority for CEE inside dcb_app is bitmask, with 0 being an invalid value */
cxgb4_setapp(struct net_device * dev,u8 app_idtype,u16 app_id,u8 app_prio)900*4882a593Smuzhiyun static int cxgb4_setapp(struct net_device *dev, u8 app_idtype, u16 app_id,
901*4882a593Smuzhiyun 			u8 app_prio)
902*4882a593Smuzhiyun {
903*4882a593Smuzhiyun 	int ret;
904*4882a593Smuzhiyun 	struct dcb_app app = {
905*4882a593Smuzhiyun 		.selector = app_idtype,
906*4882a593Smuzhiyun 		.protocol = app_id,
907*4882a593Smuzhiyun 		.priority = app_prio,
908*4882a593Smuzhiyun 	};
909*4882a593Smuzhiyun 
910*4882a593Smuzhiyun 	if (app_idtype != DCB_APP_IDTYPE_ETHTYPE &&
911*4882a593Smuzhiyun 	    app_idtype != DCB_APP_IDTYPE_PORTNUM)
912*4882a593Smuzhiyun 		return -EINVAL;
913*4882a593Smuzhiyun 
914*4882a593Smuzhiyun 	/* Convert app_idtype to a format that firmware understands */
915*4882a593Smuzhiyun 	ret = __cxgb4_setapp(dev, app_idtype == DCB_APP_IDTYPE_ETHTYPE ?
916*4882a593Smuzhiyun 			      app_idtype : 3, app_id, app_prio);
917*4882a593Smuzhiyun 	if (ret)
918*4882a593Smuzhiyun 		return ret;
919*4882a593Smuzhiyun 
920*4882a593Smuzhiyun 	return dcb_setapp(dev, &app);
921*4882a593Smuzhiyun }
922*4882a593Smuzhiyun 
923*4882a593Smuzhiyun /* Return whether IEEE Data Center Bridging has been negotiated.
924*4882a593Smuzhiyun  */
925*4882a593Smuzhiyun static inline int
cxgb4_ieee_negotiation_complete(struct net_device * dev,enum cxgb4_dcb_fw_msgs dcb_subtype)926*4882a593Smuzhiyun cxgb4_ieee_negotiation_complete(struct net_device *dev,
927*4882a593Smuzhiyun 				enum cxgb4_dcb_fw_msgs dcb_subtype)
928*4882a593Smuzhiyun {
929*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
930*4882a593Smuzhiyun 	struct port_dcb_info *dcb = &pi->dcb;
931*4882a593Smuzhiyun 
932*4882a593Smuzhiyun 	if (dcb->state == CXGB4_DCB_STATE_FW_ALLSYNCED)
933*4882a593Smuzhiyun 		if (dcb_subtype && !(dcb->msgs & dcb_subtype))
934*4882a593Smuzhiyun 			return 0;
935*4882a593Smuzhiyun 
936*4882a593Smuzhiyun 	return (cxgb4_dcb_state_synced(dcb->state) &&
937*4882a593Smuzhiyun 		(dcb->supported & DCB_CAP_DCBX_VER_IEEE));
938*4882a593Smuzhiyun }
939*4882a593Smuzhiyun 
cxgb4_ieee_read_ets(struct net_device * dev,struct ieee_ets * ets,int local)940*4882a593Smuzhiyun static int cxgb4_ieee_read_ets(struct net_device *dev, struct ieee_ets *ets,
941*4882a593Smuzhiyun 			       int local)
942*4882a593Smuzhiyun {
943*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
944*4882a593Smuzhiyun 	struct port_dcb_info *dcb = &pi->dcb;
945*4882a593Smuzhiyun 	struct adapter *adap = pi->adapter;
946*4882a593Smuzhiyun 	uint32_t tc_info;
947*4882a593Smuzhiyun 	struct fw_port_cmd pcmd;
948*4882a593Smuzhiyun 	int i, bwg, err;
949*4882a593Smuzhiyun 
950*4882a593Smuzhiyun 	if (!(dcb->msgs & (CXGB4_DCB_FW_PGID | CXGB4_DCB_FW_PGRATE)))
951*4882a593Smuzhiyun 		return 0;
952*4882a593Smuzhiyun 
953*4882a593Smuzhiyun 	ets->ets_cap =  dcb->pg_num_tcs_supported;
954*4882a593Smuzhiyun 
955*4882a593Smuzhiyun 	if (local) {
956*4882a593Smuzhiyun 		ets->willing = 1;
957*4882a593Smuzhiyun 		INIT_PORT_DCB_READ_LOCAL_CMD(pcmd, pi->port_id);
958*4882a593Smuzhiyun 	} else {
959*4882a593Smuzhiyun 		INIT_PORT_DCB_READ_PEER_CMD(pcmd, pi->port_id);
960*4882a593Smuzhiyun 	}
961*4882a593Smuzhiyun 
962*4882a593Smuzhiyun 	pcmd.u.dcb.pgid.type = FW_PORT_DCB_TYPE_PGID;
963*4882a593Smuzhiyun 	err = t4_wr_mbox(adap, adap->mbox, &pcmd, sizeof(pcmd), &pcmd);
964*4882a593Smuzhiyun 	if (err != FW_PORT_DCB_CFG_SUCCESS) {
965*4882a593Smuzhiyun 		dev_err(adap->pdev_dev, "DCB read PGID failed with %d\n", -err);
966*4882a593Smuzhiyun 		return err;
967*4882a593Smuzhiyun 	}
968*4882a593Smuzhiyun 
969*4882a593Smuzhiyun 	tc_info = be32_to_cpu(pcmd.u.dcb.pgid.pgid);
970*4882a593Smuzhiyun 
971*4882a593Smuzhiyun 	if (local)
972*4882a593Smuzhiyun 		INIT_PORT_DCB_READ_LOCAL_CMD(pcmd, pi->port_id);
973*4882a593Smuzhiyun 	else
974*4882a593Smuzhiyun 		INIT_PORT_DCB_READ_PEER_CMD(pcmd, pi->port_id);
975*4882a593Smuzhiyun 
976*4882a593Smuzhiyun 	pcmd.u.dcb.pgrate.type = FW_PORT_DCB_TYPE_PGRATE;
977*4882a593Smuzhiyun 	err = t4_wr_mbox(adap, adap->mbox, &pcmd, sizeof(pcmd), &pcmd);
978*4882a593Smuzhiyun 	if (err != FW_PORT_DCB_CFG_SUCCESS) {
979*4882a593Smuzhiyun 		dev_err(adap->pdev_dev, "DCB read PGRATE failed with %d\n",
980*4882a593Smuzhiyun 			-err);
981*4882a593Smuzhiyun 		return err;
982*4882a593Smuzhiyun 	}
983*4882a593Smuzhiyun 
984*4882a593Smuzhiyun 	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
985*4882a593Smuzhiyun 		bwg = (tc_info >> ((7 - i) * 4)) & 0xF;
986*4882a593Smuzhiyun 		ets->prio_tc[i] = bwg;
987*4882a593Smuzhiyun 		ets->tc_tx_bw[i] = pcmd.u.dcb.pgrate.pgrate[i];
988*4882a593Smuzhiyun 		ets->tc_rx_bw[i] = ets->tc_tx_bw[i];
989*4882a593Smuzhiyun 		ets->tc_tsa[i] = pcmd.u.dcb.pgrate.tsa[i];
990*4882a593Smuzhiyun 	}
991*4882a593Smuzhiyun 
992*4882a593Smuzhiyun 	return 0;
993*4882a593Smuzhiyun }
994*4882a593Smuzhiyun 
cxgb4_ieee_get_ets(struct net_device * dev,struct ieee_ets * ets)995*4882a593Smuzhiyun static int cxgb4_ieee_get_ets(struct net_device *dev, struct ieee_ets *ets)
996*4882a593Smuzhiyun {
997*4882a593Smuzhiyun 	return cxgb4_ieee_read_ets(dev, ets, 1);
998*4882a593Smuzhiyun }
999*4882a593Smuzhiyun 
1000*4882a593Smuzhiyun /* We reuse this for peer PFC as well, as we can't have it enabled one way */
cxgb4_ieee_get_pfc(struct net_device * dev,struct ieee_pfc * pfc)1001*4882a593Smuzhiyun static int cxgb4_ieee_get_pfc(struct net_device *dev, struct ieee_pfc *pfc)
1002*4882a593Smuzhiyun {
1003*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
1004*4882a593Smuzhiyun 	struct port_dcb_info *dcb = &pi->dcb;
1005*4882a593Smuzhiyun 
1006*4882a593Smuzhiyun 	memset(pfc, 0, sizeof(struct ieee_pfc));
1007*4882a593Smuzhiyun 
1008*4882a593Smuzhiyun 	if (!(dcb->msgs & CXGB4_DCB_FW_PFC))
1009*4882a593Smuzhiyun 		return 0;
1010*4882a593Smuzhiyun 
1011*4882a593Smuzhiyun 	pfc->pfc_cap = dcb->pfc_num_tcs_supported;
1012*4882a593Smuzhiyun 	pfc->pfc_en = bitswap_1(dcb->pfcen);
1013*4882a593Smuzhiyun 
1014*4882a593Smuzhiyun 	return 0;
1015*4882a593Smuzhiyun }
1016*4882a593Smuzhiyun 
cxgb4_ieee_peer_ets(struct net_device * dev,struct ieee_ets * ets)1017*4882a593Smuzhiyun static int cxgb4_ieee_peer_ets(struct net_device *dev, struct ieee_ets *ets)
1018*4882a593Smuzhiyun {
1019*4882a593Smuzhiyun 	return cxgb4_ieee_read_ets(dev, ets, 0);
1020*4882a593Smuzhiyun }
1021*4882a593Smuzhiyun 
1022*4882a593Smuzhiyun /* Fill in the Application User Priority Map associated with the
1023*4882a593Smuzhiyun  * specified Application.
1024*4882a593Smuzhiyun  * Priority for IEEE dcb_app is an integer, with 0 being a valid value
1025*4882a593Smuzhiyun  */
cxgb4_ieee_getapp(struct net_device * dev,struct dcb_app * app)1026*4882a593Smuzhiyun static int cxgb4_ieee_getapp(struct net_device *dev, struct dcb_app *app)
1027*4882a593Smuzhiyun {
1028*4882a593Smuzhiyun 	int prio;
1029*4882a593Smuzhiyun 
1030*4882a593Smuzhiyun 	if (!cxgb4_ieee_negotiation_complete(dev, CXGB4_DCB_FW_APP_ID))
1031*4882a593Smuzhiyun 		return -EINVAL;
1032*4882a593Smuzhiyun 	if (!(app->selector && app->protocol))
1033*4882a593Smuzhiyun 		return -EINVAL;
1034*4882a593Smuzhiyun 
1035*4882a593Smuzhiyun 	/* Try querying firmware first, use firmware format */
1036*4882a593Smuzhiyun 	prio = __cxgb4_getapp(dev, app->selector - 1, app->protocol, 0);
1037*4882a593Smuzhiyun 
1038*4882a593Smuzhiyun 	if (prio < 0)
1039*4882a593Smuzhiyun 		prio = dcb_ieee_getapp_mask(dev, app);
1040*4882a593Smuzhiyun 
1041*4882a593Smuzhiyun 	app->priority = ffs(prio) - 1;
1042*4882a593Smuzhiyun 	return 0;
1043*4882a593Smuzhiyun }
1044*4882a593Smuzhiyun 
1045*4882a593Smuzhiyun /* Write a new Application User Priority Map for the specified Application ID.
1046*4882a593Smuzhiyun  * Priority for IEEE dcb_app is an integer, with 0 being a valid value
1047*4882a593Smuzhiyun  */
cxgb4_ieee_setapp(struct net_device * dev,struct dcb_app * app)1048*4882a593Smuzhiyun static int cxgb4_ieee_setapp(struct net_device *dev, struct dcb_app *app)
1049*4882a593Smuzhiyun {
1050*4882a593Smuzhiyun 	int ret;
1051*4882a593Smuzhiyun 
1052*4882a593Smuzhiyun 	if (!cxgb4_ieee_negotiation_complete(dev, CXGB4_DCB_FW_APP_ID))
1053*4882a593Smuzhiyun 		return -EINVAL;
1054*4882a593Smuzhiyun 	if (!(app->selector && app->protocol))
1055*4882a593Smuzhiyun 		return -EINVAL;
1056*4882a593Smuzhiyun 
1057*4882a593Smuzhiyun 	if (!(app->selector > IEEE_8021QAZ_APP_SEL_ETHERTYPE  &&
1058*4882a593Smuzhiyun 	      app->selector < IEEE_8021QAZ_APP_SEL_ANY))
1059*4882a593Smuzhiyun 		return -EINVAL;
1060*4882a593Smuzhiyun 
1061*4882a593Smuzhiyun 	/* change selector to a format that firmware understands */
1062*4882a593Smuzhiyun 	ret = __cxgb4_setapp(dev, app->selector - 1, app->protocol,
1063*4882a593Smuzhiyun 			     (1 << app->priority));
1064*4882a593Smuzhiyun 	if (ret)
1065*4882a593Smuzhiyun 		return ret;
1066*4882a593Smuzhiyun 
1067*4882a593Smuzhiyun 	return dcb_ieee_setapp(dev, app);
1068*4882a593Smuzhiyun }
1069*4882a593Smuzhiyun 
1070*4882a593Smuzhiyun /* Return our DCBX parameters.
1071*4882a593Smuzhiyun  */
cxgb4_getdcbx(struct net_device * dev)1072*4882a593Smuzhiyun static u8 cxgb4_getdcbx(struct net_device *dev)
1073*4882a593Smuzhiyun {
1074*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
1075*4882a593Smuzhiyun 
1076*4882a593Smuzhiyun 	/* This is already set by cxgb4_set_dcb_caps, so just return it */
1077*4882a593Smuzhiyun 	return pi->dcb.supported;
1078*4882a593Smuzhiyun }
1079*4882a593Smuzhiyun 
1080*4882a593Smuzhiyun /* Set our DCBX parameters.
1081*4882a593Smuzhiyun  */
cxgb4_setdcbx(struct net_device * dev,u8 dcb_request)1082*4882a593Smuzhiyun static u8 cxgb4_setdcbx(struct net_device *dev, u8 dcb_request)
1083*4882a593Smuzhiyun {
1084*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
1085*4882a593Smuzhiyun 
1086*4882a593Smuzhiyun 	/* Filter out requests which exceed our capabilities.
1087*4882a593Smuzhiyun 	 */
1088*4882a593Smuzhiyun 	if ((dcb_request & (CXGB4_DCBX_FW_SUPPORT | CXGB4_DCBX_HOST_SUPPORT))
1089*4882a593Smuzhiyun 	    != dcb_request)
1090*4882a593Smuzhiyun 		return 1;
1091*4882a593Smuzhiyun 
1092*4882a593Smuzhiyun 	/* Can't enable DCB if we haven't successfully negotiated it.
1093*4882a593Smuzhiyun 	 */
1094*4882a593Smuzhiyun 	if (!cxgb4_dcb_state_synced(pi->dcb.state))
1095*4882a593Smuzhiyun 		return 1;
1096*4882a593Smuzhiyun 
1097*4882a593Smuzhiyun 	/* There's currently no mechanism to allow for the firmware DCBX
1098*4882a593Smuzhiyun 	 * negotiation to be changed from the Host Driver.  If the caller
1099*4882a593Smuzhiyun 	 * requests exactly the same parameters that we already have then
1100*4882a593Smuzhiyun 	 * we'll allow them to be successfully "set" ...
1101*4882a593Smuzhiyun 	 */
1102*4882a593Smuzhiyun 	if (dcb_request != pi->dcb.supported)
1103*4882a593Smuzhiyun 		return 1;
1104*4882a593Smuzhiyun 
1105*4882a593Smuzhiyun 	pi->dcb.supported = dcb_request;
1106*4882a593Smuzhiyun 	return 0;
1107*4882a593Smuzhiyun }
1108*4882a593Smuzhiyun 
cxgb4_getpeer_app(struct net_device * dev,struct dcb_peer_app_info * info,u16 * app_count)1109*4882a593Smuzhiyun static int cxgb4_getpeer_app(struct net_device *dev,
1110*4882a593Smuzhiyun 			     struct dcb_peer_app_info *info, u16 *app_count)
1111*4882a593Smuzhiyun {
1112*4882a593Smuzhiyun 	struct fw_port_cmd pcmd;
1113*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
1114*4882a593Smuzhiyun 	struct adapter *adap = pi->adapter;
1115*4882a593Smuzhiyun 	int i, err = 0;
1116*4882a593Smuzhiyun 
1117*4882a593Smuzhiyun 	if (!cxgb4_dcb_state_synced(pi->dcb.state))
1118*4882a593Smuzhiyun 		return 1;
1119*4882a593Smuzhiyun 
1120*4882a593Smuzhiyun 	info->willing = 0;
1121*4882a593Smuzhiyun 	info->error = 0;
1122*4882a593Smuzhiyun 
1123*4882a593Smuzhiyun 	*app_count = 0;
1124*4882a593Smuzhiyun 	for (i = 0; i < CXGB4_MAX_DCBX_APP_SUPPORTED; i++) {
1125*4882a593Smuzhiyun 		INIT_PORT_DCB_READ_PEER_CMD(pcmd, pi->port_id);
1126*4882a593Smuzhiyun 		pcmd.u.dcb.app_priority.type = FW_PORT_DCB_TYPE_APP_ID;
1127*4882a593Smuzhiyun 		pcmd.u.dcb.app_priority.idx = *app_count;
1128*4882a593Smuzhiyun 		err = t4_wr_mbox(adap, adap->mbox, &pcmd, sizeof(pcmd), &pcmd);
1129*4882a593Smuzhiyun 
1130*4882a593Smuzhiyun 		if (err != FW_PORT_DCB_CFG_SUCCESS) {
1131*4882a593Smuzhiyun 			dev_err(adap->pdev_dev, "DCB app table read failed with %d\n",
1132*4882a593Smuzhiyun 				-err);
1133*4882a593Smuzhiyun 			return err;
1134*4882a593Smuzhiyun 		}
1135*4882a593Smuzhiyun 
1136*4882a593Smuzhiyun 		/* find first empty slot */
1137*4882a593Smuzhiyun 		if (!pcmd.u.dcb.app_priority.protocolid)
1138*4882a593Smuzhiyun 			break;
1139*4882a593Smuzhiyun 	}
1140*4882a593Smuzhiyun 	*app_count = i;
1141*4882a593Smuzhiyun 	return err;
1142*4882a593Smuzhiyun }
1143*4882a593Smuzhiyun 
cxgb4_getpeerapp_tbl(struct net_device * dev,struct dcb_app * table)1144*4882a593Smuzhiyun static int cxgb4_getpeerapp_tbl(struct net_device *dev, struct dcb_app *table)
1145*4882a593Smuzhiyun {
1146*4882a593Smuzhiyun 	struct fw_port_cmd pcmd;
1147*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
1148*4882a593Smuzhiyun 	struct adapter *adap = pi->adapter;
1149*4882a593Smuzhiyun 	int i, err = 0;
1150*4882a593Smuzhiyun 
1151*4882a593Smuzhiyun 	if (!cxgb4_dcb_state_synced(pi->dcb.state))
1152*4882a593Smuzhiyun 		return 1;
1153*4882a593Smuzhiyun 
1154*4882a593Smuzhiyun 	for (i = 0; i < CXGB4_MAX_DCBX_APP_SUPPORTED; i++) {
1155*4882a593Smuzhiyun 		INIT_PORT_DCB_READ_PEER_CMD(pcmd, pi->port_id);
1156*4882a593Smuzhiyun 		pcmd.u.dcb.app_priority.type = FW_PORT_DCB_TYPE_APP_ID;
1157*4882a593Smuzhiyun 		pcmd.u.dcb.app_priority.idx = i;
1158*4882a593Smuzhiyun 		err = t4_wr_mbox(adap, adap->mbox, &pcmd, sizeof(pcmd), &pcmd);
1159*4882a593Smuzhiyun 
1160*4882a593Smuzhiyun 		if (err != FW_PORT_DCB_CFG_SUCCESS) {
1161*4882a593Smuzhiyun 			dev_err(adap->pdev_dev, "DCB app table read failed with %d\n",
1162*4882a593Smuzhiyun 				-err);
1163*4882a593Smuzhiyun 			return err;
1164*4882a593Smuzhiyun 		}
1165*4882a593Smuzhiyun 
1166*4882a593Smuzhiyun 		/* find first empty slot */
1167*4882a593Smuzhiyun 		if (!pcmd.u.dcb.app_priority.protocolid)
1168*4882a593Smuzhiyun 			break;
1169*4882a593Smuzhiyun 
1170*4882a593Smuzhiyun 		table[i].selector = (pcmd.u.dcb.app_priority.sel_field + 1);
1171*4882a593Smuzhiyun 		table[i].protocol =
1172*4882a593Smuzhiyun 			be16_to_cpu(pcmd.u.dcb.app_priority.protocolid);
1173*4882a593Smuzhiyun 		table[i].priority =
1174*4882a593Smuzhiyun 			ffs(pcmd.u.dcb.app_priority.user_prio_map) - 1;
1175*4882a593Smuzhiyun 	}
1176*4882a593Smuzhiyun 	return err;
1177*4882a593Smuzhiyun }
1178*4882a593Smuzhiyun 
1179*4882a593Smuzhiyun /* Return Priority Group information.
1180*4882a593Smuzhiyun  */
cxgb4_cee_peer_getpg(struct net_device * dev,struct cee_pg * pg)1181*4882a593Smuzhiyun static int cxgb4_cee_peer_getpg(struct net_device *dev, struct cee_pg *pg)
1182*4882a593Smuzhiyun {
1183*4882a593Smuzhiyun 	struct fw_port_cmd pcmd;
1184*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
1185*4882a593Smuzhiyun 	struct adapter *adap = pi->adapter;
1186*4882a593Smuzhiyun 	u32 pgid;
1187*4882a593Smuzhiyun 	int i, err;
1188*4882a593Smuzhiyun 
1189*4882a593Smuzhiyun 	/* We're always "willing" -- the Switch Fabric always dictates the
1190*4882a593Smuzhiyun 	 * DCBX parameters to us.
1191*4882a593Smuzhiyun 	 */
1192*4882a593Smuzhiyun 	pg->willing = true;
1193*4882a593Smuzhiyun 
1194*4882a593Smuzhiyun 	INIT_PORT_DCB_READ_PEER_CMD(pcmd, pi->port_id);
1195*4882a593Smuzhiyun 	pcmd.u.dcb.pgid.type = FW_PORT_DCB_TYPE_PGID;
1196*4882a593Smuzhiyun 	err = t4_wr_mbox(adap, adap->mbox, &pcmd, sizeof(pcmd), &pcmd);
1197*4882a593Smuzhiyun 	if (err != FW_PORT_DCB_CFG_SUCCESS) {
1198*4882a593Smuzhiyun 		dev_err(adap->pdev_dev, "DCB read PGID failed with %d\n", -err);
1199*4882a593Smuzhiyun 		return err;
1200*4882a593Smuzhiyun 	}
1201*4882a593Smuzhiyun 	pgid = be32_to_cpu(pcmd.u.dcb.pgid.pgid);
1202*4882a593Smuzhiyun 
1203*4882a593Smuzhiyun 	for (i = 0; i < CXGB4_MAX_PRIORITY; i++)
1204*4882a593Smuzhiyun 		pg->prio_pg[7 - i] = (pgid >> (i * 4)) & 0xF;
1205*4882a593Smuzhiyun 
1206*4882a593Smuzhiyun 	INIT_PORT_DCB_READ_PEER_CMD(pcmd, pi->port_id);
1207*4882a593Smuzhiyun 	pcmd.u.dcb.pgrate.type = FW_PORT_DCB_TYPE_PGRATE;
1208*4882a593Smuzhiyun 	err = t4_wr_mbox(adap, adap->mbox, &pcmd, sizeof(pcmd), &pcmd);
1209*4882a593Smuzhiyun 	if (err != FW_PORT_DCB_CFG_SUCCESS) {
1210*4882a593Smuzhiyun 		dev_err(adap->pdev_dev, "DCB read PGRATE failed with %d\n",
1211*4882a593Smuzhiyun 			-err);
1212*4882a593Smuzhiyun 		return err;
1213*4882a593Smuzhiyun 	}
1214*4882a593Smuzhiyun 
1215*4882a593Smuzhiyun 	for (i = 0; i < CXGB4_MAX_PRIORITY; i++)
1216*4882a593Smuzhiyun 		pg->pg_bw[i] = pcmd.u.dcb.pgrate.pgrate[i];
1217*4882a593Smuzhiyun 
1218*4882a593Smuzhiyun 	pg->tcs_supported = pcmd.u.dcb.pgrate.num_tcs_supported;
1219*4882a593Smuzhiyun 
1220*4882a593Smuzhiyun 	return 0;
1221*4882a593Smuzhiyun }
1222*4882a593Smuzhiyun 
1223*4882a593Smuzhiyun /* Return Priority Flow Control information.
1224*4882a593Smuzhiyun  */
cxgb4_cee_peer_getpfc(struct net_device * dev,struct cee_pfc * pfc)1225*4882a593Smuzhiyun static int cxgb4_cee_peer_getpfc(struct net_device *dev, struct cee_pfc *pfc)
1226*4882a593Smuzhiyun {
1227*4882a593Smuzhiyun 	struct port_info *pi = netdev2pinfo(dev);
1228*4882a593Smuzhiyun 
1229*4882a593Smuzhiyun 	cxgb4_getnumtcs(dev, DCB_NUMTCS_ATTR_PFC, &(pfc->tcs_supported));
1230*4882a593Smuzhiyun 
1231*4882a593Smuzhiyun 	/* Firmware sends this to us in a formwat that is a bit flipped version
1232*4882a593Smuzhiyun 	 * of spec, correct it before we send it to host. This is taken care of
1233*4882a593Smuzhiyun 	 * by bit shifting in other uses of pfcen
1234*4882a593Smuzhiyun 	 */
1235*4882a593Smuzhiyun 	pfc->pfc_en = bitswap_1(pi->dcb.pfcen);
1236*4882a593Smuzhiyun 
1237*4882a593Smuzhiyun 	pfc->tcs_supported = pi->dcb.pfc_num_tcs_supported;
1238*4882a593Smuzhiyun 
1239*4882a593Smuzhiyun 	return 0;
1240*4882a593Smuzhiyun }
1241*4882a593Smuzhiyun 
1242*4882a593Smuzhiyun const struct dcbnl_rtnl_ops cxgb4_dcb_ops = {
1243*4882a593Smuzhiyun 	.ieee_getets		= cxgb4_ieee_get_ets,
1244*4882a593Smuzhiyun 	.ieee_getpfc		= cxgb4_ieee_get_pfc,
1245*4882a593Smuzhiyun 	.ieee_getapp		= cxgb4_ieee_getapp,
1246*4882a593Smuzhiyun 	.ieee_setapp		= cxgb4_ieee_setapp,
1247*4882a593Smuzhiyun 	.ieee_peer_getets	= cxgb4_ieee_peer_ets,
1248*4882a593Smuzhiyun 	.ieee_peer_getpfc	= cxgb4_ieee_get_pfc,
1249*4882a593Smuzhiyun 
1250*4882a593Smuzhiyun 	/* CEE std */
1251*4882a593Smuzhiyun 	.getstate		= cxgb4_getstate,
1252*4882a593Smuzhiyun 	.setstate		= cxgb4_setstate,
1253*4882a593Smuzhiyun 	.getpgtccfgtx		= cxgb4_getpgtccfg_tx,
1254*4882a593Smuzhiyun 	.getpgbwgcfgtx		= cxgb4_getpgbwgcfg_tx,
1255*4882a593Smuzhiyun 	.getpgtccfgrx		= cxgb4_getpgtccfg_rx,
1256*4882a593Smuzhiyun 	.getpgbwgcfgrx		= cxgb4_getpgbwgcfg_rx,
1257*4882a593Smuzhiyun 	.setpgtccfgtx		= cxgb4_setpgtccfg_tx,
1258*4882a593Smuzhiyun 	.setpgbwgcfgtx		= cxgb4_setpgbwgcfg_tx,
1259*4882a593Smuzhiyun 	.setpfccfg		= cxgb4_setpfccfg,
1260*4882a593Smuzhiyun 	.getpfccfg		= cxgb4_getpfccfg,
1261*4882a593Smuzhiyun 	.setall			= cxgb4_setall,
1262*4882a593Smuzhiyun 	.getcap			= cxgb4_getcap,
1263*4882a593Smuzhiyun 	.getnumtcs		= cxgb4_getnumtcs,
1264*4882a593Smuzhiyun 	.setnumtcs		= cxgb4_setnumtcs,
1265*4882a593Smuzhiyun 	.getpfcstate		= cxgb4_getpfcstate,
1266*4882a593Smuzhiyun 	.setpfcstate		= cxgb4_setpfcstate,
1267*4882a593Smuzhiyun 	.getapp			= cxgb4_getapp,
1268*4882a593Smuzhiyun 	.setapp			= cxgb4_setapp,
1269*4882a593Smuzhiyun 
1270*4882a593Smuzhiyun 	/* DCBX configuration */
1271*4882a593Smuzhiyun 	.getdcbx		= cxgb4_getdcbx,
1272*4882a593Smuzhiyun 	.setdcbx		= cxgb4_setdcbx,
1273*4882a593Smuzhiyun 
1274*4882a593Smuzhiyun 	/* peer apps */
1275*4882a593Smuzhiyun 	.peer_getappinfo	= cxgb4_getpeer_app,
1276*4882a593Smuzhiyun 	.peer_getapptable	= cxgb4_getpeerapp_tbl,
1277*4882a593Smuzhiyun 
1278*4882a593Smuzhiyun 	/* CEE peer */
1279*4882a593Smuzhiyun 	.cee_peer_getpg		= cxgb4_cee_peer_getpg,
1280*4882a593Smuzhiyun 	.cee_peer_getpfc	= cxgb4_cee_peer_getpfc,
1281*4882a593Smuzhiyun };
1282