1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2017 Chelsio Communications. All rights reserved.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #ifndef __CUDBG_IF_H__
7*4882a593Smuzhiyun #define __CUDBG_IF_H__
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun /* Error codes */
10*4882a593Smuzhiyun #define CUDBG_STATUS_NO_MEM -19
11*4882a593Smuzhiyun #define CUDBG_STATUS_ENTITY_NOT_FOUND -24
12*4882a593Smuzhiyun #define CUDBG_STATUS_NOT_IMPLEMENTED -28
13*4882a593Smuzhiyun #define CUDBG_SYSTEM_ERROR -29
14*4882a593Smuzhiyun #define CUDBG_STATUS_CCLK_NOT_DEFINED -32
15*4882a593Smuzhiyun #define CUDBG_STATUS_PARTIAL_DATA -41
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define CUDBG_MAJOR_VERSION 1
18*4882a593Smuzhiyun #define CUDBG_MINOR_VERSION 14
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun enum cudbg_dbg_entity_type {
21*4882a593Smuzhiyun CUDBG_REG_DUMP = 1,
22*4882a593Smuzhiyun CUDBG_DEV_LOG = 2,
23*4882a593Smuzhiyun CUDBG_CIM_LA = 3,
24*4882a593Smuzhiyun CUDBG_CIM_MA_LA = 4,
25*4882a593Smuzhiyun CUDBG_CIM_QCFG = 5,
26*4882a593Smuzhiyun CUDBG_CIM_IBQ_TP0 = 6,
27*4882a593Smuzhiyun CUDBG_CIM_IBQ_TP1 = 7,
28*4882a593Smuzhiyun CUDBG_CIM_IBQ_ULP = 8,
29*4882a593Smuzhiyun CUDBG_CIM_IBQ_SGE0 = 9,
30*4882a593Smuzhiyun CUDBG_CIM_IBQ_SGE1 = 10,
31*4882a593Smuzhiyun CUDBG_CIM_IBQ_NCSI = 11,
32*4882a593Smuzhiyun CUDBG_CIM_OBQ_ULP0 = 12,
33*4882a593Smuzhiyun CUDBG_CIM_OBQ_ULP1 = 13,
34*4882a593Smuzhiyun CUDBG_CIM_OBQ_ULP2 = 14,
35*4882a593Smuzhiyun CUDBG_CIM_OBQ_ULP3 = 15,
36*4882a593Smuzhiyun CUDBG_CIM_OBQ_SGE = 16,
37*4882a593Smuzhiyun CUDBG_CIM_OBQ_NCSI = 17,
38*4882a593Smuzhiyun CUDBG_EDC0 = 18,
39*4882a593Smuzhiyun CUDBG_EDC1 = 19,
40*4882a593Smuzhiyun CUDBG_MC0 = 20,
41*4882a593Smuzhiyun CUDBG_MC1 = 21,
42*4882a593Smuzhiyun CUDBG_RSS = 22,
43*4882a593Smuzhiyun CUDBG_RSS_VF_CONF = 25,
44*4882a593Smuzhiyun CUDBG_PATH_MTU = 27,
45*4882a593Smuzhiyun CUDBG_PM_STATS = 30,
46*4882a593Smuzhiyun CUDBG_HW_SCHED = 31,
47*4882a593Smuzhiyun CUDBG_TP_INDIRECT = 36,
48*4882a593Smuzhiyun CUDBG_SGE_INDIRECT = 37,
49*4882a593Smuzhiyun CUDBG_ULPRX_LA = 41,
50*4882a593Smuzhiyun CUDBG_TP_LA = 43,
51*4882a593Smuzhiyun CUDBG_MEMINFO = 44,
52*4882a593Smuzhiyun CUDBG_CIM_PIF_LA = 45,
53*4882a593Smuzhiyun CUDBG_CLK = 46,
54*4882a593Smuzhiyun CUDBG_CIM_OBQ_RXQ0 = 47,
55*4882a593Smuzhiyun CUDBG_CIM_OBQ_RXQ1 = 48,
56*4882a593Smuzhiyun CUDBG_PCIE_INDIRECT = 50,
57*4882a593Smuzhiyun CUDBG_PM_INDIRECT = 51,
58*4882a593Smuzhiyun CUDBG_TID_INFO = 54,
59*4882a593Smuzhiyun CUDBG_PCIE_CONFIG = 55,
60*4882a593Smuzhiyun CUDBG_DUMP_CONTEXT = 56,
61*4882a593Smuzhiyun CUDBG_MPS_TCAM = 57,
62*4882a593Smuzhiyun CUDBG_VPD_DATA = 58,
63*4882a593Smuzhiyun CUDBG_LE_TCAM = 59,
64*4882a593Smuzhiyun CUDBG_CCTRL = 60,
65*4882a593Smuzhiyun CUDBG_MA_INDIRECT = 61,
66*4882a593Smuzhiyun CUDBG_ULPTX_LA = 62,
67*4882a593Smuzhiyun CUDBG_UP_CIM_INDIRECT = 64,
68*4882a593Smuzhiyun CUDBG_PBT_TABLE = 65,
69*4882a593Smuzhiyun CUDBG_MBOX_LOG = 66,
70*4882a593Smuzhiyun CUDBG_HMA_INDIRECT = 67,
71*4882a593Smuzhiyun CUDBG_HMA = 68,
72*4882a593Smuzhiyun CUDBG_QDESC = 70,
73*4882a593Smuzhiyun CUDBG_FLASH = 71,
74*4882a593Smuzhiyun CUDBG_MAX_ENTITY = 72,
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun struct cudbg_init {
78*4882a593Smuzhiyun struct adapter *adap; /* Pointer to adapter structure */
79*4882a593Smuzhiyun void *outbuf; /* Output buffer */
80*4882a593Smuzhiyun u32 outbuf_size; /* Output buffer size */
81*4882a593Smuzhiyun u8 compress_type; /* Type of compression to use */
82*4882a593Smuzhiyun void *compress_buff; /* Compression buffer */
83*4882a593Smuzhiyun u32 compress_buff_size; /* Compression buffer size */
84*4882a593Smuzhiyun void *workspace; /* Workspace for zlib */
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun
cudbg_mbytes_to_bytes(unsigned int size)87*4882a593Smuzhiyun static inline unsigned int cudbg_mbytes_to_bytes(unsigned int size)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun return size * 1024 * 1024;
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun #endif /* __CUDBG_IF_H__ */
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