xref: /OK3568_Linux_fs/kernel/drivers/net/ethernet/chelsio/cxgb3/sge_defs.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * This file is automatically generated --- any changes will be lost.
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #ifndef _SGE_DEFS_H
7*4882a593Smuzhiyun #define _SGE_DEFS_H
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #define S_EC_CREDITS    0
10*4882a593Smuzhiyun #define M_EC_CREDITS    0x7FFF
11*4882a593Smuzhiyun #define V_EC_CREDITS(x) ((x) << S_EC_CREDITS)
12*4882a593Smuzhiyun #define G_EC_CREDITS(x) (((x) >> S_EC_CREDITS) & M_EC_CREDITS)
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #define S_EC_GTS    15
15*4882a593Smuzhiyun #define V_EC_GTS(x) ((x) << S_EC_GTS)
16*4882a593Smuzhiyun #define F_EC_GTS    V_EC_GTS(1U)
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define S_EC_INDEX    16
19*4882a593Smuzhiyun #define M_EC_INDEX    0xFFFF
20*4882a593Smuzhiyun #define V_EC_INDEX(x) ((x) << S_EC_INDEX)
21*4882a593Smuzhiyun #define G_EC_INDEX(x) (((x) >> S_EC_INDEX) & M_EC_INDEX)
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #define S_EC_SIZE    0
24*4882a593Smuzhiyun #define M_EC_SIZE    0xFFFF
25*4882a593Smuzhiyun #define V_EC_SIZE(x) ((x) << S_EC_SIZE)
26*4882a593Smuzhiyun #define G_EC_SIZE(x) (((x) >> S_EC_SIZE) & M_EC_SIZE)
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #define S_EC_BASE_LO    16
29*4882a593Smuzhiyun #define M_EC_BASE_LO    0xFFFF
30*4882a593Smuzhiyun #define V_EC_BASE_LO(x) ((x) << S_EC_BASE_LO)
31*4882a593Smuzhiyun #define G_EC_BASE_LO(x) (((x) >> S_EC_BASE_LO) & M_EC_BASE_LO)
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define S_EC_BASE_HI    0
34*4882a593Smuzhiyun #define M_EC_BASE_HI    0xF
35*4882a593Smuzhiyun #define V_EC_BASE_HI(x) ((x) << S_EC_BASE_HI)
36*4882a593Smuzhiyun #define G_EC_BASE_HI(x) (((x) >> S_EC_BASE_HI) & M_EC_BASE_HI)
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #define S_EC_RESPQ    4
39*4882a593Smuzhiyun #define M_EC_RESPQ    0x7
40*4882a593Smuzhiyun #define V_EC_RESPQ(x) ((x) << S_EC_RESPQ)
41*4882a593Smuzhiyun #define G_EC_RESPQ(x) (((x) >> S_EC_RESPQ) & M_EC_RESPQ)
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #define S_EC_TYPE    7
44*4882a593Smuzhiyun #define M_EC_TYPE    0x7
45*4882a593Smuzhiyun #define V_EC_TYPE(x) ((x) << S_EC_TYPE)
46*4882a593Smuzhiyun #define G_EC_TYPE(x) (((x) >> S_EC_TYPE) & M_EC_TYPE)
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #define S_EC_GEN    10
49*4882a593Smuzhiyun #define V_EC_GEN(x) ((x) << S_EC_GEN)
50*4882a593Smuzhiyun #define F_EC_GEN    V_EC_GEN(1U)
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun #define S_EC_UP_TOKEN    11
53*4882a593Smuzhiyun #define M_EC_UP_TOKEN    0xFFFFF
54*4882a593Smuzhiyun #define V_EC_UP_TOKEN(x) ((x) << S_EC_UP_TOKEN)
55*4882a593Smuzhiyun #define G_EC_UP_TOKEN(x) (((x) >> S_EC_UP_TOKEN) & M_EC_UP_TOKEN)
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun #define S_EC_VALID    31
58*4882a593Smuzhiyun #define V_EC_VALID(x) ((x) << S_EC_VALID)
59*4882a593Smuzhiyun #define F_EC_VALID    V_EC_VALID(1U)
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun #define S_RQ_MSI_VEC    20
62*4882a593Smuzhiyun #define M_RQ_MSI_VEC    0x3F
63*4882a593Smuzhiyun #define V_RQ_MSI_VEC(x) ((x) << S_RQ_MSI_VEC)
64*4882a593Smuzhiyun #define G_RQ_MSI_VEC(x) (((x) >> S_RQ_MSI_VEC) & M_RQ_MSI_VEC)
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun #define S_RQ_INTR_EN    26
67*4882a593Smuzhiyun #define V_RQ_INTR_EN(x) ((x) << S_RQ_INTR_EN)
68*4882a593Smuzhiyun #define F_RQ_INTR_EN    V_RQ_INTR_EN(1U)
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun #define S_RQ_GEN    28
71*4882a593Smuzhiyun #define V_RQ_GEN(x) ((x) << S_RQ_GEN)
72*4882a593Smuzhiyun #define F_RQ_GEN    V_RQ_GEN(1U)
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun #define S_CQ_INDEX    0
75*4882a593Smuzhiyun #define M_CQ_INDEX    0xFFFF
76*4882a593Smuzhiyun #define V_CQ_INDEX(x) ((x) << S_CQ_INDEX)
77*4882a593Smuzhiyun #define G_CQ_INDEX(x) (((x) >> S_CQ_INDEX) & M_CQ_INDEX)
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun #define S_CQ_SIZE    16
80*4882a593Smuzhiyun #define M_CQ_SIZE    0xFFFF
81*4882a593Smuzhiyun #define V_CQ_SIZE(x) ((x) << S_CQ_SIZE)
82*4882a593Smuzhiyun #define G_CQ_SIZE(x) (((x) >> S_CQ_SIZE) & M_CQ_SIZE)
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun #define S_CQ_BASE_HI    0
85*4882a593Smuzhiyun #define M_CQ_BASE_HI    0xFFFFF
86*4882a593Smuzhiyun #define V_CQ_BASE_HI(x) ((x) << S_CQ_BASE_HI)
87*4882a593Smuzhiyun #define G_CQ_BASE_HI(x) (((x) >> S_CQ_BASE_HI) & M_CQ_BASE_HI)
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun #define S_CQ_RSPQ    20
90*4882a593Smuzhiyun #define M_CQ_RSPQ    0x3F
91*4882a593Smuzhiyun #define V_CQ_RSPQ(x) ((x) << S_CQ_RSPQ)
92*4882a593Smuzhiyun #define G_CQ_RSPQ(x) (((x) >> S_CQ_RSPQ) & M_CQ_RSPQ)
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun #define S_CQ_ASYNC_NOTIF    26
95*4882a593Smuzhiyun #define V_CQ_ASYNC_NOTIF(x) ((x) << S_CQ_ASYNC_NOTIF)
96*4882a593Smuzhiyun #define F_CQ_ASYNC_NOTIF    V_CQ_ASYNC_NOTIF(1U)
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun #define S_CQ_ARMED    27
99*4882a593Smuzhiyun #define V_CQ_ARMED(x) ((x) << S_CQ_ARMED)
100*4882a593Smuzhiyun #define F_CQ_ARMED    V_CQ_ARMED(1U)
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun #define S_CQ_ASYNC_NOTIF_SOL    28
103*4882a593Smuzhiyun #define V_CQ_ASYNC_NOTIF_SOL(x) ((x) << S_CQ_ASYNC_NOTIF_SOL)
104*4882a593Smuzhiyun #define F_CQ_ASYNC_NOTIF_SOL    V_CQ_ASYNC_NOTIF_SOL(1U)
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun #define S_CQ_GEN    29
107*4882a593Smuzhiyun #define V_CQ_GEN(x) ((x) << S_CQ_GEN)
108*4882a593Smuzhiyun #define F_CQ_GEN    V_CQ_GEN(1U)
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun #define S_CQ_ERR    30
111*4882a593Smuzhiyun #define V_CQ_ERR(x) ((x) << S_CQ_ERR)
112*4882a593Smuzhiyun #define F_CQ_ERR    V_CQ_ERR(1U)
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun #define S_CQ_OVERFLOW_MODE    31
115*4882a593Smuzhiyun #define V_CQ_OVERFLOW_MODE(x) ((x) << S_CQ_OVERFLOW_MODE)
116*4882a593Smuzhiyun #define F_CQ_OVERFLOW_MODE    V_CQ_OVERFLOW_MODE(1U)
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun #define S_CQ_CREDITS    0
119*4882a593Smuzhiyun #define M_CQ_CREDITS    0xFFFF
120*4882a593Smuzhiyun #define V_CQ_CREDITS(x) ((x) << S_CQ_CREDITS)
121*4882a593Smuzhiyun #define G_CQ_CREDITS(x) (((x) >> S_CQ_CREDITS) & M_CQ_CREDITS)
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun #define S_CQ_CREDIT_THRES    16
124*4882a593Smuzhiyun #define M_CQ_CREDIT_THRES    0x1FFF
125*4882a593Smuzhiyun #define V_CQ_CREDIT_THRES(x) ((x) << S_CQ_CREDIT_THRES)
126*4882a593Smuzhiyun #define G_CQ_CREDIT_THRES(x) (((x) >> S_CQ_CREDIT_THRES) & M_CQ_CREDIT_THRES)
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun #define S_FL_BASE_HI    0
129*4882a593Smuzhiyun #define M_FL_BASE_HI    0xFFFFF
130*4882a593Smuzhiyun #define V_FL_BASE_HI(x) ((x) << S_FL_BASE_HI)
131*4882a593Smuzhiyun #define G_FL_BASE_HI(x) (((x) >> S_FL_BASE_HI) & M_FL_BASE_HI)
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun #define S_FL_INDEX_LO    20
134*4882a593Smuzhiyun #define M_FL_INDEX_LO    0xFFF
135*4882a593Smuzhiyun #define V_FL_INDEX_LO(x) ((x) << S_FL_INDEX_LO)
136*4882a593Smuzhiyun #define G_FL_INDEX_LO(x) (((x) >> S_FL_INDEX_LO) & M_FL_INDEX_LO)
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun #define S_FL_INDEX_HI    0
139*4882a593Smuzhiyun #define M_FL_INDEX_HI    0xF
140*4882a593Smuzhiyun #define V_FL_INDEX_HI(x) ((x) << S_FL_INDEX_HI)
141*4882a593Smuzhiyun #define G_FL_INDEX_HI(x) (((x) >> S_FL_INDEX_HI) & M_FL_INDEX_HI)
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun #define S_FL_SIZE    4
144*4882a593Smuzhiyun #define M_FL_SIZE    0xFFFF
145*4882a593Smuzhiyun #define V_FL_SIZE(x) ((x) << S_FL_SIZE)
146*4882a593Smuzhiyun #define G_FL_SIZE(x) (((x) >> S_FL_SIZE) & M_FL_SIZE)
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun #define S_FL_GEN    20
149*4882a593Smuzhiyun #define V_FL_GEN(x) ((x) << S_FL_GEN)
150*4882a593Smuzhiyun #define F_FL_GEN    V_FL_GEN(1U)
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun #define S_FL_ENTRY_SIZE_LO    21
153*4882a593Smuzhiyun #define M_FL_ENTRY_SIZE_LO    0x7FF
154*4882a593Smuzhiyun #define V_FL_ENTRY_SIZE_LO(x) ((x) << S_FL_ENTRY_SIZE_LO)
155*4882a593Smuzhiyun #define G_FL_ENTRY_SIZE_LO(x) (((x) >> S_FL_ENTRY_SIZE_LO) & M_FL_ENTRY_SIZE_LO)
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun #define S_FL_ENTRY_SIZE_HI    0
158*4882a593Smuzhiyun #define M_FL_ENTRY_SIZE_HI    0x1FFFFF
159*4882a593Smuzhiyun #define V_FL_ENTRY_SIZE_HI(x) ((x) << S_FL_ENTRY_SIZE_HI)
160*4882a593Smuzhiyun #define G_FL_ENTRY_SIZE_HI(x) (((x) >> S_FL_ENTRY_SIZE_HI) & M_FL_ENTRY_SIZE_HI)
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun #define S_FL_CONG_THRES    21
163*4882a593Smuzhiyun #define M_FL_CONG_THRES    0x3FF
164*4882a593Smuzhiyun #define V_FL_CONG_THRES(x) ((x) << S_FL_CONG_THRES)
165*4882a593Smuzhiyun #define G_FL_CONG_THRES(x) (((x) >> S_FL_CONG_THRES) & M_FL_CONG_THRES)
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun #define S_FL_GTS    31
168*4882a593Smuzhiyun #define V_FL_GTS(x) ((x) << S_FL_GTS)
169*4882a593Smuzhiyun #define F_FL_GTS    V_FL_GTS(1U)
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun #define S_FLD_GEN1    31
172*4882a593Smuzhiyun #define V_FLD_GEN1(x) ((x) << S_FLD_GEN1)
173*4882a593Smuzhiyun #define F_FLD_GEN1    V_FLD_GEN1(1U)
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun #define S_FLD_GEN2    0
176*4882a593Smuzhiyun #define V_FLD_GEN2(x) ((x) << S_FLD_GEN2)
177*4882a593Smuzhiyun #define F_FLD_GEN2    V_FLD_GEN2(1U)
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun #define S_RSPD_TXQ1_CR    0
180*4882a593Smuzhiyun #define M_RSPD_TXQ1_CR    0x7F
181*4882a593Smuzhiyun #define V_RSPD_TXQ1_CR(x) ((x) << S_RSPD_TXQ1_CR)
182*4882a593Smuzhiyun #define G_RSPD_TXQ1_CR(x) (((x) >> S_RSPD_TXQ1_CR) & M_RSPD_TXQ1_CR)
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun #define S_RSPD_TXQ1_GTS    7
185*4882a593Smuzhiyun #define V_RSPD_TXQ1_GTS(x) ((x) << S_RSPD_TXQ1_GTS)
186*4882a593Smuzhiyun #define F_RSPD_TXQ1_GTS    V_RSPD_TXQ1_GTS(1U)
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun #define S_RSPD_TXQ2_CR    8
189*4882a593Smuzhiyun #define M_RSPD_TXQ2_CR    0x7F
190*4882a593Smuzhiyun #define V_RSPD_TXQ2_CR(x) ((x) << S_RSPD_TXQ2_CR)
191*4882a593Smuzhiyun #define G_RSPD_TXQ2_CR(x) (((x) >> S_RSPD_TXQ2_CR) & M_RSPD_TXQ2_CR)
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun #define S_RSPD_TXQ2_GTS    15
194*4882a593Smuzhiyun #define V_RSPD_TXQ2_GTS(x) ((x) << S_RSPD_TXQ2_GTS)
195*4882a593Smuzhiyun #define F_RSPD_TXQ2_GTS    V_RSPD_TXQ2_GTS(1U)
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun #define S_RSPD_TXQ0_CR    16
198*4882a593Smuzhiyun #define M_RSPD_TXQ0_CR    0x7F
199*4882a593Smuzhiyun #define V_RSPD_TXQ0_CR(x) ((x) << S_RSPD_TXQ0_CR)
200*4882a593Smuzhiyun #define G_RSPD_TXQ0_CR(x) (((x) >> S_RSPD_TXQ0_CR) & M_RSPD_TXQ0_CR)
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun #define S_RSPD_TXQ0_GTS    23
203*4882a593Smuzhiyun #define V_RSPD_TXQ0_GTS(x) ((x) << S_RSPD_TXQ0_GTS)
204*4882a593Smuzhiyun #define F_RSPD_TXQ0_GTS    V_RSPD_TXQ0_GTS(1U)
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun #define S_RSPD_EOP    24
207*4882a593Smuzhiyun #define V_RSPD_EOP(x) ((x) << S_RSPD_EOP)
208*4882a593Smuzhiyun #define F_RSPD_EOP    V_RSPD_EOP(1U)
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun #define S_RSPD_SOP    25
211*4882a593Smuzhiyun #define V_RSPD_SOP(x) ((x) << S_RSPD_SOP)
212*4882a593Smuzhiyun #define F_RSPD_SOP    V_RSPD_SOP(1U)
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun #define S_RSPD_ASYNC_NOTIF    26
215*4882a593Smuzhiyun #define V_RSPD_ASYNC_NOTIF(x) ((x) << S_RSPD_ASYNC_NOTIF)
216*4882a593Smuzhiyun #define F_RSPD_ASYNC_NOTIF    V_RSPD_ASYNC_NOTIF(1U)
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun #define S_RSPD_FL0_GTS    27
219*4882a593Smuzhiyun #define V_RSPD_FL0_GTS(x) ((x) << S_RSPD_FL0_GTS)
220*4882a593Smuzhiyun #define F_RSPD_FL0_GTS    V_RSPD_FL0_GTS(1U)
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun #define S_RSPD_FL1_GTS    28
223*4882a593Smuzhiyun #define V_RSPD_FL1_GTS(x) ((x) << S_RSPD_FL1_GTS)
224*4882a593Smuzhiyun #define F_RSPD_FL1_GTS    V_RSPD_FL1_GTS(1U)
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun #define S_RSPD_IMM_DATA_VALID    29
227*4882a593Smuzhiyun #define V_RSPD_IMM_DATA_VALID(x) ((x) << S_RSPD_IMM_DATA_VALID)
228*4882a593Smuzhiyun #define F_RSPD_IMM_DATA_VALID    V_RSPD_IMM_DATA_VALID(1U)
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun #define S_RSPD_OFFLOAD    30
231*4882a593Smuzhiyun #define V_RSPD_OFFLOAD(x) ((x) << S_RSPD_OFFLOAD)
232*4882a593Smuzhiyun #define F_RSPD_OFFLOAD    V_RSPD_OFFLOAD(1U)
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun #define S_RSPD_GEN1    31
235*4882a593Smuzhiyun #define V_RSPD_GEN1(x) ((x) << S_RSPD_GEN1)
236*4882a593Smuzhiyun #define F_RSPD_GEN1    V_RSPD_GEN1(1U)
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun #define S_RSPD_LEN    0
239*4882a593Smuzhiyun #define M_RSPD_LEN    0x7FFFFFFF
240*4882a593Smuzhiyun #define V_RSPD_LEN(x) ((x) << S_RSPD_LEN)
241*4882a593Smuzhiyun #define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN)
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun #define S_RSPD_FLQ    31
244*4882a593Smuzhiyun #define V_RSPD_FLQ(x) ((x) << S_RSPD_FLQ)
245*4882a593Smuzhiyun #define F_RSPD_FLQ    V_RSPD_FLQ(1U)
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun #define S_RSPD_GEN2    0
248*4882a593Smuzhiyun #define V_RSPD_GEN2(x) ((x) << S_RSPD_GEN2)
249*4882a593Smuzhiyun #define F_RSPD_GEN2    V_RSPD_GEN2(1U)
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun #define S_RSPD_INR_VEC    1
252*4882a593Smuzhiyun #define M_RSPD_INR_VEC    0x7F
253*4882a593Smuzhiyun #define V_RSPD_INR_VEC(x) ((x) << S_RSPD_INR_VEC)
254*4882a593Smuzhiyun #define G_RSPD_INR_VEC(x) (((x) >> S_RSPD_INR_VEC) & M_RSPD_INR_VEC)
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun #endif				/* _SGE_DEFS_H */
257