xref: /OK3568_Linux_fs/kernel/drivers/net/ethernet/chelsio/cxgb3/aq100x.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * This software is available to you under a choice of one of two
5*4882a593Smuzhiyun  * licenses.  You may choose to be licensed under the terms of the GNU
6*4882a593Smuzhiyun  * General Public License (GPL) Version 2, available from the file
7*4882a593Smuzhiyun  * COPYING in the main directory of this source tree, or the
8*4882a593Smuzhiyun  * OpenIB.org BSD license below:
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  *     Redistribution and use in source and binary forms, with or
11*4882a593Smuzhiyun  *     without modification, are permitted provided that the following
12*4882a593Smuzhiyun  *     conditions are met:
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  *      - Redistributions of source code must retain the above
15*4882a593Smuzhiyun  *        copyright notice, this list of conditions and the following
16*4882a593Smuzhiyun  *        disclaimer.
17*4882a593Smuzhiyun  *
18*4882a593Smuzhiyun  *      - Redistributions in binary form must reproduce the above
19*4882a593Smuzhiyun  *        copyright notice, this list of conditions and the following
20*4882a593Smuzhiyun  *        disclaimer in the documentation and/or other materials
21*4882a593Smuzhiyun  *        provided with the distribution.
22*4882a593Smuzhiyun  *
23*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24*4882a593Smuzhiyun  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25*4882a593Smuzhiyun  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26*4882a593Smuzhiyun  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27*4882a593Smuzhiyun  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28*4882a593Smuzhiyun  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29*4882a593Smuzhiyun  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30*4882a593Smuzhiyun  * SOFTWARE.
31*4882a593Smuzhiyun  */
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #include "common.h"
34*4882a593Smuzhiyun #include "regs.h"
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun enum {
37*4882a593Smuzhiyun 	/* MDIO_DEV_PMA_PMD registers */
38*4882a593Smuzhiyun 	AQ_LINK_STAT	= 0xe800,
39*4882a593Smuzhiyun 	AQ_IMASK_PMA	= 0xf000,
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun 	/* MDIO_DEV_XGXS registers */
42*4882a593Smuzhiyun 	AQ_XAUI_RX_CFG	= 0xc400,
43*4882a593Smuzhiyun 	AQ_XAUI_TX_CFG	= 0xe400,
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 	/* MDIO_DEV_ANEG registers */
46*4882a593Smuzhiyun 	AQ_1G_CTRL	= 0xc400,
47*4882a593Smuzhiyun 	AQ_ANEG_STAT	= 0xc800,
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 	/* MDIO_DEV_VEND1 registers */
50*4882a593Smuzhiyun 	AQ_FW_VERSION	= 0x0020,
51*4882a593Smuzhiyun 	AQ_IFLAG_GLOBAL	= 0xfc00,
52*4882a593Smuzhiyun 	AQ_IMASK_GLOBAL	= 0xff00,
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun enum {
56*4882a593Smuzhiyun 	IMASK_PMA	= 1 << 2,
57*4882a593Smuzhiyun 	IMASK_GLOBAL	= 1 << 15,
58*4882a593Smuzhiyun 	ADV_1G_FULL	= 1 << 15,
59*4882a593Smuzhiyun 	ADV_1G_HALF	= 1 << 14,
60*4882a593Smuzhiyun 	ADV_10G_FULL	= 1 << 12,
61*4882a593Smuzhiyun 	AQ_RESET	= (1 << 14) | (1 << 15),
62*4882a593Smuzhiyun 	AQ_LOWPOWER	= 1 << 12,
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun 
aq100x_reset(struct cphy * phy,int wait)65*4882a593Smuzhiyun static int aq100x_reset(struct cphy *phy, int wait)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun 	/*
68*4882a593Smuzhiyun 	 * Ignore the caller specified wait time; always wait for the reset to
69*4882a593Smuzhiyun 	 * complete. Can take up to 3s.
70*4882a593Smuzhiyun 	 */
71*4882a593Smuzhiyun 	int err = t3_phy_reset(phy, MDIO_MMD_VEND1, 3000);
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	if (err)
74*4882a593Smuzhiyun 		CH_WARN(phy->adapter, "PHY%d: reset failed (0x%x).\n",
75*4882a593Smuzhiyun 			phy->mdio.prtad, err);
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	return err;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun 
aq100x_intr_enable(struct cphy * phy)80*4882a593Smuzhiyun static int aq100x_intr_enable(struct cphy *phy)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun 	int err = t3_mdio_write(phy, MDIO_MMD_PMAPMD, AQ_IMASK_PMA, IMASK_PMA);
83*4882a593Smuzhiyun 	if (err)
84*4882a593Smuzhiyun 		return err;
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	err = t3_mdio_write(phy, MDIO_MMD_VEND1, AQ_IMASK_GLOBAL, IMASK_GLOBAL);
87*4882a593Smuzhiyun 	return err;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun 
aq100x_intr_disable(struct cphy * phy)90*4882a593Smuzhiyun static int aq100x_intr_disable(struct cphy *phy)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun 	return t3_mdio_write(phy, MDIO_MMD_VEND1, AQ_IMASK_GLOBAL, 0);
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun 
aq100x_intr_clear(struct cphy * phy)95*4882a593Smuzhiyun static int aq100x_intr_clear(struct cphy *phy)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun 	unsigned int v;
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_IFLAG_GLOBAL, &v);
100*4882a593Smuzhiyun 	t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_STAT1, &v);
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	return 0;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun 
aq100x_intr_handler(struct cphy * phy)105*4882a593Smuzhiyun static int aq100x_intr_handler(struct cphy *phy)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun 	int err;
108*4882a593Smuzhiyun 	unsigned int cause, v;
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	err = t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_IFLAG_GLOBAL, &cause);
111*4882a593Smuzhiyun 	if (err)
112*4882a593Smuzhiyun 		return err;
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	/* Read (and reset) the latching version of the status */
115*4882a593Smuzhiyun 	t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_STAT1, &v);
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	return cphy_cause_link_change;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun 
aq100x_power_down(struct cphy * phy,int off)120*4882a593Smuzhiyun static int aq100x_power_down(struct cphy *phy, int off)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun 	return mdio_set_flag(&phy->mdio, phy->mdio.prtad,
123*4882a593Smuzhiyun 			     MDIO_MMD_PMAPMD, MDIO_CTRL1,
124*4882a593Smuzhiyun 			     MDIO_CTRL1_LPOWER, off);
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun 
aq100x_autoneg_enable(struct cphy * phy)127*4882a593Smuzhiyun static int aq100x_autoneg_enable(struct cphy *phy)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun 	int err;
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	err = aq100x_power_down(phy, 0);
132*4882a593Smuzhiyun 	if (!err)
133*4882a593Smuzhiyun 		err = mdio_set_flag(&phy->mdio, phy->mdio.prtad,
134*4882a593Smuzhiyun 				    MDIO_MMD_AN, MDIO_CTRL1,
135*4882a593Smuzhiyun 				    BMCR_ANENABLE | BMCR_ANRESTART, 1);
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	return err;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun 
aq100x_autoneg_restart(struct cphy * phy)140*4882a593Smuzhiyun static int aq100x_autoneg_restart(struct cphy *phy)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun 	int err;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	err = aq100x_power_down(phy, 0);
145*4882a593Smuzhiyun 	if (!err)
146*4882a593Smuzhiyun 		err = mdio_set_flag(&phy->mdio, phy->mdio.prtad,
147*4882a593Smuzhiyun 				    MDIO_MMD_AN, MDIO_CTRL1,
148*4882a593Smuzhiyun 				    BMCR_ANENABLE | BMCR_ANRESTART, 1);
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	return err;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun 
aq100x_advertise(struct cphy * phy,unsigned int advertise_map)153*4882a593Smuzhiyun static int aq100x_advertise(struct cphy *phy, unsigned int advertise_map)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun 	unsigned int adv;
156*4882a593Smuzhiyun 	int err;
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	/* 10G advertisement */
159*4882a593Smuzhiyun 	adv = 0;
160*4882a593Smuzhiyun 	if (advertise_map & ADVERTISED_10000baseT_Full)
161*4882a593Smuzhiyun 		adv |= ADV_10G_FULL;
162*4882a593Smuzhiyun 	err = t3_mdio_change_bits(phy, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
163*4882a593Smuzhiyun 				  ADV_10G_FULL, adv);
164*4882a593Smuzhiyun 	if (err)
165*4882a593Smuzhiyun 		return err;
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	/* 1G advertisement */
168*4882a593Smuzhiyun 	adv = 0;
169*4882a593Smuzhiyun 	if (advertise_map & ADVERTISED_1000baseT_Full)
170*4882a593Smuzhiyun 		adv |= ADV_1G_FULL;
171*4882a593Smuzhiyun 	if (advertise_map & ADVERTISED_1000baseT_Half)
172*4882a593Smuzhiyun 		adv |= ADV_1G_HALF;
173*4882a593Smuzhiyun 	err = t3_mdio_change_bits(phy, MDIO_MMD_AN, AQ_1G_CTRL,
174*4882a593Smuzhiyun 				  ADV_1G_FULL | ADV_1G_HALF, adv);
175*4882a593Smuzhiyun 	if (err)
176*4882a593Smuzhiyun 		return err;
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	/* 100M, pause advertisement */
179*4882a593Smuzhiyun 	adv = 0;
180*4882a593Smuzhiyun 	if (advertise_map & ADVERTISED_100baseT_Half)
181*4882a593Smuzhiyun 		adv |= ADVERTISE_100HALF;
182*4882a593Smuzhiyun 	if (advertise_map & ADVERTISED_100baseT_Full)
183*4882a593Smuzhiyun 		adv |= ADVERTISE_100FULL;
184*4882a593Smuzhiyun 	if (advertise_map & ADVERTISED_Pause)
185*4882a593Smuzhiyun 		adv |= ADVERTISE_PAUSE_CAP;
186*4882a593Smuzhiyun 	if (advertise_map & ADVERTISED_Asym_Pause)
187*4882a593Smuzhiyun 		adv |= ADVERTISE_PAUSE_ASYM;
188*4882a593Smuzhiyun 	err = t3_mdio_change_bits(phy, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
189*4882a593Smuzhiyun 				  0xfe0, adv);
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	return err;
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun 
aq100x_set_loopback(struct cphy * phy,int mmd,int dir,int enable)194*4882a593Smuzhiyun static int aq100x_set_loopback(struct cphy *phy, int mmd, int dir, int enable)
195*4882a593Smuzhiyun {
196*4882a593Smuzhiyun 	return mdio_set_flag(&phy->mdio, phy->mdio.prtad,
197*4882a593Smuzhiyun 			     MDIO_MMD_PMAPMD, MDIO_CTRL1,
198*4882a593Smuzhiyun 			     BMCR_LOOPBACK, enable);
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun 
aq100x_set_speed_duplex(struct cphy * phy,int speed,int duplex)201*4882a593Smuzhiyun static int aq100x_set_speed_duplex(struct cphy *phy, int speed, int duplex)
202*4882a593Smuzhiyun {
203*4882a593Smuzhiyun 	/* no can do */
204*4882a593Smuzhiyun 	return -1;
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun 
aq100x_get_link_status(struct cphy * phy,int * link_ok,int * speed,int * duplex,int * fc)207*4882a593Smuzhiyun static int aq100x_get_link_status(struct cphy *phy, int *link_ok,
208*4882a593Smuzhiyun 				  int *speed, int *duplex, int *fc)
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun 	int err;
211*4882a593Smuzhiyun 	unsigned int v;
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 	if (link_ok) {
214*4882a593Smuzhiyun 		err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, AQ_LINK_STAT, &v);
215*4882a593Smuzhiyun 		if (err)
216*4882a593Smuzhiyun 			return err;
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 		*link_ok = v & 1;
219*4882a593Smuzhiyun 		if (!*link_ok)
220*4882a593Smuzhiyun 			return 0;
221*4882a593Smuzhiyun 	}
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	err = t3_mdio_read(phy, MDIO_MMD_AN, AQ_ANEG_STAT, &v);
224*4882a593Smuzhiyun 	if (err)
225*4882a593Smuzhiyun 		return err;
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 	if (speed) {
228*4882a593Smuzhiyun 		switch (v & 0x6) {
229*4882a593Smuzhiyun 		case 0x6:
230*4882a593Smuzhiyun 			*speed = SPEED_10000;
231*4882a593Smuzhiyun 			break;
232*4882a593Smuzhiyun 		case 0x4:
233*4882a593Smuzhiyun 			*speed = SPEED_1000;
234*4882a593Smuzhiyun 			break;
235*4882a593Smuzhiyun 		case 0x2:
236*4882a593Smuzhiyun 			*speed = SPEED_100;
237*4882a593Smuzhiyun 			break;
238*4882a593Smuzhiyun 		case 0x0:
239*4882a593Smuzhiyun 			*speed = SPEED_10;
240*4882a593Smuzhiyun 			break;
241*4882a593Smuzhiyun 		}
242*4882a593Smuzhiyun 	}
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	if (duplex)
245*4882a593Smuzhiyun 		*duplex = v & 1 ? DUPLEX_FULL : DUPLEX_HALF;
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun 	return 0;
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun static const struct cphy_ops aq100x_ops = {
251*4882a593Smuzhiyun 	.reset             = aq100x_reset,
252*4882a593Smuzhiyun 	.intr_enable       = aq100x_intr_enable,
253*4882a593Smuzhiyun 	.intr_disable      = aq100x_intr_disable,
254*4882a593Smuzhiyun 	.intr_clear        = aq100x_intr_clear,
255*4882a593Smuzhiyun 	.intr_handler      = aq100x_intr_handler,
256*4882a593Smuzhiyun 	.autoneg_enable    = aq100x_autoneg_enable,
257*4882a593Smuzhiyun 	.autoneg_restart   = aq100x_autoneg_restart,
258*4882a593Smuzhiyun 	.advertise         = aq100x_advertise,
259*4882a593Smuzhiyun 	.set_loopback      = aq100x_set_loopback,
260*4882a593Smuzhiyun 	.set_speed_duplex  = aq100x_set_speed_duplex,
261*4882a593Smuzhiyun 	.get_link_status   = aq100x_get_link_status,
262*4882a593Smuzhiyun 	.power_down        = aq100x_power_down,
263*4882a593Smuzhiyun 	.mmds 		   = MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | MDIO_DEVS_PHYXS,
264*4882a593Smuzhiyun };
265*4882a593Smuzhiyun 
t3_aq100x_phy_prep(struct cphy * phy,struct adapter * adapter,int phy_addr,const struct mdio_ops * mdio_ops)266*4882a593Smuzhiyun int t3_aq100x_phy_prep(struct cphy *phy, struct adapter *adapter, int phy_addr,
267*4882a593Smuzhiyun 		       const struct mdio_ops *mdio_ops)
268*4882a593Smuzhiyun {
269*4882a593Smuzhiyun 	unsigned int v, v2, gpio, wait;
270*4882a593Smuzhiyun 	int err;
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	cphy_init(phy, adapter, phy_addr, &aq100x_ops, mdio_ops,
273*4882a593Smuzhiyun 		  SUPPORTED_1000baseT_Full | SUPPORTED_10000baseT_Full |
274*4882a593Smuzhiyun 		  SUPPORTED_TP | SUPPORTED_Autoneg | SUPPORTED_AUI,
275*4882a593Smuzhiyun 		  "1000/10GBASE-T");
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 	/*
278*4882a593Smuzhiyun 	 * The PHY has been out of reset ever since the system powered up.  So
279*4882a593Smuzhiyun 	 * we do a hard reset over here.
280*4882a593Smuzhiyun 	 */
281*4882a593Smuzhiyun 	gpio = phy_addr ? F_GPIO10_OUT_VAL : F_GPIO6_OUT_VAL;
282*4882a593Smuzhiyun 	t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, gpio, 0);
283*4882a593Smuzhiyun 	msleep(1);
284*4882a593Smuzhiyun 	t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, gpio, gpio);
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 	/*
287*4882a593Smuzhiyun 	 * Give it enough time to load the firmware and get ready for mdio.
288*4882a593Smuzhiyun 	 */
289*4882a593Smuzhiyun 	msleep(1000);
290*4882a593Smuzhiyun 	wait = 500; /* in 10ms increments */
291*4882a593Smuzhiyun 	do {
292*4882a593Smuzhiyun 		err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v);
293*4882a593Smuzhiyun 		if (err || v == 0xffff) {
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun 			/* Allow prep_adapter to succeed when ffff is read */
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun 			CH_WARN(adapter, "PHY%d: reset failed (0x%x, 0x%x).\n",
298*4882a593Smuzhiyun 				phy_addr, err, v);
299*4882a593Smuzhiyun 			goto done;
300*4882a593Smuzhiyun 		}
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 		v &= AQ_RESET;
303*4882a593Smuzhiyun 		if (v)
304*4882a593Smuzhiyun 			msleep(10);
305*4882a593Smuzhiyun 	} while (v && --wait);
306*4882a593Smuzhiyun 	if (v) {
307*4882a593Smuzhiyun 		CH_WARN(adapter, "PHY%d: reset timed out (0x%x).\n",
308*4882a593Smuzhiyun 			phy_addr, v);
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun 		goto done; /* let prep_adapter succeed */
311*4882a593Smuzhiyun 	}
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 	/* Datasheet says 3s max but this has been observed */
314*4882a593Smuzhiyun 	wait = (500 - wait) * 10 + 1000;
315*4882a593Smuzhiyun 	if (wait > 3000)
316*4882a593Smuzhiyun 		CH_WARN(adapter, "PHY%d: reset took %ums\n", phy_addr, wait);
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 	/* Firmware version check. */
319*4882a593Smuzhiyun 	t3_mdio_read(phy, MDIO_MMD_VEND1, AQ_FW_VERSION, &v);
320*4882a593Smuzhiyun 	if (v != 101)
321*4882a593Smuzhiyun 		CH_WARN(adapter, "PHY%d: unsupported firmware %d\n",
322*4882a593Smuzhiyun 			phy_addr, v);
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun 	/*
325*4882a593Smuzhiyun 	 * The PHY should start in really-low-power mode.  Prepare it for normal
326*4882a593Smuzhiyun 	 * operations.
327*4882a593Smuzhiyun 	 */
328*4882a593Smuzhiyun 	err = t3_mdio_read(phy, MDIO_MMD_VEND1, MDIO_CTRL1, &v);
329*4882a593Smuzhiyun 	if (err)
330*4882a593Smuzhiyun 		return err;
331*4882a593Smuzhiyun 	if (v & AQ_LOWPOWER) {
332*4882a593Smuzhiyun 		err = t3_mdio_change_bits(phy, MDIO_MMD_VEND1, MDIO_CTRL1,
333*4882a593Smuzhiyun 					  AQ_LOWPOWER, 0);
334*4882a593Smuzhiyun 		if (err)
335*4882a593Smuzhiyun 			return err;
336*4882a593Smuzhiyun 		msleep(10);
337*4882a593Smuzhiyun 	} else
338*4882a593Smuzhiyun 		CH_WARN(adapter, "PHY%d does not start in low power mode.\n",
339*4882a593Smuzhiyun 			phy_addr);
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun 	/*
342*4882a593Smuzhiyun 	 * Verify XAUI settings, but let prep succeed no matter what.
343*4882a593Smuzhiyun 	 */
344*4882a593Smuzhiyun 	v = v2 = 0;
345*4882a593Smuzhiyun 	t3_mdio_read(phy, MDIO_MMD_PHYXS, AQ_XAUI_RX_CFG, &v);
346*4882a593Smuzhiyun 	t3_mdio_read(phy, MDIO_MMD_PHYXS, AQ_XAUI_TX_CFG, &v2);
347*4882a593Smuzhiyun 	if (v != 0x1b || v2 != 0x1b)
348*4882a593Smuzhiyun 		CH_WARN(adapter,
349*4882a593Smuzhiyun 			"PHY%d: incorrect XAUI settings (0x%x, 0x%x).\n",
350*4882a593Smuzhiyun 			phy_addr, v, v2);
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun done:
353*4882a593Smuzhiyun 	return err;
354*4882a593Smuzhiyun }
355