xref: /OK3568_Linux_fs/kernel/drivers/net/ethernet/chelsio/cxgb3/adapter.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * This software is available to you under a choice of one of two
5*4882a593Smuzhiyun  * licenses.  You may choose to be licensed under the terms of the GNU
6*4882a593Smuzhiyun  * General Public License (GPL) Version 2, available from the file
7*4882a593Smuzhiyun  * COPYING in the main directory of this source tree, or the
8*4882a593Smuzhiyun  * OpenIB.org BSD license below:
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  *     Redistribution and use in source and binary forms, with or
11*4882a593Smuzhiyun  *     without modification, are permitted provided that the following
12*4882a593Smuzhiyun  *     conditions are met:
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  *      - Redistributions of source code must retain the above
15*4882a593Smuzhiyun  *        copyright notice, this list of conditions and the following
16*4882a593Smuzhiyun  *        disclaimer.
17*4882a593Smuzhiyun  *
18*4882a593Smuzhiyun  *      - Redistributions in binary form must reproduce the above
19*4882a593Smuzhiyun  *        copyright notice, this list of conditions and the following
20*4882a593Smuzhiyun  *        disclaimer in the documentation and/or other materials
21*4882a593Smuzhiyun  *        provided with the distribution.
22*4882a593Smuzhiyun  *
23*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24*4882a593Smuzhiyun  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25*4882a593Smuzhiyun  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26*4882a593Smuzhiyun  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27*4882a593Smuzhiyun  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28*4882a593Smuzhiyun  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29*4882a593Smuzhiyun  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30*4882a593Smuzhiyun  * SOFTWARE.
31*4882a593Smuzhiyun  */
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun /* This file should not be included directly.  Include common.h instead. */
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun #ifndef __T3_ADAPTER_H__
36*4882a593Smuzhiyun #define __T3_ADAPTER_H__
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #include <linux/pci.h>
39*4882a593Smuzhiyun #include <linux/spinlock.h>
40*4882a593Smuzhiyun #include <linux/interrupt.h>
41*4882a593Smuzhiyun #include <linux/timer.h>
42*4882a593Smuzhiyun #include <linux/cache.h>
43*4882a593Smuzhiyun #include <linux/mutex.h>
44*4882a593Smuzhiyun #include <linux/bitops.h>
45*4882a593Smuzhiyun #include "t3cdev.h"
46*4882a593Smuzhiyun #include <asm/io.h>
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun struct adapter;
49*4882a593Smuzhiyun struct sge_qset;
50*4882a593Smuzhiyun struct port_info;
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun enum mac_idx_types {
53*4882a593Smuzhiyun 	LAN_MAC_IDX	= 0,
54*4882a593Smuzhiyun 	SAN_MAC_IDX,
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun 	MAX_MAC_IDX
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun struct iscsi_config {
60*4882a593Smuzhiyun 	__u8	mac_addr[ETH_ALEN];
61*4882a593Smuzhiyun 	__u32	flags;
62*4882a593Smuzhiyun 	int (*send)(struct port_info *pi, struct sk_buff **skb);
63*4882a593Smuzhiyun 	int (*recv)(struct port_info *pi, struct sk_buff *skb);
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun struct port_info {
67*4882a593Smuzhiyun 	struct adapter *adapter;
68*4882a593Smuzhiyun 	struct sge_qset *qs;
69*4882a593Smuzhiyun 	u8 port_id;
70*4882a593Smuzhiyun 	u8 nqsets;
71*4882a593Smuzhiyun 	u8 first_qset;
72*4882a593Smuzhiyun 	struct cphy phy;
73*4882a593Smuzhiyun 	struct cmac mac;
74*4882a593Smuzhiyun 	struct link_config link_config;
75*4882a593Smuzhiyun 	int activity;
76*4882a593Smuzhiyun 	__be32 iscsi_ipv4addr;
77*4882a593Smuzhiyun 	struct iscsi_config iscsic;
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	int link_fault; /* link fault was detected */
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun enum {				/* adapter flags */
83*4882a593Smuzhiyun 	FULL_INIT_DONE = (1 << 0),
84*4882a593Smuzhiyun 	USING_MSI = (1 << 1),
85*4882a593Smuzhiyun 	USING_MSIX = (1 << 2),
86*4882a593Smuzhiyun 	QUEUES_BOUND = (1 << 3),
87*4882a593Smuzhiyun 	TP_PARITY_INIT = (1 << 4),
88*4882a593Smuzhiyun 	NAPI_INIT = (1 << 5),
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun struct fl_pg_chunk {
92*4882a593Smuzhiyun 	struct page *page;
93*4882a593Smuzhiyun 	void *va;
94*4882a593Smuzhiyun 	unsigned int offset;
95*4882a593Smuzhiyun 	unsigned long *p_cnt;
96*4882a593Smuzhiyun 	dma_addr_t mapping;
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun struct rx_desc;
100*4882a593Smuzhiyun struct rx_sw_desc;
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun struct sge_fl {                     /* SGE per free-buffer list state */
103*4882a593Smuzhiyun 	unsigned int buf_size;      /* size of each Rx buffer */
104*4882a593Smuzhiyun 	unsigned int credits;       /* # of available Rx buffers */
105*4882a593Smuzhiyun 	unsigned int pend_cred;     /* new buffers since last FL DB ring */
106*4882a593Smuzhiyun 	unsigned int size;          /* capacity of free list */
107*4882a593Smuzhiyun 	unsigned int cidx;          /* consumer index */
108*4882a593Smuzhiyun 	unsigned int pidx;          /* producer index */
109*4882a593Smuzhiyun 	unsigned int gen;           /* free list generation */
110*4882a593Smuzhiyun 	struct fl_pg_chunk pg_chunk;/* page chunk cache */
111*4882a593Smuzhiyun 	unsigned int use_pages;     /* whether FL uses pages or sk_buffs */
112*4882a593Smuzhiyun 	unsigned int order;	    /* order of page allocations */
113*4882a593Smuzhiyun 	unsigned int alloc_size;    /* size of allocated buffer */
114*4882a593Smuzhiyun 	struct rx_desc *desc;       /* address of HW Rx descriptor ring */
115*4882a593Smuzhiyun 	struct rx_sw_desc *sdesc;   /* address of SW Rx descriptor ring */
116*4882a593Smuzhiyun 	dma_addr_t   phys_addr;     /* physical address of HW ring start */
117*4882a593Smuzhiyun 	unsigned int cntxt_id;      /* SGE context id for the free list */
118*4882a593Smuzhiyun 	unsigned long empty;        /* # of times queue ran out of buffers */
119*4882a593Smuzhiyun 	unsigned long alloc_failed; /* # of times buffer allocation failed */
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun /*
123*4882a593Smuzhiyun  * Bundle size for grouping offload RX packets for delivery to the stack.
124*4882a593Smuzhiyun  * Don't make this too big as we do prefetch on each packet in a bundle.
125*4882a593Smuzhiyun  */
126*4882a593Smuzhiyun # define RX_BUNDLE_SIZE 8
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun struct rsp_desc;
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun struct sge_rspq {		/* state for an SGE response queue */
131*4882a593Smuzhiyun 	unsigned int credits;	/* # of pending response credits */
132*4882a593Smuzhiyun 	unsigned int size;	/* capacity of response queue */
133*4882a593Smuzhiyun 	unsigned int cidx;	/* consumer index */
134*4882a593Smuzhiyun 	unsigned int gen;	/* current generation bit */
135*4882a593Smuzhiyun 	unsigned int polling;	/* is the queue serviced through NAPI? */
136*4882a593Smuzhiyun 	unsigned int holdoff_tmr;	/* interrupt holdoff timer in 100ns */
137*4882a593Smuzhiyun 	unsigned int next_holdoff;	/* holdoff time for next interrupt */
138*4882a593Smuzhiyun 	unsigned int rx_recycle_buf; /* whether recycling occurred
139*4882a593Smuzhiyun 					within current sop-eop */
140*4882a593Smuzhiyun 	struct rsp_desc *desc;	/* address of HW response ring */
141*4882a593Smuzhiyun 	dma_addr_t phys_addr;	/* physical address of the ring */
142*4882a593Smuzhiyun 	unsigned int cntxt_id;	/* SGE context id for the response q */
143*4882a593Smuzhiyun 	spinlock_t lock;	/* guards response processing */
144*4882a593Smuzhiyun 	struct sk_buff_head rx_queue; /* offload packet receive queue */
145*4882a593Smuzhiyun 	struct sk_buff *pg_skb; /* used to build frag list in napi handler */
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	unsigned long offload_pkts;
148*4882a593Smuzhiyun 	unsigned long offload_bundles;
149*4882a593Smuzhiyun 	unsigned long eth_pkts;	/* # of ethernet packets */
150*4882a593Smuzhiyun 	unsigned long pure_rsps;	/* # of pure (non-data) responses */
151*4882a593Smuzhiyun 	unsigned long imm_data;	/* responses with immediate data */
152*4882a593Smuzhiyun 	unsigned long rx_drops;	/* # of packets dropped due to no mem */
153*4882a593Smuzhiyun 	unsigned long async_notif; /* # of asynchronous notification events */
154*4882a593Smuzhiyun 	unsigned long empty;	/* # of times queue ran out of credits */
155*4882a593Smuzhiyun 	unsigned long nomem;	/* # of responses deferred due to no mem */
156*4882a593Smuzhiyun 	unsigned long unhandled_irqs;	/* # of spurious intrs */
157*4882a593Smuzhiyun 	unsigned long starved;
158*4882a593Smuzhiyun 	unsigned long restarted;
159*4882a593Smuzhiyun };
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun struct tx_desc;
162*4882a593Smuzhiyun struct tx_sw_desc;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun struct sge_txq {		/* state for an SGE Tx queue */
165*4882a593Smuzhiyun 	unsigned long flags;	/* HW DMA fetch status */
166*4882a593Smuzhiyun 	unsigned int in_use;	/* # of in-use Tx descriptors */
167*4882a593Smuzhiyun 	unsigned int size;	/* # of descriptors */
168*4882a593Smuzhiyun 	unsigned int processed;	/* total # of descs HW has processed */
169*4882a593Smuzhiyun 	unsigned int cleaned;	/* total # of descs SW has reclaimed */
170*4882a593Smuzhiyun 	unsigned int stop_thres;	/* SW TX queue suspend threshold */
171*4882a593Smuzhiyun 	unsigned int cidx;	/* consumer index */
172*4882a593Smuzhiyun 	unsigned int pidx;	/* producer index */
173*4882a593Smuzhiyun 	unsigned int gen;	/* current value of generation bit */
174*4882a593Smuzhiyun 	unsigned int unacked;	/* Tx descriptors used since last COMPL */
175*4882a593Smuzhiyun 	struct tx_desc *desc;	/* address of HW Tx descriptor ring */
176*4882a593Smuzhiyun 	struct tx_sw_desc *sdesc;	/* address of SW Tx descriptor ring */
177*4882a593Smuzhiyun 	spinlock_t lock;	/* guards enqueueing of new packets */
178*4882a593Smuzhiyun 	unsigned int token;	/* WR token */
179*4882a593Smuzhiyun 	dma_addr_t phys_addr;	/* physical address of the ring */
180*4882a593Smuzhiyun 	struct sk_buff_head sendq;	/* List of backpressured offload packets */
181*4882a593Smuzhiyun 	struct tasklet_struct qresume_tsk;	/* restarts the queue */
182*4882a593Smuzhiyun 	unsigned int cntxt_id;	/* SGE context id for the Tx q */
183*4882a593Smuzhiyun 	unsigned long stops;	/* # of times q has been stopped */
184*4882a593Smuzhiyun 	unsigned long restarts;	/* # of queue restarts */
185*4882a593Smuzhiyun };
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun enum {				/* per port SGE statistics */
188*4882a593Smuzhiyun 	SGE_PSTAT_TSO,		/* # of TSO requests */
189*4882a593Smuzhiyun 	SGE_PSTAT_RX_CSUM_GOOD,	/* # of successful RX csum offloads */
190*4882a593Smuzhiyun 	SGE_PSTAT_TX_CSUM,	/* # of TX checksum offloads */
191*4882a593Smuzhiyun 	SGE_PSTAT_VLANEX,	/* # of VLAN tag extractions */
192*4882a593Smuzhiyun 	SGE_PSTAT_VLANINS,	/* # of VLAN tag insertions */
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	SGE_PSTAT_MAX		/* must be last */
195*4882a593Smuzhiyun };
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun struct napi_gro_fraginfo;
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun struct sge_qset {		/* an SGE queue set */
200*4882a593Smuzhiyun 	struct adapter *adap;
201*4882a593Smuzhiyun 	struct napi_struct napi;
202*4882a593Smuzhiyun 	struct sge_rspq rspq;
203*4882a593Smuzhiyun 	struct sge_fl fl[SGE_RXQ_PER_SET];
204*4882a593Smuzhiyun 	struct sge_txq txq[SGE_TXQ_PER_SET];
205*4882a593Smuzhiyun 	int nomem;
206*4882a593Smuzhiyun 	void *lro_va;
207*4882a593Smuzhiyun 	struct net_device *netdev;
208*4882a593Smuzhiyun 	struct netdev_queue *tx_q;	/* associated netdev TX queue */
209*4882a593Smuzhiyun 	unsigned long txq_stopped;	/* which Tx queues are stopped */
210*4882a593Smuzhiyun 	struct timer_list tx_reclaim_timer;	/* reclaims TX buffers */
211*4882a593Smuzhiyun 	struct timer_list rx_reclaim_timer;	/* reclaims RX buffers */
212*4882a593Smuzhiyun 	unsigned long port_stats[SGE_PSTAT_MAX];
213*4882a593Smuzhiyun } ____cacheline_aligned;
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun struct sge {
216*4882a593Smuzhiyun 	struct sge_qset qs[SGE_QSETS];
217*4882a593Smuzhiyun 	spinlock_t reg_lock;	/* guards non-atomic SGE registers (eg context) */
218*4882a593Smuzhiyun };
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun struct adapter {
221*4882a593Smuzhiyun 	struct t3cdev tdev;
222*4882a593Smuzhiyun 	struct list_head adapter_list;
223*4882a593Smuzhiyun 	void __iomem *regs;
224*4882a593Smuzhiyun 	struct pci_dev *pdev;
225*4882a593Smuzhiyun 	unsigned long registered_device_map;
226*4882a593Smuzhiyun 	unsigned long open_device_map;
227*4882a593Smuzhiyun 	unsigned long flags;
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	const char *name;
230*4882a593Smuzhiyun 	int msg_enable;
231*4882a593Smuzhiyun 	unsigned int mmio_len;
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 	struct adapter_params params;
234*4882a593Smuzhiyun 	unsigned int slow_intr_mask;
235*4882a593Smuzhiyun 	unsigned long irq_stats[IRQ_NUM_STATS];
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	int msix_nvectors;
238*4882a593Smuzhiyun 	struct {
239*4882a593Smuzhiyun 		unsigned short vec;
240*4882a593Smuzhiyun 		char desc[22];
241*4882a593Smuzhiyun 	} msix_info[SGE_QSETS + 1];
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	/* T3 modules */
244*4882a593Smuzhiyun 	struct sge sge;
245*4882a593Smuzhiyun 	struct mc7 pmrx;
246*4882a593Smuzhiyun 	struct mc7 pmtx;
247*4882a593Smuzhiyun 	struct mc7 cm;
248*4882a593Smuzhiyun 	struct mc5 mc5;
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	struct net_device *port[MAX_NPORTS];
251*4882a593Smuzhiyun 	unsigned int check_task_cnt;
252*4882a593Smuzhiyun 	struct delayed_work adap_check_task;
253*4882a593Smuzhiyun 	struct work_struct ext_intr_handler_task;
254*4882a593Smuzhiyun 	struct work_struct fatal_error_handler_task;
255*4882a593Smuzhiyun 	struct work_struct link_fault_handler_task;
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	struct work_struct db_full_task;
258*4882a593Smuzhiyun 	struct work_struct db_empty_task;
259*4882a593Smuzhiyun 	struct work_struct db_drop_task;
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun 	struct dentry *debugfs_root;
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	struct mutex mdio_lock;
264*4882a593Smuzhiyun 	spinlock_t stats_lock;
265*4882a593Smuzhiyun 	spinlock_t work_lock;
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 	struct sk_buff *nofail_skb;
268*4882a593Smuzhiyun };
269*4882a593Smuzhiyun 
t3_read_reg(struct adapter * adapter,u32 reg_addr)270*4882a593Smuzhiyun static inline u32 t3_read_reg(struct adapter *adapter, u32 reg_addr)
271*4882a593Smuzhiyun {
272*4882a593Smuzhiyun 	u32 val = readl(adapter->regs + reg_addr);
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 	CH_DBG(adapter, MMIO, "read register 0x%x value 0x%x\n", reg_addr, val);
275*4882a593Smuzhiyun 	return val;
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun 
t3_write_reg(struct adapter * adapter,u32 reg_addr,u32 val)278*4882a593Smuzhiyun static inline void t3_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
279*4882a593Smuzhiyun {
280*4882a593Smuzhiyun 	CH_DBG(adapter, MMIO, "setting register 0x%x to 0x%x\n", reg_addr, val);
281*4882a593Smuzhiyun 	writel(val, adapter->regs + reg_addr);
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun 
adap2pinfo(struct adapter * adap,int idx)284*4882a593Smuzhiyun static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
285*4882a593Smuzhiyun {
286*4882a593Smuzhiyun 	return netdev_priv(adap->port[idx]);
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun 
phy2portid(struct cphy * phy)289*4882a593Smuzhiyun static inline int phy2portid(struct cphy *phy)
290*4882a593Smuzhiyun {
291*4882a593Smuzhiyun 	struct adapter *adap = phy->adapter;
292*4882a593Smuzhiyun 	struct port_info *port0 = adap2pinfo(adap, 0);
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun 	return &port0->phy == phy ? 0 : 1;
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun #define OFFLOAD_DEVMAP_BIT 15
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun #define tdev2adap(d) container_of(d, struct adapter, tdev)
300*4882a593Smuzhiyun 
offload_running(struct adapter * adapter)301*4882a593Smuzhiyun static inline int offload_running(struct adapter *adapter)
302*4882a593Smuzhiyun {
303*4882a593Smuzhiyun 	return test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map);
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun int t3_offload_tx(struct t3cdev *tdev, struct sk_buff *skb);
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun void t3_os_ext_intr_handler(struct adapter *adapter);
309*4882a593Smuzhiyun void t3_os_link_changed(struct adapter *adapter, int port_id, int link_status,
310*4882a593Smuzhiyun 			int speed, int duplex, int fc);
311*4882a593Smuzhiyun void t3_os_phymod_changed(struct adapter *adap, int port_id);
312*4882a593Smuzhiyun void t3_os_link_fault(struct adapter *adapter, int port_id, int state);
313*4882a593Smuzhiyun void t3_os_link_fault_handler(struct adapter *adapter, int port_id);
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun void t3_sge_start(struct adapter *adap);
316*4882a593Smuzhiyun void t3_sge_stop_dma(struct adapter *adap);
317*4882a593Smuzhiyun void t3_sge_stop(struct adapter *adap);
318*4882a593Smuzhiyun void t3_start_sge_timers(struct adapter *adap);
319*4882a593Smuzhiyun void t3_stop_sge_timers(struct adapter *adap);
320*4882a593Smuzhiyun void t3_free_sge_resources(struct adapter *adap);
321*4882a593Smuzhiyun void t3_sge_err_intr_handler(struct adapter *adapter);
322*4882a593Smuzhiyun irq_handler_t t3_intr_handler(struct adapter *adap, int polling);
323*4882a593Smuzhiyun netdev_tx_t t3_eth_xmit(struct sk_buff *skb, struct net_device *dev);
324*4882a593Smuzhiyun int t3_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
325*4882a593Smuzhiyun void t3_update_qset_coalesce(struct sge_qset *qs, const struct qset_params *p);
326*4882a593Smuzhiyun int t3_sge_alloc_qset(struct adapter *adapter, unsigned int id, int nports,
327*4882a593Smuzhiyun 		      int irq_vec_idx, const struct qset_params *p,
328*4882a593Smuzhiyun 		      int ntxq, struct net_device *dev,
329*4882a593Smuzhiyun 		      struct netdev_queue *netdevq);
330*4882a593Smuzhiyun extern struct workqueue_struct *cxgb3_wq;
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun int t3_get_edc_fw(struct cphy *phy, int edc_idx, int size);
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun #endif				/* __T3_ADAPTER_H__ */
335