1*4882a593Smuzhiyun /***************************************************************************** 2*4882a593Smuzhiyun * * 3*4882a593Smuzhiyun * File: suni1x10gexp_regs.h * 4*4882a593Smuzhiyun * $Revision: 1.9 $ * 5*4882a593Smuzhiyun * $Date: 2005/06/22 00:17:04 $ * 6*4882a593Smuzhiyun * Description: * 7*4882a593Smuzhiyun * PMC/SIERRA (pm3393) MAC-PHY functionality. * 8*4882a593Smuzhiyun * part of the Chelsio 10Gb Ethernet Driver. * 9*4882a593Smuzhiyun * * 10*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify * 11*4882a593Smuzhiyun * it under the terms of the GNU General Public License, version 2, as * 12*4882a593Smuzhiyun * published by the Free Software Foundation. * 13*4882a593Smuzhiyun * * 14*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License along * 15*4882a593Smuzhiyun * with this program; if not, see <http://www.gnu.org/licenses/>. * 16*4882a593Smuzhiyun * * 17*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED * 18*4882a593Smuzhiyun * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF * 19*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. * 20*4882a593Smuzhiyun * * 21*4882a593Smuzhiyun * http://www.chelsio.com * 22*4882a593Smuzhiyun * * 23*4882a593Smuzhiyun * Maintainers: maintainers@chelsio.com * 24*4882a593Smuzhiyun * * 25*4882a593Smuzhiyun * Authors: PMC/SIERRA * 26*4882a593Smuzhiyun * * 27*4882a593Smuzhiyun * History: * 28*4882a593Smuzhiyun * * 29*4882a593Smuzhiyun ****************************************************************************/ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #ifndef _CXGB_SUNI1x10GEXP_REGS_H_ 32*4882a593Smuzhiyun #define _CXGB_SUNI1x10GEXP_REGS_H_ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* 35*4882a593Smuzhiyun ** Space allocated for each Exact Match Filter 36*4882a593Smuzhiyun ** There are 8 filter configurations 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER 0x0003 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId) ( (filterId) * SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER ) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* 43*4882a593Smuzhiyun ** Space allocated for VLAN-Id Filter 44*4882a593Smuzhiyun ** There are 8 filter configurations 45*4882a593Smuzhiyun */ 46*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER 0x0001 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define mSUNI1x10GEXP_MAC_VID_FILTER_OFFSET(filterId) ( (filterId) * SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER ) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* 51*4882a593Smuzhiyun ** Space allocated for each MSTAT Counter 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT 0x0004 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId) ( (countId) * SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT ) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /******************************************************************************/ 59*4882a593Smuzhiyun /** S/UNI-1x10GE-XP REGISTER ADDRESS MAP **/ 60*4882a593Smuzhiyun /******************************************************************************/ 61*4882a593Smuzhiyun /* Refer to the Register Bit Masks bellow for the naming of each register and */ 62*4882a593Smuzhiyun /* to the S/UNI-1x10GE-XP Data Sheet for the signification of each bit */ 63*4882a593Smuzhiyun /******************************************************************************/ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_IDENTIFICATION 0x0000 67*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_PRODUCT_REVISION 0x0001 68*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_CONFIG_AND_RESET_CONTROL 0x0002 69*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_LOOPBACK_MISC_CTRL 0x0003 70*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_DEVICE_STATUS 0x0004 71*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_GLOBAL_PERFORMANCE_MONITOR_UPDATE 0x0005 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MDIO_COMMAND 0x0006 74*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MDIO_INTERRUPT_ENABLE 0x0007 75*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MDIO_INTERRUPT_STATUS 0x0008 76*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MMD_PHY_ADDRESS 0x0009 77*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MMD_CONTROL_ADDRESS_DATA 0x000A 78*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MDIO_READ_STATUS_DATA 0x000B 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_OAM_INTF_CTRL 0x000C 81*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS 0x000D 82*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE 0x000E 83*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_FREE 0x000F 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_XTEF_MISC_CTRL 0x0010 86*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_XRF_MISC_CTRL 0x0011 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_1 0x0100 89*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_SERDES_3125_CONFIG_2 0x0101 90*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE 0x0102 91*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_VISIBLE 0x0103 92*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS 0x0104 93*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_SERDES_3125_TEST_CONFIG 0x0107 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_CONFIG_1 0x2040 96*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_CONFIG_2 0x2041 97*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_CONFIG_3 0x2042 98*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_INTERRUPT 0x2043 99*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH 0x2045 100*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_SA_15_0 0x2046 101*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_SA_31_16 0x2047 102*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_SA_47_32 0x2048 103*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_RECEIVE_FIFO_THRESHOLD 0x2049 104*4882a593Smuzhiyun #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_LOW(filterId) (0x204A + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId)) 105*4882a593Smuzhiyun #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_MID(filterId) (0x204B + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId)) 106*4882a593Smuzhiyun #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_HIGH(filterId)(0x204C + mSUNI1x10GEXP_MAC_FILTER_OFFSET(filterId)) 107*4882a593Smuzhiyun #define mSUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID(filterId) (0x2062 + mSUNI1x10GEXP_MAC_VID_FILTER_OFFSET(filterId)) 108*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_LOW 0x204A 109*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_MID 0x204B 110*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_0_HIGH 0x204C 111*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW 0x204D 112*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID 0x204E 113*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH 0x204F 114*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_LOW 0x2050 115*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_MID 0x2051 116*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_2_HIGH 0x2052 117*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_LOW 0x2053 118*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_MID 0x2054 119*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_3_HIGH 0x2055 120*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_LOW 0x2056 121*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_MID 0x2057 122*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_4_HIGH 0x2058 123*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_LOW 0x2059 124*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_MID 0x205A 125*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_5_HIGH 0x205B 126*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_LOW 0x205C 127*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_MID 0x205D 128*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_6_HIGH 0x205E 129*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_LOW 0x205F 130*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_MID 0x2060 131*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_7_HIGH 0x2061 132*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_0 0x2062 133*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_1 0x2063 134*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_2 0x2064 135*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_3 0x2065 136*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_4 0x2066 137*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_5 0x2067 138*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_6 0x2068 139*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_VID_7 0x2069 140*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW 0x206A 141*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW 0x206B 142*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH 0x206C 143*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH 0x206D 144*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0 0x206E 145*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_1 0x206F 146*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2 0x2070 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_XRF_PATTERN_GEN_CTRL 0x2081 149*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_0 0x2084 150*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_1 0x2085 151*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_2 0x2086 152*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_XRF_8BTB_ERR_COUNT_LANE_3 0x2087 153*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE 0x2088 154*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS 0x2089 155*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_XRF_ERR_STATUS 0x208A 156*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE 0x208B 157*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS 0x208C 158*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_XRF_CODE_ERR_THRES 0x2092 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXOAM_CONFIG 0x20C0 161*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXOAM_FILTER_1_CONFIG 0x20C1 162*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXOAM_FILTER_2_CONFIG 0x20C2 163*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXOAM_CONFIG_2 0x20C3 164*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXOAM_HEC_CONFIG 0x20C4 165*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_THRES 0x20C5 166*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE 0x20C7 167*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS 0x20C8 168*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXOAM_STATUS 0x20C9 169*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXOAM_HEC_ERR_COUNT 0x20CA 170*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXOAM_FIFO_OVERFLOW_COUNT 0x20CB 171*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_LSB 0x20CC 172*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_COUNT_MSB 0x20CD 173*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_LSB 0x20CE 174*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXOAM_FILTER_1_MISMATCH_COUNT_MSB 0x20CF 175*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_LSB 0x20D0 176*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXOAM_FILTER_2_MISMATCH_COUNT_MSB 0x20D1 177*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_LSB 0x20D2 178*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXOAM_OAM_EXTRACT_COUNT_MSB 0x20D3 179*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_LSB 0x20D4 180*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXOAM_MINI_PACKET_COUNT_MSB 0x20D5 181*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_LSB 0x20D6 182*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_RXOAM_FILTER_MISMATCH_THRES_MSB 0x20D7 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_CONTROL 0x2100 185*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0 0x2101 186*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_1 0x2102 187*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_2 0x2103 188*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_3 0x2104 189*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0 0x2105 190*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1 0x2106 191*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2 0x2107 192*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3 0x2108 193*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_ADDRESS 0x2109 194*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_LOW 0x210A 195*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_MIDDLE 0x210B 196*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_WRITE_DATA_HIGH 0x210C 197*4882a593Smuzhiyun #define mSUNI1x10GEXP_REG_MSTAT_COUNTER_LOW(countId) (0x2110 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId)) 198*4882a593Smuzhiyun #define mSUNI1x10GEXP_REG_MSTAT_COUNTER_MID(countId) (0x2111 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId)) 199*4882a593Smuzhiyun #define mSUNI1x10GEXP_REG_MSTAT_COUNTER_HIGH(countId) (0x2112 + mSUNI1x10GEXP_MSTAT_COUNT_OFFSET(countId)) 200*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW 0x2110 201*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_MID 0x2111 202*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_HIGH 0x2112 203*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_0_RESVD 0x2113 204*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW 0x2114 205*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_MID 0x2115 206*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_HIGH 0x2116 207*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_1_RESVD 0x2117 208*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_LOW 0x2118 209*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_MID 0x2119 210*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_HIGH 0x211A 211*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_2_RESVD 0x211B 212*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_LOW 0x211C 213*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_MID 0x211D 214*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_HIGH 0x211E 215*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_3_RESVD 0x211F 216*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_LOW 0x2120 217*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_MID 0x2121 218*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_HIGH 0x2122 219*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_4_RESVD 0x2123 220*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_LOW 0x2124 221*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_MID 0x2125 222*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_HIGH 0x2126 223*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_5_RESVD 0x2127 224*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_LOW 0x2128 225*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_MID 0x2129 226*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_HIGH 0x212A 227*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_6_RESVD 0x212B 228*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_LOW 0x212C 229*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_MID 0x212D 230*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_HIGH 0x212E 231*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_7_RESVD 0x212F 232*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_LOW 0x2130 233*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_MID 0x2131 234*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_HIGH 0x2132 235*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_8_RESVD 0x2133 236*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_LOW 0x2134 237*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_MID 0x2135 238*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_HIGH 0x2136 239*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_9_RESVD 0x2137 240*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_LOW 0x2138 241*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_MID 0x2139 242*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_HIGH 0x213A 243*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_10_RESVD 0x213B 244*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_LOW 0x213C 245*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_MID 0x213D 246*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_HIGH 0x213E 247*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_11_RESVD 0x213F 248*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_LOW 0x2140 249*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_MID 0x2141 250*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_HIGH 0x2142 251*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_12_RESVD 0x2143 252*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_LOW 0x2144 253*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_MID 0x2145 254*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_HIGH 0x2146 255*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_13_RESVD 0x2147 256*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_LOW 0x2148 257*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_MID 0x2149 258*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_HIGH 0x214A 259*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_14_RESVD 0x214B 260*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_LOW 0x214C 261*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_MID 0x214D 262*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_HIGH 0x214E 263*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_15_RESVD 0x214F 264*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW 0x2150 265*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_MID 0x2151 266*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_HIGH 0x2152 267*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_16_RESVD 0x2153 268*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW 0x2154 269*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_MID 0x2155 270*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_HIGH 0x2156 271*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_17_RESVD 0x2157 272*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW 0x2158 273*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_MID 0x2159 274*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_HIGH 0x215A 275*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_18_RESVD 0x215B 276*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_LOW 0x215C 277*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_MID 0x215D 278*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_HIGH 0x215E 279*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_19_RESVD 0x215F 280*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_LOW 0x2160 281*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_MID 0x2161 282*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_HIGH 0x2162 283*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_20_RESVD 0x2163 284*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_LOW 0x2164 285*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_MID 0x2165 286*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_HIGH 0x2166 287*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_21_RESVD 0x2167 288*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_LOW 0x2168 289*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_MID 0x2169 290*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_HIGH 0x216A 291*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_22_RESVD 0x216B 292*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_LOW 0x216C 293*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_MID 0x216D 294*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_HIGH 0x216E 295*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_23_RESVD 0x216F 296*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_LOW 0x2170 297*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_MID 0x2171 298*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_HIGH 0x2172 299*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_24_RESVD 0x2173 300*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_LOW 0x2174 301*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_MID 0x2175 302*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_HIGH 0x2176 303*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_25_RESVD 0x2177 304*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_LOW 0x2178 305*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_MID 0x2179 306*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_HIGH 0x217a 307*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_26_RESVD 0x217b 308*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_LOW 0x217c 309*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_MID 0x217d 310*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_HIGH 0x217e 311*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_27_RESVD 0x217f 312*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_LOW 0x2180 313*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_MID 0x2181 314*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_HIGH 0x2182 315*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_28_RESVD 0x2183 316*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_LOW 0x2184 317*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_MID 0x2185 318*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_HIGH 0x2186 319*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_29_RESVD 0x2187 320*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_LOW 0x2188 321*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_MID 0x2189 322*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_HIGH 0x218A 323*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_30_RESVD 0x218B 324*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_LOW 0x218C 325*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_MID 0x218D 326*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_HIGH 0x218E 327*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_31_RESVD 0x218F 328*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_LOW 0x2190 329*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_MID 0x2191 330*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_HIGH 0x2192 331*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_32_RESVD 0x2193 332*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW 0x2194 333*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_MID 0x2195 334*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_HIGH 0x2196 335*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_33_RESVD 0x2197 336*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_LOW 0x2198 337*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_MID 0x2199 338*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_HIGH 0x219A 339*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_34_RESVD 0x219B 340*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW 0x219C 341*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_MID 0x219D 342*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_HIGH 0x219E 343*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_35_RESVD 0x219F 344*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_LOW 0x21A0 345*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_MID 0x21A1 346*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_HIGH 0x21A2 347*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_36_RESVD 0x21A3 348*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_LOW 0x21A4 349*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_MID 0x21A5 350*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_HIGH 0x21A6 351*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_37_RESVD 0x21A7 352*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW 0x21A8 353*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_MID 0x21A9 354*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_HIGH 0x21AA 355*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_38_RESVD 0x21AB 356*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_LOW 0x21AC 357*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_MID 0x21AD 358*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_HIGH 0x21AE 359*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_39_RESVD 0x21AF 360*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW 0x21B0 361*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_MID 0x21B1 362*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_HIGH 0x21B2 363*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_40_RESVD 0x21B3 364*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_LOW 0x21B4 365*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_MID 0x21B5 366*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_HIGH 0x21B6 367*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_41_RESVD 0x21B7 368*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW 0x21B8 369*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_MID 0x21B9 370*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_HIGH 0x21BA 371*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_42_RESVD 0x21BB 372*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW 0x21BC 373*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_MID 0x21BD 374*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_HIGH 0x21BE 375*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_43_RESVD 0x21BF 376*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_LOW 0x21C0 377*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_MID 0x21C1 378*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_HIGH 0x21C2 379*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_44_RESVD 0x21C3 380*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_LOW 0x21C4 381*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_MID 0x21C5 382*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_HIGH 0x21C6 383*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_45_RESVD 0x21C7 384*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_LOW 0x21C8 385*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_MID 0x21C9 386*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_HIGH 0x21CA 387*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_46_RESVD 0x21CB 388*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_LOW 0x21CC 389*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_MID 0x21CD 390*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_HIGH 0x21CE 391*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_47_RESVD 0x21CF 392*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_LOW 0x21D0 393*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_MID 0x21D1 394*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_HIGH 0x21D2 395*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_48_RESVD 0x21D3 396*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_LOW 0x21D4 397*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_MID 0x21D5 398*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_HIGH 0x21D6 399*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_49_RESVD 0x21D7 400*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_LOW 0x21D8 401*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_MID 0x21D9 402*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_HIGH 0x21DA 403*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_50_RESVD 0x21DB 404*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_LOW 0x21DC 405*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_MID 0x21DD 406*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_HIGH 0x21DE 407*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_51_RESVD 0x21DF 408*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_LOW 0x21E0 409*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_MID 0x21E1 410*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_HIGH 0x21E2 411*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_52_RESVD 0x21E3 412*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_LOW 0x21E4 413*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_MID 0x21E5 414*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MSTAT_COUNTER_53_HIGH 0x21E6 415*4882a593Smuzhiyun #define SUNI1x10GEXP_CNTR_MAC_ETHERNET_NUM 51 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_IFLX_GLOBAL_CONFIG 0x2200 418*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_IFLX_CHANNEL_PROVISION 0x2201 419*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE 0x2209 420*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT 0x220A 421*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_IFLX_INDIR_CHANNEL_ADDRESS 0x220D 422*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_LOW_LIMIT_PROVISION 0x220E 423*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_IFLX_INDIR_LOGICAL_FIFO_HIGH_LIMIT 0x220F 424*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_IFLX_INDIR_FULL_ALMOST_FULL_STATUS_LIMIT 0x2210 425*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_IFLX_INDIR_EMPTY_ALMOST_EMPTY_STATUS_LIMIT 0x2211 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_PL4MOS_CONFIG 0x2240 428*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_PL4MOS_MASK 0x2241 429*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_PL4MOS_FAIRNESS_MASKING 0x2242 430*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_PL4MOS_MAXBURST1 0x2243 431*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_PL4MOS_MAXBURST2 0x2244 432*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_PL4MOS_TRANSFER_SIZE 0x2245 433*4882a593Smuzhiyun 434*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_PL4ODP_CONFIG 0x2280 435*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK 0x2282 436*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_PL4ODP_INTERRUPT 0x2283 437*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_PL4ODP_CONFIG_MAX_T 0x2284 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS 0x2300 440*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE 0x2301 441*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK 0x2302 442*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_LIMITS 0x2303 443*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_PL4IO_CALENDAR_REPETITIONS 0x2304 444*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_PL4IO_CONFIG 0x2305 445*4882a593Smuzhiyun 446*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXXG_CONFIG_1 0x3040 447*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXXG_CONFIG_2 0x3041 448*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXXG_CONFIG_3 0x3042 449*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXXG_INTERRUPT 0x3043 450*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXXG_STATUS 0x3044 451*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE 0x3045 452*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXXG_MIN_FRAME_SIZE 0x3046 453*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXXG_SA_15_0 0x3047 454*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXXG_SA_31_16 0x3048 455*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXXG_SA_47_32 0x3049 456*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXXG_PAUSE_TIMER 0x304D 457*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXXG_PAUSE_TIMER_INTERVAL 0x304E 458*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXXG_FILTER_ERROR_COUNTER 0x3051 459*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXXG_PAUSE_QUANTUM_CONFIG 0x3052 460*4882a593Smuzhiyun 461*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_XTEF_CTRL 0x3080 462*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS 0x3084 463*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE 0x3085 464*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_XTEF_VISIBILITY 0x3086 465*4882a593Smuzhiyun 466*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXOAM_OAM_CONFIG 0x30C0 467*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXOAM_MINI_RATE_CONFIG 0x30C1 468*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXOAM_MINI_GAP_FIFO_CONFIG 0x30C2 469*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXOAM_P1P2_STATIC_VALUES 0x30C3 470*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXOAM_P3P4_STATIC_VALUES 0x30C4 471*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXOAM_P5P6_STATIC_VALUES 0x30C5 472*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE 0x30C6 473*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS 0x30C7 474*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXOAM_INSERT_COUNT_LSB 0x30C8 475*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXOAM_INSERT_COUNT_MSB 0x30C9 476*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXOAM_OAM_MINI_COUNT_LSB 0x30CA 477*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXOAM_OAM_MINI_COUNT_MSB 0x30CB 478*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXOAM_P1P2_MINI_MASK 0x30CC 479*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXOAM_P3P4_MINI_MASK 0x30CD 480*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXOAM_P5P6_MINI_MASK 0x30CE 481*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXOAM_COSET 0x30CF 482*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXOAM_EMPTY_FIFO_INS_OP_CNT_LSB 0x30D0 483*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXOAM_EMPTY_FIFO_INS_OP_CNT_MSB 0x30D1 484*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXOAM_STATIC_VALUE_MINI_COUNT_LSB 0x30D2 485*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_TXOAM_STATIC_VALUE_MINI_COUNT_MSB 0x30D3 486*4882a593Smuzhiyun 487*4882a593Smuzhiyun 488*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_EFLX_GLOBAL_CONFIG 0x3200 489*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_EFLX_ERCU_GLOBAL_STATUS 0x3201 490*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_EFLX_INDIR_CHANNEL_ADDRESS 0x3202 491*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_LOW_LIMIT 0x3203 492*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_HIGH_LIMIT 0x3204 493*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_EFLX_INDIR_FULL_ALMOST_FULL_STATUS_AND_LIMIT 0x3205 494*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_EFLX_INDIR_EMPTY_ALMOST_EMPTY_STATUS_AND_LIMIT 0x3206 495*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_EFLX_INDIR_FIFO_CUT_THROUGH_THRESHOLD 0x3207 496*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE 0x320C 497*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION 0x320D 498*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_EFLX_CHANNEL_PROVISION 0x3210 499*4882a593Smuzhiyun 500*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_PL4IDU_CONFIG 0x3280 501*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK 0x3282 502*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_PL4IDU_INTERRUPT 0x3283 503*4882a593Smuzhiyun 504*4882a593Smuzhiyun 505*4882a593Smuzhiyun /*----------------------------------------*/ 506*4882a593Smuzhiyun #define SUNI1x10GEXP_REG_MAX_OFFSET 0x3480 507*4882a593Smuzhiyun 508*4882a593Smuzhiyun /******************************************************************************/ 509*4882a593Smuzhiyun /* -- End register offset definitions -- */ 510*4882a593Smuzhiyun /******************************************************************************/ 511*4882a593Smuzhiyun 512*4882a593Smuzhiyun /******************************************************************************/ 513*4882a593Smuzhiyun /** SUNI-1x10GE-XP REGISTER BIT MASKS **/ 514*4882a593Smuzhiyun /******************************************************************************/ 515*4882a593Smuzhiyun 516*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_BITS_1 0x00001 517*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_BITS_2 0x00003 518*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_BITS_3 0x00007 519*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_BITS_4 0x0000f 520*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_BITS_5 0x0001f 521*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_BITS_6 0x0003f 522*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_BITS_7 0x0007f 523*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_BITS_8 0x000ff 524*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_BITS_9 0x001ff 525*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_BITS_10 0x003ff 526*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_BITS_11 0x007ff 527*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_BITS_12 0x00fff 528*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_BITS_13 0x01fff 529*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_BITS_14 0x03fff 530*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_BITS_15 0x07fff 531*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_BITS_16 0x0ffff 532*4882a593Smuzhiyun 533*4882a593Smuzhiyun #define mSUNI1x10GEXP_CLR_MSBITS_1(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_15) 534*4882a593Smuzhiyun #define mSUNI1x10GEXP_CLR_MSBITS_2(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_14) 535*4882a593Smuzhiyun #define mSUNI1x10GEXP_CLR_MSBITS_3(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_13) 536*4882a593Smuzhiyun #define mSUNI1x10GEXP_CLR_MSBITS_4(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_12) 537*4882a593Smuzhiyun #define mSUNI1x10GEXP_CLR_MSBITS_5(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_11) 538*4882a593Smuzhiyun #define mSUNI1x10GEXP_CLR_MSBITS_6(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_10) 539*4882a593Smuzhiyun #define mSUNI1x10GEXP_CLR_MSBITS_7(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_9) 540*4882a593Smuzhiyun #define mSUNI1x10GEXP_CLR_MSBITS_8(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_8) 541*4882a593Smuzhiyun #define mSUNI1x10GEXP_CLR_MSBITS_9(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_7) 542*4882a593Smuzhiyun #define mSUNI1x10GEXP_CLR_MSBITS_10(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_6) 543*4882a593Smuzhiyun #define mSUNI1x10GEXP_CLR_MSBITS_11(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_5) 544*4882a593Smuzhiyun #define mSUNI1x10GEXP_CLR_MSBITS_12(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_4) 545*4882a593Smuzhiyun #define mSUNI1x10GEXP_CLR_MSBITS_13(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_3) 546*4882a593Smuzhiyun #define mSUNI1x10GEXP_CLR_MSBITS_14(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_2) 547*4882a593Smuzhiyun #define mSUNI1x10GEXP_CLR_MSBITS_15(v) ((v) & SUNI1x10GEXP_BITMSK_BITS_1) 548*4882a593Smuzhiyun 549*4882a593Smuzhiyun #define mSUNI1x10GEXP_GET_BIT(val, bitMsk) (((val)&(bitMsk)) ? 1:0) 550*4882a593Smuzhiyun 551*4882a593Smuzhiyun 552*4882a593Smuzhiyun 553*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 554*4882a593Smuzhiyun * Register 0x0001: S/UNI-1x10GE-XP Product Revision 555*4882a593Smuzhiyun * Bit 3-0 REVISION 556*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 557*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_REVISION 0x000F 558*4882a593Smuzhiyun 559*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 560*4882a593Smuzhiyun * Register 0x0002: S/UNI-1x10GE-XP Configuration and Reset Control 561*4882a593Smuzhiyun * Bit 2 XAUI_ARESETB 562*4882a593Smuzhiyun * Bit 1 PL4_ARESETB 563*4882a593Smuzhiyun * Bit 0 DRESETB 564*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 565*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_XAUI_ARESET 0x0004 566*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4_ARESET 0x0002 567*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_DRESETB 0x0001 568*4882a593Smuzhiyun 569*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 570*4882a593Smuzhiyun * Register 0x0003: S/UNI-1x10GE-XP Loop Back and Miscellaneous Control 571*4882a593Smuzhiyun * Bit 11 PL4IO_OUTCLKSEL 572*4882a593Smuzhiyun * Bit 9 SYSPCSLB 573*4882a593Smuzhiyun * Bit 8 LINEPCSLB 574*4882a593Smuzhiyun * Bit 7 MSTAT_BYPASS 575*4882a593Smuzhiyun * Bit 6 RXXG_BYPASS 576*4882a593Smuzhiyun * Bit 5 TXXG_BYPASS 577*4882a593Smuzhiyun * Bit 4 SOP_PAD_EN 578*4882a593Smuzhiyun * Bit 1 LOS_INV 579*4882a593Smuzhiyun * Bit 0 OVERRIDE_LOS 580*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 581*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_OUTCLKSEL 0x0800 582*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_SYSPCSLB 0x0200 583*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_LINEPCSLB 0x0100 584*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_MSTAT_BYPASS 0x0080 585*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_BYPASS 0x0040 586*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXXG_BYPASS 0x0020 587*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_SOP_PAD_EN 0x0010 588*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_LOS_INV 0x0002 589*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_OVERRIDE_LOS 0x0001 590*4882a593Smuzhiyun 591*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 592*4882a593Smuzhiyun * Register 0x0004: S/UNI-1x10GE-XP Device Status 593*4882a593Smuzhiyun * Bit 9 TOP_SXRA_EXPIRED 594*4882a593Smuzhiyun * Bit 8 TOP_MDIO_BUSY 595*4882a593Smuzhiyun * Bit 7 TOP_DTRB 596*4882a593Smuzhiyun * Bit 6 TOP_EXPIRED 597*4882a593Smuzhiyun * Bit 5 TOP_PAUSED 598*4882a593Smuzhiyun * Bit 4 TOP_PL4_ID_DOOL 599*4882a593Smuzhiyun * Bit 3 TOP_PL4_IS_DOOL 600*4882a593Smuzhiyun * Bit 2 TOP_PL4_ID_ROOL 601*4882a593Smuzhiyun * Bit 1 TOP_PL4_IS_ROOL 602*4882a593Smuzhiyun * Bit 0 TOP_PL4_OUT_ROOL 603*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 604*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_SXRA_EXPIRED 0x0200 605*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_MDIO_BUSY 0x0100 606*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_DTRB 0x0080 607*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_EXPIRED 0x0040 608*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_PAUSED 0x0020 609*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_DOOL 0x0010 610*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL 0x0008 611*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_PL4_ID_ROOL 0x0004 612*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_PL4_IS_ROOL 0x0002 613*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_PL4_OUT_ROOL 0x0001 614*4882a593Smuzhiyun 615*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 616*4882a593Smuzhiyun * Register 0x0005: Global Performance Update and Clock Monitors 617*4882a593Smuzhiyun * Bit 15 TIP 618*4882a593Smuzhiyun * Bit 8 XAUI_REF_CLKA 619*4882a593Smuzhiyun * Bit 7 RXLANE3CLKA 620*4882a593Smuzhiyun * Bit 6 RXLANE2CLKA 621*4882a593Smuzhiyun * Bit 5 RXLANE1CLKA 622*4882a593Smuzhiyun * Bit 4 RXLANE0CLKA 623*4882a593Smuzhiyun * Bit 3 CSUCLKA 624*4882a593Smuzhiyun * Bit 2 TDCLKA 625*4882a593Smuzhiyun * Bit 1 RSCLKA 626*4882a593Smuzhiyun * Bit 0 RDCLKA 627*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 628*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TIP 0x8000 629*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_XAUI_REF_CLKA 0x0100 630*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXLANE3CLKA 0x0080 631*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXLANE2CLKA 0x0040 632*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXLANE1CLKA 0x0020 633*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXLANE0CLKA 0x0010 634*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_CSUCLKA 0x0008 635*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TDCLKA 0x0004 636*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RSCLKA 0x0002 637*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RDCLKA 0x0001 638*4882a593Smuzhiyun 639*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 640*4882a593Smuzhiyun * Register 0x0006: MDIO Command 641*4882a593Smuzhiyun * Bit 4 MDIO_RDINC 642*4882a593Smuzhiyun * Bit 3 MDIO_RSTAT 643*4882a593Smuzhiyun * Bit 2 MDIO_LCTLD 644*4882a593Smuzhiyun * Bit 1 MDIO_LCTLA 645*4882a593Smuzhiyun * Bit 0 MDIO_SPRE 646*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 647*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_MDIO_RDINC 0x0010 648*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_MDIO_RSTAT 0x0008 649*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_MDIO_LCTLD 0x0004 650*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_MDIO_LCTLA 0x0002 651*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_MDIO_SPRE 0x0001 652*4882a593Smuzhiyun 653*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 654*4882a593Smuzhiyun * Register 0x0007: MDIO Interrupt Enable 655*4882a593Smuzhiyun * Bit 0 MDIO_BUSY_EN 656*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 657*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_MDIO_BUSY_EN 0x0001 658*4882a593Smuzhiyun 659*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 660*4882a593Smuzhiyun * Register 0x0008: MDIO Interrupt Status 661*4882a593Smuzhiyun * Bit 0 MDIO_BUSYI 662*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 663*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_MDIO_BUSYI 0x0001 664*4882a593Smuzhiyun 665*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 666*4882a593Smuzhiyun * Register 0x0009: MMD PHY Address 667*4882a593Smuzhiyun * Bit 12-8 MDIO_DEVADR 668*4882a593Smuzhiyun * Bit 4-0 MDIO_PRTADR 669*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 670*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_MDIO_DEVADR 0x1F00 671*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_MDIO_DEVADR 8 672*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_MDIO_PRTADR 0x001F 673*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_MDIO_PRTADR 0 674*4882a593Smuzhiyun 675*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 676*4882a593Smuzhiyun * Register 0x000C: OAM Interface Control 677*4882a593Smuzhiyun * Bit 6 MDO_OD_ENB 678*4882a593Smuzhiyun * Bit 5 MDI_INV 679*4882a593Smuzhiyun * Bit 4 MDI_SEL 680*4882a593Smuzhiyun * Bit 3 RXOAMEN 681*4882a593Smuzhiyun * Bit 2 RXOAMCLKEN 682*4882a593Smuzhiyun * Bit 1 TXOAMEN 683*4882a593Smuzhiyun * Bit 0 TXOAMCLKEN 684*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 685*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_MDO_OD_ENB 0x0040 686*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_MDI_INV 0x0020 687*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_MDI_SEL 0x0010 688*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAMEN 0x0008 689*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAMCLKEN 0x0004 690*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXOAMEN 0x0002 691*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXOAMCLKEN 0x0001 692*4882a593Smuzhiyun 693*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 694*4882a593Smuzhiyun * Register 0x000D: S/UNI-1x10GE-XP Master Interrupt Status 695*4882a593Smuzhiyun * Bit 15 TOP_PL4IO_INT 696*4882a593Smuzhiyun * Bit 14 TOP_IRAM_INT 697*4882a593Smuzhiyun * Bit 13 TOP_ERAM_INT 698*4882a593Smuzhiyun * Bit 12 TOP_XAUI_INT 699*4882a593Smuzhiyun * Bit 11 TOP_MSTAT_INT 700*4882a593Smuzhiyun * Bit 10 TOP_RXXG_INT 701*4882a593Smuzhiyun * Bit 9 TOP_TXXG_INT 702*4882a593Smuzhiyun * Bit 8 TOP_XRF_INT 703*4882a593Smuzhiyun * Bit 7 TOP_XTEF_INT 704*4882a593Smuzhiyun * Bit 6 TOP_MDIO_BUSY_INT 705*4882a593Smuzhiyun * Bit 5 TOP_RXOAM_INT 706*4882a593Smuzhiyun * Bit 4 TOP_TXOAM_INT 707*4882a593Smuzhiyun * Bit 3 TOP_IFLX_INT 708*4882a593Smuzhiyun * Bit 2 TOP_EFLX_INT 709*4882a593Smuzhiyun * Bit 1 TOP_PL4ODP_INT 710*4882a593Smuzhiyun * Bit 0 TOP_PL4IDU_INT 711*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 712*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_PL4IO_INT 0x8000 713*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_IRAM_INT 0x4000 714*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_ERAM_INT 0x2000 715*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_XAUI_INT 0x1000 716*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_MSTAT_INT 0x0800 717*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_RXXG_INT 0x0400 718*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_TXXG_INT 0x0200 719*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_XRF_INT 0x0100 720*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_XTEF_INT 0x0080 721*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_MDIO_BUSY_INT 0x0040 722*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_RXOAM_INT 0x0020 723*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_TXOAM_INT 0x0010 724*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_IFLX_INT 0x0008 725*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_EFLX_INT 0x0004 726*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_PL4ODP_INT 0x0002 727*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_PL4IDU_INT 0x0001 728*4882a593Smuzhiyun 729*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 730*4882a593Smuzhiyun * Register 0x000E:PM3393 Global interrupt enable 731*4882a593Smuzhiyun * Bit 15 TOP_INTE 732*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 733*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TOP_INTE 0x8000 734*4882a593Smuzhiyun 735*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 736*4882a593Smuzhiyun * Register 0x0010: XTEF Miscellaneous Control 737*4882a593Smuzhiyun * Bit 7 RF_VAL 738*4882a593Smuzhiyun * Bit 6 RF_OVERRIDE 739*4882a593Smuzhiyun * Bit 5 LF_VAL 740*4882a593Smuzhiyun * Bit 4 LF_OVERRIDE 741*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 742*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RF_VAL 0x0080 743*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RF_OVERRIDE 0x0040 744*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_LF_VAL 0x0020 745*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_LF_OVERRIDE 0x0010 746*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_LFRF_OVERRIDE_VAL 0x00F0 747*4882a593Smuzhiyun 748*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 749*4882a593Smuzhiyun * Register 0x0011: XRF Miscellaneous Control 750*4882a593Smuzhiyun * Bit 6-4 EN_IDLE_REP 751*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 752*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_EN_IDLE_REP 0x0070 753*4882a593Smuzhiyun 754*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 755*4882a593Smuzhiyun * Register 0x0100: SERDES 3125 Configuration Register 1 756*4882a593Smuzhiyun * Bit 10 RXEQB_3 757*4882a593Smuzhiyun * Bit 8 RXEQB_2 758*4882a593Smuzhiyun * Bit 6 RXEQB_1 759*4882a593Smuzhiyun * Bit 4 RXEQB_0 760*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 761*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXEQB 0x0FF0 762*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_RXEQB_3 10 763*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_RXEQB_2 8 764*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_RXEQB_1 6 765*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_RXEQB_0 4 766*4882a593Smuzhiyun 767*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 768*4882a593Smuzhiyun * Register 0x0101: SERDES 3125 Configuration Register 2 769*4882a593Smuzhiyun * Bit 12 YSEL 770*4882a593Smuzhiyun * Bit 7 PRE_EMPH_3 771*4882a593Smuzhiyun * Bit 6 PRE_EMPH_2 772*4882a593Smuzhiyun * Bit 5 PRE_EMPH_1 773*4882a593Smuzhiyun * Bit 4 PRE_EMPH_0 774*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 775*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_YSEL 0x1000 776*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PRE_EMPH 0x00F0 777*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PRE_EMPH_3 0x0080 778*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PRE_EMPH_2 0x0040 779*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PRE_EMPH_1 0x0020 780*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PRE_EMPH_0 0x0010 781*4882a593Smuzhiyun 782*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 783*4882a593Smuzhiyun * Register 0x0102: SERDES 3125 Interrupt Enable Register 784*4882a593Smuzhiyun * Bit 3 LASIE 785*4882a593Smuzhiyun * Bit 2 SPLL_RAE 786*4882a593Smuzhiyun * Bit 1 MPLL_RAE 787*4882a593Smuzhiyun * Bit 0 PLL_LOCKE 788*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 789*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_LASIE 0x0008 790*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_SPLL_RAE 0x0004 791*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_MPLL_RAE 0x0002 792*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PLL_LOCKE 0x0001 793*4882a593Smuzhiyun 794*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 795*4882a593Smuzhiyun * Register 0x0103: SERDES 3125 Interrupt Visibility Register 796*4882a593Smuzhiyun * Bit 3 LASIV 797*4882a593Smuzhiyun * Bit 2 SPLL_RAV 798*4882a593Smuzhiyun * Bit 1 MPLL_RAV 799*4882a593Smuzhiyun * Bit 0 PLL_LOCKV 800*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 801*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_LASIV 0x0008 802*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_SPLL_RAV 0x0004 803*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_MPLL_RAV 0x0002 804*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PLL_LOCKV 0x0001 805*4882a593Smuzhiyun 806*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 807*4882a593Smuzhiyun * Register 0x0104: SERDES 3125 Interrupt Status Register 808*4882a593Smuzhiyun * Bit 3 LASII 809*4882a593Smuzhiyun * Bit 2 SPLL_RAI 810*4882a593Smuzhiyun * Bit 1 MPLL_RAI 811*4882a593Smuzhiyun * Bit 0 PLL_LOCKI 812*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 813*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_LASII 0x0008 814*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_SPLL_RAI 0x0004 815*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_MPLL_RAI 0x0002 816*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PLL_LOCKI 0x0001 817*4882a593Smuzhiyun 818*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 819*4882a593Smuzhiyun * Register 0x0107: SERDES 3125 Test Configuration 820*4882a593Smuzhiyun * Bit 12 DUALTX 821*4882a593Smuzhiyun * Bit 10 HC_1 822*4882a593Smuzhiyun * Bit 9 HC_0 823*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 824*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_DUALTX 0x1000 825*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_HC 0x0600 826*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_HC_0 9 827*4882a593Smuzhiyun 828*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 829*4882a593Smuzhiyun * Register 0x2040: RXXG Configuration 1 830*4882a593Smuzhiyun * Bit 15 RXXG_RXEN 831*4882a593Smuzhiyun * Bit 14 RXXG_ROCF 832*4882a593Smuzhiyun * Bit 13 RXXG_PAD_STRIP 833*4882a593Smuzhiyun * Bit 10 RXXG_PUREP 834*4882a593Smuzhiyun * Bit 9 RXXG_LONGP 835*4882a593Smuzhiyun * Bit 8 RXXG_PARF 836*4882a593Smuzhiyun * Bit 7 RXXG_FLCHK 837*4882a593Smuzhiyun * Bit 5 RXXG_PASS_CTRL 838*4882a593Smuzhiyun * Bit 3 RXXG_CRC_STRIP 839*4882a593Smuzhiyun * Bit 2-0 RXXG_MIFG 840*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 841*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_RXEN 0x8000 842*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_ROCF 0x4000 843*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_PAD_STRIP 0x2000 844*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_PUREP 0x0400 845*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_LONGP 0x0200 846*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_PARF 0x0100 847*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_FLCHK 0x0080 848*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_PASS_CTRL 0x0020 849*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_CRC_STRIP 0x0008 850*4882a593Smuzhiyun 851*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 852*4882a593Smuzhiyun * Register 0x02041: RXXG Configuration 2 853*4882a593Smuzhiyun * Bit 7-0 RXXG_HDRSIZE 854*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 855*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_HDRSIZE 0x00FF 856*4882a593Smuzhiyun 857*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 858*4882a593Smuzhiyun * Register 0x2042: RXXG Configuration 3 859*4882a593Smuzhiyun * Bit 15 RXXG_MIN_LERRE 860*4882a593Smuzhiyun * Bit 14 RXXG_MAX_LERRE 861*4882a593Smuzhiyun * Bit 12 RXXG_LINE_ERRE 862*4882a593Smuzhiyun * Bit 10 RXXG_RX_OVRE 863*4882a593Smuzhiyun * Bit 9 RXXG_ADR_FILTERE 864*4882a593Smuzhiyun * Bit 8 RXXG_ERR_FILTERE 865*4882a593Smuzhiyun * Bit 5 RXXG_PRMB_ERRE 866*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 867*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_MIN_LERRE 0x8000 868*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_MAX_LERRE 0x4000 869*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_LINE_ERRE 0x1000 870*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_RX_OVRE 0x0400 871*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_ADR_FILTERE 0x0200 872*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_ERR_FILTERRE 0x0100 873*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_PRMB_ERRE 0x0020 874*4882a593Smuzhiyun 875*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 876*4882a593Smuzhiyun * Register 0x2043: RXXG Interrupt 877*4882a593Smuzhiyun * Bit 15 RXXG_MIN_LERRI 878*4882a593Smuzhiyun * Bit 14 RXXG_MAX_LERRI 879*4882a593Smuzhiyun * Bit 12 RXXG_LINE_ERRI 880*4882a593Smuzhiyun * Bit 10 RXXG_RX_OVRI 881*4882a593Smuzhiyun * Bit 9 RXXG_ADR_FILTERI 882*4882a593Smuzhiyun * Bit 8 RXXG_ERR_FILTERI 883*4882a593Smuzhiyun * Bit 5 RXXG_PRMB_ERRE 884*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 885*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_MIN_LERRI 0x8000 886*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_MAX_LERRI 0x4000 887*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_LINE_ERRI 0x1000 888*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_RX_OVRI 0x0400 889*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_ADR_FILTERI 0x0200 890*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_ERR_FILTERI 0x0100 891*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_PRMB_ERRE 0x0020 892*4882a593Smuzhiyun 893*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 894*4882a593Smuzhiyun * Register 0x2049: RXXG Receive FIFO Threshold 895*4882a593Smuzhiyun * Bit 2-0 RXXG_CUT_THRU 896*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 897*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_CUT_THRU 0x0007 898*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_RXXG_CUT_THRU 0 899*4882a593Smuzhiyun 900*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 901*4882a593Smuzhiyun * Register 0x2062H - 0x2069: RXXG Exact Match VID 902*4882a593Smuzhiyun * Bit 11-0 RXXG_VID_MATCH 903*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 904*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_VID_MATCH 0x0FFF 905*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_RXXG_VID_MATCH 0 906*4882a593Smuzhiyun 907*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 908*4882a593Smuzhiyun * Register 0x206EH - 0x206F: RXXG Address Filter Control 909*4882a593Smuzhiyun * Bit 3 RXXG_FORWARD_ENABLE 910*4882a593Smuzhiyun * Bit 2 RXXG_VLAN_ENABLE 911*4882a593Smuzhiyun * Bit 1 RXXG_SRC_ADDR 912*4882a593Smuzhiyun * Bit 0 RXXG_MATCH_ENABLE 913*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 914*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_FORWARD_ENABLE 0x0008 915*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_VLAN_ENABLE 0x0004 916*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_SRC_ADDR 0x0002 917*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_MATCH_ENABLE 0x0001 918*4882a593Smuzhiyun 919*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 920*4882a593Smuzhiyun * Register 0x2070: RXXG Address Filter Control 2 921*4882a593Smuzhiyun * Bit 1 RXXG_PMODE 922*4882a593Smuzhiyun * Bit 0 RXXG_MHASH_EN 923*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 924*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_PMODE 0x0002 925*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN 0x0001 926*4882a593Smuzhiyun 927*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 928*4882a593Smuzhiyun * Register 0x2081: XRF Control Register 2 929*4882a593Smuzhiyun * Bit 6 EN_PKT_GEN 930*4882a593Smuzhiyun * Bit 4-2 PATT 931*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 932*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_EN_PKT_GEN 0x0040 933*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PATT 0x001C 934*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_PATT 2 935*4882a593Smuzhiyun 936*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 937*4882a593Smuzhiyun * Register 0x2088: XRF Interrupt Enable 938*4882a593Smuzhiyun * Bit 12-9 LANE_HICERE 939*4882a593Smuzhiyun * Bit 8-5 HS_SD_LANEE 940*4882a593Smuzhiyun * Bit 4 ALIGN_STATUS_ERRE 941*4882a593Smuzhiyun * Bit 3-0 LANE_SYNC_STAT_ERRE 942*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 943*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_LANE_HICERE 0x1E00 944*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_LANE_HICERE 9 945*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_HS_SD_LANEE 0x01E0 946*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_HS_SD_LANEE 5 947*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERRE 0x0010 948*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_LANE_SYNC_STAT_ERRE 0x000F 949*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRE 0 950*4882a593Smuzhiyun 951*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 952*4882a593Smuzhiyun * Register 0x2089: XRF Interrupt Status 953*4882a593Smuzhiyun * Bit 12-9 LANE_HICERI 954*4882a593Smuzhiyun * Bit 8-5 HS_SD_LANEI 955*4882a593Smuzhiyun * Bit 4 ALIGN_STATUS_ERRI 956*4882a593Smuzhiyun * Bit 3-0 LANE_SYNC_STAT_ERRI 957*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 958*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_LANE_HICERI 0x1E00 959*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_LANE_HICERI 9 960*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_HS_SD_LANEI 0x01E0 961*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_HS_SD_LANEI 5 962*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERRI 0x0010 963*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_LANE_SYNC_STAT_ERRI 0x000F 964*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_LANE_SYNC_STAT_ERRI 0 965*4882a593Smuzhiyun 966*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 967*4882a593Smuzhiyun * Register 0x208A: XRF Error Status 968*4882a593Smuzhiyun * Bit 8-5 HS_SD_LANE 969*4882a593Smuzhiyun * Bit 4 ALIGN_STATUS_ERR 970*4882a593Smuzhiyun * Bit 3-0 LANE_SYNC_STAT_ERR 971*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 972*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_HS_SD_LANE3 0x0100 973*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_HS_SD_LANE2 0x0080 974*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_HS_SD_LANE1 0x0040 975*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_HS_SD_LANE0 0x0020 976*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_ALIGN_STATUS_ERR 0x0010 977*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_LANE3_SYNC_STAT_ERR 0x0008 978*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_LANE2_SYNC_STAT_ERR 0x0004 979*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_LANE1_SYNC_STAT_ERR 0x0002 980*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_LANE0_SYNC_STAT_ERR 0x0001 981*4882a593Smuzhiyun 982*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 983*4882a593Smuzhiyun * Register 0x208B: XRF Diagnostic Interrupt Enable 984*4882a593Smuzhiyun * Bit 7-4 LANE_OVERRUNE 985*4882a593Smuzhiyun * Bit 3-0 LANE_UNDERRUNE 986*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 987*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_LANE_OVERRUNE 0x00F0 988*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_LANE_OVERRUNE 4 989*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_LANE_UNDERRUNE 0x000F 990*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNE 0 991*4882a593Smuzhiyun 992*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 993*4882a593Smuzhiyun * Register 0x208C: XRF Diagnostic Interrupt Status 994*4882a593Smuzhiyun * Bit 7-4 LANE_OVERRUNI 995*4882a593Smuzhiyun * Bit 3-0 LANE_UNDERRUNI 996*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 997*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_LANE_OVERRUNI 0x00F0 998*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_LANE_OVERRUNI 4 999*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_LANE_UNDERRUNI 0x000F 1000*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_LANE_UNDERRUNI 0 1001*4882a593Smuzhiyun 1002*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1003*4882a593Smuzhiyun * Register 0x20C0: RXOAM Configuration 1004*4882a593Smuzhiyun * Bit 15 RXOAM_BUSY 1005*4882a593Smuzhiyun * Bit 14-12 RXOAM_F2_SEL 1006*4882a593Smuzhiyun * Bit 10-8 RXOAM_F1_SEL 1007*4882a593Smuzhiyun * Bit 7-6 RXOAM_FILTER_CTRL 1008*4882a593Smuzhiyun * Bit 5-0 RXOAM_PX_EN 1009*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1010*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_BUSY 0x8000 1011*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_F2_SEL 0x7000 1012*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_RXOAM_F2_SEL 12 1013*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_F1_SEL 0x0700 1014*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_RXOAM_F1_SEL 8 1015*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_CTRL 0x00C0 1016*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_RXOAM_FILTER_CTRL 6 1017*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_PX_EN 0x003F 1018*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_RXOAM_PX_EN 0 1019*4882a593Smuzhiyun 1020*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1021*4882a593Smuzhiyun * Register 0x20C1,0x20C2: RXOAM Filter Configuration 1022*4882a593Smuzhiyun * Bit 15-8 RXOAM_FX_MASK 1023*4882a593Smuzhiyun * Bit 7-0 RXOAM_FX_VAL 1024*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1025*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_FX_MASK 0xFF00 1026*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_RXOAM_FX_MASK 8 1027*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_FX_VAL 0x00FF 1028*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_RXOAM_FX_VAl 0 1029*4882a593Smuzhiyun 1030*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1031*4882a593Smuzhiyun * Register 0x20C3: RXOAM Configuration Register 2 1032*4882a593Smuzhiyun * Bit 13 RXOAM_REC_BYTE_VAL 1033*4882a593Smuzhiyun * Bit 11-10 RXOAM_BYPASS_MODE 1034*4882a593Smuzhiyun * Bit 5-0 RXOAM_PX_CLEAR 1035*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1036*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_REC_BYTE_VAL 0x2000 1037*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_BYPASS_MODE 0x0C00 1038*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_RXOAM_BYPASS_MODE 10 1039*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_PX_CLEAR 0x003F 1040*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_RXOAM_PX_CLEAR 0 1041*4882a593Smuzhiyun 1042*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1043*4882a593Smuzhiyun * Register 0x20C4: RXOAM HEC Configuration 1044*4882a593Smuzhiyun * Bit 15-8 RXOAM_COSET 1045*4882a593Smuzhiyun * Bit 2 RXOAM_HEC_ERR_PKT 1046*4882a593Smuzhiyun * Bit 0 RXOAM_HEC_EN 1047*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1048*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_COSET 0xFF00 1049*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_RXOAM_COSET 8 1050*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_HEC_ERR_PKT 0x0004 1051*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_HEC_EN 0x0001 1052*4882a593Smuzhiyun 1053*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1054*4882a593Smuzhiyun * Register 0x20C7: RXOAM Interrupt Enable 1055*4882a593Smuzhiyun * Bit 10 RXOAM_FILTER_THRSHE 1056*4882a593Smuzhiyun * Bit 9 RXOAM_OAM_ERRE 1057*4882a593Smuzhiyun * Bit 8 RXOAM_HECE_THRSHE 1058*4882a593Smuzhiyun * Bit 7 RXOAM_SOPE 1059*4882a593Smuzhiyun * Bit 6 RXOAM_RFE 1060*4882a593Smuzhiyun * Bit 5 RXOAM_LFE 1061*4882a593Smuzhiyun * Bit 4 RXOAM_DV_ERRE 1062*4882a593Smuzhiyun * Bit 3 RXOAM_DATA_INVALIDE 1063*4882a593Smuzhiyun * Bit 2 RXOAM_FILTER_DROPE 1064*4882a593Smuzhiyun * Bit 1 RXOAM_HECE 1065*4882a593Smuzhiyun * Bit 0 RXOAM_OFLE 1066*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1067*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHE 0x0400 1068*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_OAM_ERRE 0x0200 1069*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHE 0x0100 1070*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_SOPE 0x0080 1071*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_RFE 0x0040 1072*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_LFE 0x0020 1073*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_DV_ERRE 0x0010 1074*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_DATA_INVALIDE 0x0008 1075*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_DROPE 0x0004 1076*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_HECE 0x0002 1077*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_OFLE 0x0001 1078*4882a593Smuzhiyun 1079*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1080*4882a593Smuzhiyun * Register 0x20C8: RXOAM Interrupt Status 1081*4882a593Smuzhiyun * Bit 10 RXOAM_FILTER_THRSHI 1082*4882a593Smuzhiyun * Bit 9 RXOAM_OAM_ERRI 1083*4882a593Smuzhiyun * Bit 8 RXOAM_HECE_THRSHI 1084*4882a593Smuzhiyun * Bit 7 RXOAM_SOPI 1085*4882a593Smuzhiyun * Bit 6 RXOAM_RFI 1086*4882a593Smuzhiyun * Bit 5 RXOAM_LFI 1087*4882a593Smuzhiyun * Bit 4 RXOAM_DV_ERRI 1088*4882a593Smuzhiyun * Bit 3 RXOAM_DATA_INVALIDI 1089*4882a593Smuzhiyun * Bit 2 RXOAM_FILTER_DROPI 1090*4882a593Smuzhiyun * Bit 1 RXOAM_HECI 1091*4882a593Smuzhiyun * Bit 0 RXOAM_OFLI 1092*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1093*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHI 0x0400 1094*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_OAM_ERRI 0x0200 1095*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHI 0x0100 1096*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_SOPI 0x0080 1097*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_RFI 0x0040 1098*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_LFI 0x0020 1099*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_DV_ERRI 0x0010 1100*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_DATA_INVALIDI 0x0008 1101*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_DROPI 0x0004 1102*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_HECI 0x0002 1103*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_OFLI 0x0001 1104*4882a593Smuzhiyun 1105*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1106*4882a593Smuzhiyun * Register 0x20C9: RXOAM Status 1107*4882a593Smuzhiyun * Bit 10 RXOAM_FILTER_THRSHV 1108*4882a593Smuzhiyun * Bit 8 RXOAM_HECE_THRSHV 1109*4882a593Smuzhiyun * Bit 6 RXOAM_RFV 1110*4882a593Smuzhiyun * Bit 5 RXOAM_LFV 1111*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1112*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_FILTER_THRSHV 0x0400 1113*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_HECE_THRSHV 0x0100 1114*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_RFV 0x0040 1115*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_RXOAM_LFV 0x0020 1116*4882a593Smuzhiyun 1117*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1118*4882a593Smuzhiyun * Register 0x2100: MSTAT Control 1119*4882a593Smuzhiyun * Bit 2 MSTAT_WRITE 1120*4882a593Smuzhiyun * Bit 1 MSTAT_CLEAR 1121*4882a593Smuzhiyun * Bit 0 MSTAT_SNAP 1122*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1123*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_MSTAT_WRITE 0x0004 1124*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_MSTAT_CLEAR 0x0002 1125*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_MSTAT_SNAP 0x0001 1126*4882a593Smuzhiyun 1127*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1128*4882a593Smuzhiyun * Register 0x2109: MSTAT Counter Write Address 1129*4882a593Smuzhiyun * Bit 5-0 MSTAT_WRITE_ADDRESS 1130*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1131*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_MSTAT_WRITE_ADDRESS 0x003F 1132*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_MSTAT_WRITE_ADDRESS 0 1133*4882a593Smuzhiyun 1134*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1135*4882a593Smuzhiyun * Register 0x2200: IFLX Global Configuration Register 1136*4882a593Smuzhiyun * Bit 15 IFLX_IRCU_ENABLE 1137*4882a593Smuzhiyun * Bit 14 IFLX_IDSWT_ENABLE 1138*4882a593Smuzhiyun * Bit 13-0 IFLX_IFD_CNT 1139*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1140*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_IFLX_IRCU_ENABLE 0x8000 1141*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_IFLX_IDSWT_ENABLE 0x4000 1142*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_IFLX_IFD_CNT 0x3FFF 1143*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_IFLX_IFD_CNT 0 1144*4882a593Smuzhiyun 1145*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1146*4882a593Smuzhiyun * Register 0x2209: IFLX FIFO Overflow Enable 1147*4882a593Smuzhiyun * Bit 0 IFLX_OVFE 1148*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1149*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_IFLX_OVFE 0x0001 1150*4882a593Smuzhiyun 1151*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1152*4882a593Smuzhiyun * Register 0x220A: IFLX FIFO Overflow Interrupt 1153*4882a593Smuzhiyun * Bit 0 IFLX_OVFI 1154*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1155*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_IFLX_OVFI 0x0001 1156*4882a593Smuzhiyun 1157*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1158*4882a593Smuzhiyun * Register 0x220D: IFLX Indirect Channel Address 1159*4882a593Smuzhiyun * Bit 15 IFLX_BUSY 1160*4882a593Smuzhiyun * Bit 14 IFLX_RWB 1161*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1162*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_IFLX_BUSY 0x8000 1163*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_IFLX_RWB 0x4000 1164*4882a593Smuzhiyun 1165*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1166*4882a593Smuzhiyun * Register 0x220E: IFLX Indirect Logical FIFO Low Limit & Provision 1167*4882a593Smuzhiyun * Bit 9-0 IFLX_LOLIM 1168*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1169*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_IFLX_LOLIM 0x03FF 1170*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_IFLX_LOLIM 0 1171*4882a593Smuzhiyun 1172*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1173*4882a593Smuzhiyun * Register 0x220F: IFLX Indirect Logical FIFO High Limit 1174*4882a593Smuzhiyun * Bit 9-0 IFLX_HILIM 1175*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1176*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_IFLX_HILIM 0x03FF 1177*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_IFLX_HILIM 0 1178*4882a593Smuzhiyun 1179*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1180*4882a593Smuzhiyun * Register 0x2210: IFLX Indirect Full/Almost Full Status & Limit 1181*4882a593Smuzhiyun * Bit 15 IFLX_FULL 1182*4882a593Smuzhiyun * Bit 14 IFLX_AFULL 1183*4882a593Smuzhiyun * Bit 13-0 IFLX_AFTH 1184*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1185*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_IFLX_FULL 0x8000 1186*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_IFLX_AFULL 0x4000 1187*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_IFLX_AFTH 0x3FFF 1188*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_IFLX_AFTH 0 1189*4882a593Smuzhiyun 1190*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1191*4882a593Smuzhiyun * Register 0x2211: IFLX Indirect Empty/Almost Empty Status & Limit 1192*4882a593Smuzhiyun * Bit 15 IFLX_EMPTY 1193*4882a593Smuzhiyun * Bit 14 IFLX_AEMPTY 1194*4882a593Smuzhiyun * Bit 13-0 IFLX_AETH 1195*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1196*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_IFLX_EMPTY 0x8000 1197*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_IFLX_AEMPTY 0x4000 1198*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_IFLX_AETH 0x3FFF 1199*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_IFLX_AETH 0 1200*4882a593Smuzhiyun 1201*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1202*4882a593Smuzhiyun * Register 0x2240: PL4MOS Configuration Register 1203*4882a593Smuzhiyun * Bit 3 PL4MOS_RE_INIT 1204*4882a593Smuzhiyun * Bit 2 PL4MOS_EN 1205*4882a593Smuzhiyun * Bit 1 PL4MOS_NO_STATUS 1206*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1207*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4MOS_RE_INIT 0x0008 1208*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4MOS_EN 0x0004 1209*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4MOS_NO_STATUS 0x0002 1210*4882a593Smuzhiyun 1211*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1212*4882a593Smuzhiyun * Register 0x2243: PL4MOS MaxBurst1 Register 1213*4882a593Smuzhiyun * Bit 11-0 PL4MOS_MAX_BURST1 1214*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1215*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_BURST1 0x0FFF 1216*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST1 0 1217*4882a593Smuzhiyun 1218*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1219*4882a593Smuzhiyun * Register 0x2244: PL4MOS MaxBurst2 Register 1220*4882a593Smuzhiyun * Bit 11-0 PL4MOS_MAX_BURST2 1221*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1222*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_BURST2 0x0FFF 1223*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_BURST2 0 1224*4882a593Smuzhiyun 1225*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1226*4882a593Smuzhiyun * Register 0x2245: PL4MOS Transfer Size Register 1227*4882a593Smuzhiyun * Bit 7-0 PL4MOS_MAX_TRANSFER 1228*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1229*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4MOS_MAX_TRANSFER 0x00FF 1230*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_PL4MOS_MAX_TRANSFER 0 1231*4882a593Smuzhiyun 1232*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1233*4882a593Smuzhiyun * Register 0x2280: PL4ODP Configuration 1234*4882a593Smuzhiyun * Bit 15-12 PL4ODP_REPEAT_T 1235*4882a593Smuzhiyun * Bit 8 PL4ODP_SOP_RULE 1236*4882a593Smuzhiyun * Bit 1 PL4ODP_EN_PORTS 1237*4882a593Smuzhiyun * Bit 0 PL4ODP_EN_DFWD 1238*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1239*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4ODP_REPEAT_T 0xF000 1240*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_PL4ODP_REPEAT_T 12 1241*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4ODP_SOP_RULE 0x0100 1242*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4ODP_EN_PORTS 0x0002 1243*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4ODP_EN_DFWD 0x0001 1244*4882a593Smuzhiyun 1245*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1246*4882a593Smuzhiyun * Register 0x2282: PL4ODP Interrupt Mask 1247*4882a593Smuzhiyun * Bit 0 PL4ODP_OUT_DISE 1248*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1249*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4ODP_OUT_DISE 0x0001 1250*4882a593Smuzhiyun 1251*4882a593Smuzhiyun 1252*4882a593Smuzhiyun 1253*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_EOPEOBE 0x0080 1254*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_ERREOPE 0x0040 1255*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MEOPE 0x0008 1256*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MSOPE 0x0004 1257*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4ODP_ES_OVRE 0x0002 1258*4882a593Smuzhiyun 1259*4882a593Smuzhiyun 1260*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1261*4882a593Smuzhiyun * Register 0x2283: PL4ODP Interrupt 1262*4882a593Smuzhiyun * Bit 0 PL4ODP_OUT_DISI 1263*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1264*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4ODP_OUT_DISI 0x0001 1265*4882a593Smuzhiyun 1266*4882a593Smuzhiyun 1267*4882a593Smuzhiyun 1268*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_EOPEOBI 0x0080 1269*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_ERREOPI 0x0040 1270*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MEOPI 0x0008 1271*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4ODP_PPE_MSOPI 0x0004 1272*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4ODP_ES_OVRI 0x0002 1273*4882a593Smuzhiyun 1274*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1275*4882a593Smuzhiyun * Register 0x2300: PL4IO Lock Detect Status 1276*4882a593Smuzhiyun * Bit 15 PL4IO_OUT_ROOLV 1277*4882a593Smuzhiyun * Bit 12 PL4IO_IS_ROOLV 1278*4882a593Smuzhiyun * Bit 11 PL4IO_DIP2_ERRV 1279*4882a593Smuzhiyun * Bit 8 PL4IO_ID_ROOLV 1280*4882a593Smuzhiyun * Bit 4 PL4IO_IS_DOOLV 1281*4882a593Smuzhiyun * Bit 0 PL4IO_ID_DOOLV 1282*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1283*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLV 0x8000 1284*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLV 0x1000 1285*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRV 0x0800 1286*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLV 0x0100 1287*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLV 0x0010 1288*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLV 0x0001 1289*4882a593Smuzhiyun 1290*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1291*4882a593Smuzhiyun * Register 0x2301: PL4IO Lock Detect Change 1292*4882a593Smuzhiyun * Bit 15 PL4IO_OUT_ROOLI 1293*4882a593Smuzhiyun * Bit 12 PL4IO_IS_ROOLI 1294*4882a593Smuzhiyun * Bit 11 PL4IO_DIP2_ERRI 1295*4882a593Smuzhiyun * Bit 8 PL4IO_ID_ROOLI 1296*4882a593Smuzhiyun * Bit 4 PL4IO_IS_DOOLI 1297*4882a593Smuzhiyun * Bit 0 PL4IO_ID_DOOLI 1298*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1299*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLI 0x8000 1300*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLI 0x1000 1301*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRI 0x0800 1302*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLI 0x0100 1303*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLI 0x0010 1304*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLI 0x0001 1305*4882a593Smuzhiyun 1306*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1307*4882a593Smuzhiyun * Register 0x2302: PL4IO Lock Detect Mask 1308*4882a593Smuzhiyun * Bit 15 PL4IO_OUT_ROOLE 1309*4882a593Smuzhiyun * Bit 12 PL4IO_IS_ROOLE 1310*4882a593Smuzhiyun * Bit 11 PL4IO_DIP2_ERRE 1311*4882a593Smuzhiyun * Bit 8 PL4IO_ID_ROOLE 1312*4882a593Smuzhiyun * Bit 4 PL4IO_IS_DOOLE 1313*4882a593Smuzhiyun * Bit 0 PL4IO_ID_DOOLE 1314*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1315*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_ROOLE 0x8000 1316*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_IS_ROOLE 0x1000 1317*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERRE 0x0800 1318*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_ID_ROOLE 0x0100 1319*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_IS_DOOLE 0x0010 1320*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_ID_DOOLE 0x0001 1321*4882a593Smuzhiyun 1322*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1323*4882a593Smuzhiyun * Register 0x2303: PL4IO Lock Detect Limits 1324*4882a593Smuzhiyun * Bit 15-8 PL4IO_REF_LIMIT 1325*4882a593Smuzhiyun * Bit 7-0 PL4IO_TRAN_LIMIT 1326*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1327*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_REF_LIMIT 0xFF00 1328*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_PL4IO_REF_LIMIT 8 1329*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_TRAN_LIMIT 0x00FF 1330*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_PL4IO_TRAN_LIMIT 0 1331*4882a593Smuzhiyun 1332*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1333*4882a593Smuzhiyun * Register 0x2304: PL4IO Calendar Repetitions 1334*4882a593Smuzhiyun * Bit 15-8 PL4IO_IN_MUL 1335*4882a593Smuzhiyun * Bit 7-0 PL4IO_OUT_MUL 1336*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1337*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_IN_MUL 0xFF00 1338*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_PL4IO_IN_MUL 8 1339*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_OUT_MUL 0x00FF 1340*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_PL4IO_OUT_MUL 0 1341*4882a593Smuzhiyun 1342*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1343*4882a593Smuzhiyun * Register 0x2305: PL4IO Configuration 1344*4882a593Smuzhiyun * Bit 15 PL4IO_DIP2_ERR_CHK 1345*4882a593Smuzhiyun * Bit 11 PL4IO_ODAT_DIS 1346*4882a593Smuzhiyun * Bit 10 PL4IO_TRAIN_DIS 1347*4882a593Smuzhiyun * Bit 9 PL4IO_OSTAT_DIS 1348*4882a593Smuzhiyun * Bit 8 PL4IO_ISTAT_DIS 1349*4882a593Smuzhiyun * Bit 7 PL4IO_NO_ISTAT 1350*4882a593Smuzhiyun * Bit 6 PL4IO_STAT_OUTSEL 1351*4882a593Smuzhiyun * Bit 5 PL4IO_INSEL 1352*4882a593Smuzhiyun * Bit 4 PL4IO_DLSEL 1353*4882a593Smuzhiyun * Bit 1-0 PL4IO_OUTSEL 1354*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1355*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_DIP2_ERR_CHK 0x8000 1356*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_ODAT_DIS 0x0800 1357*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_TRAIN_DIS 0x0400 1358*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_OSTAT_DIS 0x0200 1359*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_ISTAT_DIS 0x0100 1360*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_NO_ISTAT 0x0080 1361*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_STAT_OUTSEL 0x0040 1362*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_INSEL 0x0020 1363*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_DLSEL 0x0010 1364*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IO_OUTSEL 0x0003 1365*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_PL4IO_OUTSEL 0 1366*4882a593Smuzhiyun 1367*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1368*4882a593Smuzhiyun * Register 0x3040: TXXG Configuration Register 1 1369*4882a593Smuzhiyun * Bit 15 TXXG_TXEN0 1370*4882a593Smuzhiyun * Bit 13 TXXG_HOSTPAUSE 1371*4882a593Smuzhiyun * Bit 12-7 TXXG_IPGT 1372*4882a593Smuzhiyun * Bit 5 TXXG_32BIT_ALIGN 1373*4882a593Smuzhiyun * Bit 4 TXXG_CRCEN 1374*4882a593Smuzhiyun * Bit 3 TXXG_FCTX 1375*4882a593Smuzhiyun * Bit 2 TXXG_FCRX 1376*4882a593Smuzhiyun * Bit 1 TXXG_PADEN 1377*4882a593Smuzhiyun * Bit 0 TXXG_SPRE 1378*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1379*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXXG_TXEN0 0x8000 1380*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXXG_HOSTPAUSE 0x2000 1381*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXXG_IPGT 0x1F80 1382*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_TXXG_IPGT 7 1383*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXXG_32BIT_ALIGN 0x0020 1384*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXXG_CRCEN 0x0010 1385*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXXG_FCTX 0x0008 1386*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXXG_FCRX 0x0004 1387*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXXG_PADEN 0x0002 1388*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXXG_SPRE 0x0001 1389*4882a593Smuzhiyun 1390*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1391*4882a593Smuzhiyun * Register 0x3041: TXXG Configuration Register 2 1392*4882a593Smuzhiyun * Bit 7-0 TXXG_HDRSIZE 1393*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1394*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXXG_HDRSIZE 0x00FF 1395*4882a593Smuzhiyun 1396*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1397*4882a593Smuzhiyun * Register 0x3042: TXXG Configuration Register 3 1398*4882a593Smuzhiyun * Bit 15 TXXG_FIFO_ERRE 1399*4882a593Smuzhiyun * Bit 14 TXXG_FIFO_UDRE 1400*4882a593Smuzhiyun * Bit 13 TXXG_MAX_LERRE 1401*4882a593Smuzhiyun * Bit 12 TXXG_MIN_LERRE 1402*4882a593Smuzhiyun * Bit 11 TXXG_XFERE 1403*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1404*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_ERRE 0x8000 1405*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_UDRE 0x4000 1406*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXXG_MAX_LERRE 0x2000 1407*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXXG_MIN_LERRE 0x1000 1408*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXXG_XFERE 0x0800 1409*4882a593Smuzhiyun 1410*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1411*4882a593Smuzhiyun * Register 0x3043: TXXG Interrupt 1412*4882a593Smuzhiyun * Bit 15 TXXG_FIFO_ERRI 1413*4882a593Smuzhiyun * Bit 14 TXXG_FIFO_UDRI 1414*4882a593Smuzhiyun * Bit 13 TXXG_MAX_LERRI 1415*4882a593Smuzhiyun * Bit 12 TXXG_MIN_LERRI 1416*4882a593Smuzhiyun * Bit 11 TXXG_XFERI 1417*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1418*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_ERRI 0x8000 1419*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXXG_FIFO_UDRI 0x4000 1420*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXXG_MAX_LERRI 0x2000 1421*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXXG_MIN_LERRI 0x1000 1422*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXXG_XFERI 0x0800 1423*4882a593Smuzhiyun 1424*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1425*4882a593Smuzhiyun * Register 0x3044: TXXG Status Register 1426*4882a593Smuzhiyun * Bit 1 TXXG_TXACTIVE 1427*4882a593Smuzhiyun * Bit 0 TXXG_PAUSED 1428*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1429*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXXG_TXACTIVE 0x0002 1430*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXXG_PAUSED 0x0001 1431*4882a593Smuzhiyun 1432*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1433*4882a593Smuzhiyun * Register 0x3046: TXXG TX_MINFR - Transmit Min Frame Size Register 1434*4882a593Smuzhiyun * Bit 7-0 TXXG_TX_MINFR 1435*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1436*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXXG_TX_MINFR 0x00FF 1437*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_TXXG_TX_MINFR 0 1438*4882a593Smuzhiyun 1439*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1440*4882a593Smuzhiyun * Register 0x3052: TXXG Pause Quantum Value Configuration Register 1441*4882a593Smuzhiyun * Bit 7-0 TXXG_FC_PAUSE_QNTM 1442*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1443*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXXG_FC_PAUSE_QNTM 0x00FF 1444*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_TXXG_FC_PAUSE_QNTM 0 1445*4882a593Smuzhiyun 1446*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1447*4882a593Smuzhiyun * Register 0x3080: XTEF Control 1448*4882a593Smuzhiyun * Bit 3-0 XTEF_FORCE_PARITY_ERR 1449*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1450*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_XTEF_FORCE_PARITY_ERR 0x000F 1451*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_XTEF_FORCE_PARITY_ERR 0 1452*4882a593Smuzhiyun 1453*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1454*4882a593Smuzhiyun * Register 0x3084: XTEF Interrupt Event Register 1455*4882a593Smuzhiyun * Bit 0 XTEF_LOST_SYNCI 1456*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1457*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCI 0x0001 1458*4882a593Smuzhiyun 1459*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1460*4882a593Smuzhiyun * Register 0x3085: XTEF Interrupt Enable Register 1461*4882a593Smuzhiyun * Bit 0 XTEF_LOST_SYNCE 1462*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1463*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCE 0x0001 1464*4882a593Smuzhiyun 1465*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1466*4882a593Smuzhiyun * Register 0x3086: XTEF Visibility Register 1467*4882a593Smuzhiyun * Bit 0 XTEF_LOST_SYNCV 1468*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1469*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_XTEF_LOST_SYNCV 0x0001 1470*4882a593Smuzhiyun 1471*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1472*4882a593Smuzhiyun * Register 0x30C0: TXOAM OAM Configuration 1473*4882a593Smuzhiyun * Bit 15 TXOAM_HEC_EN 1474*4882a593Smuzhiyun * Bit 14 TXOAM_EMPTYCODE_EN 1475*4882a593Smuzhiyun * Bit 13 TXOAM_FORCE_IDLE 1476*4882a593Smuzhiyun * Bit 12 TXOAM_IGNORE_IDLE 1477*4882a593Smuzhiyun * Bit 11-6 TXOAM_PX_OVERWRITE 1478*4882a593Smuzhiyun * Bit 5-0 TXOAM_PX_SEL 1479*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1480*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXOAM_HEC_EN 0x8000 1481*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXOAM_EMPTYCODE_EN 0x4000 1482*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXOAM_FORCE_IDLE 0x2000 1483*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXOAM_IGNORE_IDLE 0x1000 1484*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXOAM_PX_OVERWRITE 0x0FC0 1485*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_TXOAM_PX_OVERWRITE 6 1486*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXOAM_PX_SEL 0x003F 1487*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_TXOAM_PX_SEL 0 1488*4882a593Smuzhiyun 1489*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1490*4882a593Smuzhiyun * Register 0x30C1: TXOAM Mini-Packet Rate Configuration 1491*4882a593Smuzhiyun * Bit 15 TXOAM_MINIDIS 1492*4882a593Smuzhiyun * Bit 14 TXOAM_BUSY 1493*4882a593Smuzhiyun * Bit 13 TXOAM_TRANS_EN 1494*4882a593Smuzhiyun * Bit 10-0 TXOAM_MINIRATE 1495*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1496*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXOAM_MINIDIS 0x8000 1497*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXOAM_BUSY 0x4000 1498*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXOAM_TRANS_EN 0x2000 1499*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXOAM_MINIRATE 0x07FF 1500*4882a593Smuzhiyun 1501*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1502*4882a593Smuzhiyun * Register 0x30C2: TXOAM Mini-Packet Gap and FIFO Configuration 1503*4882a593Smuzhiyun * Bit 13-10 TXOAM_FTHRESH 1504*4882a593Smuzhiyun * Bit 9-6 TXOAM_MINIPOST 1505*4882a593Smuzhiyun * Bit 5-0 TXOAM_MINIPRE 1506*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1507*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXOAM_FTHRESH 0x3C00 1508*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_TXOAM_FTHRESH 10 1509*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXOAM_MINIPOST 0x03C0 1510*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_TXOAM_MINIPOST 6 1511*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXOAM_MINIPRE 0x003F 1512*4882a593Smuzhiyun 1513*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1514*4882a593Smuzhiyun * Register 0x30C6: TXOAM Interrupt Enable 1515*4882a593Smuzhiyun * Bit 2 TXOAM_SOP_ERRE 1516*4882a593Smuzhiyun * Bit 1 TXOAM_OFLE 1517*4882a593Smuzhiyun * Bit 0 TXOAM_ERRE 1518*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1519*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXOAM_SOP_ERRE 0x0004 1520*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXOAM_OFLE 0x0002 1521*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXOAM_ERRE 0x0001 1522*4882a593Smuzhiyun 1523*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1524*4882a593Smuzhiyun * Register 0x30C7: TXOAM Interrupt Status 1525*4882a593Smuzhiyun * Bit 2 TXOAM_SOP_ERRI 1526*4882a593Smuzhiyun * Bit 1 TXOAM_OFLI 1527*4882a593Smuzhiyun * Bit 0 TXOAM_ERRI 1528*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1529*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXOAM_SOP_ERRI 0x0004 1530*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXOAM_OFLI 0x0002 1531*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXOAM_ERRI 0x0001 1532*4882a593Smuzhiyun 1533*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1534*4882a593Smuzhiyun * Register 0x30CF: TXOAM Coset 1535*4882a593Smuzhiyun * Bit 7-0 TXOAM_COSET 1536*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1537*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_TXOAM_COSET 0x00FF 1538*4882a593Smuzhiyun 1539*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1540*4882a593Smuzhiyun * Register 0x3200: EFLX Global Configuration 1541*4882a593Smuzhiyun * Bit 15 EFLX_ERCU_EN 1542*4882a593Smuzhiyun * Bit 7 EFLX_EN_EDSWT 1543*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1544*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_EFLX_ERCU_EN 0x8000 1545*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_EFLX_EN_EDSWT 0x0080 1546*4882a593Smuzhiyun 1547*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1548*4882a593Smuzhiyun * Register 0x3201: EFLX ERCU Global Status 1549*4882a593Smuzhiyun * Bit 13 EFLX_OVF_ERR 1550*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1551*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_EFLX_OVF_ERR 0x2000 1552*4882a593Smuzhiyun 1553*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1554*4882a593Smuzhiyun * Register 0x3202: EFLX Indirect Channel Address 1555*4882a593Smuzhiyun * Bit 15 EFLX_BUSY 1556*4882a593Smuzhiyun * Bit 14 EFLX_RDWRB 1557*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1558*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_EFLX_BUSY 0x8000 1559*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_EFLX_RDWRB 0x4000 1560*4882a593Smuzhiyun 1561*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1562*4882a593Smuzhiyun * Register 0x3203: EFLX Indirect Logical FIFO Low Limit 1563*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1564*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_EFLX_LOLIM 0x03FF 1565*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_EFLX_LOLIM 0 1566*4882a593Smuzhiyun 1567*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1568*4882a593Smuzhiyun * Register 0x3204: EFLX Indirect Logical FIFO High Limit 1569*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1570*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_EFLX_HILIM 0x03FF 1571*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_EFLX_HILIM 0 1572*4882a593Smuzhiyun 1573*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1574*4882a593Smuzhiyun * Register 0x3205: EFLX Indirect Full/Almost-Full Status and Limit 1575*4882a593Smuzhiyun * Bit 15 EFLX_FULL 1576*4882a593Smuzhiyun * Bit 14 EFLX_AFULL 1577*4882a593Smuzhiyun * Bit 13-0 EFLX_AFTH 1578*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1579*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_EFLX_FULL 0x8000 1580*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_EFLX_AFULL 0x4000 1581*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_EFLX_AFTH 0x3FFF 1582*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_EFLX_AFTH 0 1583*4882a593Smuzhiyun 1584*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1585*4882a593Smuzhiyun * Register 0x3206: EFLX Indirect Empty/Almost-Empty Status and Limit 1586*4882a593Smuzhiyun * Bit 15 EFLX_EMPTY 1587*4882a593Smuzhiyun * Bit 14 EFLX_AEMPTY 1588*4882a593Smuzhiyun * Bit 13-0 EFLX_AETH 1589*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1590*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_EFLX_EMPTY 0x8000 1591*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_EFLX_AEMPTY 0x4000 1592*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_EFLX_AETH 0x3FFF 1593*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_EFLX_AETH 0 1594*4882a593Smuzhiyun 1595*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1596*4882a593Smuzhiyun * Register 0x3207: EFLX Indirect FIFO Cut-Through Threshold 1597*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1598*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_EFLX_CUT_THRU 0x3FFF 1599*4882a593Smuzhiyun #define SUNI1x10GEXP_BITOFF_EFLX_CUT_THRU 0 1600*4882a593Smuzhiyun 1601*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1602*4882a593Smuzhiyun * Register 0x320C: EFLX FIFO Overflow Error Enable 1603*4882a593Smuzhiyun * Bit 0 EFLX_OVFE 1604*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1605*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_EFLX_OVFE 0x0001 1606*4882a593Smuzhiyun 1607*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1608*4882a593Smuzhiyun * Register 0x320D: EFLX FIFO Overflow Error Indication 1609*4882a593Smuzhiyun * Bit 0 EFLX_OVFI 1610*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1611*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_EFLX_OVFI 0x0001 1612*4882a593Smuzhiyun 1613*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1614*4882a593Smuzhiyun * Register 0x3210: EFLX Channel Provision 1615*4882a593Smuzhiyun * Bit 0 EFLX_PROV 1616*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1617*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_EFLX_PROV 0x0001 1618*4882a593Smuzhiyun 1619*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1620*4882a593Smuzhiyun * Register 0x3280: PL4IDU Configuration 1621*4882a593Smuzhiyun * Bit 2 PL4IDU_SYNCH_ON_TRAIN 1622*4882a593Smuzhiyun * Bit 1 PL4IDU_EN_PORTS 1623*4882a593Smuzhiyun * Bit 0 PL4IDU_EN_DFWD 1624*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1625*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IDU_SYNCH_ON_TRAIN 0x0004 1626*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IDU_EN_PORTS 0x0002 1627*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IDU_EN_DFWD 0x0001 1628*4882a593Smuzhiyun 1629*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1630*4882a593Smuzhiyun * Register 0x3282: PL4IDU Interrupt Mask 1631*4882a593Smuzhiyun * Bit 1 PL4IDU_DIP4E 1632*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1633*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IDU_DIP4E 0x0002 1634*4882a593Smuzhiyun 1635*4882a593Smuzhiyun /*---------------------------------------------------------------------------- 1636*4882a593Smuzhiyun * Register 0x3283: PL4IDU Interrupt 1637*4882a593Smuzhiyun * Bit 1 PL4IDU_DIP4I 1638*4882a593Smuzhiyun *----------------------------------------------------------------------------*/ 1639*4882a593Smuzhiyun #define SUNI1x10GEXP_BITMSK_PL4IDU_DIP4I 0x0002 1640*4882a593Smuzhiyun 1641*4882a593Smuzhiyun #endif /* _CXGB_SUNI1x10GEXP_REGS_H_ */ 1642*4882a593Smuzhiyun 1643