1*4882a593Smuzhiyun /*****************************************************************************
2*4882a593Smuzhiyun * *
3*4882a593Smuzhiyun * File: cphy.h *
4*4882a593Smuzhiyun * $Revision: 1.7 $ *
5*4882a593Smuzhiyun * $Date: 2005/06/21 18:29:47 $ *
6*4882a593Smuzhiyun * Description: *
7*4882a593Smuzhiyun * part of the Chelsio 10Gb Ethernet Driver. *
8*4882a593Smuzhiyun * *
9*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify *
10*4882a593Smuzhiyun * it under the terms of the GNU General Public License, version 2, as *
11*4882a593Smuzhiyun * published by the Free Software Foundation. *
12*4882a593Smuzhiyun * *
13*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License along *
14*4882a593Smuzhiyun * with this program; if not, see <http://www.gnu.org/licenses/>. *
15*4882a593Smuzhiyun * *
16*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
17*4882a593Smuzhiyun * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
18*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
19*4882a593Smuzhiyun * *
20*4882a593Smuzhiyun * http://www.chelsio.com *
21*4882a593Smuzhiyun * *
22*4882a593Smuzhiyun * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
23*4882a593Smuzhiyun * All rights reserved. *
24*4882a593Smuzhiyun * *
25*4882a593Smuzhiyun * Maintainers: maintainers@chelsio.com *
26*4882a593Smuzhiyun * *
27*4882a593Smuzhiyun * Authors: Dimitrios Michailidis <dm@chelsio.com> *
28*4882a593Smuzhiyun * Tina Yang <tainay@chelsio.com> *
29*4882a593Smuzhiyun * Felix Marti <felix@chelsio.com> *
30*4882a593Smuzhiyun * Scott Bardone <sbardone@chelsio.com> *
31*4882a593Smuzhiyun * Kurt Ottaway <kottaway@chelsio.com> *
32*4882a593Smuzhiyun * Frank DiMambro <frank@chelsio.com> *
33*4882a593Smuzhiyun * *
34*4882a593Smuzhiyun * History: *
35*4882a593Smuzhiyun * *
36*4882a593Smuzhiyun ****************************************************************************/
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #ifndef _CXGB_CPHY_H_
39*4882a593Smuzhiyun #define _CXGB_CPHY_H_
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #include "common.h"
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun struct mdio_ops {
44*4882a593Smuzhiyun void (*init)(adapter_t *adapter, const struct board_info *bi);
45*4882a593Smuzhiyun int (*read)(struct net_device *dev, int phy_addr, int mmd_addr,
46*4882a593Smuzhiyun u16 reg_addr);
47*4882a593Smuzhiyun int (*write)(struct net_device *dev, int phy_addr, int mmd_addr,
48*4882a593Smuzhiyun u16 reg_addr, u16 val);
49*4882a593Smuzhiyun unsigned mode_support;
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* PHY interrupt types */
53*4882a593Smuzhiyun enum {
54*4882a593Smuzhiyun cphy_cause_link_change = 0x1,
55*4882a593Smuzhiyun cphy_cause_error = 0x2,
56*4882a593Smuzhiyun cphy_cause_fifo_error = 0x3
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun enum {
60*4882a593Smuzhiyun PHY_LINK_UP = 0x1,
61*4882a593Smuzhiyun PHY_AUTONEG_RDY = 0x2,
62*4882a593Smuzhiyun PHY_AUTONEG_EN = 0x4
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun struct cphy;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* PHY operations */
68*4882a593Smuzhiyun struct cphy_ops {
69*4882a593Smuzhiyun void (*destroy)(struct cphy *);
70*4882a593Smuzhiyun int (*reset)(struct cphy *, int wait);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun int (*interrupt_enable)(struct cphy *);
73*4882a593Smuzhiyun int (*interrupt_disable)(struct cphy *);
74*4882a593Smuzhiyun int (*interrupt_clear)(struct cphy *);
75*4882a593Smuzhiyun int (*interrupt_handler)(struct cphy *);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun int (*autoneg_enable)(struct cphy *);
78*4882a593Smuzhiyun int (*autoneg_disable)(struct cphy *);
79*4882a593Smuzhiyun int (*autoneg_restart)(struct cphy *);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun int (*advertise)(struct cphy *phy, unsigned int advertise_map);
82*4882a593Smuzhiyun int (*set_loopback)(struct cphy *, int on);
83*4882a593Smuzhiyun int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);
84*4882a593Smuzhiyun int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
85*4882a593Smuzhiyun int *duplex, int *fc);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun u32 mmds;
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /* A PHY instance */
91*4882a593Smuzhiyun struct cphy {
92*4882a593Smuzhiyun int state; /* Link status state machine */
93*4882a593Smuzhiyun adapter_t *adapter; /* associated adapter */
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun struct delayed_work phy_update;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun u16 bmsr;
98*4882a593Smuzhiyun int count;
99*4882a593Smuzhiyun int act_count;
100*4882a593Smuzhiyun int act_on;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun u32 elmer_gpo;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun const struct cphy_ops *ops; /* PHY operations */
105*4882a593Smuzhiyun struct mdio_if_info mdio;
106*4882a593Smuzhiyun struct cphy_instance *instance;
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* Convenience MDIO read/write wrappers */
cphy_mdio_read(struct cphy * cphy,int mmd,int reg,unsigned int * valp)110*4882a593Smuzhiyun static inline int cphy_mdio_read(struct cphy *cphy, int mmd, int reg,
111*4882a593Smuzhiyun unsigned int *valp)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun int rc = cphy->mdio.mdio_read(cphy->mdio.dev, cphy->mdio.prtad, mmd,
114*4882a593Smuzhiyun reg);
115*4882a593Smuzhiyun *valp = (rc >= 0) ? rc : -1;
116*4882a593Smuzhiyun return (rc >= 0) ? 0 : rc;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
cphy_mdio_write(struct cphy * cphy,int mmd,int reg,unsigned int val)119*4882a593Smuzhiyun static inline int cphy_mdio_write(struct cphy *cphy, int mmd, int reg,
120*4882a593Smuzhiyun unsigned int val)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun return cphy->mdio.mdio_write(cphy->mdio.dev, cphy->mdio.prtad, mmd,
123*4882a593Smuzhiyun reg, val);
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
simple_mdio_read(struct cphy * cphy,int reg,unsigned int * valp)126*4882a593Smuzhiyun static inline int simple_mdio_read(struct cphy *cphy, int reg,
127*4882a593Smuzhiyun unsigned int *valp)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun return cphy_mdio_read(cphy, MDIO_DEVAD_NONE, reg, valp);
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
simple_mdio_write(struct cphy * cphy,int reg,unsigned int val)132*4882a593Smuzhiyun static inline int simple_mdio_write(struct cphy *cphy, int reg,
133*4882a593Smuzhiyun unsigned int val)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun return cphy_mdio_write(cphy, MDIO_DEVAD_NONE, reg, val);
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun /* Convenience initializer */
cphy_init(struct cphy * phy,struct net_device * dev,int phy_addr,const struct cphy_ops * phy_ops,const struct mdio_ops * mdio_ops)139*4882a593Smuzhiyun static inline void cphy_init(struct cphy *phy, struct net_device *dev,
140*4882a593Smuzhiyun int phy_addr, const struct cphy_ops *phy_ops,
141*4882a593Smuzhiyun const struct mdio_ops *mdio_ops)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun struct adapter *adapter = netdev_priv(dev);
144*4882a593Smuzhiyun phy->adapter = adapter;
145*4882a593Smuzhiyun phy->ops = phy_ops;
146*4882a593Smuzhiyun if (mdio_ops) {
147*4882a593Smuzhiyun phy->mdio.prtad = phy_addr;
148*4882a593Smuzhiyun phy->mdio.mmds = phy_ops->mmds;
149*4882a593Smuzhiyun phy->mdio.mode_support = mdio_ops->mode_support;
150*4882a593Smuzhiyun phy->mdio.mdio_read = mdio_ops->read;
151*4882a593Smuzhiyun phy->mdio.mdio_write = mdio_ops->write;
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun phy->mdio.dev = dev;
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun /* Operations of the PHY-instance factory */
157*4882a593Smuzhiyun struct gphy {
158*4882a593Smuzhiyun /* Construct a PHY instance with the given PHY address */
159*4882a593Smuzhiyun struct cphy *(*create)(struct net_device *dev, int phy_addr,
160*4882a593Smuzhiyun const struct mdio_ops *mdio_ops);
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun /*
163*4882a593Smuzhiyun * Reset the PHY chip. This resets the whole PHY chip, not individual
164*4882a593Smuzhiyun * ports.
165*4882a593Smuzhiyun */
166*4882a593Smuzhiyun int (*reset)(adapter_t *adapter);
167*4882a593Smuzhiyun };
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun extern const struct gphy t1_my3126_ops;
170*4882a593Smuzhiyun extern const struct gphy t1_mv88e1xxx_ops;
171*4882a593Smuzhiyun extern const struct gphy t1_vsc8244_ops;
172*4882a593Smuzhiyun extern const struct gphy t1_mv88x201x_ops;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun #endif /* _CXGB_CPHY_H_ */
175