1*4882a593Smuzhiyun /*****************************************************************************
2*4882a593Smuzhiyun * *
3*4882a593Smuzhiyun * File: common.h *
4*4882a593Smuzhiyun * $Revision: 1.21 $ *
5*4882a593Smuzhiyun * $Date: 2005/06/22 00:43:25 $ *
6*4882a593Smuzhiyun * Description: *
7*4882a593Smuzhiyun * part of the Chelsio 10Gb Ethernet Driver. *
8*4882a593Smuzhiyun * *
9*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify *
10*4882a593Smuzhiyun * it under the terms of the GNU General Public License, version 2, as *
11*4882a593Smuzhiyun * published by the Free Software Foundation. *
12*4882a593Smuzhiyun * *
13*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License along *
14*4882a593Smuzhiyun * with this program; if not, see <http://www.gnu.org/licenses/>. *
15*4882a593Smuzhiyun * *
16*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
17*4882a593Smuzhiyun * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
18*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
19*4882a593Smuzhiyun * *
20*4882a593Smuzhiyun * http://www.chelsio.com *
21*4882a593Smuzhiyun * *
22*4882a593Smuzhiyun * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
23*4882a593Smuzhiyun * All rights reserved. *
24*4882a593Smuzhiyun * *
25*4882a593Smuzhiyun * Maintainers: maintainers@chelsio.com *
26*4882a593Smuzhiyun * *
27*4882a593Smuzhiyun * Authors: Dimitrios Michailidis <dm@chelsio.com> *
28*4882a593Smuzhiyun * Tina Yang <tainay@chelsio.com> *
29*4882a593Smuzhiyun * Felix Marti <felix@chelsio.com> *
30*4882a593Smuzhiyun * Scott Bardone <sbardone@chelsio.com> *
31*4882a593Smuzhiyun * Kurt Ottaway <kottaway@chelsio.com> *
32*4882a593Smuzhiyun * Frank DiMambro <frank@chelsio.com> *
33*4882a593Smuzhiyun * *
34*4882a593Smuzhiyun * History: *
35*4882a593Smuzhiyun * *
36*4882a593Smuzhiyun ****************************************************************************/
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #define pr_fmt(fmt) "cxgb: " fmt
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #ifndef _CXGB_COMMON_H_
41*4882a593Smuzhiyun #define _CXGB_COMMON_H_
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #include <linux/module.h>
44*4882a593Smuzhiyun #include <linux/netdevice.h>
45*4882a593Smuzhiyun #include <linux/types.h>
46*4882a593Smuzhiyun #include <linux/delay.h>
47*4882a593Smuzhiyun #include <linux/pci.h>
48*4882a593Smuzhiyun #include <linux/ethtool.h>
49*4882a593Smuzhiyun #include <linux/if_vlan.h>
50*4882a593Smuzhiyun #include <linux/mdio.h>
51*4882a593Smuzhiyun #include <linux/crc32.h>
52*4882a593Smuzhiyun #include <linux/slab.h>
53*4882a593Smuzhiyun #include <asm/io.h>
54*4882a593Smuzhiyun #include <linux/pci_ids.h>
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun #define DRV_DESCRIPTION "Chelsio 10Gb Ethernet Driver"
57*4882a593Smuzhiyun #define DRV_NAME "cxgb"
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun #define CH_DEVICE(devid, ssid, idx) \
60*4882a593Smuzhiyun { PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, ssid, 0, 0, idx }
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun #define SUPPORTED_PAUSE (1 << 13)
63*4882a593Smuzhiyun #define SUPPORTED_LOOPBACK (1 << 15)
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun #define ADVERTISED_PAUSE (1 << 13)
66*4882a593Smuzhiyun #define ADVERTISED_ASYM_PAUSE (1 << 14)
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun typedef struct adapter adapter_t;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun struct t1_rx_mode {
71*4882a593Smuzhiyun struct net_device *dev;
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun #define t1_rx_mode_promisc(rm) (rm->dev->flags & IFF_PROMISC)
75*4882a593Smuzhiyun #define t1_rx_mode_allmulti(rm) (rm->dev->flags & IFF_ALLMULTI)
76*4882a593Smuzhiyun #define t1_rx_mode_mc_cnt(rm) (netdev_mc_count(rm->dev))
77*4882a593Smuzhiyun #define t1_get_netdev(rm) (rm->dev)
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun #define MAX_NPORTS 4
80*4882a593Smuzhiyun #define PORT_MASK ((1 << MAX_NPORTS) - 1)
81*4882a593Smuzhiyun #define NMTUS 8
82*4882a593Smuzhiyun #define TCB_SIZE 128
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun #define SPEED_INVALID 0xffff
85*4882a593Smuzhiyun #define DUPLEX_INVALID 0xff
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* Max frame size PM3393 can handle. Includes Ethernet header and CRC. */
88*4882a593Smuzhiyun #define PM3393_MAX_FRAME_SIZE 9600
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun #define VSC7326_MAX_MTU 9600
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun enum {
93*4882a593Smuzhiyun CHBT_BOARD_N110,
94*4882a593Smuzhiyun CHBT_BOARD_N210,
95*4882a593Smuzhiyun CHBT_BOARD_7500,
96*4882a593Smuzhiyun CHBT_BOARD_8000,
97*4882a593Smuzhiyun CHBT_BOARD_CHT101,
98*4882a593Smuzhiyun CHBT_BOARD_CHT110,
99*4882a593Smuzhiyun CHBT_BOARD_CHT210,
100*4882a593Smuzhiyun CHBT_BOARD_CHT204,
101*4882a593Smuzhiyun CHBT_BOARD_CHT204V,
102*4882a593Smuzhiyun CHBT_BOARD_CHT204E,
103*4882a593Smuzhiyun CHBT_BOARD_CHN204,
104*4882a593Smuzhiyun CHBT_BOARD_COUGAR,
105*4882a593Smuzhiyun CHBT_BOARD_6800,
106*4882a593Smuzhiyun CHBT_BOARD_SIMUL,
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun enum {
110*4882a593Smuzhiyun CHBT_TERM_FPGA,
111*4882a593Smuzhiyun CHBT_TERM_T1,
112*4882a593Smuzhiyun CHBT_TERM_T2,
113*4882a593Smuzhiyun CHBT_TERM_T3
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun enum {
117*4882a593Smuzhiyun CHBT_MAC_CHELSIO_A,
118*4882a593Smuzhiyun CHBT_MAC_IXF1010,
119*4882a593Smuzhiyun CHBT_MAC_PM3393,
120*4882a593Smuzhiyun CHBT_MAC_VSC7321,
121*4882a593Smuzhiyun CHBT_MAC_DUMMY
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun enum {
125*4882a593Smuzhiyun CHBT_PHY_88E1041,
126*4882a593Smuzhiyun CHBT_PHY_88E1111,
127*4882a593Smuzhiyun CHBT_PHY_88X2010,
128*4882a593Smuzhiyun CHBT_PHY_XPAK,
129*4882a593Smuzhiyun CHBT_PHY_MY3126,
130*4882a593Smuzhiyun CHBT_PHY_8244,
131*4882a593Smuzhiyun CHBT_PHY_DUMMY
132*4882a593Smuzhiyun };
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun enum {
135*4882a593Smuzhiyun PAUSE_RX = 1 << 0,
136*4882a593Smuzhiyun PAUSE_TX = 1 << 1,
137*4882a593Smuzhiyun PAUSE_AUTONEG = 1 << 2
138*4882a593Smuzhiyun };
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun /* Revisions of T1 chip */
141*4882a593Smuzhiyun enum {
142*4882a593Smuzhiyun TERM_T1A = 0,
143*4882a593Smuzhiyun TERM_T1B = 1,
144*4882a593Smuzhiyun TERM_T2 = 3
145*4882a593Smuzhiyun };
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun struct sge_params {
148*4882a593Smuzhiyun unsigned int cmdQ_size[2];
149*4882a593Smuzhiyun unsigned int freelQ_size[2];
150*4882a593Smuzhiyun unsigned int large_buf_capacity;
151*4882a593Smuzhiyun unsigned int rx_coalesce_usecs;
152*4882a593Smuzhiyun unsigned int last_rx_coalesce_raw;
153*4882a593Smuzhiyun unsigned int default_rx_coalesce_usecs;
154*4882a593Smuzhiyun unsigned int sample_interval_usecs;
155*4882a593Smuzhiyun unsigned int coalesce_enable;
156*4882a593Smuzhiyun unsigned int polling;
157*4882a593Smuzhiyun };
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun struct chelsio_pci_params {
160*4882a593Smuzhiyun unsigned short speed;
161*4882a593Smuzhiyun unsigned char width;
162*4882a593Smuzhiyun unsigned char is_pcix;
163*4882a593Smuzhiyun };
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun struct tp_params {
166*4882a593Smuzhiyun unsigned int pm_size;
167*4882a593Smuzhiyun unsigned int cm_size;
168*4882a593Smuzhiyun unsigned int pm_rx_base;
169*4882a593Smuzhiyun unsigned int pm_tx_base;
170*4882a593Smuzhiyun unsigned int pm_rx_pg_size;
171*4882a593Smuzhiyun unsigned int pm_tx_pg_size;
172*4882a593Smuzhiyun unsigned int pm_rx_num_pgs;
173*4882a593Smuzhiyun unsigned int pm_tx_num_pgs;
174*4882a593Smuzhiyun unsigned int rx_coalescing_size;
175*4882a593Smuzhiyun unsigned int use_5tuple_mode;
176*4882a593Smuzhiyun };
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun struct mc5_params {
179*4882a593Smuzhiyun unsigned int mode; /* selects MC5 width */
180*4882a593Smuzhiyun unsigned int nservers; /* size of server region */
181*4882a593Smuzhiyun unsigned int nroutes; /* size of routing region */
182*4882a593Smuzhiyun };
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun /* Default MC5 region sizes */
185*4882a593Smuzhiyun #define DEFAULT_SERVER_REGION_LEN 256
186*4882a593Smuzhiyun #define DEFAULT_RT_REGION_LEN 1024
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun struct adapter_params {
189*4882a593Smuzhiyun struct sge_params sge;
190*4882a593Smuzhiyun struct mc5_params mc5;
191*4882a593Smuzhiyun struct tp_params tp;
192*4882a593Smuzhiyun struct chelsio_pci_params pci;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun const struct board_info *brd_info;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun unsigned short mtus[NMTUS];
197*4882a593Smuzhiyun unsigned int nports; /* # of ethernet ports */
198*4882a593Smuzhiyun unsigned int stats_update_period;
199*4882a593Smuzhiyun unsigned short chip_revision;
200*4882a593Smuzhiyun unsigned char chip_version;
201*4882a593Smuzhiyun unsigned char is_asic;
202*4882a593Smuzhiyun unsigned char has_msi;
203*4882a593Smuzhiyun };
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun struct link_config {
206*4882a593Smuzhiyun unsigned int supported; /* link capabilities */
207*4882a593Smuzhiyun unsigned int advertising; /* advertised capabilities */
208*4882a593Smuzhiyun unsigned short requested_speed; /* speed user has requested */
209*4882a593Smuzhiyun unsigned short speed; /* actual link speed */
210*4882a593Smuzhiyun unsigned char requested_duplex; /* duplex user has requested */
211*4882a593Smuzhiyun unsigned char duplex; /* actual link duplex */
212*4882a593Smuzhiyun unsigned char requested_fc; /* flow control user has requested */
213*4882a593Smuzhiyun unsigned char fc; /* actual link flow control */
214*4882a593Smuzhiyun unsigned char autoneg; /* autonegotiating? */
215*4882a593Smuzhiyun };
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun struct cmac;
218*4882a593Smuzhiyun struct cphy;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun struct port_info {
221*4882a593Smuzhiyun struct net_device *dev;
222*4882a593Smuzhiyun struct cmac *mac;
223*4882a593Smuzhiyun struct cphy *phy;
224*4882a593Smuzhiyun struct link_config link_config;
225*4882a593Smuzhiyun };
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun struct sge;
228*4882a593Smuzhiyun struct peespi;
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun struct adapter {
231*4882a593Smuzhiyun u8 __iomem *regs;
232*4882a593Smuzhiyun struct pci_dev *pdev;
233*4882a593Smuzhiyun unsigned long registered_device_map;
234*4882a593Smuzhiyun unsigned long open_device_map;
235*4882a593Smuzhiyun unsigned long flags;
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun const char *name;
238*4882a593Smuzhiyun int msg_enable;
239*4882a593Smuzhiyun u32 mmio_len;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun struct work_struct ext_intr_handler_task;
242*4882a593Smuzhiyun struct adapter_params params;
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun /* Terminator modules. */
245*4882a593Smuzhiyun struct sge *sge;
246*4882a593Smuzhiyun struct peespi *espi;
247*4882a593Smuzhiyun struct petp *tp;
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun struct napi_struct napi;
250*4882a593Smuzhiyun struct port_info port[MAX_NPORTS];
251*4882a593Smuzhiyun struct delayed_work stats_update_task;
252*4882a593Smuzhiyun struct timer_list stats_update_timer;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun spinlock_t tpi_lock;
255*4882a593Smuzhiyun spinlock_t work_lock;
256*4882a593Smuzhiyun spinlock_t mac_lock;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun /* guards async operations */
259*4882a593Smuzhiyun spinlock_t async_lock ____cacheline_aligned;
260*4882a593Smuzhiyun u32 slow_intr_mask;
261*4882a593Smuzhiyun int t1powersave;
262*4882a593Smuzhiyun };
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun enum { /* adapter flags */
265*4882a593Smuzhiyun FULL_INIT_DONE = 1 << 0,
266*4882a593Smuzhiyun };
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun struct mdio_ops;
269*4882a593Smuzhiyun struct gmac;
270*4882a593Smuzhiyun struct gphy;
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun struct board_info {
273*4882a593Smuzhiyun unsigned char board;
274*4882a593Smuzhiyun unsigned char port_number;
275*4882a593Smuzhiyun unsigned long caps;
276*4882a593Smuzhiyun unsigned char chip_term;
277*4882a593Smuzhiyun unsigned char chip_mac;
278*4882a593Smuzhiyun unsigned char chip_phy;
279*4882a593Smuzhiyun unsigned int clock_core;
280*4882a593Smuzhiyun unsigned int clock_mc3;
281*4882a593Smuzhiyun unsigned int clock_mc4;
282*4882a593Smuzhiyun unsigned int espi_nports;
283*4882a593Smuzhiyun unsigned int clock_elmer0;
284*4882a593Smuzhiyun unsigned char mdio_mdien;
285*4882a593Smuzhiyun unsigned char mdio_mdiinv;
286*4882a593Smuzhiyun unsigned char mdio_mdc;
287*4882a593Smuzhiyun unsigned char mdio_phybaseaddr;
288*4882a593Smuzhiyun const struct gmac *gmac;
289*4882a593Smuzhiyun const struct gphy *gphy;
290*4882a593Smuzhiyun const struct mdio_ops *mdio_ops;
291*4882a593Smuzhiyun const char *desc;
292*4882a593Smuzhiyun };
293*4882a593Smuzhiyun
t1_is_asic(const adapter_t * adapter)294*4882a593Smuzhiyun static inline int t1_is_asic(const adapter_t *adapter)
295*4882a593Smuzhiyun {
296*4882a593Smuzhiyun return adapter->params.is_asic;
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun extern const struct pci_device_id t1_pci_tbl[];
300*4882a593Smuzhiyun
adapter_matches_type(const adapter_t * adapter,int version,int revision)301*4882a593Smuzhiyun static inline int adapter_matches_type(const adapter_t *adapter,
302*4882a593Smuzhiyun int version, int revision)
303*4882a593Smuzhiyun {
304*4882a593Smuzhiyun return adapter->params.chip_version == version &&
305*4882a593Smuzhiyun adapter->params.chip_revision == revision;
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun #define t1_is_T1B(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1B)
309*4882a593Smuzhiyun #define is_T2(adap) adapter_matches_type(adap, CHBT_TERM_T2, TERM_T2)
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun /* Returns true if an adapter supports VLAN acceleration and TSO */
vlan_tso_capable(const adapter_t * adapter)312*4882a593Smuzhiyun static inline int vlan_tso_capable(const adapter_t *adapter)
313*4882a593Smuzhiyun {
314*4882a593Smuzhiyun return !t1_is_T1B(adapter);
315*4882a593Smuzhiyun }
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun #define for_each_port(adapter, iter) \
318*4882a593Smuzhiyun for (iter = 0; iter < (adapter)->params.nports; ++iter)
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun #define board_info(adapter) ((adapter)->params.brd_info)
321*4882a593Smuzhiyun #define is_10G(adapter) (board_info(adapter)->caps & SUPPORTED_10000baseT_Full)
322*4882a593Smuzhiyun
core_ticks_per_usec(const adapter_t * adap)323*4882a593Smuzhiyun static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
324*4882a593Smuzhiyun {
325*4882a593Smuzhiyun return board_info(adap)->clock_core / 1000000;
326*4882a593Smuzhiyun }
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp);
329*4882a593Smuzhiyun int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
330*4882a593Smuzhiyun int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
331*4882a593Smuzhiyun int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *value);
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun void t1_interrupts_enable(adapter_t *adapter);
334*4882a593Smuzhiyun void t1_interrupts_disable(adapter_t *adapter);
335*4882a593Smuzhiyun void t1_interrupts_clear(adapter_t *adapter);
336*4882a593Smuzhiyun int t1_elmer0_ext_intr_handler(adapter_t *adapter);
337*4882a593Smuzhiyun void t1_elmer0_ext_intr(adapter_t *adapter);
338*4882a593Smuzhiyun int t1_slow_intr_handler(adapter_t *adapter);
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
341*4882a593Smuzhiyun const struct board_info *t1_get_board_info(unsigned int board_id);
342*4882a593Smuzhiyun const struct board_info *t1_get_board_info_from_ids(unsigned int devid,
343*4882a593Smuzhiyun unsigned short ssid);
344*4882a593Smuzhiyun int t1_seeprom_read(adapter_t *adapter, u32 addr, __le32 *data);
345*4882a593Smuzhiyun int t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
346*4882a593Smuzhiyun struct adapter_params *p);
347*4882a593Smuzhiyun int t1_init_hw_modules(adapter_t *adapter);
348*4882a593Smuzhiyun int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi);
349*4882a593Smuzhiyun void t1_free_sw_modules(adapter_t *adapter);
350*4882a593Smuzhiyun void t1_fatal_err(adapter_t *adapter);
351*4882a593Smuzhiyun void t1_link_changed(adapter_t *adapter, int port_id);
352*4882a593Smuzhiyun void t1_link_negotiated(adapter_t *adapter, int port_id, int link_stat,
353*4882a593Smuzhiyun int speed, int duplex, int pause);
354*4882a593Smuzhiyun #endif /* _CXGB_COMMON_H_ */
355