xref: /OK3568_Linux_fs/kernel/drivers/net/ethernet/cavium/liquidio/octeon_main.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /**********************************************************************
2*4882a593Smuzhiyun  * Author: Cavium, Inc.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Contact: support@cavium.com
5*4882a593Smuzhiyun  *          Please include "LiquidIO" in the subject.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Copyright (c) 2003-2016 Cavium, Inc.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * This file is free software; you can redistribute it and/or modify
10*4882a593Smuzhiyun  * it under the terms of the GNU General Public License, Version 2, as
11*4882a593Smuzhiyun  * published by the Free Software Foundation.
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  * This file is distributed in the hope that it will be useful, but
14*4882a593Smuzhiyun  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15*4882a593Smuzhiyun  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16*4882a593Smuzhiyun  * NONINFRINGEMENT.  See the GNU General Public License for more details.
17*4882a593Smuzhiyun  ***********************************************************************/
18*4882a593Smuzhiyun /*! \file octeon_main.h
19*4882a593Smuzhiyun  *  \brief Host Driver: This file is included by all host driver source files
20*4882a593Smuzhiyun  *  to include common definitions.
21*4882a593Smuzhiyun  */
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #ifndef _OCTEON_MAIN_H_
24*4882a593Smuzhiyun #define  _OCTEON_MAIN_H_
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #include <linux/sched/signal.h>
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #if BITS_PER_LONG == 32
29*4882a593Smuzhiyun #define CVM_CAST64(v) ((long long)(v))
30*4882a593Smuzhiyun #elif BITS_PER_LONG == 64
31*4882a593Smuzhiyun #define CVM_CAST64(v) ((long long)(long)(v))
32*4882a593Smuzhiyun #else
33*4882a593Smuzhiyun #error "Unknown system architecture"
34*4882a593Smuzhiyun #endif
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define DRV_NAME "LiquidIO"
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun struct octeon_device_priv {
39*4882a593Smuzhiyun 	/** Tasklet structures for this device. */
40*4882a593Smuzhiyun 	struct tasklet_struct droq_tasklet;
41*4882a593Smuzhiyun 	unsigned long napi_mask;
42*4882a593Smuzhiyun 	struct octeon_device *dev;
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun /** This structure is used by NIC driver to store information required
46*4882a593Smuzhiyun  * to free the sk_buff when the packet has been fetched by Octeon.
47*4882a593Smuzhiyun  * Bytes offset below assume worst-case of a 64-bit system.
48*4882a593Smuzhiyun  */
49*4882a593Smuzhiyun struct octnet_buf_free_info {
50*4882a593Smuzhiyun 	/** Bytes 1-8.  Pointer to network device private structure. */
51*4882a593Smuzhiyun 	struct lio *lio;
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun 	/** Bytes 9-16.  Pointer to sk_buff. */
54*4882a593Smuzhiyun 	struct sk_buff *skb;
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun 	/** Bytes 17-24.  Pointer to gather list. */
57*4882a593Smuzhiyun 	struct octnic_gather *g;
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 	/** Bytes 25-32. Physical address of skb->data or gather list. */
60*4882a593Smuzhiyun 	u64 dptr;
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	/** Bytes 33-47. Piggybacked soft command, if any */
63*4882a593Smuzhiyun 	struct octeon_soft_command *sc;
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun /* BQL-related functions */
67*4882a593Smuzhiyun int octeon_report_sent_bytes_to_bql(void *buf, int reqtype);
68*4882a593Smuzhiyun void octeon_update_tx_completion_counters(void *buf, int reqtype,
69*4882a593Smuzhiyun 					  unsigned int *pkts_compl,
70*4882a593Smuzhiyun 					  unsigned int *bytes_compl);
71*4882a593Smuzhiyun void octeon_report_tx_completion_to_bql(void *txq, unsigned int pkts_compl,
72*4882a593Smuzhiyun 					unsigned int bytes_compl);
73*4882a593Smuzhiyun void octeon_pf_changed_vf_macaddr(struct octeon_device *oct, u8 *mac);
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun void octeon_schedule_rxq_oom_work(struct octeon_device *oct,
76*4882a593Smuzhiyun 				  struct octeon_droq *droq);
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun /** Swap 8B blocks */
octeon_swap_8B_data(u64 * data,u32 blocks)79*4882a593Smuzhiyun static inline void octeon_swap_8B_data(u64 *data, u32 blocks)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun 	while (blocks) {
82*4882a593Smuzhiyun 		cpu_to_be64s(data);
83*4882a593Smuzhiyun 		blocks--;
84*4882a593Smuzhiyun 		data++;
85*4882a593Smuzhiyun 	}
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun /**
89*4882a593Smuzhiyun  * \brief unmaps a PCI BAR
90*4882a593Smuzhiyun  * @param oct Pointer to Octeon device
91*4882a593Smuzhiyun  * @param baridx bar index
92*4882a593Smuzhiyun  */
octeon_unmap_pci_barx(struct octeon_device * oct,int baridx)93*4882a593Smuzhiyun static inline void octeon_unmap_pci_barx(struct octeon_device *oct, int baridx)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun 	dev_dbg(&oct->pci_dev->dev, "Freeing PCI mapped regions for Bar%d\n",
96*4882a593Smuzhiyun 		baridx);
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	if (oct->mmio[baridx].done)
99*4882a593Smuzhiyun 		iounmap(oct->mmio[baridx].hw_addr);
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	if (oct->mmio[baridx].start)
102*4882a593Smuzhiyun 		pci_release_region(oct->pci_dev, baridx * 2);
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun /**
106*4882a593Smuzhiyun  * \brief maps a PCI BAR
107*4882a593Smuzhiyun  * @param oct Pointer to Octeon device
108*4882a593Smuzhiyun  * @param baridx bar index
109*4882a593Smuzhiyun  * @param max_map_len maximum length of mapped memory
110*4882a593Smuzhiyun  */
octeon_map_pci_barx(struct octeon_device * oct,int baridx,int max_map_len)111*4882a593Smuzhiyun static inline int octeon_map_pci_barx(struct octeon_device *oct,
112*4882a593Smuzhiyun 				      int baridx, int max_map_len)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun 	u32 mapped_len = 0;
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	if (pci_request_region(oct->pci_dev, baridx * 2, DRV_NAME)) {
117*4882a593Smuzhiyun 		dev_err(&oct->pci_dev->dev, "pci_request_region failed for bar %d\n",
118*4882a593Smuzhiyun 			baridx);
119*4882a593Smuzhiyun 		return 1;
120*4882a593Smuzhiyun 	}
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	oct->mmio[baridx].start = pci_resource_start(oct->pci_dev, baridx * 2);
123*4882a593Smuzhiyun 	oct->mmio[baridx].len = pci_resource_len(oct->pci_dev, baridx * 2);
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	mapped_len = oct->mmio[baridx].len;
126*4882a593Smuzhiyun 	if (!mapped_len)
127*4882a593Smuzhiyun 		goto err_release_region;
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	if (max_map_len && (mapped_len > max_map_len))
130*4882a593Smuzhiyun 		mapped_len = max_map_len;
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	oct->mmio[baridx].hw_addr =
133*4882a593Smuzhiyun 		ioremap(oct->mmio[baridx].start, mapped_len);
134*4882a593Smuzhiyun 	oct->mmio[baridx].mapped_len = mapped_len;
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	dev_dbg(&oct->pci_dev->dev, "BAR%d start: 0x%llx mapped %u of %u bytes\n",
137*4882a593Smuzhiyun 		baridx, oct->mmio[baridx].start, mapped_len,
138*4882a593Smuzhiyun 		oct->mmio[baridx].len);
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	if (!oct->mmio[baridx].hw_addr) {
141*4882a593Smuzhiyun 		dev_err(&oct->pci_dev->dev, "error ioremap for bar %d\n",
142*4882a593Smuzhiyun 			baridx);
143*4882a593Smuzhiyun 		goto err_release_region;
144*4882a593Smuzhiyun 	}
145*4882a593Smuzhiyun 	oct->mmio[baridx].done = 1;
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	return 0;
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun err_release_region:
150*4882a593Smuzhiyun 	pci_release_region(oct->pci_dev, baridx * 2);
151*4882a593Smuzhiyun 	return 1;
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun /* input parameter:
155*4882a593Smuzhiyun  * sc: pointer to a soft request
156*4882a593Smuzhiyun  * timeout: milli sec which an application wants to wait for the
157*4882a593Smuzhiyun 	    response of the request.
158*4882a593Smuzhiyun  *          0: the request will wait until its response gets back
159*4882a593Smuzhiyun  *	       from the firmware within LIO_SC_MAX_TMO_MS milli sec.
160*4882a593Smuzhiyun  *	       It the response does not return within
161*4882a593Smuzhiyun  *	       LIO_SC_MAX_TMO_MS milli sec, lio_process_ordered_list()
162*4882a593Smuzhiyun  *	       will move the request to zombie response list.
163*4882a593Smuzhiyun  *
164*4882a593Smuzhiyun  * return value:
165*4882a593Smuzhiyun  * 0: got the response from firmware for the sc request.
166*4882a593Smuzhiyun  * errno -EINTR: user abort the command.
167*4882a593Smuzhiyun  * errno -ETIME: user spefified timeout value has been expired.
168*4882a593Smuzhiyun  * errno -EBUSY: the response of the request does not return in
169*4882a593Smuzhiyun  *               resonable time (LIO_SC_MAX_TMO_MS).
170*4882a593Smuzhiyun  *               the sc wll be move to zombie response list by
171*4882a593Smuzhiyun  *               lio_process_ordered_list()
172*4882a593Smuzhiyun  *
173*4882a593Smuzhiyun  * A request with non-zero return value, the sc->caller_is_done
174*4882a593Smuzhiyun  *  will be marked 1.
175*4882a593Smuzhiyun  * When getting a request with zero return value, the requestor
176*4882a593Smuzhiyun  *  should mark sc->caller_is_done with 1 after examing the
177*4882a593Smuzhiyun  *  response of sc.
178*4882a593Smuzhiyun  * lio_process_ordered_list() will free the soft command on behalf
179*4882a593Smuzhiyun  * of the soft command requestor.
180*4882a593Smuzhiyun  * This is to fix the possible race condition of both timeout process
181*4882a593Smuzhiyun  * and lio_process_ordered_list()/callback function to free a
182*4882a593Smuzhiyun  * sc strucutre.
183*4882a593Smuzhiyun  */
184*4882a593Smuzhiyun static inline int
wait_for_sc_completion_timeout(struct octeon_device * oct_dev,struct octeon_soft_command * sc,unsigned long timeout)185*4882a593Smuzhiyun wait_for_sc_completion_timeout(struct octeon_device *oct_dev,
186*4882a593Smuzhiyun 			       struct octeon_soft_command *sc,
187*4882a593Smuzhiyun 			       unsigned long timeout)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun 	int errno = 0;
190*4882a593Smuzhiyun 	long timeout_jiff;
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	if (timeout)
193*4882a593Smuzhiyun 		timeout_jiff = msecs_to_jiffies(timeout);
194*4882a593Smuzhiyun 	else
195*4882a593Smuzhiyun 		timeout_jiff = MAX_SCHEDULE_TIMEOUT;
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	timeout_jiff =
198*4882a593Smuzhiyun 		wait_for_completion_interruptible_timeout(&sc->complete,
199*4882a593Smuzhiyun 							  timeout_jiff);
200*4882a593Smuzhiyun 	if (timeout_jiff == 0) {
201*4882a593Smuzhiyun 		dev_err(&oct_dev->pci_dev->dev, "%s: sc is timeout\n",
202*4882a593Smuzhiyun 			__func__);
203*4882a593Smuzhiyun 		WRITE_ONCE(sc->caller_is_done, true);
204*4882a593Smuzhiyun 		errno = -ETIME;
205*4882a593Smuzhiyun 	} else if (timeout_jiff == -ERESTARTSYS) {
206*4882a593Smuzhiyun 		dev_err(&oct_dev->pci_dev->dev, "%s: sc is interrupted\n",
207*4882a593Smuzhiyun 			__func__);
208*4882a593Smuzhiyun 		WRITE_ONCE(sc->caller_is_done, true);
209*4882a593Smuzhiyun 		errno = -EINTR;
210*4882a593Smuzhiyun 	} else  if (sc->sc_status == OCTEON_REQUEST_TIMEOUT) {
211*4882a593Smuzhiyun 		dev_err(&oct_dev->pci_dev->dev, "%s: sc has fatal timeout\n",
212*4882a593Smuzhiyun 			__func__);
213*4882a593Smuzhiyun 		WRITE_ONCE(sc->caller_is_done, true);
214*4882a593Smuzhiyun 		errno = -EBUSY;
215*4882a593Smuzhiyun 	}
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	return errno;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun #ifndef ROUNDUP4
221*4882a593Smuzhiyun #define ROUNDUP4(val) (((val) + 3) & 0xfffffffc)
222*4882a593Smuzhiyun #endif
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun #ifndef ROUNDUP8
225*4882a593Smuzhiyun #define ROUNDUP8(val) (((val) + 7) & 0xfffffff8)
226*4882a593Smuzhiyun #endif
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun #ifndef ROUNDUP16
229*4882a593Smuzhiyun #define ROUNDUP16(val) (((val) + 15) & 0xfffffff0)
230*4882a593Smuzhiyun #endif
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun #ifndef ROUNDUP128
233*4882a593Smuzhiyun #define ROUNDUP128(val) (((val) + 127) & 0xffffff80)
234*4882a593Smuzhiyun #endif
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun #endif /* _OCTEON_MAIN_H_ */
237