1*4882a593Smuzhiyun /********************************************************************** 2*4882a593Smuzhiyun * Author: Cavium, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Contact: support@cavium.com 5*4882a593Smuzhiyun * Please include "LiquidIO" in the subject. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (c) 2003-2016 Cavium, Inc. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This file is free software; you can redistribute it and/or modify 10*4882a593Smuzhiyun * it under the terms of the GNU General Public License, Version 2, as 11*4882a593Smuzhiyun * published by the Free Software Foundation. 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * This file is distributed in the hope that it will be useful, but 14*4882a593Smuzhiyun * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16*4882a593Smuzhiyun * NONINFRINGEMENT. See the GNU General Public License for more details. 17*4882a593Smuzhiyun ***********************************************************************/ 18*4882a593Smuzhiyun /*! \file cn66xx_device.h 19*4882a593Smuzhiyun * \brief Host Driver: Routines that perform CN66XX specific operations. 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #ifndef __CN66XX_DEVICE_H__ 23*4882a593Smuzhiyun #define __CN66XX_DEVICE_H__ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Register address and configuration for a CN6XXX devices. 26*4882a593Smuzhiyun * If device specific changes need to be made then add a struct to include 27*4882a593Smuzhiyun * device specific fields as shown in the commented section 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun struct octeon_cn6xxx { 30*4882a593Smuzhiyun /** PCI interrupt summary register */ 31*4882a593Smuzhiyun u8 __iomem *intr_sum_reg64; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /** PCI interrupt enable register */ 34*4882a593Smuzhiyun u8 __iomem *intr_enb_reg64; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /** The PCI interrupt mask used by interrupt handler */ 37*4882a593Smuzhiyun u64 intr_mask64; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun struct octeon_config *conf; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Example additional fields - not used currently 42*4882a593Smuzhiyun * struct { 43*4882a593Smuzhiyun * }cn6xyz; 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* For the purpose of atomic access to interrupt enable reg */ 47*4882a593Smuzhiyun spinlock_t lock_for_droq_int_enb_reg; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun enum octeon_pcie_mps { 52*4882a593Smuzhiyun PCIE_MPS_DEFAULT = -1, /* Use the default setup by BIOS */ 53*4882a593Smuzhiyun PCIE_MPS_128B = 0, 54*4882a593Smuzhiyun PCIE_MPS_256B = 1 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun enum octeon_pcie_mrrs { 58*4882a593Smuzhiyun PCIE_MRRS_DEFAULT = -1, /* Use the default setup by BIOS */ 59*4882a593Smuzhiyun PCIE_MRRS_128B = 0, 60*4882a593Smuzhiyun PCIE_MRRS_256B = 1, 61*4882a593Smuzhiyun PCIE_MRRS_512B = 2, 62*4882a593Smuzhiyun PCIE_MRRS_1024B = 3, 63*4882a593Smuzhiyun PCIE_MRRS_2048B = 4, 64*4882a593Smuzhiyun PCIE_MRRS_4096B = 5 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* Common functions for 66xx and 68xx */ 68*4882a593Smuzhiyun int lio_cn6xxx_soft_reset(struct octeon_device *oct); 69*4882a593Smuzhiyun void lio_cn6xxx_enable_error_reporting(struct octeon_device *oct); 70*4882a593Smuzhiyun void lio_cn6xxx_setup_pcie_mps(struct octeon_device *oct, 71*4882a593Smuzhiyun enum octeon_pcie_mps mps); 72*4882a593Smuzhiyun void lio_cn6xxx_setup_pcie_mrrs(struct octeon_device *oct, 73*4882a593Smuzhiyun enum octeon_pcie_mrrs mrrs); 74*4882a593Smuzhiyun void lio_cn6xxx_setup_global_input_regs(struct octeon_device *oct); 75*4882a593Smuzhiyun void lio_cn6xxx_setup_global_output_regs(struct octeon_device *oct); 76*4882a593Smuzhiyun void lio_cn6xxx_setup_iq_regs(struct octeon_device *oct, u32 iq_no); 77*4882a593Smuzhiyun void lio_cn6xxx_setup_oq_regs(struct octeon_device *oct, u32 oq_no); 78*4882a593Smuzhiyun int lio_cn6xxx_enable_io_queues(struct octeon_device *oct); 79*4882a593Smuzhiyun void lio_cn6xxx_disable_io_queues(struct octeon_device *oct); 80*4882a593Smuzhiyun irqreturn_t lio_cn6xxx_process_interrupt_regs(void *dev); 81*4882a593Smuzhiyun void lio_cn6xxx_bar1_idx_setup(struct octeon_device *oct, u64 core_addr, 82*4882a593Smuzhiyun u32 idx, int valid); 83*4882a593Smuzhiyun void lio_cn6xxx_bar1_idx_write(struct octeon_device *oct, u32 idx, u32 mask); 84*4882a593Smuzhiyun u32 lio_cn6xxx_bar1_idx_read(struct octeon_device *oct, u32 idx); 85*4882a593Smuzhiyun u32 86*4882a593Smuzhiyun lio_cn6xxx_update_read_index(struct octeon_instr_queue *iq); 87*4882a593Smuzhiyun void lio_cn6xxx_enable_interrupt(struct octeon_device *oct, u8 unused); 88*4882a593Smuzhiyun void lio_cn6xxx_disable_interrupt(struct octeon_device *oct, u8 unused); 89*4882a593Smuzhiyun void cn6xxx_get_pcie_qlmport(struct octeon_device *oct); 90*4882a593Smuzhiyun void lio_cn6xxx_setup_reg_address(struct octeon_device *oct, void *chip, 91*4882a593Smuzhiyun struct octeon_reg_list *reg_list); 92*4882a593Smuzhiyun u32 lio_cn6xxx_coprocessor_clock(struct octeon_device *oct); 93*4882a593Smuzhiyun u32 lio_cn6xxx_get_oq_ticks(struct octeon_device *oct, u32 time_intr_in_us); 94*4882a593Smuzhiyun int lio_setup_cn66xx_octeon_device(struct octeon_device *oct); 95*4882a593Smuzhiyun int lio_validate_cn6xxx_config_info(struct octeon_device *oct, 96*4882a593Smuzhiyun struct octeon_config *conf6xxx); 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #endif 99