1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Linux network driver for QLogic BR-series Converged Network Adapter. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * Copyright (c) 2005-2014 Brocade Communications Systems, Inc. 7*4882a593Smuzhiyun * Copyright (c) 2014-2015 QLogic Corporation 8*4882a593Smuzhiyun * All rights reserved 9*4882a593Smuzhiyun * www.qlogic.com 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __BFA_DEFS_H__ 13*4882a593Smuzhiyun #define __BFA_DEFS_H__ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include "cna.h" 16*4882a593Smuzhiyun #include "bfa_defs_status.h" 17*4882a593Smuzhiyun #include "bfa_defs_mfg_comm.h" 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define BFA_VERSION_LEN 64 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* ---------------------- adapter definitions ------------ */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* BFA adapter level attributes. */ 24*4882a593Smuzhiyun enum { 25*4882a593Smuzhiyun BFA_ADAPTER_SERIAL_NUM_LEN = STRSZ(BFA_MFG_SERIALNUM_SIZE), 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun *!< adapter serial num length 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun BFA_ADAPTER_MODEL_NAME_LEN = 16, /*!< model name length */ 30*4882a593Smuzhiyun BFA_ADAPTER_MODEL_DESCR_LEN = 128, /*!< model description length */ 31*4882a593Smuzhiyun BFA_ADAPTER_MFG_NAME_LEN = 8, /*!< manufacturer name length */ 32*4882a593Smuzhiyun BFA_ADAPTER_SYM_NAME_LEN = 64, /*!< adapter symbolic name length */ 33*4882a593Smuzhiyun BFA_ADAPTER_OS_TYPE_LEN = 64, /*!< adapter os type length */ 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun struct bfa_adapter_attr { 37*4882a593Smuzhiyun char manufacturer[BFA_ADAPTER_MFG_NAME_LEN]; 38*4882a593Smuzhiyun char serial_num[BFA_ADAPTER_SERIAL_NUM_LEN]; 39*4882a593Smuzhiyun u32 card_type; 40*4882a593Smuzhiyun char model[BFA_ADAPTER_MODEL_NAME_LEN]; 41*4882a593Smuzhiyun char model_descr[BFA_ADAPTER_MODEL_DESCR_LEN]; 42*4882a593Smuzhiyun u64 pwwn; 43*4882a593Smuzhiyun char node_symname[FC_SYMNAME_MAX]; 44*4882a593Smuzhiyun char hw_ver[BFA_VERSION_LEN]; 45*4882a593Smuzhiyun char fw_ver[BFA_VERSION_LEN]; 46*4882a593Smuzhiyun char optrom_ver[BFA_VERSION_LEN]; 47*4882a593Smuzhiyun char os_type[BFA_ADAPTER_OS_TYPE_LEN]; 48*4882a593Smuzhiyun struct bfa_mfg_vpd vpd; 49*4882a593Smuzhiyun u8 mac[ETH_ALEN]; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun u8 nports; 52*4882a593Smuzhiyun u8 max_speed; 53*4882a593Smuzhiyun u8 prototype; 54*4882a593Smuzhiyun char asic_rev; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun u8 pcie_gen; 57*4882a593Smuzhiyun u8 pcie_lanes_orig; 58*4882a593Smuzhiyun u8 pcie_lanes; 59*4882a593Smuzhiyun u8 cna_capable; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun u8 is_mezz; 62*4882a593Smuzhiyun u8 trunk_capable; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* ---------------------- IOC definitions ------------ */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun enum { 68*4882a593Smuzhiyun BFA_IOC_DRIVER_LEN = 16, 69*4882a593Smuzhiyun BFA_IOC_CHIP_REV_LEN = 8, 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* Driver and firmware versions. */ 73*4882a593Smuzhiyun struct bfa_ioc_driver_attr { 74*4882a593Smuzhiyun char driver[BFA_IOC_DRIVER_LEN]; /*!< driver name */ 75*4882a593Smuzhiyun char driver_ver[BFA_VERSION_LEN]; /*!< driver version */ 76*4882a593Smuzhiyun char fw_ver[BFA_VERSION_LEN]; /*!< firmware version */ 77*4882a593Smuzhiyun char bios_ver[BFA_VERSION_LEN]; /*!< bios version */ 78*4882a593Smuzhiyun char efi_ver[BFA_VERSION_LEN]; /*!< EFI version */ 79*4882a593Smuzhiyun char ob_ver[BFA_VERSION_LEN]; /*!< openboot version */ 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* IOC PCI device attributes */ 83*4882a593Smuzhiyun struct bfa_ioc_pci_attr { 84*4882a593Smuzhiyun u16 vendor_id; /*!< PCI vendor ID */ 85*4882a593Smuzhiyun u16 device_id; /*!< PCI device ID */ 86*4882a593Smuzhiyun u16 ssid; /*!< subsystem ID */ 87*4882a593Smuzhiyun u16 ssvid; /*!< subsystem vendor ID */ 88*4882a593Smuzhiyun u32 pcifn; /*!< PCI device function */ 89*4882a593Smuzhiyun u32 rsvd; /* padding */ 90*4882a593Smuzhiyun char chip_rev[BFA_IOC_CHIP_REV_LEN]; /*!< chip revision */ 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* IOC states */ 94*4882a593Smuzhiyun enum bfa_ioc_state { 95*4882a593Smuzhiyun BFA_IOC_UNINIT = 1, /*!< IOC is in uninit state */ 96*4882a593Smuzhiyun BFA_IOC_RESET = 2, /*!< IOC is in reset state */ 97*4882a593Smuzhiyun BFA_IOC_SEMWAIT = 3, /*!< Waiting for IOC h/w semaphore */ 98*4882a593Smuzhiyun BFA_IOC_HWINIT = 4, /*!< IOC h/w is being initialized */ 99*4882a593Smuzhiyun BFA_IOC_GETATTR = 5, /*!< IOC is being configured */ 100*4882a593Smuzhiyun BFA_IOC_OPERATIONAL = 6, /*!< IOC is operational */ 101*4882a593Smuzhiyun BFA_IOC_INITFAIL = 7, /*!< IOC hardware failure */ 102*4882a593Smuzhiyun BFA_IOC_FAIL = 8, /*!< IOC heart-beat failure */ 103*4882a593Smuzhiyun BFA_IOC_DISABLING = 9, /*!< IOC is being disabled */ 104*4882a593Smuzhiyun BFA_IOC_DISABLED = 10, /*!< IOC is disabled */ 105*4882a593Smuzhiyun BFA_IOC_FWMISMATCH = 11, /*!< IOC f/w different from drivers */ 106*4882a593Smuzhiyun BFA_IOC_ENABLING = 12, /*!< IOC is being enabled */ 107*4882a593Smuzhiyun BFA_IOC_HWFAIL = 13, /*!< PCI mapping doesn't exist */ 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* IOC firmware stats */ 111*4882a593Smuzhiyun struct bfa_fw_ioc_stats { 112*4882a593Smuzhiyun u32 enable_reqs; 113*4882a593Smuzhiyun u32 disable_reqs; 114*4882a593Smuzhiyun u32 get_attr_reqs; 115*4882a593Smuzhiyun u32 dbg_sync; 116*4882a593Smuzhiyun u32 dbg_dump; 117*4882a593Smuzhiyun u32 unknown_reqs; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* IOC driver stats */ 121*4882a593Smuzhiyun struct bfa_ioc_drv_stats { 122*4882a593Smuzhiyun u32 ioc_isrs; 123*4882a593Smuzhiyun u32 ioc_enables; 124*4882a593Smuzhiyun u32 ioc_disables; 125*4882a593Smuzhiyun u32 ioc_hbfails; 126*4882a593Smuzhiyun u32 ioc_boots; 127*4882a593Smuzhiyun u32 stats_tmos; 128*4882a593Smuzhiyun u32 hb_count; 129*4882a593Smuzhiyun u32 disable_reqs; 130*4882a593Smuzhiyun u32 enable_reqs; 131*4882a593Smuzhiyun u32 disable_replies; 132*4882a593Smuzhiyun u32 enable_replies; 133*4882a593Smuzhiyun u32 rsvd; 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* IOC statistics */ 137*4882a593Smuzhiyun struct bfa_ioc_stats { 138*4882a593Smuzhiyun struct bfa_ioc_drv_stats drv_stats; /*!< driver IOC stats */ 139*4882a593Smuzhiyun struct bfa_fw_ioc_stats fw_stats; /*!< firmware IOC stats */ 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun enum bfa_ioc_type { 143*4882a593Smuzhiyun BFA_IOC_TYPE_FC = 1, 144*4882a593Smuzhiyun BFA_IOC_TYPE_FCoE = 2, 145*4882a593Smuzhiyun BFA_IOC_TYPE_LL = 3, 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* IOC attributes returned in queries */ 149*4882a593Smuzhiyun struct bfa_ioc_attr { 150*4882a593Smuzhiyun enum bfa_ioc_type ioc_type; 151*4882a593Smuzhiyun enum bfa_ioc_state state; /*!< IOC state */ 152*4882a593Smuzhiyun struct bfa_adapter_attr adapter_attr; /*!< HBA attributes */ 153*4882a593Smuzhiyun struct bfa_ioc_driver_attr driver_attr; /*!< driver attr */ 154*4882a593Smuzhiyun struct bfa_ioc_pci_attr pci_attr; 155*4882a593Smuzhiyun u8 port_id; /*!< port number */ 156*4882a593Smuzhiyun u8 port_mode; /*!< enum bfa_mode */ 157*4882a593Smuzhiyun u8 cap_bm; /*!< capability */ 158*4882a593Smuzhiyun u8 port_mode_cfg; /*!< enum bfa_mode */ 159*4882a593Smuzhiyun u8 def_fn; /*!< 1 if default fn */ 160*4882a593Smuzhiyun u8 rsvd[3]; /*!< 64bit align */ 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun /* Adapter capability mask definition */ 164*4882a593Smuzhiyun enum { 165*4882a593Smuzhiyun BFA_CM_HBA = 0x01, 166*4882a593Smuzhiyun BFA_CM_CNA = 0x02, 167*4882a593Smuzhiyun BFA_CM_NIC = 0x04, 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun /* ---------------------- mfg definitions ------------ */ 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun /* Checksum size */ 173*4882a593Smuzhiyun #define BFA_MFG_CHKSUM_SIZE 16 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun #define BFA_MFG_PARTNUM_SIZE 14 176*4882a593Smuzhiyun #define BFA_MFG_SUPPLIER_ID_SIZE 10 177*4882a593Smuzhiyun #define BFA_MFG_SUPPLIER_PARTNUM_SIZE 20 178*4882a593Smuzhiyun #define BFA_MFG_SUPPLIER_SERIALNUM_SIZE 20 179*4882a593Smuzhiyun #define BFA_MFG_SUPPLIER_REVISION_SIZE 4 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun /* BFA adapter manufacturing block definition. 182*4882a593Smuzhiyun * 183*4882a593Smuzhiyun * All numerical fields are in big-endian format. 184*4882a593Smuzhiyun */ 185*4882a593Smuzhiyun struct bfa_mfg_block { 186*4882a593Smuzhiyun u8 version; /* manufacturing block version */ 187*4882a593Smuzhiyun u8 mfg_sig[3]; /* characters 'M', 'F', 'G' */ 188*4882a593Smuzhiyun u16 mfgsize; /* mfg block size */ 189*4882a593Smuzhiyun u16 u16_chksum; /* old u16 checksum */ 190*4882a593Smuzhiyun char brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)]; 191*4882a593Smuzhiyun char brcd_partnum[STRSZ(BFA_MFG_PARTNUM_SIZE)]; 192*4882a593Smuzhiyun u8 mfg_day; /* manufacturing day */ 193*4882a593Smuzhiyun u8 mfg_month; /* manufacturing month */ 194*4882a593Smuzhiyun u16 mfg_year; /* manufacturing year */ 195*4882a593Smuzhiyun u64 mfg_wwn; /* wwn base for this adapter */ 196*4882a593Smuzhiyun u8 num_wwn; /* number of wwns assigned */ 197*4882a593Smuzhiyun u8 mfg_speeds; /* speeds allowed for this adapter */ 198*4882a593Smuzhiyun u8 rsv[2]; 199*4882a593Smuzhiyun char supplier_id[STRSZ(BFA_MFG_SUPPLIER_ID_SIZE)]; 200*4882a593Smuzhiyun char supplier_partnum[STRSZ(BFA_MFG_SUPPLIER_PARTNUM_SIZE)]; 201*4882a593Smuzhiyun char supplier_serialnum[STRSZ(BFA_MFG_SUPPLIER_SERIALNUM_SIZE)]; 202*4882a593Smuzhiyun char supplier_revision[STRSZ(BFA_MFG_SUPPLIER_REVISION_SIZE)]; 203*4882a593Smuzhiyun u8 mfg_mac[ETH_ALEN]; /* base mac address */ 204*4882a593Smuzhiyun u8 num_mac; /* number of mac addresses */ 205*4882a593Smuzhiyun u8 rsv2; 206*4882a593Smuzhiyun u32 card_type; /* card type */ 207*4882a593Smuzhiyun char cap_nic; /* capability nic */ 208*4882a593Smuzhiyun char cap_cna; /* capability cna */ 209*4882a593Smuzhiyun char cap_hba; /* capability hba */ 210*4882a593Smuzhiyun char cap_fc16g; /* capability fc 16g */ 211*4882a593Smuzhiyun char cap_sriov; /* capability sriov */ 212*4882a593Smuzhiyun char cap_mezz; /* capability mezz */ 213*4882a593Smuzhiyun u8 rsv3; 214*4882a593Smuzhiyun u8 mfg_nports; /* number of ports */ 215*4882a593Smuzhiyun char media[8]; /* xfi/xaui */ 216*4882a593Smuzhiyun char initial_mode[8]; /* initial mode: hba/cna/nic */ 217*4882a593Smuzhiyun u8 rsv4[84]; 218*4882a593Smuzhiyun u8 md5_chksum[BFA_MFG_CHKSUM_SIZE]; /* md5 checksum */ 219*4882a593Smuzhiyun } __packed; 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun /* ---------------------- pci definitions ------------ */ 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun /* 224*4882a593Smuzhiyun * PCI device ID information 225*4882a593Smuzhiyun */ 226*4882a593Smuzhiyun enum { 227*4882a593Smuzhiyun BFA_PCI_DEVICE_ID_CT2 = 0x22, 228*4882a593Smuzhiyun }; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun #define bfa_asic_id_ct(device) \ 231*4882a593Smuzhiyun ((device) == PCI_DEVICE_ID_BROCADE_CT || \ 232*4882a593Smuzhiyun (device) == PCI_DEVICE_ID_BROCADE_CT_FC) 233*4882a593Smuzhiyun #define bfa_asic_id_ct2(device) \ 234*4882a593Smuzhiyun ((device) == BFA_PCI_DEVICE_ID_CT2) 235*4882a593Smuzhiyun #define bfa_asic_id_ctc(device) \ 236*4882a593Smuzhiyun (bfa_asic_id_ct(device) || bfa_asic_id_ct2(device)) 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun /* PCI sub-system device and vendor ID information */ 239*4882a593Smuzhiyun enum { 240*4882a593Smuzhiyun BFA_PCI_FCOE_SSDEVICE_ID = 0x14, 241*4882a593Smuzhiyun BFA_PCI_CT2_SSID_FCoE = 0x22, 242*4882a593Smuzhiyun BFA_PCI_CT2_SSID_ETH = 0x23, 243*4882a593Smuzhiyun BFA_PCI_CT2_SSID_FC = 0x24, 244*4882a593Smuzhiyun }; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun enum bfa_mode { 247*4882a593Smuzhiyun BFA_MODE_HBA = 1, 248*4882a593Smuzhiyun BFA_MODE_CNA = 2, 249*4882a593Smuzhiyun BFA_MODE_NIC = 3 250*4882a593Smuzhiyun }; 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun /* 253*4882a593Smuzhiyun * Flash module specific 254*4882a593Smuzhiyun */ 255*4882a593Smuzhiyun #define BFA_FLASH_PART_ENTRY_SIZE 32 /* partition entry size */ 256*4882a593Smuzhiyun #define BFA_FLASH_PART_MAX 32 /* maximal # of partitions */ 257*4882a593Smuzhiyun #define BFA_TOTAL_FLASH_SIZE 0x400000 258*4882a593Smuzhiyun #define BFA_FLASH_PART_FWIMG 2 259*4882a593Smuzhiyun #define BFA_FLASH_PART_MFG 7 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun /* 262*4882a593Smuzhiyun * flash partition attributes 263*4882a593Smuzhiyun */ 264*4882a593Smuzhiyun struct bfa_flash_part_attr { 265*4882a593Smuzhiyun u32 part_type; /* partition type */ 266*4882a593Smuzhiyun u32 part_instance; /* partition instance */ 267*4882a593Smuzhiyun u32 part_off; /* partition offset */ 268*4882a593Smuzhiyun u32 part_size; /* partition size */ 269*4882a593Smuzhiyun u32 part_len; /* partition content length */ 270*4882a593Smuzhiyun u32 part_status; /* partition status */ 271*4882a593Smuzhiyun char rsv[BFA_FLASH_PART_ENTRY_SIZE - 24]; 272*4882a593Smuzhiyun }; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun /* 275*4882a593Smuzhiyun * flash attributes 276*4882a593Smuzhiyun */ 277*4882a593Smuzhiyun struct bfa_flash_attr { 278*4882a593Smuzhiyun u32 status; /* flash overall status */ 279*4882a593Smuzhiyun u32 npart; /* num of partitions */ 280*4882a593Smuzhiyun struct bfa_flash_part_attr part[BFA_FLASH_PART_MAX]; 281*4882a593Smuzhiyun }; 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun #endif /* __BFA_DEFS_H__ */ 284