xref: /OK3568_Linux_fs/kernel/drivers/net/ethernet/broadcom/cnic.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* cnic.h: QLogic CNIC core network driver.
2*4882a593Smuzhiyun  *
3*4882a593Smuzhiyun  * Copyright (c) 2006-2014 Broadcom Corporation
4*4882a593Smuzhiyun  * Copyright (c) 2014 QLogic Corporation
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify
7*4882a593Smuzhiyun  * it under the terms of the GNU General Public License as published by
8*4882a593Smuzhiyun  * the Free Software Foundation.
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #ifndef CNIC_H
14*4882a593Smuzhiyun #define CNIC_H
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #define HC_INDEX_ISCSI_EQ_CONS			6
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define HC_INDEX_FCOE_EQ_CONS			3
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS		5
21*4882a593Smuzhiyun #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS	1
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #define KWQ_PAGE_CNT	4
24*4882a593Smuzhiyun #define KCQ_PAGE_CNT	16
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #define KWQ_CID 		24
27*4882a593Smuzhiyun #define KCQ_CID 		25
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun /*
30*4882a593Smuzhiyun  *	krnlq_context definition
31*4882a593Smuzhiyun  */
32*4882a593Smuzhiyun #define L5_KRNLQ_FLAGS	0x00000000
33*4882a593Smuzhiyun #define L5_KRNLQ_SIZE	0x00000000
34*4882a593Smuzhiyun #define L5_KRNLQ_TYPE	0x00000000
35*4882a593Smuzhiyun #define KRNLQ_FLAGS_PG_SZ					(0xf<<0)
36*4882a593Smuzhiyun #define KRNLQ_FLAGS_PG_SZ_256					(0<<0)
37*4882a593Smuzhiyun #define KRNLQ_FLAGS_PG_SZ_512					(1<<0)
38*4882a593Smuzhiyun #define KRNLQ_FLAGS_PG_SZ_1K					(2<<0)
39*4882a593Smuzhiyun #define KRNLQ_FLAGS_PG_SZ_2K					(3<<0)
40*4882a593Smuzhiyun #define KRNLQ_FLAGS_PG_SZ_4K					(4<<0)
41*4882a593Smuzhiyun #define KRNLQ_FLAGS_PG_SZ_8K					(5<<0)
42*4882a593Smuzhiyun #define KRNLQ_FLAGS_PG_SZ_16K					(6<<0)
43*4882a593Smuzhiyun #define KRNLQ_FLAGS_PG_SZ_32K					(7<<0)
44*4882a593Smuzhiyun #define KRNLQ_FLAGS_PG_SZ_64K					(8<<0)
45*4882a593Smuzhiyun #define KRNLQ_FLAGS_PG_SZ_128K					(9<<0)
46*4882a593Smuzhiyun #define KRNLQ_FLAGS_PG_SZ_256K					(10<<0)
47*4882a593Smuzhiyun #define KRNLQ_FLAGS_PG_SZ_512K					(11<<0)
48*4882a593Smuzhiyun #define KRNLQ_FLAGS_PG_SZ_1M					(12<<0)
49*4882a593Smuzhiyun #define KRNLQ_FLAGS_PG_SZ_2M					(13<<0)
50*4882a593Smuzhiyun #define KRNLQ_FLAGS_QE_SELF_SEQ					(1<<15)
51*4882a593Smuzhiyun #define KRNLQ_SIZE_TYPE_SIZE	((((0x28 + 0x1f) & ~0x1f) / 0x20) << 16)
52*4882a593Smuzhiyun #define KRNLQ_TYPE_TYPE						(0xf<<28)
53*4882a593Smuzhiyun #define KRNLQ_TYPE_TYPE_EMPTY					(0<<28)
54*4882a593Smuzhiyun #define KRNLQ_TYPE_TYPE_KRNLQ					(6<<28)
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun #define L5_KRNLQ_HOST_QIDX		0x00000004
57*4882a593Smuzhiyun #define L5_KRNLQ_HOST_FW_QIDX		0x00000008
58*4882a593Smuzhiyun #define L5_KRNLQ_NX_QE_SELF_SEQ 	0x0000000c
59*4882a593Smuzhiyun #define L5_KRNLQ_QE_SELF_SEQ_MAX	0x0000000c
60*4882a593Smuzhiyun #define L5_KRNLQ_NX_QE_HADDR_HI 	0x00000010
61*4882a593Smuzhiyun #define L5_KRNLQ_NX_QE_HADDR_LO 	0x00000014
62*4882a593Smuzhiyun #define L5_KRNLQ_PGTBL_PGIDX		0x00000018
63*4882a593Smuzhiyun #define L5_KRNLQ_NX_PG_QIDX 		0x00000018
64*4882a593Smuzhiyun #define L5_KRNLQ_PGTBL_NPAGES		0x0000001c
65*4882a593Smuzhiyun #define L5_KRNLQ_QIDX_INCR		0x0000001c
66*4882a593Smuzhiyun #define L5_KRNLQ_PGTBL_HADDR_HI 	0x00000020
67*4882a593Smuzhiyun #define L5_KRNLQ_PGTBL_HADDR_LO 	0x00000024
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun #define BNX2_PG_CTX_MAP			0x1a0034
70*4882a593Smuzhiyun #define BNX2_ISCSI_CTX_MAP		0x1a0074
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun #define MAX_COMPLETED_KCQE	64
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun #define MAX_CNIC_L5_CONTEXT	256
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun #define MAX_CM_SK_TBL_SZ	MAX_CNIC_L5_CONTEXT
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun #define MAX_ISCSI_TBL_SZ	256
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun #define CNIC_LOCAL_PORT_MIN	60000
81*4882a593Smuzhiyun #define CNIC_LOCAL_PORT_MAX	61024
82*4882a593Smuzhiyun #define CNIC_LOCAL_PORT_RANGE	(CNIC_LOCAL_PORT_MAX - CNIC_LOCAL_PORT_MIN)
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun #define KWQE_CNT (BNX2_PAGE_SIZE / sizeof(struct kwqe))
85*4882a593Smuzhiyun #define KCQE_CNT (BNX2_PAGE_SIZE / sizeof(struct kcqe))
86*4882a593Smuzhiyun #define MAX_KWQE_CNT (KWQE_CNT - 1)
87*4882a593Smuzhiyun #define MAX_KCQE_CNT (KCQE_CNT - 1)
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun #define MAX_KWQ_IDX	((KWQ_PAGE_CNT * KWQE_CNT) - 1)
90*4882a593Smuzhiyun #define MAX_KCQ_IDX	((KCQ_PAGE_CNT * KCQE_CNT) - 1)
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun #define KWQ_PG(x) (((x) & ~MAX_KWQE_CNT) >> (BNX2_PAGE_BITS - 5))
93*4882a593Smuzhiyun #define KWQ_IDX(x) ((x) & MAX_KWQE_CNT)
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun #define KCQ_PG(x) (((x) & ~MAX_KCQE_CNT) >> (BNX2_PAGE_BITS - 5))
96*4882a593Smuzhiyun #define KCQ_IDX(x) ((x) & MAX_KCQE_CNT)
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun #define BNX2X_NEXT_KCQE(x) (((x) & (MAX_KCQE_CNT - 1)) ==		\
99*4882a593Smuzhiyun 		(MAX_KCQE_CNT - 1)) ?					\
100*4882a593Smuzhiyun 		(x) + 2 : (x) + 1
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun #define BNX2X_KWQ_DATA_PG(cp, x) ((x) / (cp)->kwq_16_data_pp)
103*4882a593Smuzhiyun #define BNX2X_KWQ_DATA_IDX(cp, x) ((x) % (cp)->kwq_16_data_pp)
104*4882a593Smuzhiyun #define BNX2X_KWQ_DATA(cp, x)						\
105*4882a593Smuzhiyun 	&(cp)->kwq_16_data[BNX2X_KWQ_DATA_PG(cp, x)][BNX2X_KWQ_DATA_IDX(cp, x)]
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun #define DEF_IPID_START		0x8000
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun #define DEF_KA_TIMEOUT		10000
110*4882a593Smuzhiyun #define DEF_KA_INTERVAL		300000
111*4882a593Smuzhiyun #define DEF_KA_MAX_PROBE_COUNT	3
112*4882a593Smuzhiyun #define DEF_TOS			0
113*4882a593Smuzhiyun #define DEF_TTL			0xfe
114*4882a593Smuzhiyun #define DEF_SND_SEQ_SCALE	0
115*4882a593Smuzhiyun #define DEF_RCV_BUF		0xffff
116*4882a593Smuzhiyun #define DEF_SND_BUF		0xffff
117*4882a593Smuzhiyun #define DEF_SEED		0
118*4882a593Smuzhiyun #define DEF_MAX_RT_TIME		500
119*4882a593Smuzhiyun #define DEF_MAX_DA_COUNT	2
120*4882a593Smuzhiyun #define DEF_SWS_TIMER		1000
121*4882a593Smuzhiyun #define DEF_MAX_CWND		0xffff
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun struct cnic_ctx {
124*4882a593Smuzhiyun 	u32		cid;
125*4882a593Smuzhiyun 	void		*ctx;
126*4882a593Smuzhiyun 	dma_addr_t	mapping;
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun #define BNX2_MAX_CID		0x2000
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun struct cnic_dma {
132*4882a593Smuzhiyun 	int		num_pages;
133*4882a593Smuzhiyun 	void		**pg_arr;
134*4882a593Smuzhiyun 	dma_addr_t	*pg_map_arr;
135*4882a593Smuzhiyun 	int		pgtbl_size;
136*4882a593Smuzhiyun 	u32		*pgtbl;
137*4882a593Smuzhiyun 	dma_addr_t	pgtbl_map;
138*4882a593Smuzhiyun };
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun struct cnic_id_tbl {
141*4882a593Smuzhiyun 	spinlock_t	lock;
142*4882a593Smuzhiyun 	u32		start;
143*4882a593Smuzhiyun 	u32		max;
144*4882a593Smuzhiyun 	u32		next;
145*4882a593Smuzhiyun 	unsigned long	*table;
146*4882a593Smuzhiyun };
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun #define CNIC_KWQ16_DATA_SIZE	128
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun struct kwqe_16_data {
151*4882a593Smuzhiyun 	u8	data[CNIC_KWQ16_DATA_SIZE];
152*4882a593Smuzhiyun };
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun struct cnic_iscsi {
155*4882a593Smuzhiyun 	struct cnic_dma		task_array_info;
156*4882a593Smuzhiyun 	struct cnic_dma		r2tq_info;
157*4882a593Smuzhiyun 	struct cnic_dma		hq_info;
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun struct cnic_context {
161*4882a593Smuzhiyun 	u32			cid;
162*4882a593Smuzhiyun 	struct kwqe_16_data	*kwqe_data;
163*4882a593Smuzhiyun 	dma_addr_t		kwqe_data_mapping;
164*4882a593Smuzhiyun 	wait_queue_head_t	waitq;
165*4882a593Smuzhiyun 	int			wait_cond;
166*4882a593Smuzhiyun 	unsigned long		timestamp;
167*4882a593Smuzhiyun 	unsigned long		ctx_flags;
168*4882a593Smuzhiyun #define	CTX_FL_OFFLD_START	0
169*4882a593Smuzhiyun #define	CTX_FL_DELETE_WAIT	1
170*4882a593Smuzhiyun #define	CTX_FL_CID_ERROR	2
171*4882a593Smuzhiyun 	u8			ulp_proto_id;
172*4882a593Smuzhiyun 	union {
173*4882a593Smuzhiyun 		struct cnic_iscsi	*iscsi;
174*4882a593Smuzhiyun 	} proto;
175*4882a593Smuzhiyun };
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun struct kcq_info {
178*4882a593Smuzhiyun 	struct cnic_dma	dma;
179*4882a593Smuzhiyun 	struct kcqe	**kcq;
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	u16		*hw_prod_idx_ptr;
182*4882a593Smuzhiyun 	u16		sw_prod_idx;
183*4882a593Smuzhiyun 	u16		*status_idx_ptr;
184*4882a593Smuzhiyun 	u32		io_addr;
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	u16		(*next_idx)(u16);
187*4882a593Smuzhiyun 	u16		(*hw_idx)(u16);
188*4882a593Smuzhiyun };
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun #define UIO_USE_TX_DOORBELL 0x017855DB
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun struct cnic_uio_dev {
193*4882a593Smuzhiyun 	struct uio_info		cnic_uinfo;
194*4882a593Smuzhiyun 	u32			uio_dev;
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	int			l2_ring_size;
197*4882a593Smuzhiyun 	void			*l2_ring;
198*4882a593Smuzhiyun 	dma_addr_t		l2_ring_map;
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	int			l2_buf_size;
201*4882a593Smuzhiyun 	void			*l2_buf;
202*4882a593Smuzhiyun 	dma_addr_t		l2_buf_map;
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	struct cnic_dev		*dev;
205*4882a593Smuzhiyun 	struct pci_dev		*pdev;
206*4882a593Smuzhiyun 	struct list_head	list;
207*4882a593Smuzhiyun };
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun struct cnic_local {
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	spinlock_t cnic_ulp_lock;
212*4882a593Smuzhiyun 	void *ulp_handle[MAX_CNIC_ULP_TYPE];
213*4882a593Smuzhiyun 	unsigned long ulp_flags[MAX_CNIC_ULP_TYPE];
214*4882a593Smuzhiyun #define ULP_F_INIT	0
215*4882a593Smuzhiyun #define ULP_F_START	1
216*4882a593Smuzhiyun #define ULP_F_CALL_PENDING	2
217*4882a593Smuzhiyun 	struct cnic_ulp_ops __rcu *ulp_ops[MAX_CNIC_ULP_TYPE];
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 	unsigned long cnic_local_flags;
220*4882a593Smuzhiyun #define	CNIC_LCL_FL_KWQ_INIT		0x0
221*4882a593Smuzhiyun #define	CNIC_LCL_FL_L2_WAIT		0x1
222*4882a593Smuzhiyun #define	CNIC_LCL_FL_RINGS_INITED	0x2
223*4882a593Smuzhiyun #define	CNIC_LCL_FL_STOP_ISCSI		0x4
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	struct cnic_dev *dev;
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 	struct cnic_eth_dev *ethdev;
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	struct cnic_uio_dev *udev;
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 	int		l2_rx_ring_size;
232*4882a593Smuzhiyun 	int		l2_single_buf_size;
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	u16		*rx_cons_ptr;
235*4882a593Smuzhiyun 	u16		*tx_cons_ptr;
236*4882a593Smuzhiyun 	u16		rx_cons;
237*4882a593Smuzhiyun 	u16		tx_cons;
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 	struct cnic_dma		kwq_info;
240*4882a593Smuzhiyun 	struct kwqe		**kwq;
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	struct cnic_dma		kwq_16_data_info;
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	u16		max_kwq_idx;
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	u16		kwq_prod_idx;
247*4882a593Smuzhiyun 	u32		kwq_io_addr;
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun 	u16		*kwq_con_idx_ptr;
250*4882a593Smuzhiyun 	u16		kwq_con_idx;
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	struct kcq_info	kcq1;
253*4882a593Smuzhiyun 	struct kcq_info	kcq2;
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	union {
256*4882a593Smuzhiyun 		void				*gen;
257*4882a593Smuzhiyun 		struct status_block_msix	*bnx2;
258*4882a593Smuzhiyun 		struct host_hc_status_block_e1x	*bnx2x_e1x;
259*4882a593Smuzhiyun 		/* index values - which counter to update */
260*4882a593Smuzhiyun 		#define SM_RX_ID		0
261*4882a593Smuzhiyun 		#define SM_TX_ID		1
262*4882a593Smuzhiyun 	} status_blk;
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 	struct host_sp_status_block	*bnx2x_def_status_blk;
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	u32				status_blk_num;
267*4882a593Smuzhiyun 	u32				bnx2x_igu_sb_id;
268*4882a593Smuzhiyun 	u32				int_num;
269*4882a593Smuzhiyun 	u32				last_status_idx;
270*4882a593Smuzhiyun 	struct tasklet_struct		cnic_irq_task;
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	struct kcqe		*completed_kcq[MAX_COMPLETED_KCQE];
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 	struct cnic_sock	*csk_tbl;
275*4882a593Smuzhiyun 	struct cnic_id_tbl	csk_port_tbl;
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 	struct cnic_dma		gbl_buf_info;
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	struct cnic_iscsi	*iscsi_tbl;
280*4882a593Smuzhiyun 	struct cnic_context	*ctx_tbl;
281*4882a593Smuzhiyun 	struct cnic_id_tbl	cid_tbl;
282*4882a593Smuzhiyun 	atomic_t		iscsi_conn;
283*4882a593Smuzhiyun 	u32			iscsi_start_cid;
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 	u32			fcoe_init_cid;
286*4882a593Smuzhiyun 	u32			fcoe_start_cid;
287*4882a593Smuzhiyun 	struct cnic_id_tbl	fcoe_cid_tbl;
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun 	u32			max_cid_space;
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	/* per connection parameters */
292*4882a593Smuzhiyun 	int			num_iscsi_tasks;
293*4882a593Smuzhiyun 	int			num_ccells;
294*4882a593Smuzhiyun 	int			task_array_size;
295*4882a593Smuzhiyun 	int			r2tq_size;
296*4882a593Smuzhiyun 	int			hq_size;
297*4882a593Smuzhiyun 	int			num_cqs;
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun 	struct delayed_work	delete_task;
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 	struct cnic_ctx		*ctx_arr;
302*4882a593Smuzhiyun 	int			ctx_blks;
303*4882a593Smuzhiyun 	int			ctx_blk_size;
304*4882a593Smuzhiyun 	unsigned long		ctx_align;
305*4882a593Smuzhiyun 	int			cids_per_blk;
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 	u32			chip_id;
308*4882a593Smuzhiyun 	int			func;
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun 	u32			shmem_base;
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	struct cnic_ops		*cnic_ops;
313*4882a593Smuzhiyun 	int			(*start_hw)(struct cnic_dev *);
314*4882a593Smuzhiyun 	void			(*stop_hw)(struct cnic_dev *);
315*4882a593Smuzhiyun 	void			(*setup_pgtbl)(struct cnic_dev *,
316*4882a593Smuzhiyun 					       struct cnic_dma *);
317*4882a593Smuzhiyun 	int			(*alloc_resc)(struct cnic_dev *);
318*4882a593Smuzhiyun 	void			(*free_resc)(struct cnic_dev *);
319*4882a593Smuzhiyun 	int			(*start_cm)(struct cnic_dev *);
320*4882a593Smuzhiyun 	void			(*stop_cm)(struct cnic_dev *);
321*4882a593Smuzhiyun 	void			(*enable_int)(struct cnic_dev *);
322*4882a593Smuzhiyun 	void			(*disable_int_sync)(struct cnic_dev *);
323*4882a593Smuzhiyun 	void			(*ack_int)(struct cnic_dev *);
324*4882a593Smuzhiyun 	void			(*arm_int)(struct cnic_dev *, u32 index);
325*4882a593Smuzhiyun 	void			(*close_conn)(struct cnic_sock *, u32 opcode);
326*4882a593Smuzhiyun };
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun struct bnx2x_bd_chain_next {
329*4882a593Smuzhiyun 	u32	addr_lo;
330*4882a593Smuzhiyun 	u32	addr_hi;
331*4882a593Smuzhiyun 	u8	reserved[8];
332*4882a593Smuzhiyun };
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun #define ISCSI_DEFAULT_MAX_OUTSTANDING_R2T 	(1)
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun #define ISCSI_RAMROD_CMD_ID_UPDATE_CONN		(ISCSI_KCQE_OPCODE_UPDATE_CONN)
337*4882a593Smuzhiyun #define ISCSI_RAMROD_CMD_ID_INIT		(ISCSI_KCQE_OPCODE_INIT)
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun #define CDU_REGION_NUMBER_XCM_AG 2
340*4882a593Smuzhiyun #define CDU_REGION_NUMBER_UCM_AG 4
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun #define CDU_VALID_DATA(_cid, _region, _type)	\
343*4882a593Smuzhiyun 	(((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun #define CDU_CRC8(_cid, _region, _type)	\
346*4882a593Smuzhiyun 	(calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun #define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type)	\
349*4882a593Smuzhiyun 	(0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun #define BNX2X_CONTEXT_MEM_SIZE		1024
352*4882a593Smuzhiyun #define BNX2X_FCOE_CID			16
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun #define BNX2X_ISCSI_START_CID		18
355*4882a593Smuzhiyun #define BNX2X_ISCSI_NUM_CONNECTIONS	128
356*4882a593Smuzhiyun #define BNX2X_ISCSI_TASK_CONTEXT_SIZE	128
357*4882a593Smuzhiyun #define BNX2X_ISCSI_MAX_PENDING_R2TS	4
358*4882a593Smuzhiyun #define BNX2X_ISCSI_R2TQE_SIZE		8
359*4882a593Smuzhiyun #define BNX2X_ISCSI_HQ_BD_SIZE		64
360*4882a593Smuzhiyun #define BNX2X_ISCSI_GLB_BUF_SIZE	64
361*4882a593Smuzhiyun #define BNX2X_ISCSI_PBL_NOT_CACHED	0xff
362*4882a593Smuzhiyun #define BNX2X_ISCSI_PDU_HEADER_NOT_CACHED	0xff
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun #define BNX2X_FCOE_NUM_CONNECTIONS	1024
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun #define BNX2X_FCOE_L5_CID_BASE		MAX_ISCSI_TBL_SZ
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun #define BNX2X_CHIP_IS_E2_PLUS(bp) (CHIP_IS_E2(bp) || CHIP_IS_E3(bp))
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun #define BNX2X_RX_DESC_CNT		(BNX2_PAGE_SIZE / \
371*4882a593Smuzhiyun 					 sizeof(struct eth_rx_bd))
372*4882a593Smuzhiyun #define BNX2X_MAX_RX_DESC_CNT		(BNX2X_RX_DESC_CNT - 2)
373*4882a593Smuzhiyun #define BNX2X_RCQ_DESC_CNT		(BNX2_PAGE_SIZE / \
374*4882a593Smuzhiyun 					 sizeof(union eth_rx_cqe))
375*4882a593Smuzhiyun #define BNX2X_MAX_RCQ_DESC_CNT		(BNX2X_RCQ_DESC_CNT - 1)
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun #define BNX2X_NEXT_RCQE(x) (((x) & BNX2X_MAX_RCQ_DESC_CNT) ==		\
378*4882a593Smuzhiyun 		(BNX2X_MAX_RCQ_DESC_CNT - 1)) ?				\
379*4882a593Smuzhiyun 		((x) + 2) : ((x) + 1)
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun #define BNX2X_DEF_SB_ID			HC_SP_SB_ID
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun #define BNX2X_SHMEM_MF_BLK_OFFSET	0x7e4
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun #define BNX2X_SHMEM_ADDR(base, field)	(base + \
386*4882a593Smuzhiyun 					 offsetof(struct shmem_region, field))
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun #define BNX2X_SHMEM2_ADDR(base, field)	(base + \
389*4882a593Smuzhiyun 					 offsetof(struct shmem2_region, field))
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun #define BNX2X_SHMEM2_HAS(base, field)				\
392*4882a593Smuzhiyun 		((base) &&					\
393*4882a593Smuzhiyun 		 (CNIC_RD(dev, BNX2X_SHMEM2_ADDR(base, size)) >	\
394*4882a593Smuzhiyun 		  offsetof(struct shmem2_region, field)))
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun #define BNX2X_MF_CFG_ADDR(base, field)				\
397*4882a593Smuzhiyun 			((base) + offsetof(struct mf_cfg, field))
398*4882a593Smuzhiyun 
399*4882a593Smuzhiyun #ifndef ETH_MAX_RX_CLIENTS_E2
400*4882a593Smuzhiyun #define ETH_MAX_RX_CLIENTS_E2 		ETH_MAX_RX_CLIENTS_E1H
401*4882a593Smuzhiyun #endif
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun #define CNIC_FUNC(cp)			((cp)->func)
404*4882a593Smuzhiyun 
405*4882a593Smuzhiyun #define BNX2X_HW_CID(bp, x)		((BP_PORT(bp) << 23) | \
406*4882a593Smuzhiyun 					 (BP_VN(bp) << 17) | (x))
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun #define BNX2X_SW_CID(x)			(x & 0x1ffff)
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun #define BNX2X_CL_QZONE_ID(bp, cli)					\
411*4882a593Smuzhiyun 		(BNX2X_CHIP_IS_E2_PLUS(bp) ? cli :			\
412*4882a593Smuzhiyun 		 cli + (BP_PORT(bp) * ETH_MAX_RX_CLIENTS_E1H))
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun #ifndef MAX_STAT_COUNTER_ID
415*4882a593Smuzhiyun #define MAX_STAT_COUNTER_ID						\
416*4882a593Smuzhiyun 	(CHIP_IS_E1H(bp) ? MAX_STAT_COUNTER_ID_E1H :			\
417*4882a593Smuzhiyun 	 ((BNX2X_CHIP_IS_E2_PLUS(bp)) ? MAX_STAT_COUNTER_ID_E2 :	\
418*4882a593Smuzhiyun 	  MAX_STAT_COUNTER_ID_E1))
419*4882a593Smuzhiyun #endif
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun #define CNIC_SUPPORTS_FCOE(cp)						\
422*4882a593Smuzhiyun 	(BNX2X_CHIP_IS_E2_PLUS(bp) && !NO_FCOE(bp))
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun #define CNIC_RAMROD_TMO			(HZ / 4)
425*4882a593Smuzhiyun 
426*4882a593Smuzhiyun #endif
427*4882a593Smuzhiyun 
428