1*4882a593Smuzhiyun /* Broadcom NetXtreme-C/E network driver. 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (c) 2014-2016 Broadcom Corporation 4*4882a593Smuzhiyun * Copyright (c) 2014-2018 Broadcom Limited 5*4882a593Smuzhiyun * Copyright (c) 2018-2020 Broadcom Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 8*4882a593Smuzhiyun * it under the terms of the GNU General Public License as published by 9*4882a593Smuzhiyun * the Free Software Foundation. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * DO NOT MODIFY!!! This file is automatically generated. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef _BNXT_HSI_H_ 15*4882a593Smuzhiyun #define _BNXT_HSI_H_ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* hwrm_cmd_hdr (size:128b/16B) */ 18*4882a593Smuzhiyun struct hwrm_cmd_hdr { 19*4882a593Smuzhiyun __le16 req_type; 20*4882a593Smuzhiyun __le16 cmpl_ring; 21*4882a593Smuzhiyun __le16 seq_id; 22*4882a593Smuzhiyun __le16 target_id; 23*4882a593Smuzhiyun __le64 resp_addr; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* hwrm_resp_hdr (size:64b/8B) */ 27*4882a593Smuzhiyun struct hwrm_resp_hdr { 28*4882a593Smuzhiyun __le16 error_code; 29*4882a593Smuzhiyun __le16 req_type; 30*4882a593Smuzhiyun __le16 seq_id; 31*4882a593Smuzhiyun __le16 resp_len; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define CMD_DISCR_TLV_ENCAP 0x8000UL 35*4882a593Smuzhiyun #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define TLV_TYPE_HWRM_REQUEST 0x1UL 39*4882a593Smuzhiyun #define TLV_TYPE_HWRM_RESPONSE 0x2UL 40*4882a593Smuzhiyun #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 41*4882a593Smuzhiyun #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL 42*4882a593Smuzhiyun #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL 43*4882a593Smuzhiyun #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL 44*4882a593Smuzhiyun #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 45*4882a593Smuzhiyun #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 46*4882a593Smuzhiyun #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 47*4882a593Smuzhiyun #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL 48*4882a593Smuzhiyun #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL 49*4882a593Smuzhiyun #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 50*4882a593Smuzhiyun #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL 51*4882a593Smuzhiyun #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL 52*4882a593Smuzhiyun #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* tlv (size:64b/8B) */ 56*4882a593Smuzhiyun struct tlv { 57*4882a593Smuzhiyun __le16 cmd_discr; 58*4882a593Smuzhiyun u8 reserved_8b; 59*4882a593Smuzhiyun u8 flags; 60*4882a593Smuzhiyun #define TLV_FLAGS_MORE 0x1UL 61*4882a593Smuzhiyun #define TLV_FLAGS_MORE_LAST 0x0UL 62*4882a593Smuzhiyun #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 63*4882a593Smuzhiyun #define TLV_FLAGS_REQUIRED 0x2UL 64*4882a593Smuzhiyun #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 65*4882a593Smuzhiyun #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 66*4882a593Smuzhiyun #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 67*4882a593Smuzhiyun __le16 tlv_type; 68*4882a593Smuzhiyun __le16 length; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* input (size:128b/16B) */ 72*4882a593Smuzhiyun struct input { 73*4882a593Smuzhiyun __le16 req_type; 74*4882a593Smuzhiyun __le16 cmpl_ring; 75*4882a593Smuzhiyun __le16 seq_id; 76*4882a593Smuzhiyun __le16 target_id; 77*4882a593Smuzhiyun __le64 resp_addr; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* output (size:64b/8B) */ 81*4882a593Smuzhiyun struct output { 82*4882a593Smuzhiyun __le16 error_code; 83*4882a593Smuzhiyun __le16 req_type; 84*4882a593Smuzhiyun __le16 seq_id; 85*4882a593Smuzhiyun __le16 resp_len; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* hwrm_short_input (size:128b/16B) */ 89*4882a593Smuzhiyun struct hwrm_short_input { 90*4882a593Smuzhiyun __le16 req_type; 91*4882a593Smuzhiyun __le16 signature; 92*4882a593Smuzhiyun #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 93*4882a593Smuzhiyun #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 94*4882a593Smuzhiyun __le16 target_id; 95*4882a593Smuzhiyun #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL 96*4882a593Smuzhiyun #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL 97*4882a593Smuzhiyun #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS 98*4882a593Smuzhiyun __le16 size; 99*4882a593Smuzhiyun __le64 req_addr; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* cmd_nums (size:64b/8B) */ 103*4882a593Smuzhiyun struct cmd_nums { 104*4882a593Smuzhiyun __le16 req_type; 105*4882a593Smuzhiyun #define HWRM_VER_GET 0x0UL 106*4882a593Smuzhiyun #define HWRM_ERROR_RECOVERY_QCFG 0xcUL 107*4882a593Smuzhiyun #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL 108*4882a593Smuzhiyun #define HWRM_FUNC_BUF_UNRGTR 0xeUL 109*4882a593Smuzhiyun #define HWRM_FUNC_VF_CFG 0xfUL 110*4882a593Smuzhiyun #define HWRM_RESERVED1 0x10UL 111*4882a593Smuzhiyun #define HWRM_FUNC_RESET 0x11UL 112*4882a593Smuzhiyun #define HWRM_FUNC_GETFID 0x12UL 113*4882a593Smuzhiyun #define HWRM_FUNC_VF_ALLOC 0x13UL 114*4882a593Smuzhiyun #define HWRM_FUNC_VF_FREE 0x14UL 115*4882a593Smuzhiyun #define HWRM_FUNC_QCAPS 0x15UL 116*4882a593Smuzhiyun #define HWRM_FUNC_QCFG 0x16UL 117*4882a593Smuzhiyun #define HWRM_FUNC_CFG 0x17UL 118*4882a593Smuzhiyun #define HWRM_FUNC_QSTATS 0x18UL 119*4882a593Smuzhiyun #define HWRM_FUNC_CLR_STATS 0x19UL 120*4882a593Smuzhiyun #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 121*4882a593Smuzhiyun #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 122*4882a593Smuzhiyun #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 123*4882a593Smuzhiyun #define HWRM_FUNC_DRV_RGTR 0x1dUL 124*4882a593Smuzhiyun #define HWRM_FUNC_DRV_QVER 0x1eUL 125*4882a593Smuzhiyun #define HWRM_FUNC_BUF_RGTR 0x1fUL 126*4882a593Smuzhiyun #define HWRM_PORT_PHY_CFG 0x20UL 127*4882a593Smuzhiyun #define HWRM_PORT_MAC_CFG 0x21UL 128*4882a593Smuzhiyun #define HWRM_PORT_TS_QUERY 0x22UL 129*4882a593Smuzhiyun #define HWRM_PORT_QSTATS 0x23UL 130*4882a593Smuzhiyun #define HWRM_PORT_LPBK_QSTATS 0x24UL 131*4882a593Smuzhiyun #define HWRM_PORT_CLR_STATS 0x25UL 132*4882a593Smuzhiyun #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 133*4882a593Smuzhiyun #define HWRM_PORT_PHY_QCFG 0x27UL 134*4882a593Smuzhiyun #define HWRM_PORT_MAC_QCFG 0x28UL 135*4882a593Smuzhiyun #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 136*4882a593Smuzhiyun #define HWRM_PORT_PHY_QCAPS 0x2aUL 137*4882a593Smuzhiyun #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 138*4882a593Smuzhiyun #define HWRM_PORT_PHY_I2C_READ 0x2cUL 139*4882a593Smuzhiyun #define HWRM_PORT_LED_CFG 0x2dUL 140*4882a593Smuzhiyun #define HWRM_PORT_LED_QCFG 0x2eUL 141*4882a593Smuzhiyun #define HWRM_PORT_LED_QCAPS 0x2fUL 142*4882a593Smuzhiyun #define HWRM_QUEUE_QPORTCFG 0x30UL 143*4882a593Smuzhiyun #define HWRM_QUEUE_QCFG 0x31UL 144*4882a593Smuzhiyun #define HWRM_QUEUE_CFG 0x32UL 145*4882a593Smuzhiyun #define HWRM_FUNC_VLAN_CFG 0x33UL 146*4882a593Smuzhiyun #define HWRM_FUNC_VLAN_QCFG 0x34UL 147*4882a593Smuzhiyun #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 148*4882a593Smuzhiyun #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 149*4882a593Smuzhiyun #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 150*4882a593Smuzhiyun #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 151*4882a593Smuzhiyun #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 152*4882a593Smuzhiyun #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 153*4882a593Smuzhiyun #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 154*4882a593Smuzhiyun #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 155*4882a593Smuzhiyun #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 156*4882a593Smuzhiyun #define HWRM_VNIC_ALLOC 0x40UL 157*4882a593Smuzhiyun #define HWRM_VNIC_FREE 0x41UL 158*4882a593Smuzhiyun #define HWRM_VNIC_CFG 0x42UL 159*4882a593Smuzhiyun #define HWRM_VNIC_QCFG 0x43UL 160*4882a593Smuzhiyun #define HWRM_VNIC_TPA_CFG 0x44UL 161*4882a593Smuzhiyun #define HWRM_VNIC_TPA_QCFG 0x45UL 162*4882a593Smuzhiyun #define HWRM_VNIC_RSS_CFG 0x46UL 163*4882a593Smuzhiyun #define HWRM_VNIC_RSS_QCFG 0x47UL 164*4882a593Smuzhiyun #define HWRM_VNIC_PLCMODES_CFG 0x48UL 165*4882a593Smuzhiyun #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 166*4882a593Smuzhiyun #define HWRM_VNIC_QCAPS 0x4aUL 167*4882a593Smuzhiyun #define HWRM_RING_ALLOC 0x50UL 168*4882a593Smuzhiyun #define HWRM_RING_FREE 0x51UL 169*4882a593Smuzhiyun #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 170*4882a593Smuzhiyun #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 171*4882a593Smuzhiyun #define HWRM_RING_AGGINT_QCAPS 0x54UL 172*4882a593Smuzhiyun #define HWRM_RING_SCHQ_ALLOC 0x55UL 173*4882a593Smuzhiyun #define HWRM_RING_SCHQ_CFG 0x56UL 174*4882a593Smuzhiyun #define HWRM_RING_SCHQ_FREE 0x57UL 175*4882a593Smuzhiyun #define HWRM_RING_RESET 0x5eUL 176*4882a593Smuzhiyun #define HWRM_RING_GRP_ALLOC 0x60UL 177*4882a593Smuzhiyun #define HWRM_RING_GRP_FREE 0x61UL 178*4882a593Smuzhiyun #define HWRM_RING_CFG 0x62UL 179*4882a593Smuzhiyun #define HWRM_RING_QCFG 0x63UL 180*4882a593Smuzhiyun #define HWRM_RESERVED5 0x64UL 181*4882a593Smuzhiyun #define HWRM_RESERVED6 0x65UL 182*4882a593Smuzhiyun #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 183*4882a593Smuzhiyun #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 184*4882a593Smuzhiyun #define HWRM_QUEUE_MPLS_QCAPS 0x80UL 185*4882a593Smuzhiyun #define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL 186*4882a593Smuzhiyun #define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL 187*4882a593Smuzhiyun #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 188*4882a593Smuzhiyun #define HWRM_CFA_L2_FILTER_FREE 0x91UL 189*4882a593Smuzhiyun #define HWRM_CFA_L2_FILTER_CFG 0x92UL 190*4882a593Smuzhiyun #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 191*4882a593Smuzhiyun #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 192*4882a593Smuzhiyun #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 193*4882a593Smuzhiyun #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 194*4882a593Smuzhiyun #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 195*4882a593Smuzhiyun #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 196*4882a593Smuzhiyun #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 197*4882a593Smuzhiyun #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 198*4882a593Smuzhiyun #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 199*4882a593Smuzhiyun #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 200*4882a593Smuzhiyun #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 201*4882a593Smuzhiyun #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 202*4882a593Smuzhiyun #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 203*4882a593Smuzhiyun #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 204*4882a593Smuzhiyun #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 205*4882a593Smuzhiyun #define HWRM_STAT_CTX_ENG_QUERY 0xafUL 206*4882a593Smuzhiyun #define HWRM_STAT_CTX_ALLOC 0xb0UL 207*4882a593Smuzhiyun #define HWRM_STAT_CTX_FREE 0xb1UL 208*4882a593Smuzhiyun #define HWRM_STAT_CTX_QUERY 0xb2UL 209*4882a593Smuzhiyun #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 210*4882a593Smuzhiyun #define HWRM_PORT_QSTATS_EXT 0xb4UL 211*4882a593Smuzhiyun #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL 212*4882a593Smuzhiyun #define HWRM_PORT_PHY_MDIO_READ 0xb6UL 213*4882a593Smuzhiyun #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL 214*4882a593Smuzhiyun #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL 215*4882a593Smuzhiyun #define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL 216*4882a593Smuzhiyun #define HWRM_RESERVED7 0xbaUL 217*4882a593Smuzhiyun #define HWRM_PORT_TX_FIR_CFG 0xbbUL 218*4882a593Smuzhiyun #define HWRM_PORT_TX_FIR_QCFG 0xbcUL 219*4882a593Smuzhiyun #define HWRM_PORT_ECN_QSTATS 0xbdUL 220*4882a593Smuzhiyun #define HWRM_FW_RESET 0xc0UL 221*4882a593Smuzhiyun #define HWRM_FW_QSTATUS 0xc1UL 222*4882a593Smuzhiyun #define HWRM_FW_HEALTH_CHECK 0xc2UL 223*4882a593Smuzhiyun #define HWRM_FW_SYNC 0xc3UL 224*4882a593Smuzhiyun #define HWRM_FW_STATE_QCAPS 0xc4UL 225*4882a593Smuzhiyun #define HWRM_FW_STATE_QUIESCE 0xc5UL 226*4882a593Smuzhiyun #define HWRM_FW_STATE_BACKUP 0xc6UL 227*4882a593Smuzhiyun #define HWRM_FW_STATE_RESTORE 0xc7UL 228*4882a593Smuzhiyun #define HWRM_FW_SET_TIME 0xc8UL 229*4882a593Smuzhiyun #define HWRM_FW_GET_TIME 0xc9UL 230*4882a593Smuzhiyun #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 231*4882a593Smuzhiyun #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 232*4882a593Smuzhiyun #define HWRM_FW_IPC_MAILBOX 0xccUL 233*4882a593Smuzhiyun #define HWRM_FW_ECN_CFG 0xcdUL 234*4882a593Smuzhiyun #define HWRM_FW_ECN_QCFG 0xceUL 235*4882a593Smuzhiyun #define HWRM_FW_SECURE_CFG 0xcfUL 236*4882a593Smuzhiyun #define HWRM_EXEC_FWD_RESP 0xd0UL 237*4882a593Smuzhiyun #define HWRM_REJECT_FWD_RESP 0xd1UL 238*4882a593Smuzhiyun #define HWRM_FWD_RESP 0xd2UL 239*4882a593Smuzhiyun #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 240*4882a593Smuzhiyun #define HWRM_OEM_CMD 0xd4UL 241*4882a593Smuzhiyun #define HWRM_PORT_PRBS_TEST 0xd5UL 242*4882a593Smuzhiyun #define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL 243*4882a593Smuzhiyun #define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL 244*4882a593Smuzhiyun #define HWRM_FW_STATE_UNQUIESCE 0xd8UL 245*4882a593Smuzhiyun #define HWRM_PORT_DSC_DUMP 0xd9UL 246*4882a593Smuzhiyun #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 247*4882a593Smuzhiyun #define HWRM_REG_POWER_QUERY 0xe1UL 248*4882a593Smuzhiyun #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL 249*4882a593Smuzhiyun #define HWRM_REG_POWER_HISTOGRAM 0xe3UL 250*4882a593Smuzhiyun #define HWRM_WOL_FILTER_ALLOC 0xf0UL 251*4882a593Smuzhiyun #define HWRM_WOL_FILTER_FREE 0xf1UL 252*4882a593Smuzhiyun #define HWRM_WOL_FILTER_QCFG 0xf2UL 253*4882a593Smuzhiyun #define HWRM_WOL_REASON_QCFG 0xf3UL 254*4882a593Smuzhiyun #define HWRM_CFA_METER_QCAPS 0xf4UL 255*4882a593Smuzhiyun #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 256*4882a593Smuzhiyun #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 257*4882a593Smuzhiyun #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 258*4882a593Smuzhiyun #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 259*4882a593Smuzhiyun #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 260*4882a593Smuzhiyun #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL 261*4882a593Smuzhiyun #define HWRM_CFA_VFR_ALLOC 0xfdUL 262*4882a593Smuzhiyun #define HWRM_CFA_VFR_FREE 0xfeUL 263*4882a593Smuzhiyun #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 264*4882a593Smuzhiyun #define HWRM_CFA_VF_PAIR_FREE 0x101UL 265*4882a593Smuzhiyun #define HWRM_CFA_VF_PAIR_INFO 0x102UL 266*4882a593Smuzhiyun #define HWRM_CFA_FLOW_ALLOC 0x103UL 267*4882a593Smuzhiyun #define HWRM_CFA_FLOW_FREE 0x104UL 268*4882a593Smuzhiyun #define HWRM_CFA_FLOW_FLUSH 0x105UL 269*4882a593Smuzhiyun #define HWRM_CFA_FLOW_STATS 0x106UL 270*4882a593Smuzhiyun #define HWRM_CFA_FLOW_INFO 0x107UL 271*4882a593Smuzhiyun #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 272*4882a593Smuzhiyun #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 273*4882a593Smuzhiyun #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 274*4882a593Smuzhiyun #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 275*4882a593Smuzhiyun #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 276*4882a593Smuzhiyun #define HWRM_CFA_PAIR_ALLOC 0x10dUL 277*4882a593Smuzhiyun #define HWRM_CFA_PAIR_FREE 0x10eUL 278*4882a593Smuzhiyun #define HWRM_CFA_PAIR_INFO 0x10fUL 279*4882a593Smuzhiyun #define HWRM_FW_IPC_MSG 0x110UL 280*4882a593Smuzhiyun #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 281*4882a593Smuzhiyun #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 282*4882a593Smuzhiyun #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL 283*4882a593Smuzhiyun #define HWRM_CFA_FLOW_AGING_CFG 0x114UL 284*4882a593Smuzhiyun #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL 285*4882a593Smuzhiyun #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL 286*4882a593Smuzhiyun #define HWRM_CFA_CTX_MEM_RGTR 0x117UL 287*4882a593Smuzhiyun #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL 288*4882a593Smuzhiyun #define HWRM_CFA_CTX_MEM_QCTX 0x119UL 289*4882a593Smuzhiyun #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL 290*4882a593Smuzhiyun #define HWRM_CFA_COUNTER_QCAPS 0x11bUL 291*4882a593Smuzhiyun #define HWRM_CFA_COUNTER_CFG 0x11cUL 292*4882a593Smuzhiyun #define HWRM_CFA_COUNTER_QCFG 0x11dUL 293*4882a593Smuzhiyun #define HWRM_CFA_COUNTER_QSTATS 0x11eUL 294*4882a593Smuzhiyun #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL 295*4882a593Smuzhiyun #define HWRM_CFA_EEM_QCAPS 0x120UL 296*4882a593Smuzhiyun #define HWRM_CFA_EEM_CFG 0x121UL 297*4882a593Smuzhiyun #define HWRM_CFA_EEM_QCFG 0x122UL 298*4882a593Smuzhiyun #define HWRM_CFA_EEM_OP 0x123UL 299*4882a593Smuzhiyun #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL 300*4882a593Smuzhiyun #define HWRM_CFA_TFLIB 0x125UL 301*4882a593Smuzhiyun #define HWRM_ENGINE_CKV_STATUS 0x12eUL 302*4882a593Smuzhiyun #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 303*4882a593Smuzhiyun #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 304*4882a593Smuzhiyun #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 305*4882a593Smuzhiyun #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 306*4882a593Smuzhiyun #define HWRM_ENGINE_CKV_FLUSH 0x133UL 307*4882a593Smuzhiyun #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 308*4882a593Smuzhiyun #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 309*4882a593Smuzhiyun #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL 310*4882a593Smuzhiyun #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL 311*4882a593Smuzhiyun #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 312*4882a593Smuzhiyun #define HWRM_ENGINE_QG_QUERY 0x13dUL 313*4882a593Smuzhiyun #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 314*4882a593Smuzhiyun #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 315*4882a593Smuzhiyun #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 316*4882a593Smuzhiyun #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 317*4882a593Smuzhiyun #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 318*4882a593Smuzhiyun #define HWRM_ENGINE_QG_METER_BIND 0x143UL 319*4882a593Smuzhiyun #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 320*4882a593Smuzhiyun #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 321*4882a593Smuzhiyun #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 322*4882a593Smuzhiyun #define HWRM_ENGINE_SG_QUERY 0x147UL 323*4882a593Smuzhiyun #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 324*4882a593Smuzhiyun #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 325*4882a593Smuzhiyun #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 326*4882a593Smuzhiyun #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 327*4882a593Smuzhiyun #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 328*4882a593Smuzhiyun #define HWRM_ENGINE_STATS_CONFIG 0x155UL 329*4882a593Smuzhiyun #define HWRM_ENGINE_STATS_CLEAR 0x156UL 330*4882a593Smuzhiyun #define HWRM_ENGINE_STATS_QUERY 0x157UL 331*4882a593Smuzhiyun #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL 332*4882a593Smuzhiyun #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 333*4882a593Smuzhiyun #define HWRM_ENGINE_RQ_FREE 0x15fUL 334*4882a593Smuzhiyun #define HWRM_ENGINE_CQ_ALLOC 0x160UL 335*4882a593Smuzhiyun #define HWRM_ENGINE_CQ_FREE 0x161UL 336*4882a593Smuzhiyun #define HWRM_ENGINE_NQ_ALLOC 0x162UL 337*4882a593Smuzhiyun #define HWRM_ENGINE_NQ_FREE 0x163UL 338*4882a593Smuzhiyun #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 339*4882a593Smuzhiyun #define HWRM_ENGINE_FUNC_QCFG 0x165UL 340*4882a593Smuzhiyun #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 341*4882a593Smuzhiyun #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 342*4882a593Smuzhiyun #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL 343*4882a593Smuzhiyun #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL 344*4882a593Smuzhiyun #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL 345*4882a593Smuzhiyun #define HWRM_FUNC_VF_BW_CFG 0x195UL 346*4882a593Smuzhiyun #define HWRM_FUNC_VF_BW_QCFG 0x196UL 347*4882a593Smuzhiyun #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL 348*4882a593Smuzhiyun #define HWRM_FUNC_QSTATS_EXT 0x198UL 349*4882a593Smuzhiyun #define HWRM_STAT_EXT_CTX_QUERY 0x199UL 350*4882a593Smuzhiyun #define HWRM_SELFTEST_QLIST 0x200UL 351*4882a593Smuzhiyun #define HWRM_SELFTEST_EXEC 0x201UL 352*4882a593Smuzhiyun #define HWRM_SELFTEST_IRQ 0x202UL 353*4882a593Smuzhiyun #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 354*4882a593Smuzhiyun #define HWRM_PCIE_QSTATS 0x204UL 355*4882a593Smuzhiyun #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL 356*4882a593Smuzhiyun #define HWRM_MFG_TIMERS_QUERY 0x206UL 357*4882a593Smuzhiyun #define HWRM_MFG_OTP_CFG 0x207UL 358*4882a593Smuzhiyun #define HWRM_MFG_OTP_QCFG 0x208UL 359*4882a593Smuzhiyun #define HWRM_MFG_HDMA_TEST 0x209UL 360*4882a593Smuzhiyun #define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL 361*4882a593Smuzhiyun #define HWRM_MFG_FRU_EEPROM_READ 0x20bUL 362*4882a593Smuzhiyun #define HWRM_TF 0x2bcUL 363*4882a593Smuzhiyun #define HWRM_TF_VERSION_GET 0x2bdUL 364*4882a593Smuzhiyun #define HWRM_TF_SESSION_OPEN 0x2c6UL 365*4882a593Smuzhiyun #define HWRM_TF_SESSION_ATTACH 0x2c7UL 366*4882a593Smuzhiyun #define HWRM_TF_SESSION_REGISTER 0x2c8UL 367*4882a593Smuzhiyun #define HWRM_TF_SESSION_UNREGISTER 0x2c9UL 368*4882a593Smuzhiyun #define HWRM_TF_SESSION_CLOSE 0x2caUL 369*4882a593Smuzhiyun #define HWRM_TF_SESSION_QCFG 0x2cbUL 370*4882a593Smuzhiyun #define HWRM_TF_SESSION_RESC_QCAPS 0x2ccUL 371*4882a593Smuzhiyun #define HWRM_TF_SESSION_RESC_ALLOC 0x2cdUL 372*4882a593Smuzhiyun #define HWRM_TF_SESSION_RESC_FREE 0x2ceUL 373*4882a593Smuzhiyun #define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL 374*4882a593Smuzhiyun #define HWRM_TF_TBL_TYPE_GET 0x2daUL 375*4882a593Smuzhiyun #define HWRM_TF_TBL_TYPE_SET 0x2dbUL 376*4882a593Smuzhiyun #define HWRM_TF_TBL_TYPE_BULK_GET 0x2dcUL 377*4882a593Smuzhiyun #define HWRM_TF_CTXT_MEM_ALLOC 0x2e2UL 378*4882a593Smuzhiyun #define HWRM_TF_CTXT_MEM_FREE 0x2e3UL 379*4882a593Smuzhiyun #define HWRM_TF_CTXT_MEM_RGTR 0x2e4UL 380*4882a593Smuzhiyun #define HWRM_TF_CTXT_MEM_UNRGTR 0x2e5UL 381*4882a593Smuzhiyun #define HWRM_TF_EXT_EM_QCAPS 0x2e6UL 382*4882a593Smuzhiyun #define HWRM_TF_EXT_EM_OP 0x2e7UL 383*4882a593Smuzhiyun #define HWRM_TF_EXT_EM_CFG 0x2e8UL 384*4882a593Smuzhiyun #define HWRM_TF_EXT_EM_QCFG 0x2e9UL 385*4882a593Smuzhiyun #define HWRM_TF_EM_INSERT 0x2eaUL 386*4882a593Smuzhiyun #define HWRM_TF_EM_DELETE 0x2ebUL 387*4882a593Smuzhiyun #define HWRM_TF_TCAM_SET 0x2f8UL 388*4882a593Smuzhiyun #define HWRM_TF_TCAM_GET 0x2f9UL 389*4882a593Smuzhiyun #define HWRM_TF_TCAM_MOVE 0x2faUL 390*4882a593Smuzhiyun #define HWRM_TF_TCAM_FREE 0x2fbUL 391*4882a593Smuzhiyun #define HWRM_TF_GLOBAL_CFG_SET 0x2fcUL 392*4882a593Smuzhiyun #define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL 393*4882a593Smuzhiyun #define HWRM_TF_IF_TBL_SET 0x2feUL 394*4882a593Smuzhiyun #define HWRM_TF_IF_TBL_GET 0x2ffUL 395*4882a593Smuzhiyun #define HWRM_SV 0x400UL 396*4882a593Smuzhiyun #define HWRM_DBG_READ_DIRECT 0xff10UL 397*4882a593Smuzhiyun #define HWRM_DBG_READ_INDIRECT 0xff11UL 398*4882a593Smuzhiyun #define HWRM_DBG_WRITE_DIRECT 0xff12UL 399*4882a593Smuzhiyun #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 400*4882a593Smuzhiyun #define HWRM_DBG_DUMP 0xff14UL 401*4882a593Smuzhiyun #define HWRM_DBG_ERASE_NVM 0xff15UL 402*4882a593Smuzhiyun #define HWRM_DBG_CFG 0xff16UL 403*4882a593Smuzhiyun #define HWRM_DBG_COREDUMP_LIST 0xff17UL 404*4882a593Smuzhiyun #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 405*4882a593Smuzhiyun #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 406*4882a593Smuzhiyun #define HWRM_DBG_FW_CLI 0xff1aUL 407*4882a593Smuzhiyun #define HWRM_DBG_I2C_CMD 0xff1bUL 408*4882a593Smuzhiyun #define HWRM_DBG_RING_INFO_GET 0xff1cUL 409*4882a593Smuzhiyun #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL 410*4882a593Smuzhiyun #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL 411*4882a593Smuzhiyun #define HWRM_DBG_DRV_TRACE 0xff1fUL 412*4882a593Smuzhiyun #define HWRM_DBG_QCAPS 0xff20UL 413*4882a593Smuzhiyun #define HWRM_DBG_QCFG 0xff21UL 414*4882a593Smuzhiyun #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL 415*4882a593Smuzhiyun #define HWRM_NVM_REQ_ARBITRATION 0xffedUL 416*4882a593Smuzhiyun #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 417*4882a593Smuzhiyun #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 418*4882a593Smuzhiyun #define HWRM_NVM_FLUSH 0xfff0UL 419*4882a593Smuzhiyun #define HWRM_NVM_GET_VARIABLE 0xfff1UL 420*4882a593Smuzhiyun #define HWRM_NVM_SET_VARIABLE 0xfff2UL 421*4882a593Smuzhiyun #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 422*4882a593Smuzhiyun #define HWRM_NVM_MODIFY 0xfff4UL 423*4882a593Smuzhiyun #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 424*4882a593Smuzhiyun #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 425*4882a593Smuzhiyun #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 426*4882a593Smuzhiyun #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 427*4882a593Smuzhiyun #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 428*4882a593Smuzhiyun #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 429*4882a593Smuzhiyun #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 430*4882a593Smuzhiyun #define HWRM_NVM_RAW_DUMP 0xfffcUL 431*4882a593Smuzhiyun #define HWRM_NVM_READ 0xfffdUL 432*4882a593Smuzhiyun #define HWRM_NVM_WRITE 0xfffeUL 433*4882a593Smuzhiyun #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 434*4882a593Smuzhiyun #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 435*4882a593Smuzhiyun __le16 unused_0[3]; 436*4882a593Smuzhiyun }; 437*4882a593Smuzhiyun 438*4882a593Smuzhiyun /* ret_codes (size:64b/8B) */ 439*4882a593Smuzhiyun struct ret_codes { 440*4882a593Smuzhiyun __le16 error_code; 441*4882a593Smuzhiyun #define HWRM_ERR_CODE_SUCCESS 0x0UL 442*4882a593Smuzhiyun #define HWRM_ERR_CODE_FAIL 0x1UL 443*4882a593Smuzhiyun #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 444*4882a593Smuzhiyun #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 445*4882a593Smuzhiyun #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 446*4882a593Smuzhiyun #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 447*4882a593Smuzhiyun #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 448*4882a593Smuzhiyun #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 449*4882a593Smuzhiyun #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 450*4882a593Smuzhiyun #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 451*4882a593Smuzhiyun #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL 452*4882a593Smuzhiyun #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL 453*4882a593Smuzhiyun #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL 454*4882a593Smuzhiyun #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL 455*4882a593Smuzhiyun #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL 456*4882a593Smuzhiyun #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 457*4882a593Smuzhiyun #define HWRM_ERR_CODE_BUSY 0x10UL 458*4882a593Smuzhiyun #define HWRM_ERR_CODE_RESOURCE_LOCKED 0x11UL 459*4882a593Smuzhiyun #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 460*4882a593Smuzhiyun #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 461*4882a593Smuzhiyun #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 462*4882a593Smuzhiyun #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 463*4882a593Smuzhiyun __le16 unused_0[3]; 464*4882a593Smuzhiyun }; 465*4882a593Smuzhiyun 466*4882a593Smuzhiyun /* hwrm_err_output (size:128b/16B) */ 467*4882a593Smuzhiyun struct hwrm_err_output { 468*4882a593Smuzhiyun __le16 error_code; 469*4882a593Smuzhiyun __le16 req_type; 470*4882a593Smuzhiyun __le16 seq_id; 471*4882a593Smuzhiyun __le16 resp_len; 472*4882a593Smuzhiyun __le32 opaque_0; 473*4882a593Smuzhiyun __le16 opaque_1; 474*4882a593Smuzhiyun u8 cmd_err; 475*4882a593Smuzhiyun u8 valid; 476*4882a593Smuzhiyun }; 477*4882a593Smuzhiyun #define HWRM_NA_SIGNATURE ((__le32)(-1)) 478*4882a593Smuzhiyun #define HWRM_MAX_REQ_LEN 128 479*4882a593Smuzhiyun #define HWRM_MAX_RESP_LEN 704 480*4882a593Smuzhiyun #define HW_HASH_INDEX_SIZE 0x80 481*4882a593Smuzhiyun #define HW_HASH_KEY_SIZE 40 482*4882a593Smuzhiyun #define HWRM_RESP_VALID_KEY 1 483*4882a593Smuzhiyun #define HWRM_TARGET_ID_BONO 0xFFF8 484*4882a593Smuzhiyun #define HWRM_TARGET_ID_KONG 0xFFF9 485*4882a593Smuzhiyun #define HWRM_TARGET_ID_APE 0xFFFA 486*4882a593Smuzhiyun #define HWRM_TARGET_ID_TOOLS 0xFFFD 487*4882a593Smuzhiyun #define HWRM_VERSION_MAJOR 1 488*4882a593Smuzhiyun #define HWRM_VERSION_MINOR 10 489*4882a593Smuzhiyun #define HWRM_VERSION_UPDATE 1 490*4882a593Smuzhiyun #define HWRM_VERSION_RSVD 68 491*4882a593Smuzhiyun #define HWRM_VERSION_STR "1.10.1.68" 492*4882a593Smuzhiyun 493*4882a593Smuzhiyun /* hwrm_ver_get_input (size:192b/24B) */ 494*4882a593Smuzhiyun struct hwrm_ver_get_input { 495*4882a593Smuzhiyun __le16 req_type; 496*4882a593Smuzhiyun __le16 cmpl_ring; 497*4882a593Smuzhiyun __le16 seq_id; 498*4882a593Smuzhiyun __le16 target_id; 499*4882a593Smuzhiyun __le64 resp_addr; 500*4882a593Smuzhiyun u8 hwrm_intf_maj; 501*4882a593Smuzhiyun u8 hwrm_intf_min; 502*4882a593Smuzhiyun u8 hwrm_intf_upd; 503*4882a593Smuzhiyun u8 unused_0[5]; 504*4882a593Smuzhiyun }; 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun /* hwrm_ver_get_output (size:1408b/176B) */ 507*4882a593Smuzhiyun struct hwrm_ver_get_output { 508*4882a593Smuzhiyun __le16 error_code; 509*4882a593Smuzhiyun __le16 req_type; 510*4882a593Smuzhiyun __le16 seq_id; 511*4882a593Smuzhiyun __le16 resp_len; 512*4882a593Smuzhiyun u8 hwrm_intf_maj_8b; 513*4882a593Smuzhiyun u8 hwrm_intf_min_8b; 514*4882a593Smuzhiyun u8 hwrm_intf_upd_8b; 515*4882a593Smuzhiyun u8 hwrm_intf_rsvd_8b; 516*4882a593Smuzhiyun u8 hwrm_fw_maj_8b; 517*4882a593Smuzhiyun u8 hwrm_fw_min_8b; 518*4882a593Smuzhiyun u8 hwrm_fw_bld_8b; 519*4882a593Smuzhiyun u8 hwrm_fw_rsvd_8b; 520*4882a593Smuzhiyun u8 mgmt_fw_maj_8b; 521*4882a593Smuzhiyun u8 mgmt_fw_min_8b; 522*4882a593Smuzhiyun u8 mgmt_fw_bld_8b; 523*4882a593Smuzhiyun u8 mgmt_fw_rsvd_8b; 524*4882a593Smuzhiyun u8 netctrl_fw_maj_8b; 525*4882a593Smuzhiyun u8 netctrl_fw_min_8b; 526*4882a593Smuzhiyun u8 netctrl_fw_bld_8b; 527*4882a593Smuzhiyun u8 netctrl_fw_rsvd_8b; 528*4882a593Smuzhiyun __le32 dev_caps_cfg; 529*4882a593Smuzhiyun #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 530*4882a593Smuzhiyun #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 531*4882a593Smuzhiyun #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 532*4882a593Smuzhiyun #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 533*4882a593Smuzhiyun #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL 534*4882a593Smuzhiyun #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL 535*4882a593Smuzhiyun #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 536*4882a593Smuzhiyun #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 537*4882a593Smuzhiyun #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 538*4882a593Smuzhiyun #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL 539*4882a593Smuzhiyun #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL 540*4882a593Smuzhiyun #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL 541*4882a593Smuzhiyun #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL 542*4882a593Smuzhiyun #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL 543*4882a593Smuzhiyun #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL 544*4882a593Smuzhiyun u8 roce_fw_maj_8b; 545*4882a593Smuzhiyun u8 roce_fw_min_8b; 546*4882a593Smuzhiyun u8 roce_fw_bld_8b; 547*4882a593Smuzhiyun u8 roce_fw_rsvd_8b; 548*4882a593Smuzhiyun char hwrm_fw_name[16]; 549*4882a593Smuzhiyun char mgmt_fw_name[16]; 550*4882a593Smuzhiyun char netctrl_fw_name[16]; 551*4882a593Smuzhiyun char active_pkg_name[16]; 552*4882a593Smuzhiyun char roce_fw_name[16]; 553*4882a593Smuzhiyun __le16 chip_num; 554*4882a593Smuzhiyun u8 chip_rev; 555*4882a593Smuzhiyun u8 chip_metal; 556*4882a593Smuzhiyun u8 chip_bond_id; 557*4882a593Smuzhiyun u8 chip_platform_type; 558*4882a593Smuzhiyun #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 559*4882a593Smuzhiyun #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 560*4882a593Smuzhiyun #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 561*4882a593Smuzhiyun #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 562*4882a593Smuzhiyun __le16 max_req_win_len; 563*4882a593Smuzhiyun __le16 max_resp_len; 564*4882a593Smuzhiyun __le16 def_req_timeout; 565*4882a593Smuzhiyun u8 flags; 566*4882a593Smuzhiyun #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 567*4882a593Smuzhiyun #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 568*4882a593Smuzhiyun u8 unused_0[2]; 569*4882a593Smuzhiyun u8 always_1; 570*4882a593Smuzhiyun __le16 hwrm_intf_major; 571*4882a593Smuzhiyun __le16 hwrm_intf_minor; 572*4882a593Smuzhiyun __le16 hwrm_intf_build; 573*4882a593Smuzhiyun __le16 hwrm_intf_patch; 574*4882a593Smuzhiyun __le16 hwrm_fw_major; 575*4882a593Smuzhiyun __le16 hwrm_fw_minor; 576*4882a593Smuzhiyun __le16 hwrm_fw_build; 577*4882a593Smuzhiyun __le16 hwrm_fw_patch; 578*4882a593Smuzhiyun __le16 mgmt_fw_major; 579*4882a593Smuzhiyun __le16 mgmt_fw_minor; 580*4882a593Smuzhiyun __le16 mgmt_fw_build; 581*4882a593Smuzhiyun __le16 mgmt_fw_patch; 582*4882a593Smuzhiyun __le16 netctrl_fw_major; 583*4882a593Smuzhiyun __le16 netctrl_fw_minor; 584*4882a593Smuzhiyun __le16 netctrl_fw_build; 585*4882a593Smuzhiyun __le16 netctrl_fw_patch; 586*4882a593Smuzhiyun __le16 roce_fw_major; 587*4882a593Smuzhiyun __le16 roce_fw_minor; 588*4882a593Smuzhiyun __le16 roce_fw_build; 589*4882a593Smuzhiyun __le16 roce_fw_patch; 590*4882a593Smuzhiyun __le16 max_ext_req_len; 591*4882a593Smuzhiyun u8 unused_1[5]; 592*4882a593Smuzhiyun u8 valid; 593*4882a593Smuzhiyun }; 594*4882a593Smuzhiyun 595*4882a593Smuzhiyun /* eject_cmpl (size:128b/16B) */ 596*4882a593Smuzhiyun struct eject_cmpl { 597*4882a593Smuzhiyun __le16 type; 598*4882a593Smuzhiyun #define EJECT_CMPL_TYPE_MASK 0x3fUL 599*4882a593Smuzhiyun #define EJECT_CMPL_TYPE_SFT 0 600*4882a593Smuzhiyun #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 601*4882a593Smuzhiyun #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 602*4882a593Smuzhiyun #define EJECT_CMPL_FLAGS_MASK 0xffc0UL 603*4882a593Smuzhiyun #define EJECT_CMPL_FLAGS_SFT 6 604*4882a593Smuzhiyun #define EJECT_CMPL_FLAGS_ERROR 0x40UL 605*4882a593Smuzhiyun __le16 len; 606*4882a593Smuzhiyun __le32 opaque; 607*4882a593Smuzhiyun __le16 v; 608*4882a593Smuzhiyun #define EJECT_CMPL_V 0x1UL 609*4882a593Smuzhiyun #define EJECT_CMPL_ERRORS_MASK 0xfffeUL 610*4882a593Smuzhiyun #define EJECT_CMPL_ERRORS_SFT 1 611*4882a593Smuzhiyun #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL 612*4882a593Smuzhiyun #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 613*4882a593Smuzhiyun #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1) 614*4882a593Smuzhiyun #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1) 615*4882a593Smuzhiyun #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1) 616*4882a593Smuzhiyun #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1) 617*4882a593Smuzhiyun #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH 618*4882a593Smuzhiyun __le16 reserved16; 619*4882a593Smuzhiyun __le32 unused_2; 620*4882a593Smuzhiyun }; 621*4882a593Smuzhiyun 622*4882a593Smuzhiyun /* hwrm_cmpl (size:128b/16B) */ 623*4882a593Smuzhiyun struct hwrm_cmpl { 624*4882a593Smuzhiyun __le16 type; 625*4882a593Smuzhiyun #define CMPL_TYPE_MASK 0x3fUL 626*4882a593Smuzhiyun #define CMPL_TYPE_SFT 0 627*4882a593Smuzhiyun #define CMPL_TYPE_HWRM_DONE 0x20UL 628*4882a593Smuzhiyun #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 629*4882a593Smuzhiyun __le16 sequence_id; 630*4882a593Smuzhiyun __le32 unused_1; 631*4882a593Smuzhiyun __le32 v; 632*4882a593Smuzhiyun #define CMPL_V 0x1UL 633*4882a593Smuzhiyun __le32 unused_3; 634*4882a593Smuzhiyun }; 635*4882a593Smuzhiyun 636*4882a593Smuzhiyun /* hwrm_fwd_req_cmpl (size:128b/16B) */ 637*4882a593Smuzhiyun struct hwrm_fwd_req_cmpl { 638*4882a593Smuzhiyun __le16 req_len_type; 639*4882a593Smuzhiyun #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 640*4882a593Smuzhiyun #define FWD_REQ_CMPL_TYPE_SFT 0 641*4882a593Smuzhiyun #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 642*4882a593Smuzhiyun #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 643*4882a593Smuzhiyun #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 644*4882a593Smuzhiyun #define FWD_REQ_CMPL_REQ_LEN_SFT 6 645*4882a593Smuzhiyun __le16 source_id; 646*4882a593Smuzhiyun __le32 unused0; 647*4882a593Smuzhiyun __le32 req_buf_addr_v[2]; 648*4882a593Smuzhiyun #define FWD_REQ_CMPL_V 0x1UL 649*4882a593Smuzhiyun #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 650*4882a593Smuzhiyun #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 651*4882a593Smuzhiyun }; 652*4882a593Smuzhiyun 653*4882a593Smuzhiyun /* hwrm_fwd_resp_cmpl (size:128b/16B) */ 654*4882a593Smuzhiyun struct hwrm_fwd_resp_cmpl { 655*4882a593Smuzhiyun __le16 type; 656*4882a593Smuzhiyun #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 657*4882a593Smuzhiyun #define FWD_RESP_CMPL_TYPE_SFT 0 658*4882a593Smuzhiyun #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 659*4882a593Smuzhiyun #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 660*4882a593Smuzhiyun __le16 source_id; 661*4882a593Smuzhiyun __le16 resp_len; 662*4882a593Smuzhiyun __le16 unused_1; 663*4882a593Smuzhiyun __le32 resp_buf_addr_v[2]; 664*4882a593Smuzhiyun #define FWD_RESP_CMPL_V 0x1UL 665*4882a593Smuzhiyun #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 666*4882a593Smuzhiyun #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 667*4882a593Smuzhiyun }; 668*4882a593Smuzhiyun 669*4882a593Smuzhiyun /* hwrm_async_event_cmpl (size:128b/16B) */ 670*4882a593Smuzhiyun struct hwrm_async_event_cmpl { 671*4882a593Smuzhiyun __le16 type; 672*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 673*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_TYPE_SFT 0 674*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 675*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 676*4882a593Smuzhiyun __le16 event_id; 677*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 678*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 679*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 680*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 681*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 682*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 683*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 684*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 685*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL 686*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL 687*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG 0xaUL 688*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 689*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 690*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 691*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 692*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 693*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 694*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 695*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 696*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 697*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 698*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 699*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 700*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL 701*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 702*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 703*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL 704*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL 705*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL 706*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL 707*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL 708*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL 709*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL 710*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL 711*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 712*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 713*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 714*4882a593Smuzhiyun __le32 event_data2; 715*4882a593Smuzhiyun u8 opaque_v; 716*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_V 0x1UL 717*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 718*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 719*4882a593Smuzhiyun u8 timestamp_lo; 720*4882a593Smuzhiyun __le16 timestamp_hi; 721*4882a593Smuzhiyun __le32 event_data1; 722*4882a593Smuzhiyun }; 723*4882a593Smuzhiyun 724*4882a593Smuzhiyun /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 725*4882a593Smuzhiyun struct hwrm_async_event_cmpl_link_status_change { 726*4882a593Smuzhiyun __le16 type; 727*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 728*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 729*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 730*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 731*4882a593Smuzhiyun __le16 event_id; 732*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 733*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 734*4882a593Smuzhiyun __le32 event_data2; 735*4882a593Smuzhiyun u8 opaque_v; 736*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 737*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 738*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 739*4882a593Smuzhiyun u8 timestamp_lo; 740*4882a593Smuzhiyun __le16 timestamp_hi; 741*4882a593Smuzhiyun __le32 event_data1; 742*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 743*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 744*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 745*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 746*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 747*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 748*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 749*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 750*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL 751*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20 752*4882a593Smuzhiyun }; 753*4882a593Smuzhiyun 754*4882a593Smuzhiyun /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 755*4882a593Smuzhiyun struct hwrm_async_event_cmpl_port_conn_not_allowed { 756*4882a593Smuzhiyun __le16 type; 757*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 758*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 759*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 760*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 761*4882a593Smuzhiyun __le16 event_id; 762*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 763*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 764*4882a593Smuzhiyun __le32 event_data2; 765*4882a593Smuzhiyun u8 opaque_v; 766*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 767*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 768*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 769*4882a593Smuzhiyun u8 timestamp_lo; 770*4882a593Smuzhiyun __le16 timestamp_hi; 771*4882a593Smuzhiyun __le32 event_data1; 772*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 773*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 774*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 775*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 776*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 777*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 778*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 779*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 780*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 781*4882a593Smuzhiyun }; 782*4882a593Smuzhiyun 783*4882a593Smuzhiyun /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 784*4882a593Smuzhiyun struct hwrm_async_event_cmpl_link_speed_cfg_change { 785*4882a593Smuzhiyun __le16 type; 786*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 787*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 788*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 789*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 790*4882a593Smuzhiyun __le16 event_id; 791*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 792*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 793*4882a593Smuzhiyun __le32 event_data2; 794*4882a593Smuzhiyun u8 opaque_v; 795*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 796*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 797*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 798*4882a593Smuzhiyun u8 timestamp_lo; 799*4882a593Smuzhiyun __le16 timestamp_hi; 800*4882a593Smuzhiyun __le32 event_data1; 801*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 802*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 803*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 804*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 805*4882a593Smuzhiyun }; 806*4882a593Smuzhiyun 807*4882a593Smuzhiyun /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ 808*4882a593Smuzhiyun struct hwrm_async_event_cmpl_reset_notify { 809*4882a593Smuzhiyun __le16 type; 810*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL 811*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 812*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 813*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 814*4882a593Smuzhiyun __le16 event_id; 815*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL 816*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 817*4882a593Smuzhiyun __le32 event_data2; 818*4882a593Smuzhiyun u8 opaque_v; 819*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL 820*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL 821*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 822*4882a593Smuzhiyun u8 timestamp_lo; 823*4882a593Smuzhiyun __le16 timestamp_hi; 824*4882a593Smuzhiyun __le32 event_data1; 825*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL 826*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0 827*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL 828*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL 829*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 830*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL 831*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8 832*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8) 833*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8) 834*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8) 835*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL 836*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL 837*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16 838*4882a593Smuzhiyun }; 839*4882a593Smuzhiyun 840*4882a593Smuzhiyun /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ 841*4882a593Smuzhiyun struct hwrm_async_event_cmpl_error_recovery { 842*4882a593Smuzhiyun __le16 type; 843*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL 844*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 845*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 846*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 847*4882a593Smuzhiyun __le16 event_id; 848*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL 849*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 850*4882a593Smuzhiyun __le32 event_data2; 851*4882a593Smuzhiyun u8 opaque_v; 852*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL 853*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL 854*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 855*4882a593Smuzhiyun u8 timestamp_lo; 856*4882a593Smuzhiyun __le16 timestamp_hi; 857*4882a593Smuzhiyun __le32 event_data1; 858*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL 859*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0 860*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL 861*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL 862*4882a593Smuzhiyun }; 863*4882a593Smuzhiyun 864*4882a593Smuzhiyun /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */ 865*4882a593Smuzhiyun struct hwrm_async_event_cmpl_ring_monitor_msg { 866*4882a593Smuzhiyun __le16 type; 867*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK 0x3fUL 868*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0 869*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 0x2eUL 870*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 871*4882a593Smuzhiyun __le16 event_id; 872*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL 873*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 874*4882a593Smuzhiyun __le32 event_data2; 875*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL 876*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0 877*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX 0x0UL 878*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX 0x1UL 879*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 0x2UL 880*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 881*4882a593Smuzhiyun u8 opaque_v; 882*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V 0x1UL 883*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL 884*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1 885*4882a593Smuzhiyun u8 timestamp_lo; 886*4882a593Smuzhiyun __le16 timestamp_hi; 887*4882a593Smuzhiyun __le32 event_data1; 888*4882a593Smuzhiyun }; 889*4882a593Smuzhiyun 890*4882a593Smuzhiyun /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 891*4882a593Smuzhiyun struct hwrm_async_event_cmpl_vf_cfg_change { 892*4882a593Smuzhiyun __le16 type; 893*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 894*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 895*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 896*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 897*4882a593Smuzhiyun __le16 event_id; 898*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 899*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 900*4882a593Smuzhiyun __le32 event_data2; 901*4882a593Smuzhiyun u8 opaque_v; 902*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 903*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 904*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 905*4882a593Smuzhiyun u8 timestamp_lo; 906*4882a593Smuzhiyun __le16 timestamp_hi; 907*4882a593Smuzhiyun __le32 event_data1; 908*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 909*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 910*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 911*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 912*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 913*4882a593Smuzhiyun }; 914*4882a593Smuzhiyun 915*4882a593Smuzhiyun /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ 916*4882a593Smuzhiyun struct hwrm_async_event_cmpl_default_vnic_change { 917*4882a593Smuzhiyun __le16 type; 918*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL 919*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0 920*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 921*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 922*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL 923*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6 924*4882a593Smuzhiyun __le16 event_id; 925*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL 926*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 927*4882a593Smuzhiyun __le32 event_data2; 928*4882a593Smuzhiyun u8 opaque_v; 929*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL 930*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL 931*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1 932*4882a593Smuzhiyun u8 timestamp_lo; 933*4882a593Smuzhiyun __le16 timestamp_hi; 934*4882a593Smuzhiyun __le32 event_data1; 935*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL 936*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0 937*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL 938*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL 939*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 940*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL 941*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2 942*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL 943*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10 944*4882a593Smuzhiyun }; 945*4882a593Smuzhiyun 946*4882a593Smuzhiyun /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ 947*4882a593Smuzhiyun struct hwrm_async_event_cmpl_hw_flow_aged { 948*4882a593Smuzhiyun __le16 type; 949*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL 950*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 951*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 952*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 953*4882a593Smuzhiyun __le16 event_id; 954*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL 955*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 956*4882a593Smuzhiyun __le32 event_data2; 957*4882a593Smuzhiyun u8 opaque_v; 958*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL 959*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL 960*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 961*4882a593Smuzhiyun u8 timestamp_lo; 962*4882a593Smuzhiyun __le16 timestamp_hi; 963*4882a593Smuzhiyun __le32 event_data1; 964*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL 965*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0 966*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL 967*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31) 968*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31) 969*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX 970*4882a593Smuzhiyun }; 971*4882a593Smuzhiyun 972*4882a593Smuzhiyun /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ 973*4882a593Smuzhiyun struct hwrm_async_event_cmpl_eem_cache_flush_req { 974*4882a593Smuzhiyun __le16 type; 975*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL 976*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0 977*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL 978*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 979*4882a593Smuzhiyun __le16 event_id; 980*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 981*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 982*4882a593Smuzhiyun __le32 event_data2; 983*4882a593Smuzhiyun u8 opaque_v; 984*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL 985*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL 986*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 987*4882a593Smuzhiyun u8 timestamp_lo; 988*4882a593Smuzhiyun __le16 timestamp_hi; 989*4882a593Smuzhiyun __le32 event_data1; 990*4882a593Smuzhiyun }; 991*4882a593Smuzhiyun 992*4882a593Smuzhiyun /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ 993*4882a593Smuzhiyun struct hwrm_async_event_cmpl_eem_cache_flush_done { 994*4882a593Smuzhiyun __le16 type; 995*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL 996*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0 997*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 998*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 999*4882a593Smuzhiyun __le16 event_id; 1000*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 1001*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 1002*4882a593Smuzhiyun __le32 event_data2; 1003*4882a593Smuzhiyun u8 opaque_v; 1004*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL 1005*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL 1006*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 1007*4882a593Smuzhiyun u8 timestamp_lo; 1008*4882a593Smuzhiyun __le16 timestamp_hi; 1009*4882a593Smuzhiyun __le32 event_data1; 1010*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL 1011*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0 1012*4882a593Smuzhiyun }; 1013*4882a593Smuzhiyun 1014*4882a593Smuzhiyun /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */ 1015*4882a593Smuzhiyun struct hwrm_async_event_cmpl_deferred_response { 1016*4882a593Smuzhiyun __le16 type; 1017*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK 0x3fUL 1018*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0 1019*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1020*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 1021*4882a593Smuzhiyun __le16 event_id; 1022*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL 1023*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 1024*4882a593Smuzhiyun __le32 event_data2; 1025*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL 1026*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0 1027*4882a593Smuzhiyun u8 opaque_v; 1028*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V 0x1UL 1029*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL 1030*4882a593Smuzhiyun #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1 1031*4882a593Smuzhiyun u8 timestamp_lo; 1032*4882a593Smuzhiyun __le16 timestamp_hi; 1033*4882a593Smuzhiyun __le32 event_data1; 1034*4882a593Smuzhiyun }; 1035*4882a593Smuzhiyun 1036*4882a593Smuzhiyun /* hwrm_func_reset_input (size:192b/24B) */ 1037*4882a593Smuzhiyun struct hwrm_func_reset_input { 1038*4882a593Smuzhiyun __le16 req_type; 1039*4882a593Smuzhiyun __le16 cmpl_ring; 1040*4882a593Smuzhiyun __le16 seq_id; 1041*4882a593Smuzhiyun __le16 target_id; 1042*4882a593Smuzhiyun __le64 resp_addr; 1043*4882a593Smuzhiyun __le32 enables; 1044*4882a593Smuzhiyun #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 1045*4882a593Smuzhiyun __le16 vf_id; 1046*4882a593Smuzhiyun u8 func_reset_level; 1047*4882a593Smuzhiyun #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 1048*4882a593Smuzhiyun #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 1049*4882a593Smuzhiyun #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 1050*4882a593Smuzhiyun #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 1051*4882a593Smuzhiyun #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 1052*4882a593Smuzhiyun u8 unused_0; 1053*4882a593Smuzhiyun }; 1054*4882a593Smuzhiyun 1055*4882a593Smuzhiyun /* hwrm_func_reset_output (size:128b/16B) */ 1056*4882a593Smuzhiyun struct hwrm_func_reset_output { 1057*4882a593Smuzhiyun __le16 error_code; 1058*4882a593Smuzhiyun __le16 req_type; 1059*4882a593Smuzhiyun __le16 seq_id; 1060*4882a593Smuzhiyun __le16 resp_len; 1061*4882a593Smuzhiyun u8 unused_0[7]; 1062*4882a593Smuzhiyun u8 valid; 1063*4882a593Smuzhiyun }; 1064*4882a593Smuzhiyun 1065*4882a593Smuzhiyun /* hwrm_func_getfid_input (size:192b/24B) */ 1066*4882a593Smuzhiyun struct hwrm_func_getfid_input { 1067*4882a593Smuzhiyun __le16 req_type; 1068*4882a593Smuzhiyun __le16 cmpl_ring; 1069*4882a593Smuzhiyun __le16 seq_id; 1070*4882a593Smuzhiyun __le16 target_id; 1071*4882a593Smuzhiyun __le64 resp_addr; 1072*4882a593Smuzhiyun __le32 enables; 1073*4882a593Smuzhiyun #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 1074*4882a593Smuzhiyun __le16 pci_id; 1075*4882a593Smuzhiyun u8 unused_0[2]; 1076*4882a593Smuzhiyun }; 1077*4882a593Smuzhiyun 1078*4882a593Smuzhiyun /* hwrm_func_getfid_output (size:128b/16B) */ 1079*4882a593Smuzhiyun struct hwrm_func_getfid_output { 1080*4882a593Smuzhiyun __le16 error_code; 1081*4882a593Smuzhiyun __le16 req_type; 1082*4882a593Smuzhiyun __le16 seq_id; 1083*4882a593Smuzhiyun __le16 resp_len; 1084*4882a593Smuzhiyun __le16 fid; 1085*4882a593Smuzhiyun u8 unused_0[5]; 1086*4882a593Smuzhiyun u8 valid; 1087*4882a593Smuzhiyun }; 1088*4882a593Smuzhiyun 1089*4882a593Smuzhiyun /* hwrm_func_vf_alloc_input (size:192b/24B) */ 1090*4882a593Smuzhiyun struct hwrm_func_vf_alloc_input { 1091*4882a593Smuzhiyun __le16 req_type; 1092*4882a593Smuzhiyun __le16 cmpl_ring; 1093*4882a593Smuzhiyun __le16 seq_id; 1094*4882a593Smuzhiyun __le16 target_id; 1095*4882a593Smuzhiyun __le64 resp_addr; 1096*4882a593Smuzhiyun __le32 enables; 1097*4882a593Smuzhiyun #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 1098*4882a593Smuzhiyun __le16 first_vf_id; 1099*4882a593Smuzhiyun __le16 num_vfs; 1100*4882a593Smuzhiyun }; 1101*4882a593Smuzhiyun 1102*4882a593Smuzhiyun /* hwrm_func_vf_alloc_output (size:128b/16B) */ 1103*4882a593Smuzhiyun struct hwrm_func_vf_alloc_output { 1104*4882a593Smuzhiyun __le16 error_code; 1105*4882a593Smuzhiyun __le16 req_type; 1106*4882a593Smuzhiyun __le16 seq_id; 1107*4882a593Smuzhiyun __le16 resp_len; 1108*4882a593Smuzhiyun __le16 first_vf_id; 1109*4882a593Smuzhiyun u8 unused_0[5]; 1110*4882a593Smuzhiyun u8 valid; 1111*4882a593Smuzhiyun }; 1112*4882a593Smuzhiyun 1113*4882a593Smuzhiyun /* hwrm_func_vf_free_input (size:192b/24B) */ 1114*4882a593Smuzhiyun struct hwrm_func_vf_free_input { 1115*4882a593Smuzhiyun __le16 req_type; 1116*4882a593Smuzhiyun __le16 cmpl_ring; 1117*4882a593Smuzhiyun __le16 seq_id; 1118*4882a593Smuzhiyun __le16 target_id; 1119*4882a593Smuzhiyun __le64 resp_addr; 1120*4882a593Smuzhiyun __le32 enables; 1121*4882a593Smuzhiyun #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 1122*4882a593Smuzhiyun __le16 first_vf_id; 1123*4882a593Smuzhiyun __le16 num_vfs; 1124*4882a593Smuzhiyun }; 1125*4882a593Smuzhiyun 1126*4882a593Smuzhiyun /* hwrm_func_vf_free_output (size:128b/16B) */ 1127*4882a593Smuzhiyun struct hwrm_func_vf_free_output { 1128*4882a593Smuzhiyun __le16 error_code; 1129*4882a593Smuzhiyun __le16 req_type; 1130*4882a593Smuzhiyun __le16 seq_id; 1131*4882a593Smuzhiyun __le16 resp_len; 1132*4882a593Smuzhiyun u8 unused_0[7]; 1133*4882a593Smuzhiyun u8 valid; 1134*4882a593Smuzhiyun }; 1135*4882a593Smuzhiyun 1136*4882a593Smuzhiyun /* hwrm_func_vf_cfg_input (size:448b/56B) */ 1137*4882a593Smuzhiyun struct hwrm_func_vf_cfg_input { 1138*4882a593Smuzhiyun __le16 req_type; 1139*4882a593Smuzhiyun __le16 cmpl_ring; 1140*4882a593Smuzhiyun __le16 seq_id; 1141*4882a593Smuzhiyun __le16 target_id; 1142*4882a593Smuzhiyun __le64 resp_addr; 1143*4882a593Smuzhiyun __le32 enables; 1144*4882a593Smuzhiyun #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 1145*4882a593Smuzhiyun #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 1146*4882a593Smuzhiyun #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 1147*4882a593Smuzhiyun #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 1148*4882a593Smuzhiyun #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 1149*4882a593Smuzhiyun #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 1150*4882a593Smuzhiyun #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 1151*4882a593Smuzhiyun #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 1152*4882a593Smuzhiyun #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 1153*4882a593Smuzhiyun #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 1154*4882a593Smuzhiyun #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 1155*4882a593Smuzhiyun #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 1156*4882a593Smuzhiyun __le16 mtu; 1157*4882a593Smuzhiyun __le16 guest_vlan; 1158*4882a593Smuzhiyun __le16 async_event_cr; 1159*4882a593Smuzhiyun u8 dflt_mac_addr[6]; 1160*4882a593Smuzhiyun __le32 flags; 1161*4882a593Smuzhiyun #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 1162*4882a593Smuzhiyun #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 1163*4882a593Smuzhiyun #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 1164*4882a593Smuzhiyun #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 1165*4882a593Smuzhiyun #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 1166*4882a593Smuzhiyun #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 1167*4882a593Smuzhiyun #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 1168*4882a593Smuzhiyun #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 1169*4882a593Smuzhiyun #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x100UL 1170*4882a593Smuzhiyun #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x200UL 1171*4882a593Smuzhiyun __le16 num_rsscos_ctxs; 1172*4882a593Smuzhiyun __le16 num_cmpl_rings; 1173*4882a593Smuzhiyun __le16 num_tx_rings; 1174*4882a593Smuzhiyun __le16 num_rx_rings; 1175*4882a593Smuzhiyun __le16 num_l2_ctxs; 1176*4882a593Smuzhiyun __le16 num_vnics; 1177*4882a593Smuzhiyun __le16 num_stat_ctxs; 1178*4882a593Smuzhiyun __le16 num_hw_ring_grps; 1179*4882a593Smuzhiyun u8 unused_0[4]; 1180*4882a593Smuzhiyun }; 1181*4882a593Smuzhiyun 1182*4882a593Smuzhiyun /* hwrm_func_vf_cfg_output (size:128b/16B) */ 1183*4882a593Smuzhiyun struct hwrm_func_vf_cfg_output { 1184*4882a593Smuzhiyun __le16 error_code; 1185*4882a593Smuzhiyun __le16 req_type; 1186*4882a593Smuzhiyun __le16 seq_id; 1187*4882a593Smuzhiyun __le16 resp_len; 1188*4882a593Smuzhiyun u8 unused_0[7]; 1189*4882a593Smuzhiyun u8 valid; 1190*4882a593Smuzhiyun }; 1191*4882a593Smuzhiyun 1192*4882a593Smuzhiyun /* hwrm_func_qcaps_input (size:192b/24B) */ 1193*4882a593Smuzhiyun struct hwrm_func_qcaps_input { 1194*4882a593Smuzhiyun __le16 req_type; 1195*4882a593Smuzhiyun __le16 cmpl_ring; 1196*4882a593Smuzhiyun __le16 seq_id; 1197*4882a593Smuzhiyun __le16 target_id; 1198*4882a593Smuzhiyun __le64 resp_addr; 1199*4882a593Smuzhiyun __le16 fid; 1200*4882a593Smuzhiyun u8 unused_0[6]; 1201*4882a593Smuzhiyun }; 1202*4882a593Smuzhiyun 1203*4882a593Smuzhiyun /* hwrm_func_qcaps_output (size:704b/88B) */ 1204*4882a593Smuzhiyun struct hwrm_func_qcaps_output { 1205*4882a593Smuzhiyun __le16 error_code; 1206*4882a593Smuzhiyun __le16 req_type; 1207*4882a593Smuzhiyun __le16 seq_id; 1208*4882a593Smuzhiyun __le16 resp_len; 1209*4882a593Smuzhiyun __le16 fid; 1210*4882a593Smuzhiyun __le16 port_id; 1211*4882a593Smuzhiyun __le32 flags; 1212*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1213*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 1214*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1215*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 1216*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 1217*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1218*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 1219*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1220*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1221*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1222*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 1223*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 1224*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 1225*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 1226*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 1227*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 1228*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 1229*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL 1230*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 1231*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 1232*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 1233*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL 1234*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL 1235*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL 1236*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL 1237*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL 1238*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL 1239*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL 1240*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED 0x10000000UL 1241*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED 0x20000000UL 1242*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED 0x40000000UL 1243*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED 0x80000000UL 1244*4882a593Smuzhiyun u8 mac_address[6]; 1245*4882a593Smuzhiyun __le16 max_rsscos_ctx; 1246*4882a593Smuzhiyun __le16 max_cmpl_rings; 1247*4882a593Smuzhiyun __le16 max_tx_rings; 1248*4882a593Smuzhiyun __le16 max_rx_rings; 1249*4882a593Smuzhiyun __le16 max_l2_ctxs; 1250*4882a593Smuzhiyun __le16 max_vnics; 1251*4882a593Smuzhiyun __le16 first_vf_id; 1252*4882a593Smuzhiyun __le16 max_vfs; 1253*4882a593Smuzhiyun __le16 max_stat_ctx; 1254*4882a593Smuzhiyun __le32 max_encap_records; 1255*4882a593Smuzhiyun __le32 max_decap_records; 1256*4882a593Smuzhiyun __le32 max_tx_em_flows; 1257*4882a593Smuzhiyun __le32 max_tx_wm_flows; 1258*4882a593Smuzhiyun __le32 max_rx_em_flows; 1259*4882a593Smuzhiyun __le32 max_rx_wm_flows; 1260*4882a593Smuzhiyun __le32 max_mcast_filters; 1261*4882a593Smuzhiyun __le32 max_flow_id; 1262*4882a593Smuzhiyun __le32 max_hw_ring_grps; 1263*4882a593Smuzhiyun __le16 max_sp_tx_rings; 1264*4882a593Smuzhiyun u8 unused_0[2]; 1265*4882a593Smuzhiyun __le32 flags_ext; 1266*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL 1267*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL 1268*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED 0x4UL 1269*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT 0x8UL 1270*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT 0x10UL 1271*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT 0x20UL 1272*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED 0x40UL 1273*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED 0x80UL 1274*4882a593Smuzhiyun u8 max_schqs; 1275*4882a593Smuzhiyun u8 mpc_chnls_cap; 1276*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL 1277*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE 0x2UL 1278*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA 0x4UL 1279*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA 0x8UL 1280*4882a593Smuzhiyun #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE 0x10UL 1281*4882a593Smuzhiyun u8 unused_1; 1282*4882a593Smuzhiyun u8 valid; 1283*4882a593Smuzhiyun }; 1284*4882a593Smuzhiyun 1285*4882a593Smuzhiyun /* hwrm_func_qcfg_input (size:192b/24B) */ 1286*4882a593Smuzhiyun struct hwrm_func_qcfg_input { 1287*4882a593Smuzhiyun __le16 req_type; 1288*4882a593Smuzhiyun __le16 cmpl_ring; 1289*4882a593Smuzhiyun __le16 seq_id; 1290*4882a593Smuzhiyun __le16 target_id; 1291*4882a593Smuzhiyun __le64 resp_addr; 1292*4882a593Smuzhiyun __le16 fid; 1293*4882a593Smuzhiyun u8 unused_0[6]; 1294*4882a593Smuzhiyun }; 1295*4882a593Smuzhiyun 1296*4882a593Smuzhiyun /* hwrm_func_qcfg_output (size:768b/96B) */ 1297*4882a593Smuzhiyun struct hwrm_func_qcfg_output { 1298*4882a593Smuzhiyun __le16 error_code; 1299*4882a593Smuzhiyun __le16 req_type; 1300*4882a593Smuzhiyun __le16 seq_id; 1301*4882a593Smuzhiyun __le16 resp_len; 1302*4882a593Smuzhiyun __le16 fid; 1303*4882a593Smuzhiyun __le16 port_id; 1304*4882a593Smuzhiyun __le16 vlan; 1305*4882a593Smuzhiyun __le16 flags; 1306*4882a593Smuzhiyun #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1307*4882a593Smuzhiyun #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1308*4882a593Smuzhiyun #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 1309*4882a593Smuzhiyun #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 1310*4882a593Smuzhiyun #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 1311*4882a593Smuzhiyun #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 1312*4882a593Smuzhiyun #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 1313*4882a593Smuzhiyun #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL 1314*4882a593Smuzhiyun #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL 1315*4882a593Smuzhiyun #define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED 0x200UL 1316*4882a593Smuzhiyun #define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED 0x400UL 1317*4882a593Smuzhiyun #define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED 0x800UL 1318*4882a593Smuzhiyun u8 mac_address[6]; 1319*4882a593Smuzhiyun __le16 pci_id; 1320*4882a593Smuzhiyun __le16 alloc_rsscos_ctx; 1321*4882a593Smuzhiyun __le16 alloc_cmpl_rings; 1322*4882a593Smuzhiyun __le16 alloc_tx_rings; 1323*4882a593Smuzhiyun __le16 alloc_rx_rings; 1324*4882a593Smuzhiyun __le16 alloc_l2_ctx; 1325*4882a593Smuzhiyun __le16 alloc_vnics; 1326*4882a593Smuzhiyun __le16 mtu; 1327*4882a593Smuzhiyun __le16 mru; 1328*4882a593Smuzhiyun __le16 stat_ctx_id; 1329*4882a593Smuzhiyun u8 port_partition_type; 1330*4882a593Smuzhiyun #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 1331*4882a593Smuzhiyun #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 1332*4882a593Smuzhiyun #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 1333*4882a593Smuzhiyun #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 1334*4882a593Smuzhiyun #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 1335*4882a593Smuzhiyun #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 1336*4882a593Smuzhiyun #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 1337*4882a593Smuzhiyun u8 port_pf_cnt; 1338*4882a593Smuzhiyun #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 1339*4882a593Smuzhiyun #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 1340*4882a593Smuzhiyun __le16 dflt_vnic_id; 1341*4882a593Smuzhiyun __le16 max_mtu_configured; 1342*4882a593Smuzhiyun __le32 min_bw; 1343*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1344*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 1345*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 1346*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 1347*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 1348*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 1349*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1350*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 1351*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1352*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1353*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1354*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1355*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1356*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1357*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 1358*4882a593Smuzhiyun __le32 max_bw; 1359*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1360*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 1361*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 1362*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 1363*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 1364*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 1365*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1366*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 1367*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1368*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1369*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1370*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1371*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1372*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1373*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 1374*4882a593Smuzhiyun u8 evb_mode; 1375*4882a593Smuzhiyun #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 1376*4882a593Smuzhiyun #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 1377*4882a593Smuzhiyun #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 1378*4882a593Smuzhiyun #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 1379*4882a593Smuzhiyun u8 options; 1380*4882a593Smuzhiyun #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1381*4882a593Smuzhiyun #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 1382*4882a593Smuzhiyun #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1383*4882a593Smuzhiyun #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1384*4882a593Smuzhiyun #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 1385*4882a593Smuzhiyun #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1386*4882a593Smuzhiyun #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2 1387*4882a593Smuzhiyun #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1388*4882a593Smuzhiyun #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1389*4882a593Smuzhiyun #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1390*4882a593Smuzhiyun #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO 1391*4882a593Smuzhiyun #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL 1392*4882a593Smuzhiyun #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4 1393*4882a593Smuzhiyun __le16 alloc_vfs; 1394*4882a593Smuzhiyun __le32 alloc_mcast_filters; 1395*4882a593Smuzhiyun __le32 alloc_hw_ring_grps; 1396*4882a593Smuzhiyun __le16 alloc_sp_tx_rings; 1397*4882a593Smuzhiyun __le16 alloc_stat_ctx; 1398*4882a593Smuzhiyun __le16 alloc_msix; 1399*4882a593Smuzhiyun __le16 registered_vfs; 1400*4882a593Smuzhiyun __le16 l2_doorbell_bar_size_kb; 1401*4882a593Smuzhiyun u8 unused_1; 1402*4882a593Smuzhiyun u8 always_1; 1403*4882a593Smuzhiyun __le32 reset_addr_poll; 1404*4882a593Smuzhiyun __le16 legacy_l2_db_size_kb; 1405*4882a593Smuzhiyun __le16 svif_info; 1406*4882a593Smuzhiyun #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK 0x7fffUL 1407*4882a593Smuzhiyun #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT 0 1408*4882a593Smuzhiyun #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID 0x8000UL 1409*4882a593Smuzhiyun u8 mpc_chnls; 1410*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED 0x1UL 1411*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED 0x2UL 1412*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED 0x4UL 1413*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED 0x8UL 1414*4882a593Smuzhiyun #define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED 0x10UL 1415*4882a593Smuzhiyun u8 unused_2[6]; 1416*4882a593Smuzhiyun u8 valid; 1417*4882a593Smuzhiyun }; 1418*4882a593Smuzhiyun 1419*4882a593Smuzhiyun /* hwrm_func_cfg_input (size:768b/96B) */ 1420*4882a593Smuzhiyun struct hwrm_func_cfg_input { 1421*4882a593Smuzhiyun __le16 req_type; 1422*4882a593Smuzhiyun __le16 cmpl_ring; 1423*4882a593Smuzhiyun __le16 seq_id; 1424*4882a593Smuzhiyun __le16 target_id; 1425*4882a593Smuzhiyun __le64 resp_addr; 1426*4882a593Smuzhiyun __le16 fid; 1427*4882a593Smuzhiyun __le16 num_msix; 1428*4882a593Smuzhiyun __le32 flags; 1429*4882a593Smuzhiyun #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 1430*4882a593Smuzhiyun #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 1431*4882a593Smuzhiyun #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 1432*4882a593Smuzhiyun #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 1433*4882a593Smuzhiyun #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 1434*4882a593Smuzhiyun #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 1435*4882a593Smuzhiyun #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 1436*4882a593Smuzhiyun #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 1437*4882a593Smuzhiyun #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 1438*4882a593Smuzhiyun #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 1439*4882a593Smuzhiyun #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 1440*4882a593Smuzhiyun #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 1441*4882a593Smuzhiyun #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 1442*4882a593Smuzhiyun #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 1443*4882a593Smuzhiyun #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 1444*4882a593Smuzhiyun #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 1445*4882a593Smuzhiyun #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 1446*4882a593Smuzhiyun #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL 1447*4882a593Smuzhiyun #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL 1448*4882a593Smuzhiyun #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL 1449*4882a593Smuzhiyun #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL 1450*4882a593Smuzhiyun #define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS 0x4000000UL 1451*4882a593Smuzhiyun #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x8000000UL 1452*4882a593Smuzhiyun #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x10000000UL 1453*4882a593Smuzhiyun __le32 enables; 1454*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 1455*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1456*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1457*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1458*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1459*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1460*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1461*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1462*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1463*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1464*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1465*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1466*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1467*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1468*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1469*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1470*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1471*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1472*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1473*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1474*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 1475*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL 1476*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL 1477*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT 0x800000UL 1478*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_SCHQ_ID 0x1000000UL 1479*4882a593Smuzhiyun #define FUNC_CFG_REQ_ENABLES_MPC_CHNLS 0x2000000UL 1480*4882a593Smuzhiyun __le16 mtu; 1481*4882a593Smuzhiyun __le16 mru; 1482*4882a593Smuzhiyun __le16 num_rsscos_ctxs; 1483*4882a593Smuzhiyun __le16 num_cmpl_rings; 1484*4882a593Smuzhiyun __le16 num_tx_rings; 1485*4882a593Smuzhiyun __le16 num_rx_rings; 1486*4882a593Smuzhiyun __le16 num_l2_ctxs; 1487*4882a593Smuzhiyun __le16 num_vnics; 1488*4882a593Smuzhiyun __le16 num_stat_ctxs; 1489*4882a593Smuzhiyun __le16 num_hw_ring_grps; 1490*4882a593Smuzhiyun u8 dflt_mac_addr[6]; 1491*4882a593Smuzhiyun __le16 dflt_vlan; 1492*4882a593Smuzhiyun __be32 dflt_ip_addr[4]; 1493*4882a593Smuzhiyun __le32 min_bw; 1494*4882a593Smuzhiyun #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1495*4882a593Smuzhiyun #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 1496*4882a593Smuzhiyun #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 1497*4882a593Smuzhiyun #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 1498*4882a593Smuzhiyun #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 1499*4882a593Smuzhiyun #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 1500*4882a593Smuzhiyun #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1501*4882a593Smuzhiyun #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 1502*4882a593Smuzhiyun #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1503*4882a593Smuzhiyun #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1504*4882a593Smuzhiyun #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1505*4882a593Smuzhiyun #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1506*4882a593Smuzhiyun #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1507*4882a593Smuzhiyun #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1508*4882a593Smuzhiyun #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1509*4882a593Smuzhiyun __le32 max_bw; 1510*4882a593Smuzhiyun #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1511*4882a593Smuzhiyun #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1512*4882a593Smuzhiyun #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 1513*4882a593Smuzhiyun #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 1514*4882a593Smuzhiyun #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 1515*4882a593Smuzhiyun #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 1516*4882a593Smuzhiyun #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1517*4882a593Smuzhiyun #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1518*4882a593Smuzhiyun #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1519*4882a593Smuzhiyun #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1520*4882a593Smuzhiyun #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1521*4882a593Smuzhiyun #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1522*4882a593Smuzhiyun #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1523*4882a593Smuzhiyun #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1524*4882a593Smuzhiyun #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1525*4882a593Smuzhiyun __le16 async_event_cr; 1526*4882a593Smuzhiyun u8 vlan_antispoof_mode; 1527*4882a593Smuzhiyun #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1528*4882a593Smuzhiyun #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1529*4882a593Smuzhiyun #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1530*4882a593Smuzhiyun #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1531*4882a593Smuzhiyun #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 1532*4882a593Smuzhiyun u8 allowed_vlan_pris; 1533*4882a593Smuzhiyun u8 evb_mode; 1534*4882a593Smuzhiyun #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1535*4882a593Smuzhiyun #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1536*4882a593Smuzhiyun #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1537*4882a593Smuzhiyun #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 1538*4882a593Smuzhiyun u8 options; 1539*4882a593Smuzhiyun #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1540*4882a593Smuzhiyun #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 1541*4882a593Smuzhiyun #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1542*4882a593Smuzhiyun #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1543*4882a593Smuzhiyun #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 1544*4882a593Smuzhiyun #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1545*4882a593Smuzhiyun #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2 1546*4882a593Smuzhiyun #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1547*4882a593Smuzhiyun #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1548*4882a593Smuzhiyun #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1549*4882a593Smuzhiyun #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO 1550*4882a593Smuzhiyun #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL 1551*4882a593Smuzhiyun #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4 1552*4882a593Smuzhiyun __le16 num_mcast_filters; 1553*4882a593Smuzhiyun __le16 schq_id; 1554*4882a593Smuzhiyun __le16 mpc_chnls; 1555*4882a593Smuzhiyun #define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE 0x1UL 1556*4882a593Smuzhiyun #define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE 0x2UL 1557*4882a593Smuzhiyun #define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE 0x4UL 1558*4882a593Smuzhiyun #define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE 0x8UL 1559*4882a593Smuzhiyun #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE 0x10UL 1560*4882a593Smuzhiyun #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE 0x20UL 1561*4882a593Smuzhiyun #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE 0x40UL 1562*4882a593Smuzhiyun #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE 0x80UL 1563*4882a593Smuzhiyun #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE 0x100UL 1564*4882a593Smuzhiyun #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE 0x200UL 1565*4882a593Smuzhiyun u8 unused_0[4]; 1566*4882a593Smuzhiyun }; 1567*4882a593Smuzhiyun 1568*4882a593Smuzhiyun /* hwrm_func_cfg_output (size:128b/16B) */ 1569*4882a593Smuzhiyun struct hwrm_func_cfg_output { 1570*4882a593Smuzhiyun __le16 error_code; 1571*4882a593Smuzhiyun __le16 req_type; 1572*4882a593Smuzhiyun __le16 seq_id; 1573*4882a593Smuzhiyun __le16 resp_len; 1574*4882a593Smuzhiyun u8 unused_0[7]; 1575*4882a593Smuzhiyun u8 valid; 1576*4882a593Smuzhiyun }; 1577*4882a593Smuzhiyun 1578*4882a593Smuzhiyun /* hwrm_func_qstats_input (size:192b/24B) */ 1579*4882a593Smuzhiyun struct hwrm_func_qstats_input { 1580*4882a593Smuzhiyun __le16 req_type; 1581*4882a593Smuzhiyun __le16 cmpl_ring; 1582*4882a593Smuzhiyun __le16 seq_id; 1583*4882a593Smuzhiyun __le16 target_id; 1584*4882a593Smuzhiyun __le64 resp_addr; 1585*4882a593Smuzhiyun __le16 fid; 1586*4882a593Smuzhiyun u8 flags; 1587*4882a593Smuzhiyun #define FUNC_QSTATS_REQ_FLAGS_UNUSED 0x0UL 1588*4882a593Smuzhiyun #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL 1589*4882a593Smuzhiyun #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL 1590*4882a593Smuzhiyun #define FUNC_QSTATS_REQ_FLAGS_LAST FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 1591*4882a593Smuzhiyun u8 unused_0[5]; 1592*4882a593Smuzhiyun }; 1593*4882a593Smuzhiyun 1594*4882a593Smuzhiyun /* hwrm_func_qstats_output (size:1408b/176B) */ 1595*4882a593Smuzhiyun struct hwrm_func_qstats_output { 1596*4882a593Smuzhiyun __le16 error_code; 1597*4882a593Smuzhiyun __le16 req_type; 1598*4882a593Smuzhiyun __le16 seq_id; 1599*4882a593Smuzhiyun __le16 resp_len; 1600*4882a593Smuzhiyun __le64 tx_ucast_pkts; 1601*4882a593Smuzhiyun __le64 tx_mcast_pkts; 1602*4882a593Smuzhiyun __le64 tx_bcast_pkts; 1603*4882a593Smuzhiyun __le64 tx_discard_pkts; 1604*4882a593Smuzhiyun __le64 tx_drop_pkts; 1605*4882a593Smuzhiyun __le64 tx_ucast_bytes; 1606*4882a593Smuzhiyun __le64 tx_mcast_bytes; 1607*4882a593Smuzhiyun __le64 tx_bcast_bytes; 1608*4882a593Smuzhiyun __le64 rx_ucast_pkts; 1609*4882a593Smuzhiyun __le64 rx_mcast_pkts; 1610*4882a593Smuzhiyun __le64 rx_bcast_pkts; 1611*4882a593Smuzhiyun __le64 rx_discard_pkts; 1612*4882a593Smuzhiyun __le64 rx_drop_pkts; 1613*4882a593Smuzhiyun __le64 rx_ucast_bytes; 1614*4882a593Smuzhiyun __le64 rx_mcast_bytes; 1615*4882a593Smuzhiyun __le64 rx_bcast_bytes; 1616*4882a593Smuzhiyun __le64 rx_agg_pkts; 1617*4882a593Smuzhiyun __le64 rx_agg_bytes; 1618*4882a593Smuzhiyun __le64 rx_agg_events; 1619*4882a593Smuzhiyun __le64 rx_agg_aborts; 1620*4882a593Smuzhiyun u8 unused_0[7]; 1621*4882a593Smuzhiyun u8 valid; 1622*4882a593Smuzhiyun }; 1623*4882a593Smuzhiyun 1624*4882a593Smuzhiyun /* hwrm_func_qstats_ext_input (size:256b/32B) */ 1625*4882a593Smuzhiyun struct hwrm_func_qstats_ext_input { 1626*4882a593Smuzhiyun __le16 req_type; 1627*4882a593Smuzhiyun __le16 cmpl_ring; 1628*4882a593Smuzhiyun __le16 seq_id; 1629*4882a593Smuzhiyun __le16 target_id; 1630*4882a593Smuzhiyun __le64 resp_addr; 1631*4882a593Smuzhiyun __le16 fid; 1632*4882a593Smuzhiyun u8 flags; 1633*4882a593Smuzhiyun #define FUNC_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 1634*4882a593Smuzhiyun #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL 1635*4882a593Smuzhiyun #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL 1636*4882a593Smuzhiyun #define FUNC_QSTATS_EXT_REQ_FLAGS_LAST FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 1637*4882a593Smuzhiyun u8 unused_0[1]; 1638*4882a593Smuzhiyun __le32 enables; 1639*4882a593Smuzhiyun #define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID 0x1UL 1640*4882a593Smuzhiyun __le16 schq_id; 1641*4882a593Smuzhiyun __le16 traffic_class; 1642*4882a593Smuzhiyun u8 unused_1[4]; 1643*4882a593Smuzhiyun }; 1644*4882a593Smuzhiyun 1645*4882a593Smuzhiyun /* hwrm_func_qstats_ext_output (size:1536b/192B) */ 1646*4882a593Smuzhiyun struct hwrm_func_qstats_ext_output { 1647*4882a593Smuzhiyun __le16 error_code; 1648*4882a593Smuzhiyun __le16 req_type; 1649*4882a593Smuzhiyun __le16 seq_id; 1650*4882a593Smuzhiyun __le16 resp_len; 1651*4882a593Smuzhiyun __le64 rx_ucast_pkts; 1652*4882a593Smuzhiyun __le64 rx_mcast_pkts; 1653*4882a593Smuzhiyun __le64 rx_bcast_pkts; 1654*4882a593Smuzhiyun __le64 rx_discard_pkts; 1655*4882a593Smuzhiyun __le64 rx_error_pkts; 1656*4882a593Smuzhiyun __le64 rx_ucast_bytes; 1657*4882a593Smuzhiyun __le64 rx_mcast_bytes; 1658*4882a593Smuzhiyun __le64 rx_bcast_bytes; 1659*4882a593Smuzhiyun __le64 tx_ucast_pkts; 1660*4882a593Smuzhiyun __le64 tx_mcast_pkts; 1661*4882a593Smuzhiyun __le64 tx_bcast_pkts; 1662*4882a593Smuzhiyun __le64 tx_error_pkts; 1663*4882a593Smuzhiyun __le64 tx_discard_pkts; 1664*4882a593Smuzhiyun __le64 tx_ucast_bytes; 1665*4882a593Smuzhiyun __le64 tx_mcast_bytes; 1666*4882a593Smuzhiyun __le64 tx_bcast_bytes; 1667*4882a593Smuzhiyun __le64 rx_tpa_eligible_pkt; 1668*4882a593Smuzhiyun __le64 rx_tpa_eligible_bytes; 1669*4882a593Smuzhiyun __le64 rx_tpa_pkt; 1670*4882a593Smuzhiyun __le64 rx_tpa_bytes; 1671*4882a593Smuzhiyun __le64 rx_tpa_errors; 1672*4882a593Smuzhiyun __le64 rx_tpa_events; 1673*4882a593Smuzhiyun u8 unused_0[7]; 1674*4882a593Smuzhiyun u8 valid; 1675*4882a593Smuzhiyun }; 1676*4882a593Smuzhiyun 1677*4882a593Smuzhiyun /* hwrm_func_clr_stats_input (size:192b/24B) */ 1678*4882a593Smuzhiyun struct hwrm_func_clr_stats_input { 1679*4882a593Smuzhiyun __le16 req_type; 1680*4882a593Smuzhiyun __le16 cmpl_ring; 1681*4882a593Smuzhiyun __le16 seq_id; 1682*4882a593Smuzhiyun __le16 target_id; 1683*4882a593Smuzhiyun __le64 resp_addr; 1684*4882a593Smuzhiyun __le16 fid; 1685*4882a593Smuzhiyun u8 unused_0[6]; 1686*4882a593Smuzhiyun }; 1687*4882a593Smuzhiyun 1688*4882a593Smuzhiyun /* hwrm_func_clr_stats_output (size:128b/16B) */ 1689*4882a593Smuzhiyun struct hwrm_func_clr_stats_output { 1690*4882a593Smuzhiyun __le16 error_code; 1691*4882a593Smuzhiyun __le16 req_type; 1692*4882a593Smuzhiyun __le16 seq_id; 1693*4882a593Smuzhiyun __le16 resp_len; 1694*4882a593Smuzhiyun u8 unused_0[7]; 1695*4882a593Smuzhiyun u8 valid; 1696*4882a593Smuzhiyun }; 1697*4882a593Smuzhiyun 1698*4882a593Smuzhiyun /* hwrm_func_vf_resc_free_input (size:192b/24B) */ 1699*4882a593Smuzhiyun struct hwrm_func_vf_resc_free_input { 1700*4882a593Smuzhiyun __le16 req_type; 1701*4882a593Smuzhiyun __le16 cmpl_ring; 1702*4882a593Smuzhiyun __le16 seq_id; 1703*4882a593Smuzhiyun __le16 target_id; 1704*4882a593Smuzhiyun __le64 resp_addr; 1705*4882a593Smuzhiyun __le16 vf_id; 1706*4882a593Smuzhiyun u8 unused_0[6]; 1707*4882a593Smuzhiyun }; 1708*4882a593Smuzhiyun 1709*4882a593Smuzhiyun /* hwrm_func_vf_resc_free_output (size:128b/16B) */ 1710*4882a593Smuzhiyun struct hwrm_func_vf_resc_free_output { 1711*4882a593Smuzhiyun __le16 error_code; 1712*4882a593Smuzhiyun __le16 req_type; 1713*4882a593Smuzhiyun __le16 seq_id; 1714*4882a593Smuzhiyun __le16 resp_len; 1715*4882a593Smuzhiyun u8 unused_0[7]; 1716*4882a593Smuzhiyun u8 valid; 1717*4882a593Smuzhiyun }; 1718*4882a593Smuzhiyun 1719*4882a593Smuzhiyun /* hwrm_func_drv_rgtr_input (size:896b/112B) */ 1720*4882a593Smuzhiyun struct hwrm_func_drv_rgtr_input { 1721*4882a593Smuzhiyun __le16 req_type; 1722*4882a593Smuzhiyun __le16 cmpl_ring; 1723*4882a593Smuzhiyun __le16 seq_id; 1724*4882a593Smuzhiyun __le16 target_id; 1725*4882a593Smuzhiyun __le64 resp_addr; 1726*4882a593Smuzhiyun __le32 flags; 1727*4882a593Smuzhiyun #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1728*4882a593Smuzhiyun #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1729*4882a593Smuzhiyun #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 1730*4882a593Smuzhiyun #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 1731*4882a593Smuzhiyun #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL 1732*4882a593Smuzhiyun #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL 1733*4882a593Smuzhiyun #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL 1734*4882a593Smuzhiyun __le32 enables; 1735*4882a593Smuzhiyun #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1736*4882a593Smuzhiyun #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1737*4882a593Smuzhiyun #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1738*4882a593Smuzhiyun #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1739*4882a593Smuzhiyun #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1740*4882a593Smuzhiyun __le16 os_type; 1741*4882a593Smuzhiyun #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 1742*4882a593Smuzhiyun #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 1743*4882a593Smuzhiyun #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 1744*4882a593Smuzhiyun #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 1745*4882a593Smuzhiyun #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 1746*4882a593Smuzhiyun #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 1747*4882a593Smuzhiyun #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 1748*4882a593Smuzhiyun #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 1749*4882a593Smuzhiyun #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 1750*4882a593Smuzhiyun #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 1751*4882a593Smuzhiyun #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 1752*4882a593Smuzhiyun #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 1753*4882a593Smuzhiyun u8 ver_maj_8b; 1754*4882a593Smuzhiyun u8 ver_min_8b; 1755*4882a593Smuzhiyun u8 ver_upd_8b; 1756*4882a593Smuzhiyun u8 unused_0[3]; 1757*4882a593Smuzhiyun __le32 timestamp; 1758*4882a593Smuzhiyun u8 unused_1[4]; 1759*4882a593Smuzhiyun __le32 vf_req_fwd[8]; 1760*4882a593Smuzhiyun __le32 async_event_fwd[8]; 1761*4882a593Smuzhiyun __le16 ver_maj; 1762*4882a593Smuzhiyun __le16 ver_min; 1763*4882a593Smuzhiyun __le16 ver_upd; 1764*4882a593Smuzhiyun __le16 ver_patch; 1765*4882a593Smuzhiyun }; 1766*4882a593Smuzhiyun 1767*4882a593Smuzhiyun /* hwrm_func_drv_rgtr_output (size:128b/16B) */ 1768*4882a593Smuzhiyun struct hwrm_func_drv_rgtr_output { 1769*4882a593Smuzhiyun __le16 error_code; 1770*4882a593Smuzhiyun __le16 req_type; 1771*4882a593Smuzhiyun __le16 seq_id; 1772*4882a593Smuzhiyun __le16 resp_len; 1773*4882a593Smuzhiyun __le32 flags; 1774*4882a593Smuzhiyun #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL 1775*4882a593Smuzhiyun u8 unused_0[3]; 1776*4882a593Smuzhiyun u8 valid; 1777*4882a593Smuzhiyun }; 1778*4882a593Smuzhiyun 1779*4882a593Smuzhiyun /* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 1780*4882a593Smuzhiyun struct hwrm_func_drv_unrgtr_input { 1781*4882a593Smuzhiyun __le16 req_type; 1782*4882a593Smuzhiyun __le16 cmpl_ring; 1783*4882a593Smuzhiyun __le16 seq_id; 1784*4882a593Smuzhiyun __le16 target_id; 1785*4882a593Smuzhiyun __le64 resp_addr; 1786*4882a593Smuzhiyun __le32 flags; 1787*4882a593Smuzhiyun #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1788*4882a593Smuzhiyun u8 unused_0[4]; 1789*4882a593Smuzhiyun }; 1790*4882a593Smuzhiyun 1791*4882a593Smuzhiyun /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 1792*4882a593Smuzhiyun struct hwrm_func_drv_unrgtr_output { 1793*4882a593Smuzhiyun __le16 error_code; 1794*4882a593Smuzhiyun __le16 req_type; 1795*4882a593Smuzhiyun __le16 seq_id; 1796*4882a593Smuzhiyun __le16 resp_len; 1797*4882a593Smuzhiyun u8 unused_0[7]; 1798*4882a593Smuzhiyun u8 valid; 1799*4882a593Smuzhiyun }; 1800*4882a593Smuzhiyun 1801*4882a593Smuzhiyun /* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 1802*4882a593Smuzhiyun struct hwrm_func_buf_rgtr_input { 1803*4882a593Smuzhiyun __le16 req_type; 1804*4882a593Smuzhiyun __le16 cmpl_ring; 1805*4882a593Smuzhiyun __le16 seq_id; 1806*4882a593Smuzhiyun __le16 target_id; 1807*4882a593Smuzhiyun __le64 resp_addr; 1808*4882a593Smuzhiyun __le32 enables; 1809*4882a593Smuzhiyun #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1810*4882a593Smuzhiyun #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1811*4882a593Smuzhiyun __le16 vf_id; 1812*4882a593Smuzhiyun __le16 req_buf_num_pages; 1813*4882a593Smuzhiyun __le16 req_buf_page_size; 1814*4882a593Smuzhiyun #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 1815*4882a593Smuzhiyun #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 1816*4882a593Smuzhiyun #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 1817*4882a593Smuzhiyun #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 1818*4882a593Smuzhiyun #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 1819*4882a593Smuzhiyun #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 1820*4882a593Smuzhiyun #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 1821*4882a593Smuzhiyun #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 1822*4882a593Smuzhiyun __le16 req_buf_len; 1823*4882a593Smuzhiyun __le16 resp_buf_len; 1824*4882a593Smuzhiyun u8 unused_0[2]; 1825*4882a593Smuzhiyun __le64 req_buf_page_addr0; 1826*4882a593Smuzhiyun __le64 req_buf_page_addr1; 1827*4882a593Smuzhiyun __le64 req_buf_page_addr2; 1828*4882a593Smuzhiyun __le64 req_buf_page_addr3; 1829*4882a593Smuzhiyun __le64 req_buf_page_addr4; 1830*4882a593Smuzhiyun __le64 req_buf_page_addr5; 1831*4882a593Smuzhiyun __le64 req_buf_page_addr6; 1832*4882a593Smuzhiyun __le64 req_buf_page_addr7; 1833*4882a593Smuzhiyun __le64 req_buf_page_addr8; 1834*4882a593Smuzhiyun __le64 req_buf_page_addr9; 1835*4882a593Smuzhiyun __le64 error_buf_addr; 1836*4882a593Smuzhiyun __le64 resp_buf_addr; 1837*4882a593Smuzhiyun }; 1838*4882a593Smuzhiyun 1839*4882a593Smuzhiyun /* hwrm_func_buf_rgtr_output (size:128b/16B) */ 1840*4882a593Smuzhiyun struct hwrm_func_buf_rgtr_output { 1841*4882a593Smuzhiyun __le16 error_code; 1842*4882a593Smuzhiyun __le16 req_type; 1843*4882a593Smuzhiyun __le16 seq_id; 1844*4882a593Smuzhiyun __le16 resp_len; 1845*4882a593Smuzhiyun u8 unused_0[7]; 1846*4882a593Smuzhiyun u8 valid; 1847*4882a593Smuzhiyun }; 1848*4882a593Smuzhiyun 1849*4882a593Smuzhiyun /* hwrm_func_drv_qver_input (size:192b/24B) */ 1850*4882a593Smuzhiyun struct hwrm_func_drv_qver_input { 1851*4882a593Smuzhiyun __le16 req_type; 1852*4882a593Smuzhiyun __le16 cmpl_ring; 1853*4882a593Smuzhiyun __le16 seq_id; 1854*4882a593Smuzhiyun __le16 target_id; 1855*4882a593Smuzhiyun __le64 resp_addr; 1856*4882a593Smuzhiyun __le32 reserved; 1857*4882a593Smuzhiyun __le16 fid; 1858*4882a593Smuzhiyun u8 unused_0[2]; 1859*4882a593Smuzhiyun }; 1860*4882a593Smuzhiyun 1861*4882a593Smuzhiyun /* hwrm_func_drv_qver_output (size:256b/32B) */ 1862*4882a593Smuzhiyun struct hwrm_func_drv_qver_output { 1863*4882a593Smuzhiyun __le16 error_code; 1864*4882a593Smuzhiyun __le16 req_type; 1865*4882a593Smuzhiyun __le16 seq_id; 1866*4882a593Smuzhiyun __le16 resp_len; 1867*4882a593Smuzhiyun __le16 os_type; 1868*4882a593Smuzhiyun #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 1869*4882a593Smuzhiyun #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 1870*4882a593Smuzhiyun #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 1871*4882a593Smuzhiyun #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 1872*4882a593Smuzhiyun #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 1873*4882a593Smuzhiyun #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 1874*4882a593Smuzhiyun #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 1875*4882a593Smuzhiyun #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 1876*4882a593Smuzhiyun #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 1877*4882a593Smuzhiyun #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 1878*4882a593Smuzhiyun #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 1879*4882a593Smuzhiyun #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 1880*4882a593Smuzhiyun u8 ver_maj_8b; 1881*4882a593Smuzhiyun u8 ver_min_8b; 1882*4882a593Smuzhiyun u8 ver_upd_8b; 1883*4882a593Smuzhiyun u8 unused_0[3]; 1884*4882a593Smuzhiyun __le16 ver_maj; 1885*4882a593Smuzhiyun __le16 ver_min; 1886*4882a593Smuzhiyun __le16 ver_upd; 1887*4882a593Smuzhiyun __le16 ver_patch; 1888*4882a593Smuzhiyun u8 unused_1[7]; 1889*4882a593Smuzhiyun u8 valid; 1890*4882a593Smuzhiyun }; 1891*4882a593Smuzhiyun 1892*4882a593Smuzhiyun /* hwrm_func_resource_qcaps_input (size:192b/24B) */ 1893*4882a593Smuzhiyun struct hwrm_func_resource_qcaps_input { 1894*4882a593Smuzhiyun __le16 req_type; 1895*4882a593Smuzhiyun __le16 cmpl_ring; 1896*4882a593Smuzhiyun __le16 seq_id; 1897*4882a593Smuzhiyun __le16 target_id; 1898*4882a593Smuzhiyun __le64 resp_addr; 1899*4882a593Smuzhiyun __le16 fid; 1900*4882a593Smuzhiyun u8 unused_0[6]; 1901*4882a593Smuzhiyun }; 1902*4882a593Smuzhiyun 1903*4882a593Smuzhiyun /* hwrm_func_resource_qcaps_output (size:448b/56B) */ 1904*4882a593Smuzhiyun struct hwrm_func_resource_qcaps_output { 1905*4882a593Smuzhiyun __le16 error_code; 1906*4882a593Smuzhiyun __le16 req_type; 1907*4882a593Smuzhiyun __le16 seq_id; 1908*4882a593Smuzhiyun __le16 resp_len; 1909*4882a593Smuzhiyun __le16 max_vfs; 1910*4882a593Smuzhiyun __le16 max_msix; 1911*4882a593Smuzhiyun __le16 vf_reservation_strategy; 1912*4882a593Smuzhiyun #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 1913*4882a593Smuzhiyun #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 1914*4882a593Smuzhiyun #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 1915*4882a593Smuzhiyun #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 1916*4882a593Smuzhiyun __le16 min_rsscos_ctx; 1917*4882a593Smuzhiyun __le16 max_rsscos_ctx; 1918*4882a593Smuzhiyun __le16 min_cmpl_rings; 1919*4882a593Smuzhiyun __le16 max_cmpl_rings; 1920*4882a593Smuzhiyun __le16 min_tx_rings; 1921*4882a593Smuzhiyun __le16 max_tx_rings; 1922*4882a593Smuzhiyun __le16 min_rx_rings; 1923*4882a593Smuzhiyun __le16 max_rx_rings; 1924*4882a593Smuzhiyun __le16 min_l2_ctxs; 1925*4882a593Smuzhiyun __le16 max_l2_ctxs; 1926*4882a593Smuzhiyun __le16 min_vnics; 1927*4882a593Smuzhiyun __le16 max_vnics; 1928*4882a593Smuzhiyun __le16 min_stat_ctx; 1929*4882a593Smuzhiyun __le16 max_stat_ctx; 1930*4882a593Smuzhiyun __le16 min_hw_ring_grps; 1931*4882a593Smuzhiyun __le16 max_hw_ring_grps; 1932*4882a593Smuzhiyun __le16 max_tx_scheduler_inputs; 1933*4882a593Smuzhiyun __le16 flags; 1934*4882a593Smuzhiyun #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL 1935*4882a593Smuzhiyun u8 unused_0[5]; 1936*4882a593Smuzhiyun u8 valid; 1937*4882a593Smuzhiyun }; 1938*4882a593Smuzhiyun 1939*4882a593Smuzhiyun /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ 1940*4882a593Smuzhiyun struct hwrm_func_vf_resource_cfg_input { 1941*4882a593Smuzhiyun __le16 req_type; 1942*4882a593Smuzhiyun __le16 cmpl_ring; 1943*4882a593Smuzhiyun __le16 seq_id; 1944*4882a593Smuzhiyun __le16 target_id; 1945*4882a593Smuzhiyun __le64 resp_addr; 1946*4882a593Smuzhiyun __le16 vf_id; 1947*4882a593Smuzhiyun __le16 max_msix; 1948*4882a593Smuzhiyun __le16 min_rsscos_ctx; 1949*4882a593Smuzhiyun __le16 max_rsscos_ctx; 1950*4882a593Smuzhiyun __le16 min_cmpl_rings; 1951*4882a593Smuzhiyun __le16 max_cmpl_rings; 1952*4882a593Smuzhiyun __le16 min_tx_rings; 1953*4882a593Smuzhiyun __le16 max_tx_rings; 1954*4882a593Smuzhiyun __le16 min_rx_rings; 1955*4882a593Smuzhiyun __le16 max_rx_rings; 1956*4882a593Smuzhiyun __le16 min_l2_ctxs; 1957*4882a593Smuzhiyun __le16 max_l2_ctxs; 1958*4882a593Smuzhiyun __le16 min_vnics; 1959*4882a593Smuzhiyun __le16 max_vnics; 1960*4882a593Smuzhiyun __le16 min_stat_ctx; 1961*4882a593Smuzhiyun __le16 max_stat_ctx; 1962*4882a593Smuzhiyun __le16 min_hw_ring_grps; 1963*4882a593Smuzhiyun __le16 max_hw_ring_grps; 1964*4882a593Smuzhiyun __le16 flags; 1965*4882a593Smuzhiyun #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL 1966*4882a593Smuzhiyun u8 unused_0[2]; 1967*4882a593Smuzhiyun }; 1968*4882a593Smuzhiyun 1969*4882a593Smuzhiyun /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ 1970*4882a593Smuzhiyun struct hwrm_func_vf_resource_cfg_output { 1971*4882a593Smuzhiyun __le16 error_code; 1972*4882a593Smuzhiyun __le16 req_type; 1973*4882a593Smuzhiyun __le16 seq_id; 1974*4882a593Smuzhiyun __le16 resp_len; 1975*4882a593Smuzhiyun __le16 reserved_rsscos_ctx; 1976*4882a593Smuzhiyun __le16 reserved_cmpl_rings; 1977*4882a593Smuzhiyun __le16 reserved_tx_rings; 1978*4882a593Smuzhiyun __le16 reserved_rx_rings; 1979*4882a593Smuzhiyun __le16 reserved_l2_ctxs; 1980*4882a593Smuzhiyun __le16 reserved_vnics; 1981*4882a593Smuzhiyun __le16 reserved_stat_ctx; 1982*4882a593Smuzhiyun __le16 reserved_hw_ring_grps; 1983*4882a593Smuzhiyun u8 unused_0[7]; 1984*4882a593Smuzhiyun u8 valid; 1985*4882a593Smuzhiyun }; 1986*4882a593Smuzhiyun 1987*4882a593Smuzhiyun /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ 1988*4882a593Smuzhiyun struct hwrm_func_backing_store_qcaps_input { 1989*4882a593Smuzhiyun __le16 req_type; 1990*4882a593Smuzhiyun __le16 cmpl_ring; 1991*4882a593Smuzhiyun __le16 seq_id; 1992*4882a593Smuzhiyun __le16 target_id; 1993*4882a593Smuzhiyun __le64 resp_addr; 1994*4882a593Smuzhiyun }; 1995*4882a593Smuzhiyun 1996*4882a593Smuzhiyun /* hwrm_func_backing_store_qcaps_output (size:640b/80B) */ 1997*4882a593Smuzhiyun struct hwrm_func_backing_store_qcaps_output { 1998*4882a593Smuzhiyun __le16 error_code; 1999*4882a593Smuzhiyun __le16 req_type; 2000*4882a593Smuzhiyun __le16 seq_id; 2001*4882a593Smuzhiyun __le16 resp_len; 2002*4882a593Smuzhiyun __le32 qp_max_entries; 2003*4882a593Smuzhiyun __le16 qp_min_qp1_entries; 2004*4882a593Smuzhiyun __le16 qp_max_l2_entries; 2005*4882a593Smuzhiyun __le16 qp_entry_size; 2006*4882a593Smuzhiyun __le16 srq_max_l2_entries; 2007*4882a593Smuzhiyun __le32 srq_max_entries; 2008*4882a593Smuzhiyun __le16 srq_entry_size; 2009*4882a593Smuzhiyun __le16 cq_max_l2_entries; 2010*4882a593Smuzhiyun __le32 cq_max_entries; 2011*4882a593Smuzhiyun __le16 cq_entry_size; 2012*4882a593Smuzhiyun __le16 vnic_max_vnic_entries; 2013*4882a593Smuzhiyun __le16 vnic_max_ring_table_entries; 2014*4882a593Smuzhiyun __le16 vnic_entry_size; 2015*4882a593Smuzhiyun __le32 stat_max_entries; 2016*4882a593Smuzhiyun __le16 stat_entry_size; 2017*4882a593Smuzhiyun __le16 tqm_entry_size; 2018*4882a593Smuzhiyun __le32 tqm_min_entries_per_ring; 2019*4882a593Smuzhiyun __le32 tqm_max_entries_per_ring; 2020*4882a593Smuzhiyun __le32 mrav_max_entries; 2021*4882a593Smuzhiyun __le16 mrav_entry_size; 2022*4882a593Smuzhiyun __le16 tim_entry_size; 2023*4882a593Smuzhiyun __le32 tim_max_entries; 2024*4882a593Smuzhiyun __le16 mrav_num_entries_units; 2025*4882a593Smuzhiyun u8 tqm_entries_multiple; 2026*4882a593Smuzhiyun u8 ctx_kind_initializer; 2027*4882a593Smuzhiyun __le32 rsvd; 2028*4882a593Smuzhiyun __le16 rsvd1; 2029*4882a593Smuzhiyun u8 tqm_fp_rings_count; 2030*4882a593Smuzhiyun u8 valid; 2031*4882a593Smuzhiyun }; 2032*4882a593Smuzhiyun 2033*4882a593Smuzhiyun /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */ 2034*4882a593Smuzhiyun struct hwrm_func_backing_store_cfg_input { 2035*4882a593Smuzhiyun __le16 req_type; 2036*4882a593Smuzhiyun __le16 cmpl_ring; 2037*4882a593Smuzhiyun __le16 seq_id; 2038*4882a593Smuzhiyun __le16 target_id; 2039*4882a593Smuzhiyun __le64 resp_addr; 2040*4882a593Smuzhiyun __le32 flags; 2041*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 2042*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL 2043*4882a593Smuzhiyun __le32 enables; 2044*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 2045*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 2046*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 2047*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 2048*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 2049*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 2050*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 2051*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 2052*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 2053*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 2054*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 2055*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 2056*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 2057*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 2058*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 2059*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 2060*4882a593Smuzhiyun u8 qpc_pg_size_qpc_lvl; 2061*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 2062*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 2063*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL 2064*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL 2065*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL 2066*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 2067*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL 2068*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4 2069*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4) 2070*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4) 2071*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4) 2072*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4) 2073*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4) 2074*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4) 2075*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G 2076*4882a593Smuzhiyun u8 srq_pg_size_srq_lvl; 2077*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL 2078*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0 2079*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL 2080*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL 2081*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL 2082*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 2083*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL 2084*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4 2085*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 2086*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 2087*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 2088*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 2089*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 2090*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 2091*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G 2092*4882a593Smuzhiyun u8 cq_pg_size_cq_lvl; 2093*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL 2094*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0 2095*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL 2096*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL 2097*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL 2098*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 2099*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL 2100*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4 2101*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4) 2102*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4) 2103*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4) 2104*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4) 2105*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4) 2106*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4) 2107*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G 2108*4882a593Smuzhiyun u8 vnic_pg_size_vnic_lvl; 2109*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL 2110*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0 2111*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL 2112*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL 2113*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL 2114*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 2115*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL 2116*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4 2117*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4) 2118*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4) 2119*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4) 2120*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4) 2121*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4) 2122*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4) 2123*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G 2124*4882a593Smuzhiyun u8 stat_pg_size_stat_lvl; 2125*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL 2126*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0 2127*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL 2128*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL 2129*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL 2130*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 2131*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL 2132*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4 2133*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4) 2134*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4) 2135*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4) 2136*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4) 2137*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4) 2138*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4) 2139*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G 2140*4882a593Smuzhiyun u8 tqm_sp_pg_size_tqm_sp_lvl; 2141*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL 2142*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0 2143*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL 2144*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL 2145*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL 2146*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 2147*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL 2148*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4 2149*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4) 2150*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4) 2151*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4) 2152*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4) 2153*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4) 2154*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4) 2155*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G 2156*4882a593Smuzhiyun u8 tqm_ring0_pg_size_tqm_ring0_lvl; 2157*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL 2158*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0 2159*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL 2160*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL 2161*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL 2162*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 2163*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL 2164*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4 2165*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4) 2166*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4) 2167*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4) 2168*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4) 2169*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4) 2170*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4) 2171*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G 2172*4882a593Smuzhiyun u8 tqm_ring1_pg_size_tqm_ring1_lvl; 2173*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL 2174*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0 2175*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL 2176*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL 2177*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL 2178*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 2179*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL 2180*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4 2181*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4) 2182*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4) 2183*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4) 2184*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4) 2185*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4) 2186*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4) 2187*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G 2188*4882a593Smuzhiyun u8 tqm_ring2_pg_size_tqm_ring2_lvl; 2189*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL 2190*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0 2191*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL 2192*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL 2193*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL 2194*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 2195*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL 2196*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4 2197*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4) 2198*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4) 2199*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4) 2200*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4) 2201*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4) 2202*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4) 2203*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G 2204*4882a593Smuzhiyun u8 tqm_ring3_pg_size_tqm_ring3_lvl; 2205*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL 2206*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0 2207*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL 2208*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL 2209*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL 2210*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 2211*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL 2212*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4 2213*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4) 2214*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4) 2215*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4) 2216*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4) 2217*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4) 2218*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4) 2219*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G 2220*4882a593Smuzhiyun u8 tqm_ring4_pg_size_tqm_ring4_lvl; 2221*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL 2222*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0 2223*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL 2224*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL 2225*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL 2226*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 2227*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL 2228*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4 2229*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4) 2230*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4) 2231*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4) 2232*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4) 2233*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4) 2234*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4) 2235*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G 2236*4882a593Smuzhiyun u8 tqm_ring5_pg_size_tqm_ring5_lvl; 2237*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL 2238*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0 2239*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL 2240*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL 2241*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL 2242*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 2243*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL 2244*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4 2245*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4) 2246*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4) 2247*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4) 2248*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4) 2249*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4) 2250*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4) 2251*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G 2252*4882a593Smuzhiyun u8 tqm_ring6_pg_size_tqm_ring6_lvl; 2253*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL 2254*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0 2255*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL 2256*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL 2257*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL 2258*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 2259*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL 2260*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4 2261*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4) 2262*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4) 2263*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4) 2264*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4) 2265*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4) 2266*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4) 2267*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G 2268*4882a593Smuzhiyun u8 tqm_ring7_pg_size_tqm_ring7_lvl; 2269*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL 2270*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0 2271*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL 2272*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL 2273*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL 2274*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 2275*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL 2276*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4 2277*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4) 2278*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4) 2279*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4) 2280*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4) 2281*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4) 2282*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4) 2283*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G 2284*4882a593Smuzhiyun u8 mrav_pg_size_mrav_lvl; 2285*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL 2286*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0 2287*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL 2288*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL 2289*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL 2290*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 2291*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL 2292*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4 2293*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4) 2294*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4) 2295*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4) 2296*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4) 2297*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4) 2298*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4) 2299*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G 2300*4882a593Smuzhiyun u8 tim_pg_size_tim_lvl; 2301*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL 2302*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0 2303*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL 2304*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL 2305*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL 2306*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 2307*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL 2308*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4 2309*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4) 2310*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4) 2311*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4) 2312*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4) 2313*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4) 2314*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4) 2315*4882a593Smuzhiyun #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G 2316*4882a593Smuzhiyun __le64 qpc_page_dir; 2317*4882a593Smuzhiyun __le64 srq_page_dir; 2318*4882a593Smuzhiyun __le64 cq_page_dir; 2319*4882a593Smuzhiyun __le64 vnic_page_dir; 2320*4882a593Smuzhiyun __le64 stat_page_dir; 2321*4882a593Smuzhiyun __le64 tqm_sp_page_dir; 2322*4882a593Smuzhiyun __le64 tqm_ring0_page_dir; 2323*4882a593Smuzhiyun __le64 tqm_ring1_page_dir; 2324*4882a593Smuzhiyun __le64 tqm_ring2_page_dir; 2325*4882a593Smuzhiyun __le64 tqm_ring3_page_dir; 2326*4882a593Smuzhiyun __le64 tqm_ring4_page_dir; 2327*4882a593Smuzhiyun __le64 tqm_ring5_page_dir; 2328*4882a593Smuzhiyun __le64 tqm_ring6_page_dir; 2329*4882a593Smuzhiyun __le64 tqm_ring7_page_dir; 2330*4882a593Smuzhiyun __le64 mrav_page_dir; 2331*4882a593Smuzhiyun __le64 tim_page_dir; 2332*4882a593Smuzhiyun __le32 qp_num_entries; 2333*4882a593Smuzhiyun __le32 srq_num_entries; 2334*4882a593Smuzhiyun __le32 cq_num_entries; 2335*4882a593Smuzhiyun __le32 stat_num_entries; 2336*4882a593Smuzhiyun __le32 tqm_sp_num_entries; 2337*4882a593Smuzhiyun __le32 tqm_ring0_num_entries; 2338*4882a593Smuzhiyun __le32 tqm_ring1_num_entries; 2339*4882a593Smuzhiyun __le32 tqm_ring2_num_entries; 2340*4882a593Smuzhiyun __le32 tqm_ring3_num_entries; 2341*4882a593Smuzhiyun __le32 tqm_ring4_num_entries; 2342*4882a593Smuzhiyun __le32 tqm_ring5_num_entries; 2343*4882a593Smuzhiyun __le32 tqm_ring6_num_entries; 2344*4882a593Smuzhiyun __le32 tqm_ring7_num_entries; 2345*4882a593Smuzhiyun __le32 mrav_num_entries; 2346*4882a593Smuzhiyun __le32 tim_num_entries; 2347*4882a593Smuzhiyun __le16 qp_num_qp1_entries; 2348*4882a593Smuzhiyun __le16 qp_num_l2_entries; 2349*4882a593Smuzhiyun __le16 qp_entry_size; 2350*4882a593Smuzhiyun __le16 srq_num_l2_entries; 2351*4882a593Smuzhiyun __le16 srq_entry_size; 2352*4882a593Smuzhiyun __le16 cq_num_l2_entries; 2353*4882a593Smuzhiyun __le16 cq_entry_size; 2354*4882a593Smuzhiyun __le16 vnic_num_vnic_entries; 2355*4882a593Smuzhiyun __le16 vnic_num_ring_table_entries; 2356*4882a593Smuzhiyun __le16 vnic_entry_size; 2357*4882a593Smuzhiyun __le16 stat_entry_size; 2358*4882a593Smuzhiyun __le16 tqm_entry_size; 2359*4882a593Smuzhiyun __le16 mrav_entry_size; 2360*4882a593Smuzhiyun __le16 tim_entry_size; 2361*4882a593Smuzhiyun }; 2362*4882a593Smuzhiyun 2363*4882a593Smuzhiyun /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ 2364*4882a593Smuzhiyun struct hwrm_func_backing_store_cfg_output { 2365*4882a593Smuzhiyun __le16 error_code; 2366*4882a593Smuzhiyun __le16 req_type; 2367*4882a593Smuzhiyun __le16 seq_id; 2368*4882a593Smuzhiyun __le16 resp_len; 2369*4882a593Smuzhiyun u8 unused_0[7]; 2370*4882a593Smuzhiyun u8 valid; 2371*4882a593Smuzhiyun }; 2372*4882a593Smuzhiyun 2373*4882a593Smuzhiyun /* hwrm_error_recovery_qcfg_input (size:192b/24B) */ 2374*4882a593Smuzhiyun struct hwrm_error_recovery_qcfg_input { 2375*4882a593Smuzhiyun __le16 req_type; 2376*4882a593Smuzhiyun __le16 cmpl_ring; 2377*4882a593Smuzhiyun __le16 seq_id; 2378*4882a593Smuzhiyun __le16 target_id; 2379*4882a593Smuzhiyun __le64 resp_addr; 2380*4882a593Smuzhiyun u8 unused_0[8]; 2381*4882a593Smuzhiyun }; 2382*4882a593Smuzhiyun 2383*4882a593Smuzhiyun /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ 2384*4882a593Smuzhiyun struct hwrm_error_recovery_qcfg_output { 2385*4882a593Smuzhiyun __le16 error_code; 2386*4882a593Smuzhiyun __le16 req_type; 2387*4882a593Smuzhiyun __le16 seq_id; 2388*4882a593Smuzhiyun __le16 resp_len; 2389*4882a593Smuzhiyun __le32 flags; 2390*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL 2391*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL 2392*4882a593Smuzhiyun __le32 driver_polling_freq; 2393*4882a593Smuzhiyun __le32 master_func_wait_period; 2394*4882a593Smuzhiyun __le32 normal_func_wait_period; 2395*4882a593Smuzhiyun __le32 master_func_wait_period_after_reset; 2396*4882a593Smuzhiyun __le32 max_bailout_time_after_reset; 2397*4882a593Smuzhiyun __le32 fw_health_status_reg; 2398*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL 2399*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0 2400*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2401*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL 2402*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL 2403*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL 2404*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 2405*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL 2406*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2 2407*4882a593Smuzhiyun __le32 fw_heartbeat_reg; 2408*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL 2409*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0 2410*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2411*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL 2412*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL 2413*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL 2414*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 2415*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL 2416*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2 2417*4882a593Smuzhiyun __le32 fw_reset_cnt_reg; 2418*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL 2419*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0 2420*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2421*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL 2422*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL 2423*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL 2424*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 2425*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL 2426*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2 2427*4882a593Smuzhiyun __le32 reset_inprogress_reg; 2428*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL 2429*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0 2430*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2431*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL 2432*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL 2433*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL 2434*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 2435*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL 2436*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2 2437*4882a593Smuzhiyun __le32 reset_inprogress_reg_mask; 2438*4882a593Smuzhiyun u8 unused_0[3]; 2439*4882a593Smuzhiyun u8 reg_array_cnt; 2440*4882a593Smuzhiyun __le32 reset_reg[16]; 2441*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL 2442*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0 2443*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2444*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL 2445*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL 2446*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL 2447*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 2448*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL 2449*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2 2450*4882a593Smuzhiyun __le32 reset_reg_val[16]; 2451*4882a593Smuzhiyun u8 delay_after_reset[16]; 2452*4882a593Smuzhiyun __le32 err_recovery_cnt_reg; 2453*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK 0x3UL 2454*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0 2455*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2456*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC 0x1UL 2457*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 0x2UL 2458*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 0x3UL 2459*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 2460*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK 0xfffffffcUL 2461*4882a593Smuzhiyun #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT 2 2462*4882a593Smuzhiyun u8 unused_1[3]; 2463*4882a593Smuzhiyun u8 valid; 2464*4882a593Smuzhiyun }; 2465*4882a593Smuzhiyun 2466*4882a593Smuzhiyun /* hwrm_func_drv_if_change_input (size:192b/24B) */ 2467*4882a593Smuzhiyun struct hwrm_func_drv_if_change_input { 2468*4882a593Smuzhiyun __le16 req_type; 2469*4882a593Smuzhiyun __le16 cmpl_ring; 2470*4882a593Smuzhiyun __le16 seq_id; 2471*4882a593Smuzhiyun __le16 target_id; 2472*4882a593Smuzhiyun __le64 resp_addr; 2473*4882a593Smuzhiyun __le32 flags; 2474*4882a593Smuzhiyun #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL 2475*4882a593Smuzhiyun __le32 unused; 2476*4882a593Smuzhiyun }; 2477*4882a593Smuzhiyun 2478*4882a593Smuzhiyun /* hwrm_func_drv_if_change_output (size:128b/16B) */ 2479*4882a593Smuzhiyun struct hwrm_func_drv_if_change_output { 2480*4882a593Smuzhiyun __le16 error_code; 2481*4882a593Smuzhiyun __le16 req_type; 2482*4882a593Smuzhiyun __le16 seq_id; 2483*4882a593Smuzhiyun __le16 resp_len; 2484*4882a593Smuzhiyun __le32 flags; 2485*4882a593Smuzhiyun #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 2486*4882a593Smuzhiyun #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL 2487*4882a593Smuzhiyun u8 unused_0[3]; 2488*4882a593Smuzhiyun u8 valid; 2489*4882a593Smuzhiyun }; 2490*4882a593Smuzhiyun 2491*4882a593Smuzhiyun /* hwrm_port_phy_cfg_input (size:448b/56B) */ 2492*4882a593Smuzhiyun struct hwrm_port_phy_cfg_input { 2493*4882a593Smuzhiyun __le16 req_type; 2494*4882a593Smuzhiyun __le16 cmpl_ring; 2495*4882a593Smuzhiyun __le16 seq_id; 2496*4882a593Smuzhiyun __le16 target_id; 2497*4882a593Smuzhiyun __le64 resp_addr; 2498*4882a593Smuzhiyun __le32 flags; 2499*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 2500*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 2501*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 2502*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 2503*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 2504*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 2505*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 2506*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 2507*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 2508*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 2509*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 2510*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 2511*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 2512*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 2513*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 2514*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL 2515*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL 2516*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE 0x20000UL 2517*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE 0x40000UL 2518*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE 0x80000UL 2519*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL 2520*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL 2521*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL 2522*4882a593Smuzhiyun __le32 enables; 2523*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 2524*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 2525*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 2526*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 2527*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 2528*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 2529*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 2530*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 2531*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 2532*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 2533*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 2534*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL 2535*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL 2536*4882a593Smuzhiyun __le16 port_id; 2537*4882a593Smuzhiyun __le16 force_link_speed; 2538*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 2539*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 2540*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 2541*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 2542*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 2543*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 2544*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 2545*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 2546*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 2547*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 2548*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 2549*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 2550*4882a593Smuzhiyun u8 auto_mode; 2551*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 2552*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 2553*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 2554*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 2555*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 2556*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 2557*4882a593Smuzhiyun u8 auto_duplex; 2558*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 2559*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 2560*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 2561*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 2562*4882a593Smuzhiyun u8 auto_pause; 2563*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 2564*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 2565*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 2566*4882a593Smuzhiyun u8 unused_0; 2567*4882a593Smuzhiyun __le16 auto_link_speed; 2568*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 2569*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 2570*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 2571*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 2572*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 2573*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 2574*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 2575*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 2576*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 2577*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 2578*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 2579*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 2580*4882a593Smuzhiyun __le16 auto_link_speed_mask; 2581*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 2582*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 2583*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 2584*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 2585*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 2586*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 2587*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 2588*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 2589*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 2590*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 2591*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 2592*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 2593*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 2594*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 2595*4882a593Smuzhiyun u8 wirespeed; 2596*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 2597*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 2598*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 2599*4882a593Smuzhiyun u8 lpbk; 2600*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 2601*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 2602*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 2603*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL 2604*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL 2605*4882a593Smuzhiyun u8 force_pause; 2606*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 2607*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 2608*4882a593Smuzhiyun u8 unused_1; 2609*4882a593Smuzhiyun __le32 preemphasis; 2610*4882a593Smuzhiyun __le16 eee_link_speed_mask; 2611*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2612*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 2613*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2614*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 2615*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2616*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2617*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 2618*4882a593Smuzhiyun __le16 force_pam4_link_speed; 2619*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 2620*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 2621*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 2622*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 2623*4882a593Smuzhiyun __le32 tx_lpi_timer; 2624*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 2625*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 2626*4882a593Smuzhiyun __le16 auto_link_pam4_speed_mask; 2627*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL 2628*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL 2629*4882a593Smuzhiyun #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL 2630*4882a593Smuzhiyun u8 unused_2[2]; 2631*4882a593Smuzhiyun }; 2632*4882a593Smuzhiyun 2633*4882a593Smuzhiyun /* hwrm_port_phy_cfg_output (size:128b/16B) */ 2634*4882a593Smuzhiyun struct hwrm_port_phy_cfg_output { 2635*4882a593Smuzhiyun __le16 error_code; 2636*4882a593Smuzhiyun __le16 req_type; 2637*4882a593Smuzhiyun __le16 seq_id; 2638*4882a593Smuzhiyun __le16 resp_len; 2639*4882a593Smuzhiyun u8 unused_0[7]; 2640*4882a593Smuzhiyun u8 valid; 2641*4882a593Smuzhiyun }; 2642*4882a593Smuzhiyun 2643*4882a593Smuzhiyun /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 2644*4882a593Smuzhiyun struct hwrm_port_phy_cfg_cmd_err { 2645*4882a593Smuzhiyun u8 code; 2646*4882a593Smuzhiyun #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 2647*4882a593Smuzhiyun #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 2648*4882a593Smuzhiyun #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 2649*4882a593Smuzhiyun #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 2650*4882a593Smuzhiyun u8 unused_0[7]; 2651*4882a593Smuzhiyun }; 2652*4882a593Smuzhiyun 2653*4882a593Smuzhiyun /* hwrm_port_phy_qcfg_input (size:192b/24B) */ 2654*4882a593Smuzhiyun struct hwrm_port_phy_qcfg_input { 2655*4882a593Smuzhiyun __le16 req_type; 2656*4882a593Smuzhiyun __le16 cmpl_ring; 2657*4882a593Smuzhiyun __le16 seq_id; 2658*4882a593Smuzhiyun __le16 target_id; 2659*4882a593Smuzhiyun __le64 resp_addr; 2660*4882a593Smuzhiyun __le16 port_id; 2661*4882a593Smuzhiyun u8 unused_0[6]; 2662*4882a593Smuzhiyun }; 2663*4882a593Smuzhiyun 2664*4882a593Smuzhiyun /* hwrm_port_phy_qcfg_output (size:768b/96B) */ 2665*4882a593Smuzhiyun struct hwrm_port_phy_qcfg_output { 2666*4882a593Smuzhiyun __le16 error_code; 2667*4882a593Smuzhiyun __le16 req_type; 2668*4882a593Smuzhiyun __le16 seq_id; 2669*4882a593Smuzhiyun __le16 resp_len; 2670*4882a593Smuzhiyun u8 link; 2671*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 2672*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 2673*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 2674*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 2675*4882a593Smuzhiyun u8 active_fec_signal_mode; 2676*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL 2677*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0 2678*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL 2679*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL 2680*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 2681*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL 2682*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4 2683*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4) 2684*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (0x1UL << 4) 2685*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (0x2UL << 4) 2686*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (0x3UL << 4) 2687*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (0x4UL << 4) 2688*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (0x5UL << 4) 2689*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (0x6UL << 4) 2690*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE 2691*4882a593Smuzhiyun __le16 link_speed; 2692*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 2693*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 2694*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 2695*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 2696*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 2697*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 2698*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 2699*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 2700*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 2701*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 2702*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL 2703*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 2704*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 2705*4882a593Smuzhiyun u8 duplex_cfg; 2706*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 2707*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 2708*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 2709*4882a593Smuzhiyun u8 pause; 2710*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 2711*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 2712*4882a593Smuzhiyun __le16 support_speeds; 2713*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 2714*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 2715*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 2716*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 2717*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 2718*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 2719*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 2720*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 2721*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 2722*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 2723*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 2724*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 2725*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 2726*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 2727*4882a593Smuzhiyun __le16 force_link_speed; 2728*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 2729*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 2730*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 2731*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 2732*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 2733*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 2734*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 2735*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 2736*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 2737*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 2738*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 2739*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 2740*4882a593Smuzhiyun u8 auto_mode; 2741*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 2742*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 2743*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 2744*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 2745*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 2746*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 2747*4882a593Smuzhiyun u8 auto_pause; 2748*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 2749*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 2750*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 2751*4882a593Smuzhiyun __le16 auto_link_speed; 2752*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 2753*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 2754*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 2755*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 2756*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 2757*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 2758*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 2759*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 2760*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 2761*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 2762*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 2763*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 2764*4882a593Smuzhiyun __le16 auto_link_speed_mask; 2765*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 2766*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 2767*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 2768*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 2769*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 2770*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 2771*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 2772*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 2773*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 2774*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 2775*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 2776*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 2777*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 2778*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 2779*4882a593Smuzhiyun u8 wirespeed; 2780*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 2781*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 2782*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 2783*4882a593Smuzhiyun u8 lpbk; 2784*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 2785*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 2786*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 2787*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL 2788*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 2789*4882a593Smuzhiyun u8 force_pause; 2790*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 2791*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 2792*4882a593Smuzhiyun u8 module_status; 2793*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 2794*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 2795*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 2796*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 2797*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 2798*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL 2799*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 2800*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 2801*4882a593Smuzhiyun __le32 preemphasis; 2802*4882a593Smuzhiyun u8 phy_maj; 2803*4882a593Smuzhiyun u8 phy_min; 2804*4882a593Smuzhiyun u8 phy_bld; 2805*4882a593Smuzhiyun u8 phy_type; 2806*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 2807*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 2808*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 2809*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 2810*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 2811*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 2812*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 2813*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 2814*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 2815*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 2816*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 2817*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 2818*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 2819*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 2820*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 2821*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 2822*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 2823*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 2824*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 2825*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 2826*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 2827*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 2828*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 2829*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 2830*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 2831*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 2832*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 2833*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 2834*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL 2835*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL 2836*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL 2837*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL 2838*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 2839*4882a593Smuzhiyun u8 media_type; 2840*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 2841*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 2842*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 2843*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 2844*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 2845*4882a593Smuzhiyun u8 xcvr_pkg_type; 2846*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 2847*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 2848*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 2849*4882a593Smuzhiyun u8 eee_config_phy_addr; 2850*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 2851*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 2852*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 2853*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 2854*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 2855*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 2856*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 2857*4882a593Smuzhiyun u8 parallel_detect; 2858*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 2859*4882a593Smuzhiyun __le16 link_partner_adv_speeds; 2860*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 2861*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 2862*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 2863*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 2864*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 2865*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 2866*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 2867*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 2868*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 2869*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 2870*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 2871*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 2872*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 2873*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 2874*4882a593Smuzhiyun u8 link_partner_adv_auto_mode; 2875*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 2876*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 2877*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 2878*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 2879*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 2880*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 2881*4882a593Smuzhiyun u8 link_partner_adv_pause; 2882*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 2883*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 2884*4882a593Smuzhiyun __le16 adv_eee_link_speed_mask; 2885*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2886*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 2887*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2888*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 2889*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2890*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2891*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 2892*4882a593Smuzhiyun __le16 link_partner_adv_eee_link_speed_mask; 2893*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2894*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 2895*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2896*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 2897*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2898*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2899*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 2900*4882a593Smuzhiyun __le32 xcvr_identifier_type_tx_lpi_timer; 2901*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 2902*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 2903*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 2904*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 2905*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 2906*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 2907*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 2908*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 2909*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 2910*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 2911*4882a593Smuzhiyun __le16 fec_cfg; 2912*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 2913*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 2914*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 2915*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 2916*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 2917*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 2918*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 2919*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL 2920*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL 2921*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED 0x200UL 2922*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED 0x400UL 2923*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED 0x800UL 2924*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED 0x1000UL 2925*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED 0x2000UL 2926*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED 0x4000UL 2927*4882a593Smuzhiyun u8 duplex_state; 2928*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 2929*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 2930*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 2931*4882a593Smuzhiyun u8 option_flags; 2932*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 2933*4882a593Smuzhiyun char phy_vendor_name[16]; 2934*4882a593Smuzhiyun char phy_vendor_partnumber[16]; 2935*4882a593Smuzhiyun __le16 support_pam4_speeds; 2936*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL 2937*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL 2938*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL 2939*4882a593Smuzhiyun __le16 force_pam4_link_speed; 2940*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 2941*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 2942*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 2943*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 2944*4882a593Smuzhiyun __le16 auto_pam4_link_speed_mask; 2945*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL 2946*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL 2947*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL 2948*4882a593Smuzhiyun u8 link_partner_pam4_adv_speeds; 2949*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL 2950*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL 2951*4882a593Smuzhiyun #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL 2952*4882a593Smuzhiyun u8 valid; 2953*4882a593Smuzhiyun }; 2954*4882a593Smuzhiyun 2955*4882a593Smuzhiyun /* hwrm_port_mac_cfg_input (size:384b/48B) */ 2956*4882a593Smuzhiyun struct hwrm_port_mac_cfg_input { 2957*4882a593Smuzhiyun __le16 req_type; 2958*4882a593Smuzhiyun __le16 cmpl_ring; 2959*4882a593Smuzhiyun __le16 seq_id; 2960*4882a593Smuzhiyun __le16 target_id; 2961*4882a593Smuzhiyun __le64 resp_addr; 2962*4882a593Smuzhiyun __le32 flags; 2963*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 2964*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 2965*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 2966*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 2967*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 2968*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 2969*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 2970*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 2971*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 2972*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 2973*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 2974*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 2975*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 2976*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL 2977*4882a593Smuzhiyun __le32 enables; 2978*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 2979*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 2980*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 2981*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 2982*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 2983*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 2984*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 2985*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 2986*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL 2987*4882a593Smuzhiyun __le16 port_id; 2988*4882a593Smuzhiyun u8 ipg; 2989*4882a593Smuzhiyun u8 lpbk; 2990*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 2991*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 2992*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 2993*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 2994*4882a593Smuzhiyun u8 vlan_pri2cos_map_pri; 2995*4882a593Smuzhiyun u8 reserved1; 2996*4882a593Smuzhiyun u8 tunnel_pri2cos_map_pri; 2997*4882a593Smuzhiyun u8 dscp2pri_map_pri; 2998*4882a593Smuzhiyun __le16 rx_ts_capture_ptp_msg_type; 2999*4882a593Smuzhiyun __le16 tx_ts_capture_ptp_msg_type; 3000*4882a593Smuzhiyun u8 cos_field_cfg; 3001*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 3002*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 3003*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 3004*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 3005*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 3006*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 3007*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 3008*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 3009*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 3010*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 3011*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 3012*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 3013*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 3014*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 3015*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 3016*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 3017*4882a593Smuzhiyun #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 3018*4882a593Smuzhiyun u8 unused_0[3]; 3019*4882a593Smuzhiyun __s32 ptp_freq_adj_ppb; 3020*4882a593Smuzhiyun u8 unused_1[4]; 3021*4882a593Smuzhiyun }; 3022*4882a593Smuzhiyun 3023*4882a593Smuzhiyun /* hwrm_port_mac_cfg_output (size:128b/16B) */ 3024*4882a593Smuzhiyun struct hwrm_port_mac_cfg_output { 3025*4882a593Smuzhiyun __le16 error_code; 3026*4882a593Smuzhiyun __le16 req_type; 3027*4882a593Smuzhiyun __le16 seq_id; 3028*4882a593Smuzhiyun __le16 resp_len; 3029*4882a593Smuzhiyun __le16 mru; 3030*4882a593Smuzhiyun __le16 mtu; 3031*4882a593Smuzhiyun u8 ipg; 3032*4882a593Smuzhiyun u8 lpbk; 3033*4882a593Smuzhiyun #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 3034*4882a593Smuzhiyun #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 3035*4882a593Smuzhiyun #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 3036*4882a593Smuzhiyun #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 3037*4882a593Smuzhiyun u8 unused_0; 3038*4882a593Smuzhiyun u8 valid; 3039*4882a593Smuzhiyun }; 3040*4882a593Smuzhiyun 3041*4882a593Smuzhiyun /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 3042*4882a593Smuzhiyun struct hwrm_port_mac_ptp_qcfg_input { 3043*4882a593Smuzhiyun __le16 req_type; 3044*4882a593Smuzhiyun __le16 cmpl_ring; 3045*4882a593Smuzhiyun __le16 seq_id; 3046*4882a593Smuzhiyun __le16 target_id; 3047*4882a593Smuzhiyun __le64 resp_addr; 3048*4882a593Smuzhiyun __le16 port_id; 3049*4882a593Smuzhiyun u8 unused_0[6]; 3050*4882a593Smuzhiyun }; 3051*4882a593Smuzhiyun 3052*4882a593Smuzhiyun /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ 3053*4882a593Smuzhiyun struct hwrm_port_mac_ptp_qcfg_output { 3054*4882a593Smuzhiyun __le16 error_code; 3055*4882a593Smuzhiyun __le16 req_type; 3056*4882a593Smuzhiyun __le16 seq_id; 3057*4882a593Smuzhiyun __le16 resp_len; 3058*4882a593Smuzhiyun u8 flags; 3059*4882a593Smuzhiyun #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 3060*4882a593Smuzhiyun #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL 3061*4882a593Smuzhiyun #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL 3062*4882a593Smuzhiyun u8 unused_0[3]; 3063*4882a593Smuzhiyun __le32 rx_ts_reg_off_lower; 3064*4882a593Smuzhiyun __le32 rx_ts_reg_off_upper; 3065*4882a593Smuzhiyun __le32 rx_ts_reg_off_seq_id; 3066*4882a593Smuzhiyun __le32 rx_ts_reg_off_src_id_0; 3067*4882a593Smuzhiyun __le32 rx_ts_reg_off_src_id_1; 3068*4882a593Smuzhiyun __le32 rx_ts_reg_off_src_id_2; 3069*4882a593Smuzhiyun __le32 rx_ts_reg_off_domain_id; 3070*4882a593Smuzhiyun __le32 rx_ts_reg_off_fifo; 3071*4882a593Smuzhiyun __le32 rx_ts_reg_off_fifo_adv; 3072*4882a593Smuzhiyun __le32 rx_ts_reg_off_granularity; 3073*4882a593Smuzhiyun __le32 tx_ts_reg_off_lower; 3074*4882a593Smuzhiyun __le32 tx_ts_reg_off_upper; 3075*4882a593Smuzhiyun __le32 tx_ts_reg_off_seq_id; 3076*4882a593Smuzhiyun __le32 tx_ts_reg_off_fifo; 3077*4882a593Smuzhiyun __le32 tx_ts_reg_off_granularity; 3078*4882a593Smuzhiyun u8 unused_1[7]; 3079*4882a593Smuzhiyun u8 valid; 3080*4882a593Smuzhiyun }; 3081*4882a593Smuzhiyun 3082*4882a593Smuzhiyun /* tx_port_stats (size:3264b/408B) */ 3083*4882a593Smuzhiyun struct tx_port_stats { 3084*4882a593Smuzhiyun __le64 tx_64b_frames; 3085*4882a593Smuzhiyun __le64 tx_65b_127b_frames; 3086*4882a593Smuzhiyun __le64 tx_128b_255b_frames; 3087*4882a593Smuzhiyun __le64 tx_256b_511b_frames; 3088*4882a593Smuzhiyun __le64 tx_512b_1023b_frames; 3089*4882a593Smuzhiyun __le64 tx_1024b_1518b_frames; 3090*4882a593Smuzhiyun __le64 tx_good_vlan_frames; 3091*4882a593Smuzhiyun __le64 tx_1519b_2047b_frames; 3092*4882a593Smuzhiyun __le64 tx_2048b_4095b_frames; 3093*4882a593Smuzhiyun __le64 tx_4096b_9216b_frames; 3094*4882a593Smuzhiyun __le64 tx_9217b_16383b_frames; 3095*4882a593Smuzhiyun __le64 tx_good_frames; 3096*4882a593Smuzhiyun __le64 tx_total_frames; 3097*4882a593Smuzhiyun __le64 tx_ucast_frames; 3098*4882a593Smuzhiyun __le64 tx_mcast_frames; 3099*4882a593Smuzhiyun __le64 tx_bcast_frames; 3100*4882a593Smuzhiyun __le64 tx_pause_frames; 3101*4882a593Smuzhiyun __le64 tx_pfc_frames; 3102*4882a593Smuzhiyun __le64 tx_jabber_frames; 3103*4882a593Smuzhiyun __le64 tx_fcs_err_frames; 3104*4882a593Smuzhiyun __le64 tx_control_frames; 3105*4882a593Smuzhiyun __le64 tx_oversz_frames; 3106*4882a593Smuzhiyun __le64 tx_single_dfrl_frames; 3107*4882a593Smuzhiyun __le64 tx_multi_dfrl_frames; 3108*4882a593Smuzhiyun __le64 tx_single_coll_frames; 3109*4882a593Smuzhiyun __le64 tx_multi_coll_frames; 3110*4882a593Smuzhiyun __le64 tx_late_coll_frames; 3111*4882a593Smuzhiyun __le64 tx_excessive_coll_frames; 3112*4882a593Smuzhiyun __le64 tx_frag_frames; 3113*4882a593Smuzhiyun __le64 tx_err; 3114*4882a593Smuzhiyun __le64 tx_tagged_frames; 3115*4882a593Smuzhiyun __le64 tx_dbl_tagged_frames; 3116*4882a593Smuzhiyun __le64 tx_runt_frames; 3117*4882a593Smuzhiyun __le64 tx_fifo_underruns; 3118*4882a593Smuzhiyun __le64 tx_pfc_ena_frames_pri0; 3119*4882a593Smuzhiyun __le64 tx_pfc_ena_frames_pri1; 3120*4882a593Smuzhiyun __le64 tx_pfc_ena_frames_pri2; 3121*4882a593Smuzhiyun __le64 tx_pfc_ena_frames_pri3; 3122*4882a593Smuzhiyun __le64 tx_pfc_ena_frames_pri4; 3123*4882a593Smuzhiyun __le64 tx_pfc_ena_frames_pri5; 3124*4882a593Smuzhiyun __le64 tx_pfc_ena_frames_pri6; 3125*4882a593Smuzhiyun __le64 tx_pfc_ena_frames_pri7; 3126*4882a593Smuzhiyun __le64 tx_eee_lpi_events; 3127*4882a593Smuzhiyun __le64 tx_eee_lpi_duration; 3128*4882a593Smuzhiyun __le64 tx_llfc_logical_msgs; 3129*4882a593Smuzhiyun __le64 tx_hcfc_msgs; 3130*4882a593Smuzhiyun __le64 tx_total_collisions; 3131*4882a593Smuzhiyun __le64 tx_bytes; 3132*4882a593Smuzhiyun __le64 tx_xthol_frames; 3133*4882a593Smuzhiyun __le64 tx_stat_discard; 3134*4882a593Smuzhiyun __le64 tx_stat_error; 3135*4882a593Smuzhiyun }; 3136*4882a593Smuzhiyun 3137*4882a593Smuzhiyun /* rx_port_stats (size:4224b/528B) */ 3138*4882a593Smuzhiyun struct rx_port_stats { 3139*4882a593Smuzhiyun __le64 rx_64b_frames; 3140*4882a593Smuzhiyun __le64 rx_65b_127b_frames; 3141*4882a593Smuzhiyun __le64 rx_128b_255b_frames; 3142*4882a593Smuzhiyun __le64 rx_256b_511b_frames; 3143*4882a593Smuzhiyun __le64 rx_512b_1023b_frames; 3144*4882a593Smuzhiyun __le64 rx_1024b_1518b_frames; 3145*4882a593Smuzhiyun __le64 rx_good_vlan_frames; 3146*4882a593Smuzhiyun __le64 rx_1519b_2047b_frames; 3147*4882a593Smuzhiyun __le64 rx_2048b_4095b_frames; 3148*4882a593Smuzhiyun __le64 rx_4096b_9216b_frames; 3149*4882a593Smuzhiyun __le64 rx_9217b_16383b_frames; 3150*4882a593Smuzhiyun __le64 rx_total_frames; 3151*4882a593Smuzhiyun __le64 rx_ucast_frames; 3152*4882a593Smuzhiyun __le64 rx_mcast_frames; 3153*4882a593Smuzhiyun __le64 rx_bcast_frames; 3154*4882a593Smuzhiyun __le64 rx_fcs_err_frames; 3155*4882a593Smuzhiyun __le64 rx_ctrl_frames; 3156*4882a593Smuzhiyun __le64 rx_pause_frames; 3157*4882a593Smuzhiyun __le64 rx_pfc_frames; 3158*4882a593Smuzhiyun __le64 rx_unsupported_opcode_frames; 3159*4882a593Smuzhiyun __le64 rx_unsupported_da_pausepfc_frames; 3160*4882a593Smuzhiyun __le64 rx_wrong_sa_frames; 3161*4882a593Smuzhiyun __le64 rx_align_err_frames; 3162*4882a593Smuzhiyun __le64 rx_oor_len_frames; 3163*4882a593Smuzhiyun __le64 rx_code_err_frames; 3164*4882a593Smuzhiyun __le64 rx_false_carrier_frames; 3165*4882a593Smuzhiyun __le64 rx_ovrsz_frames; 3166*4882a593Smuzhiyun __le64 rx_jbr_frames; 3167*4882a593Smuzhiyun __le64 rx_mtu_err_frames; 3168*4882a593Smuzhiyun __le64 rx_match_crc_frames; 3169*4882a593Smuzhiyun __le64 rx_promiscuous_frames; 3170*4882a593Smuzhiyun __le64 rx_tagged_frames; 3171*4882a593Smuzhiyun __le64 rx_double_tagged_frames; 3172*4882a593Smuzhiyun __le64 rx_trunc_frames; 3173*4882a593Smuzhiyun __le64 rx_good_frames; 3174*4882a593Smuzhiyun __le64 rx_pfc_xon2xoff_frames_pri0; 3175*4882a593Smuzhiyun __le64 rx_pfc_xon2xoff_frames_pri1; 3176*4882a593Smuzhiyun __le64 rx_pfc_xon2xoff_frames_pri2; 3177*4882a593Smuzhiyun __le64 rx_pfc_xon2xoff_frames_pri3; 3178*4882a593Smuzhiyun __le64 rx_pfc_xon2xoff_frames_pri4; 3179*4882a593Smuzhiyun __le64 rx_pfc_xon2xoff_frames_pri5; 3180*4882a593Smuzhiyun __le64 rx_pfc_xon2xoff_frames_pri6; 3181*4882a593Smuzhiyun __le64 rx_pfc_xon2xoff_frames_pri7; 3182*4882a593Smuzhiyun __le64 rx_pfc_ena_frames_pri0; 3183*4882a593Smuzhiyun __le64 rx_pfc_ena_frames_pri1; 3184*4882a593Smuzhiyun __le64 rx_pfc_ena_frames_pri2; 3185*4882a593Smuzhiyun __le64 rx_pfc_ena_frames_pri3; 3186*4882a593Smuzhiyun __le64 rx_pfc_ena_frames_pri4; 3187*4882a593Smuzhiyun __le64 rx_pfc_ena_frames_pri5; 3188*4882a593Smuzhiyun __le64 rx_pfc_ena_frames_pri6; 3189*4882a593Smuzhiyun __le64 rx_pfc_ena_frames_pri7; 3190*4882a593Smuzhiyun __le64 rx_sch_crc_err_frames; 3191*4882a593Smuzhiyun __le64 rx_undrsz_frames; 3192*4882a593Smuzhiyun __le64 rx_frag_frames; 3193*4882a593Smuzhiyun __le64 rx_eee_lpi_events; 3194*4882a593Smuzhiyun __le64 rx_eee_lpi_duration; 3195*4882a593Smuzhiyun __le64 rx_llfc_physical_msgs; 3196*4882a593Smuzhiyun __le64 rx_llfc_logical_msgs; 3197*4882a593Smuzhiyun __le64 rx_llfc_msgs_with_crc_err; 3198*4882a593Smuzhiyun __le64 rx_hcfc_msgs; 3199*4882a593Smuzhiyun __le64 rx_hcfc_msgs_with_crc_err; 3200*4882a593Smuzhiyun __le64 rx_bytes; 3201*4882a593Smuzhiyun __le64 rx_runt_bytes; 3202*4882a593Smuzhiyun __le64 rx_runt_frames; 3203*4882a593Smuzhiyun __le64 rx_stat_discard; 3204*4882a593Smuzhiyun __le64 rx_stat_err; 3205*4882a593Smuzhiyun }; 3206*4882a593Smuzhiyun 3207*4882a593Smuzhiyun /* hwrm_port_qstats_input (size:320b/40B) */ 3208*4882a593Smuzhiyun struct hwrm_port_qstats_input { 3209*4882a593Smuzhiyun __le16 req_type; 3210*4882a593Smuzhiyun __le16 cmpl_ring; 3211*4882a593Smuzhiyun __le16 seq_id; 3212*4882a593Smuzhiyun __le16 target_id; 3213*4882a593Smuzhiyun __le64 resp_addr; 3214*4882a593Smuzhiyun __le16 port_id; 3215*4882a593Smuzhiyun u8 flags; 3216*4882a593Smuzhiyun #define PORT_QSTATS_REQ_FLAGS_UNUSED 0x0UL 3217*4882a593Smuzhiyun #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 3218*4882a593Smuzhiyun #define PORT_QSTATS_REQ_FLAGS_LAST PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 3219*4882a593Smuzhiyun u8 unused_0[5]; 3220*4882a593Smuzhiyun __le64 tx_stat_host_addr; 3221*4882a593Smuzhiyun __le64 rx_stat_host_addr; 3222*4882a593Smuzhiyun }; 3223*4882a593Smuzhiyun 3224*4882a593Smuzhiyun /* hwrm_port_qstats_output (size:128b/16B) */ 3225*4882a593Smuzhiyun struct hwrm_port_qstats_output { 3226*4882a593Smuzhiyun __le16 error_code; 3227*4882a593Smuzhiyun __le16 req_type; 3228*4882a593Smuzhiyun __le16 seq_id; 3229*4882a593Smuzhiyun __le16 resp_len; 3230*4882a593Smuzhiyun __le16 tx_stat_size; 3231*4882a593Smuzhiyun __le16 rx_stat_size; 3232*4882a593Smuzhiyun u8 unused_0[3]; 3233*4882a593Smuzhiyun u8 valid; 3234*4882a593Smuzhiyun }; 3235*4882a593Smuzhiyun 3236*4882a593Smuzhiyun /* tx_port_stats_ext (size:2048b/256B) */ 3237*4882a593Smuzhiyun struct tx_port_stats_ext { 3238*4882a593Smuzhiyun __le64 tx_bytes_cos0; 3239*4882a593Smuzhiyun __le64 tx_bytes_cos1; 3240*4882a593Smuzhiyun __le64 tx_bytes_cos2; 3241*4882a593Smuzhiyun __le64 tx_bytes_cos3; 3242*4882a593Smuzhiyun __le64 tx_bytes_cos4; 3243*4882a593Smuzhiyun __le64 tx_bytes_cos5; 3244*4882a593Smuzhiyun __le64 tx_bytes_cos6; 3245*4882a593Smuzhiyun __le64 tx_bytes_cos7; 3246*4882a593Smuzhiyun __le64 tx_packets_cos0; 3247*4882a593Smuzhiyun __le64 tx_packets_cos1; 3248*4882a593Smuzhiyun __le64 tx_packets_cos2; 3249*4882a593Smuzhiyun __le64 tx_packets_cos3; 3250*4882a593Smuzhiyun __le64 tx_packets_cos4; 3251*4882a593Smuzhiyun __le64 tx_packets_cos5; 3252*4882a593Smuzhiyun __le64 tx_packets_cos6; 3253*4882a593Smuzhiyun __le64 tx_packets_cos7; 3254*4882a593Smuzhiyun __le64 pfc_pri0_tx_duration_us; 3255*4882a593Smuzhiyun __le64 pfc_pri0_tx_transitions; 3256*4882a593Smuzhiyun __le64 pfc_pri1_tx_duration_us; 3257*4882a593Smuzhiyun __le64 pfc_pri1_tx_transitions; 3258*4882a593Smuzhiyun __le64 pfc_pri2_tx_duration_us; 3259*4882a593Smuzhiyun __le64 pfc_pri2_tx_transitions; 3260*4882a593Smuzhiyun __le64 pfc_pri3_tx_duration_us; 3261*4882a593Smuzhiyun __le64 pfc_pri3_tx_transitions; 3262*4882a593Smuzhiyun __le64 pfc_pri4_tx_duration_us; 3263*4882a593Smuzhiyun __le64 pfc_pri4_tx_transitions; 3264*4882a593Smuzhiyun __le64 pfc_pri5_tx_duration_us; 3265*4882a593Smuzhiyun __le64 pfc_pri5_tx_transitions; 3266*4882a593Smuzhiyun __le64 pfc_pri6_tx_duration_us; 3267*4882a593Smuzhiyun __le64 pfc_pri6_tx_transitions; 3268*4882a593Smuzhiyun __le64 pfc_pri7_tx_duration_us; 3269*4882a593Smuzhiyun __le64 pfc_pri7_tx_transitions; 3270*4882a593Smuzhiyun }; 3271*4882a593Smuzhiyun 3272*4882a593Smuzhiyun /* rx_port_stats_ext (size:3648b/456B) */ 3273*4882a593Smuzhiyun struct rx_port_stats_ext { 3274*4882a593Smuzhiyun __le64 link_down_events; 3275*4882a593Smuzhiyun __le64 continuous_pause_events; 3276*4882a593Smuzhiyun __le64 resume_pause_events; 3277*4882a593Smuzhiyun __le64 continuous_roce_pause_events; 3278*4882a593Smuzhiyun __le64 resume_roce_pause_events; 3279*4882a593Smuzhiyun __le64 rx_bytes_cos0; 3280*4882a593Smuzhiyun __le64 rx_bytes_cos1; 3281*4882a593Smuzhiyun __le64 rx_bytes_cos2; 3282*4882a593Smuzhiyun __le64 rx_bytes_cos3; 3283*4882a593Smuzhiyun __le64 rx_bytes_cos4; 3284*4882a593Smuzhiyun __le64 rx_bytes_cos5; 3285*4882a593Smuzhiyun __le64 rx_bytes_cos6; 3286*4882a593Smuzhiyun __le64 rx_bytes_cos7; 3287*4882a593Smuzhiyun __le64 rx_packets_cos0; 3288*4882a593Smuzhiyun __le64 rx_packets_cos1; 3289*4882a593Smuzhiyun __le64 rx_packets_cos2; 3290*4882a593Smuzhiyun __le64 rx_packets_cos3; 3291*4882a593Smuzhiyun __le64 rx_packets_cos4; 3292*4882a593Smuzhiyun __le64 rx_packets_cos5; 3293*4882a593Smuzhiyun __le64 rx_packets_cos6; 3294*4882a593Smuzhiyun __le64 rx_packets_cos7; 3295*4882a593Smuzhiyun __le64 pfc_pri0_rx_duration_us; 3296*4882a593Smuzhiyun __le64 pfc_pri0_rx_transitions; 3297*4882a593Smuzhiyun __le64 pfc_pri1_rx_duration_us; 3298*4882a593Smuzhiyun __le64 pfc_pri1_rx_transitions; 3299*4882a593Smuzhiyun __le64 pfc_pri2_rx_duration_us; 3300*4882a593Smuzhiyun __le64 pfc_pri2_rx_transitions; 3301*4882a593Smuzhiyun __le64 pfc_pri3_rx_duration_us; 3302*4882a593Smuzhiyun __le64 pfc_pri3_rx_transitions; 3303*4882a593Smuzhiyun __le64 pfc_pri4_rx_duration_us; 3304*4882a593Smuzhiyun __le64 pfc_pri4_rx_transitions; 3305*4882a593Smuzhiyun __le64 pfc_pri5_rx_duration_us; 3306*4882a593Smuzhiyun __le64 pfc_pri5_rx_transitions; 3307*4882a593Smuzhiyun __le64 pfc_pri6_rx_duration_us; 3308*4882a593Smuzhiyun __le64 pfc_pri6_rx_transitions; 3309*4882a593Smuzhiyun __le64 pfc_pri7_rx_duration_us; 3310*4882a593Smuzhiyun __le64 pfc_pri7_rx_transitions; 3311*4882a593Smuzhiyun __le64 rx_bits; 3312*4882a593Smuzhiyun __le64 rx_buffer_passed_threshold; 3313*4882a593Smuzhiyun __le64 rx_pcs_symbol_err; 3314*4882a593Smuzhiyun __le64 rx_corrected_bits; 3315*4882a593Smuzhiyun __le64 rx_discard_bytes_cos0; 3316*4882a593Smuzhiyun __le64 rx_discard_bytes_cos1; 3317*4882a593Smuzhiyun __le64 rx_discard_bytes_cos2; 3318*4882a593Smuzhiyun __le64 rx_discard_bytes_cos3; 3319*4882a593Smuzhiyun __le64 rx_discard_bytes_cos4; 3320*4882a593Smuzhiyun __le64 rx_discard_bytes_cos5; 3321*4882a593Smuzhiyun __le64 rx_discard_bytes_cos6; 3322*4882a593Smuzhiyun __le64 rx_discard_bytes_cos7; 3323*4882a593Smuzhiyun __le64 rx_discard_packets_cos0; 3324*4882a593Smuzhiyun __le64 rx_discard_packets_cos1; 3325*4882a593Smuzhiyun __le64 rx_discard_packets_cos2; 3326*4882a593Smuzhiyun __le64 rx_discard_packets_cos3; 3327*4882a593Smuzhiyun __le64 rx_discard_packets_cos4; 3328*4882a593Smuzhiyun __le64 rx_discard_packets_cos5; 3329*4882a593Smuzhiyun __le64 rx_discard_packets_cos6; 3330*4882a593Smuzhiyun __le64 rx_discard_packets_cos7; 3331*4882a593Smuzhiyun }; 3332*4882a593Smuzhiyun 3333*4882a593Smuzhiyun /* hwrm_port_qstats_ext_input (size:320b/40B) */ 3334*4882a593Smuzhiyun struct hwrm_port_qstats_ext_input { 3335*4882a593Smuzhiyun __le16 req_type; 3336*4882a593Smuzhiyun __le16 cmpl_ring; 3337*4882a593Smuzhiyun __le16 seq_id; 3338*4882a593Smuzhiyun __le16 target_id; 3339*4882a593Smuzhiyun __le64 resp_addr; 3340*4882a593Smuzhiyun __le16 port_id; 3341*4882a593Smuzhiyun __le16 tx_stat_size; 3342*4882a593Smuzhiyun __le16 rx_stat_size; 3343*4882a593Smuzhiyun u8 flags; 3344*4882a593Smuzhiyun #define PORT_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 3345*4882a593Smuzhiyun #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL 3346*4882a593Smuzhiyun #define PORT_QSTATS_EXT_REQ_FLAGS_LAST PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 3347*4882a593Smuzhiyun u8 unused_0; 3348*4882a593Smuzhiyun __le64 tx_stat_host_addr; 3349*4882a593Smuzhiyun __le64 rx_stat_host_addr; 3350*4882a593Smuzhiyun }; 3351*4882a593Smuzhiyun 3352*4882a593Smuzhiyun /* hwrm_port_qstats_ext_output (size:128b/16B) */ 3353*4882a593Smuzhiyun struct hwrm_port_qstats_ext_output { 3354*4882a593Smuzhiyun __le16 error_code; 3355*4882a593Smuzhiyun __le16 req_type; 3356*4882a593Smuzhiyun __le16 seq_id; 3357*4882a593Smuzhiyun __le16 resp_len; 3358*4882a593Smuzhiyun __le16 tx_stat_size; 3359*4882a593Smuzhiyun __le16 rx_stat_size; 3360*4882a593Smuzhiyun __le16 total_active_cos_queues; 3361*4882a593Smuzhiyun u8 flags; 3362*4882a593Smuzhiyun #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 3363*4882a593Smuzhiyun u8 valid; 3364*4882a593Smuzhiyun }; 3365*4882a593Smuzhiyun 3366*4882a593Smuzhiyun /* hwrm_port_lpbk_qstats_input (size:128b/16B) */ 3367*4882a593Smuzhiyun struct hwrm_port_lpbk_qstats_input { 3368*4882a593Smuzhiyun __le16 req_type; 3369*4882a593Smuzhiyun __le16 cmpl_ring; 3370*4882a593Smuzhiyun __le16 seq_id; 3371*4882a593Smuzhiyun __le16 target_id; 3372*4882a593Smuzhiyun __le64 resp_addr; 3373*4882a593Smuzhiyun }; 3374*4882a593Smuzhiyun 3375*4882a593Smuzhiyun /* hwrm_port_lpbk_qstats_output (size:768b/96B) */ 3376*4882a593Smuzhiyun struct hwrm_port_lpbk_qstats_output { 3377*4882a593Smuzhiyun __le16 error_code; 3378*4882a593Smuzhiyun __le16 req_type; 3379*4882a593Smuzhiyun __le16 seq_id; 3380*4882a593Smuzhiyun __le16 resp_len; 3381*4882a593Smuzhiyun __le64 lpbk_ucast_frames; 3382*4882a593Smuzhiyun __le64 lpbk_mcast_frames; 3383*4882a593Smuzhiyun __le64 lpbk_bcast_frames; 3384*4882a593Smuzhiyun __le64 lpbk_ucast_bytes; 3385*4882a593Smuzhiyun __le64 lpbk_mcast_bytes; 3386*4882a593Smuzhiyun __le64 lpbk_bcast_bytes; 3387*4882a593Smuzhiyun __le64 tx_stat_discard; 3388*4882a593Smuzhiyun __le64 tx_stat_error; 3389*4882a593Smuzhiyun __le64 rx_stat_discard; 3390*4882a593Smuzhiyun __le64 rx_stat_error; 3391*4882a593Smuzhiyun u8 unused_0[7]; 3392*4882a593Smuzhiyun u8 valid; 3393*4882a593Smuzhiyun }; 3394*4882a593Smuzhiyun 3395*4882a593Smuzhiyun /* hwrm_port_ecn_qstats_input (size:256b/32B) */ 3396*4882a593Smuzhiyun struct hwrm_port_ecn_qstats_input { 3397*4882a593Smuzhiyun __le16 req_type; 3398*4882a593Smuzhiyun __le16 cmpl_ring; 3399*4882a593Smuzhiyun __le16 seq_id; 3400*4882a593Smuzhiyun __le16 target_id; 3401*4882a593Smuzhiyun __le64 resp_addr; 3402*4882a593Smuzhiyun __le16 port_id; 3403*4882a593Smuzhiyun __le16 ecn_stat_buf_size; 3404*4882a593Smuzhiyun u8 flags; 3405*4882a593Smuzhiyun #define PORT_ECN_QSTATS_REQ_FLAGS_UNUSED 0x0UL 3406*4882a593Smuzhiyun #define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 3407*4882a593Smuzhiyun #define PORT_ECN_QSTATS_REQ_FLAGS_LAST PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 3408*4882a593Smuzhiyun u8 unused_0[3]; 3409*4882a593Smuzhiyun __le64 ecn_stat_host_addr; 3410*4882a593Smuzhiyun }; 3411*4882a593Smuzhiyun 3412*4882a593Smuzhiyun /* hwrm_port_ecn_qstats_output (size:128b/16B) */ 3413*4882a593Smuzhiyun struct hwrm_port_ecn_qstats_output { 3414*4882a593Smuzhiyun __le16 error_code; 3415*4882a593Smuzhiyun __le16 req_type; 3416*4882a593Smuzhiyun __le16 seq_id; 3417*4882a593Smuzhiyun __le16 resp_len; 3418*4882a593Smuzhiyun __le16 ecn_stat_buf_size; 3419*4882a593Smuzhiyun u8 mark_en; 3420*4882a593Smuzhiyun u8 unused_0[4]; 3421*4882a593Smuzhiyun u8 valid; 3422*4882a593Smuzhiyun }; 3423*4882a593Smuzhiyun 3424*4882a593Smuzhiyun /* port_stats_ecn (size:512b/64B) */ 3425*4882a593Smuzhiyun struct port_stats_ecn { 3426*4882a593Smuzhiyun __le64 mark_cnt_cos0; 3427*4882a593Smuzhiyun __le64 mark_cnt_cos1; 3428*4882a593Smuzhiyun __le64 mark_cnt_cos2; 3429*4882a593Smuzhiyun __le64 mark_cnt_cos3; 3430*4882a593Smuzhiyun __le64 mark_cnt_cos4; 3431*4882a593Smuzhiyun __le64 mark_cnt_cos5; 3432*4882a593Smuzhiyun __le64 mark_cnt_cos6; 3433*4882a593Smuzhiyun __le64 mark_cnt_cos7; 3434*4882a593Smuzhiyun }; 3435*4882a593Smuzhiyun 3436*4882a593Smuzhiyun /* hwrm_port_clr_stats_input (size:192b/24B) */ 3437*4882a593Smuzhiyun struct hwrm_port_clr_stats_input { 3438*4882a593Smuzhiyun __le16 req_type; 3439*4882a593Smuzhiyun __le16 cmpl_ring; 3440*4882a593Smuzhiyun __le16 seq_id; 3441*4882a593Smuzhiyun __le16 target_id; 3442*4882a593Smuzhiyun __le64 resp_addr; 3443*4882a593Smuzhiyun __le16 port_id; 3444*4882a593Smuzhiyun u8 flags; 3445*4882a593Smuzhiyun #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL 3446*4882a593Smuzhiyun u8 unused_0[5]; 3447*4882a593Smuzhiyun }; 3448*4882a593Smuzhiyun 3449*4882a593Smuzhiyun /* hwrm_port_clr_stats_output (size:128b/16B) */ 3450*4882a593Smuzhiyun struct hwrm_port_clr_stats_output { 3451*4882a593Smuzhiyun __le16 error_code; 3452*4882a593Smuzhiyun __le16 req_type; 3453*4882a593Smuzhiyun __le16 seq_id; 3454*4882a593Smuzhiyun __le16 resp_len; 3455*4882a593Smuzhiyun u8 unused_0[7]; 3456*4882a593Smuzhiyun u8 valid; 3457*4882a593Smuzhiyun }; 3458*4882a593Smuzhiyun 3459*4882a593Smuzhiyun /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ 3460*4882a593Smuzhiyun struct hwrm_port_lpbk_clr_stats_input { 3461*4882a593Smuzhiyun __le16 req_type; 3462*4882a593Smuzhiyun __le16 cmpl_ring; 3463*4882a593Smuzhiyun __le16 seq_id; 3464*4882a593Smuzhiyun __le16 target_id; 3465*4882a593Smuzhiyun __le64 resp_addr; 3466*4882a593Smuzhiyun }; 3467*4882a593Smuzhiyun 3468*4882a593Smuzhiyun /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 3469*4882a593Smuzhiyun struct hwrm_port_lpbk_clr_stats_output { 3470*4882a593Smuzhiyun __le16 error_code; 3471*4882a593Smuzhiyun __le16 req_type; 3472*4882a593Smuzhiyun __le16 seq_id; 3473*4882a593Smuzhiyun __le16 resp_len; 3474*4882a593Smuzhiyun u8 unused_0[7]; 3475*4882a593Smuzhiyun u8 valid; 3476*4882a593Smuzhiyun }; 3477*4882a593Smuzhiyun 3478*4882a593Smuzhiyun /* hwrm_port_ts_query_input (size:192b/24B) */ 3479*4882a593Smuzhiyun struct hwrm_port_ts_query_input { 3480*4882a593Smuzhiyun __le16 req_type; 3481*4882a593Smuzhiyun __le16 cmpl_ring; 3482*4882a593Smuzhiyun __le16 seq_id; 3483*4882a593Smuzhiyun __le16 target_id; 3484*4882a593Smuzhiyun __le64 resp_addr; 3485*4882a593Smuzhiyun __le32 flags; 3486*4882a593Smuzhiyun #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL 3487*4882a593Smuzhiyun #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL 3488*4882a593Smuzhiyun #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL 3489*4882a593Smuzhiyun #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX 3490*4882a593Smuzhiyun #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL 3491*4882a593Smuzhiyun __le16 port_id; 3492*4882a593Smuzhiyun u8 unused_0[2]; 3493*4882a593Smuzhiyun }; 3494*4882a593Smuzhiyun 3495*4882a593Smuzhiyun /* hwrm_port_ts_query_output (size:192b/24B) */ 3496*4882a593Smuzhiyun struct hwrm_port_ts_query_output { 3497*4882a593Smuzhiyun __le16 error_code; 3498*4882a593Smuzhiyun __le16 req_type; 3499*4882a593Smuzhiyun __le16 seq_id; 3500*4882a593Smuzhiyun __le16 resp_len; 3501*4882a593Smuzhiyun __le64 ptp_msg_ts; 3502*4882a593Smuzhiyun __le16 ptp_msg_seqid; 3503*4882a593Smuzhiyun u8 unused_0[5]; 3504*4882a593Smuzhiyun u8 valid; 3505*4882a593Smuzhiyun }; 3506*4882a593Smuzhiyun 3507*4882a593Smuzhiyun /* hwrm_port_phy_qcaps_input (size:192b/24B) */ 3508*4882a593Smuzhiyun struct hwrm_port_phy_qcaps_input { 3509*4882a593Smuzhiyun __le16 req_type; 3510*4882a593Smuzhiyun __le16 cmpl_ring; 3511*4882a593Smuzhiyun __le16 seq_id; 3512*4882a593Smuzhiyun __le16 target_id; 3513*4882a593Smuzhiyun __le64 resp_addr; 3514*4882a593Smuzhiyun __le16 port_id; 3515*4882a593Smuzhiyun u8 unused_0[6]; 3516*4882a593Smuzhiyun }; 3517*4882a593Smuzhiyun 3518*4882a593Smuzhiyun /* hwrm_port_phy_qcaps_output (size:256b/32B) */ 3519*4882a593Smuzhiyun struct hwrm_port_phy_qcaps_output { 3520*4882a593Smuzhiyun __le16 error_code; 3521*4882a593Smuzhiyun __le16 req_type; 3522*4882a593Smuzhiyun __le16 seq_id; 3523*4882a593Smuzhiyun __le16 resp_len; 3524*4882a593Smuzhiyun u8 flags; 3525*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 3526*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL 3527*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL 3528*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL 3529*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 0x10UL 3530*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x20UL 3531*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xc0UL 3532*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 6 3533*4882a593Smuzhiyun u8 port_cnt; 3534*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 3535*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 3536*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 3537*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 3538*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 3539*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_4 3540*4882a593Smuzhiyun __le16 supported_speeds_force_mode; 3541*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 3542*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 3543*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 3544*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 3545*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 3546*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 3547*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 3548*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 3549*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 3550*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 3551*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 3552*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 3553*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 3554*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 3555*4882a593Smuzhiyun __le16 supported_speeds_auto_mode; 3556*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 3557*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 3558*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 3559*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 3560*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 3561*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 3562*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 3563*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 3564*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 3565*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 3566*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 3567*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 3568*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 3569*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 3570*4882a593Smuzhiyun __le16 supported_speeds_eee_mode; 3571*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 3572*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 3573*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 3574*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 3575*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 3576*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 3577*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 3578*4882a593Smuzhiyun __le32 tx_lpi_timer_low; 3579*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 3580*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 3581*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 3582*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 3583*4882a593Smuzhiyun __le32 valid_tx_lpi_timer_high; 3584*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 3585*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 3586*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_RSVD_MASK 0xff000000UL 3587*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_RSVD_SFT 24 3588*4882a593Smuzhiyun __le16 supported_pam4_speeds_auto_mode; 3589*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL 3590*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL 3591*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL 3592*4882a593Smuzhiyun __le16 supported_pam4_speeds_force_mode; 3593*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL 3594*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL 3595*4882a593Smuzhiyun #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL 3596*4882a593Smuzhiyun u8 unused_0[3]; 3597*4882a593Smuzhiyun u8 valid; 3598*4882a593Smuzhiyun }; 3599*4882a593Smuzhiyun 3600*4882a593Smuzhiyun /* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 3601*4882a593Smuzhiyun struct hwrm_port_phy_i2c_read_input { 3602*4882a593Smuzhiyun __le16 req_type; 3603*4882a593Smuzhiyun __le16 cmpl_ring; 3604*4882a593Smuzhiyun __le16 seq_id; 3605*4882a593Smuzhiyun __le16 target_id; 3606*4882a593Smuzhiyun __le64 resp_addr; 3607*4882a593Smuzhiyun __le32 flags; 3608*4882a593Smuzhiyun __le32 enables; 3609*4882a593Smuzhiyun #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 3610*4882a593Smuzhiyun __le16 port_id; 3611*4882a593Smuzhiyun u8 i2c_slave_addr; 3612*4882a593Smuzhiyun u8 unused_0; 3613*4882a593Smuzhiyun __le16 page_number; 3614*4882a593Smuzhiyun __le16 page_offset; 3615*4882a593Smuzhiyun u8 data_length; 3616*4882a593Smuzhiyun u8 unused_1[7]; 3617*4882a593Smuzhiyun }; 3618*4882a593Smuzhiyun 3619*4882a593Smuzhiyun /* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 3620*4882a593Smuzhiyun struct hwrm_port_phy_i2c_read_output { 3621*4882a593Smuzhiyun __le16 error_code; 3622*4882a593Smuzhiyun __le16 req_type; 3623*4882a593Smuzhiyun __le16 seq_id; 3624*4882a593Smuzhiyun __le16 resp_len; 3625*4882a593Smuzhiyun __le32 data[16]; 3626*4882a593Smuzhiyun u8 unused_0[7]; 3627*4882a593Smuzhiyun u8 valid; 3628*4882a593Smuzhiyun }; 3629*4882a593Smuzhiyun 3630*4882a593Smuzhiyun /* hwrm_port_phy_mdio_write_input (size:320b/40B) */ 3631*4882a593Smuzhiyun struct hwrm_port_phy_mdio_write_input { 3632*4882a593Smuzhiyun __le16 req_type; 3633*4882a593Smuzhiyun __le16 cmpl_ring; 3634*4882a593Smuzhiyun __le16 seq_id; 3635*4882a593Smuzhiyun __le16 target_id; 3636*4882a593Smuzhiyun __le64 resp_addr; 3637*4882a593Smuzhiyun __le32 unused_0[2]; 3638*4882a593Smuzhiyun __le16 port_id; 3639*4882a593Smuzhiyun u8 phy_addr; 3640*4882a593Smuzhiyun u8 dev_addr; 3641*4882a593Smuzhiyun __le16 reg_addr; 3642*4882a593Smuzhiyun __le16 reg_data; 3643*4882a593Smuzhiyun u8 cl45_mdio; 3644*4882a593Smuzhiyun u8 unused_1[7]; 3645*4882a593Smuzhiyun }; 3646*4882a593Smuzhiyun 3647*4882a593Smuzhiyun /* hwrm_port_phy_mdio_write_output (size:128b/16B) */ 3648*4882a593Smuzhiyun struct hwrm_port_phy_mdio_write_output { 3649*4882a593Smuzhiyun __le16 error_code; 3650*4882a593Smuzhiyun __le16 req_type; 3651*4882a593Smuzhiyun __le16 seq_id; 3652*4882a593Smuzhiyun __le16 resp_len; 3653*4882a593Smuzhiyun u8 unused_0[7]; 3654*4882a593Smuzhiyun u8 valid; 3655*4882a593Smuzhiyun }; 3656*4882a593Smuzhiyun 3657*4882a593Smuzhiyun /* hwrm_port_phy_mdio_read_input (size:256b/32B) */ 3658*4882a593Smuzhiyun struct hwrm_port_phy_mdio_read_input { 3659*4882a593Smuzhiyun __le16 req_type; 3660*4882a593Smuzhiyun __le16 cmpl_ring; 3661*4882a593Smuzhiyun __le16 seq_id; 3662*4882a593Smuzhiyun __le16 target_id; 3663*4882a593Smuzhiyun __le64 resp_addr; 3664*4882a593Smuzhiyun __le32 unused_0[2]; 3665*4882a593Smuzhiyun __le16 port_id; 3666*4882a593Smuzhiyun u8 phy_addr; 3667*4882a593Smuzhiyun u8 dev_addr; 3668*4882a593Smuzhiyun __le16 reg_addr; 3669*4882a593Smuzhiyun u8 cl45_mdio; 3670*4882a593Smuzhiyun u8 unused_1; 3671*4882a593Smuzhiyun }; 3672*4882a593Smuzhiyun 3673*4882a593Smuzhiyun /* hwrm_port_phy_mdio_read_output (size:128b/16B) */ 3674*4882a593Smuzhiyun struct hwrm_port_phy_mdio_read_output { 3675*4882a593Smuzhiyun __le16 error_code; 3676*4882a593Smuzhiyun __le16 req_type; 3677*4882a593Smuzhiyun __le16 seq_id; 3678*4882a593Smuzhiyun __le16 resp_len; 3679*4882a593Smuzhiyun __le16 reg_data; 3680*4882a593Smuzhiyun u8 unused_0[5]; 3681*4882a593Smuzhiyun u8 valid; 3682*4882a593Smuzhiyun }; 3683*4882a593Smuzhiyun 3684*4882a593Smuzhiyun /* hwrm_port_led_cfg_input (size:512b/64B) */ 3685*4882a593Smuzhiyun struct hwrm_port_led_cfg_input { 3686*4882a593Smuzhiyun __le16 req_type; 3687*4882a593Smuzhiyun __le16 cmpl_ring; 3688*4882a593Smuzhiyun __le16 seq_id; 3689*4882a593Smuzhiyun __le16 target_id; 3690*4882a593Smuzhiyun __le64 resp_addr; 3691*4882a593Smuzhiyun __le32 enables; 3692*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 3693*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 3694*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 3695*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 3696*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 3697*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 3698*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 3699*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 3700*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 3701*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 3702*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 3703*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 3704*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 3705*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 3706*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 3707*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 3708*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 3709*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 3710*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 3711*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 3712*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 3713*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 3714*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 3715*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 3716*4882a593Smuzhiyun __le16 port_id; 3717*4882a593Smuzhiyun u8 num_leds; 3718*4882a593Smuzhiyun u8 rsvd; 3719*4882a593Smuzhiyun u8 led0_id; 3720*4882a593Smuzhiyun u8 led0_state; 3721*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 3722*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 3723*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 3724*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 3725*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 3726*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 3727*4882a593Smuzhiyun u8 led0_color; 3728*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 3729*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 3730*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 3731*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 3732*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 3733*4882a593Smuzhiyun u8 unused_0; 3734*4882a593Smuzhiyun __le16 led0_blink_on; 3735*4882a593Smuzhiyun __le16 led0_blink_off; 3736*4882a593Smuzhiyun u8 led0_group_id; 3737*4882a593Smuzhiyun u8 rsvd0; 3738*4882a593Smuzhiyun u8 led1_id; 3739*4882a593Smuzhiyun u8 led1_state; 3740*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 3741*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 3742*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 3743*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 3744*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 3745*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 3746*4882a593Smuzhiyun u8 led1_color; 3747*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 3748*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 3749*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 3750*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 3751*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 3752*4882a593Smuzhiyun u8 unused_1; 3753*4882a593Smuzhiyun __le16 led1_blink_on; 3754*4882a593Smuzhiyun __le16 led1_blink_off; 3755*4882a593Smuzhiyun u8 led1_group_id; 3756*4882a593Smuzhiyun u8 rsvd1; 3757*4882a593Smuzhiyun u8 led2_id; 3758*4882a593Smuzhiyun u8 led2_state; 3759*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 3760*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 3761*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 3762*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 3763*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 3764*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 3765*4882a593Smuzhiyun u8 led2_color; 3766*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 3767*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 3768*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 3769*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 3770*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 3771*4882a593Smuzhiyun u8 unused_2; 3772*4882a593Smuzhiyun __le16 led2_blink_on; 3773*4882a593Smuzhiyun __le16 led2_blink_off; 3774*4882a593Smuzhiyun u8 led2_group_id; 3775*4882a593Smuzhiyun u8 rsvd2; 3776*4882a593Smuzhiyun u8 led3_id; 3777*4882a593Smuzhiyun u8 led3_state; 3778*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 3779*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 3780*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 3781*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 3782*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 3783*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 3784*4882a593Smuzhiyun u8 led3_color; 3785*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 3786*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 3787*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 3788*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 3789*4882a593Smuzhiyun #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 3790*4882a593Smuzhiyun u8 unused_3; 3791*4882a593Smuzhiyun __le16 led3_blink_on; 3792*4882a593Smuzhiyun __le16 led3_blink_off; 3793*4882a593Smuzhiyun u8 led3_group_id; 3794*4882a593Smuzhiyun u8 rsvd3; 3795*4882a593Smuzhiyun }; 3796*4882a593Smuzhiyun 3797*4882a593Smuzhiyun /* hwrm_port_led_cfg_output (size:128b/16B) */ 3798*4882a593Smuzhiyun struct hwrm_port_led_cfg_output { 3799*4882a593Smuzhiyun __le16 error_code; 3800*4882a593Smuzhiyun __le16 req_type; 3801*4882a593Smuzhiyun __le16 seq_id; 3802*4882a593Smuzhiyun __le16 resp_len; 3803*4882a593Smuzhiyun u8 unused_0[7]; 3804*4882a593Smuzhiyun u8 valid; 3805*4882a593Smuzhiyun }; 3806*4882a593Smuzhiyun 3807*4882a593Smuzhiyun /* hwrm_port_led_qcfg_input (size:192b/24B) */ 3808*4882a593Smuzhiyun struct hwrm_port_led_qcfg_input { 3809*4882a593Smuzhiyun __le16 req_type; 3810*4882a593Smuzhiyun __le16 cmpl_ring; 3811*4882a593Smuzhiyun __le16 seq_id; 3812*4882a593Smuzhiyun __le16 target_id; 3813*4882a593Smuzhiyun __le64 resp_addr; 3814*4882a593Smuzhiyun __le16 port_id; 3815*4882a593Smuzhiyun u8 unused_0[6]; 3816*4882a593Smuzhiyun }; 3817*4882a593Smuzhiyun 3818*4882a593Smuzhiyun /* hwrm_port_led_qcfg_output (size:448b/56B) */ 3819*4882a593Smuzhiyun struct hwrm_port_led_qcfg_output { 3820*4882a593Smuzhiyun __le16 error_code; 3821*4882a593Smuzhiyun __le16 req_type; 3822*4882a593Smuzhiyun __le16 seq_id; 3823*4882a593Smuzhiyun __le16 resp_len; 3824*4882a593Smuzhiyun u8 num_leds; 3825*4882a593Smuzhiyun u8 led0_id; 3826*4882a593Smuzhiyun u8 led0_type; 3827*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 3828*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 3829*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 3830*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 3831*4882a593Smuzhiyun u8 led0_state; 3832*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 3833*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 3834*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 3835*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 3836*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 3837*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 3838*4882a593Smuzhiyun u8 led0_color; 3839*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 3840*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 3841*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 3842*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 3843*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 3844*4882a593Smuzhiyun u8 unused_0; 3845*4882a593Smuzhiyun __le16 led0_blink_on; 3846*4882a593Smuzhiyun __le16 led0_blink_off; 3847*4882a593Smuzhiyun u8 led0_group_id; 3848*4882a593Smuzhiyun u8 led1_id; 3849*4882a593Smuzhiyun u8 led1_type; 3850*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 3851*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 3852*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 3853*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 3854*4882a593Smuzhiyun u8 led1_state; 3855*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 3856*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 3857*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 3858*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 3859*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 3860*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 3861*4882a593Smuzhiyun u8 led1_color; 3862*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 3863*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 3864*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 3865*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 3866*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 3867*4882a593Smuzhiyun u8 unused_1; 3868*4882a593Smuzhiyun __le16 led1_blink_on; 3869*4882a593Smuzhiyun __le16 led1_blink_off; 3870*4882a593Smuzhiyun u8 led1_group_id; 3871*4882a593Smuzhiyun u8 led2_id; 3872*4882a593Smuzhiyun u8 led2_type; 3873*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 3874*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 3875*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 3876*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 3877*4882a593Smuzhiyun u8 led2_state; 3878*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 3879*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 3880*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 3881*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 3882*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 3883*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 3884*4882a593Smuzhiyun u8 led2_color; 3885*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 3886*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 3887*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 3888*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 3889*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 3890*4882a593Smuzhiyun u8 unused_2; 3891*4882a593Smuzhiyun __le16 led2_blink_on; 3892*4882a593Smuzhiyun __le16 led2_blink_off; 3893*4882a593Smuzhiyun u8 led2_group_id; 3894*4882a593Smuzhiyun u8 led3_id; 3895*4882a593Smuzhiyun u8 led3_type; 3896*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 3897*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 3898*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 3899*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 3900*4882a593Smuzhiyun u8 led3_state; 3901*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 3902*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 3903*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 3904*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 3905*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 3906*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 3907*4882a593Smuzhiyun u8 led3_color; 3908*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 3909*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 3910*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 3911*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 3912*4882a593Smuzhiyun #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 3913*4882a593Smuzhiyun u8 unused_3; 3914*4882a593Smuzhiyun __le16 led3_blink_on; 3915*4882a593Smuzhiyun __le16 led3_blink_off; 3916*4882a593Smuzhiyun u8 led3_group_id; 3917*4882a593Smuzhiyun u8 unused_4[6]; 3918*4882a593Smuzhiyun u8 valid; 3919*4882a593Smuzhiyun }; 3920*4882a593Smuzhiyun 3921*4882a593Smuzhiyun /* hwrm_port_led_qcaps_input (size:192b/24B) */ 3922*4882a593Smuzhiyun struct hwrm_port_led_qcaps_input { 3923*4882a593Smuzhiyun __le16 req_type; 3924*4882a593Smuzhiyun __le16 cmpl_ring; 3925*4882a593Smuzhiyun __le16 seq_id; 3926*4882a593Smuzhiyun __le16 target_id; 3927*4882a593Smuzhiyun __le64 resp_addr; 3928*4882a593Smuzhiyun __le16 port_id; 3929*4882a593Smuzhiyun u8 unused_0[6]; 3930*4882a593Smuzhiyun }; 3931*4882a593Smuzhiyun 3932*4882a593Smuzhiyun /* hwrm_port_led_qcaps_output (size:384b/48B) */ 3933*4882a593Smuzhiyun struct hwrm_port_led_qcaps_output { 3934*4882a593Smuzhiyun __le16 error_code; 3935*4882a593Smuzhiyun __le16 req_type; 3936*4882a593Smuzhiyun __le16 seq_id; 3937*4882a593Smuzhiyun __le16 resp_len; 3938*4882a593Smuzhiyun u8 num_leds; 3939*4882a593Smuzhiyun u8 unused[3]; 3940*4882a593Smuzhiyun u8 led0_id; 3941*4882a593Smuzhiyun u8 led0_type; 3942*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 3943*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 3944*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 3945*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 3946*4882a593Smuzhiyun u8 led0_group_id; 3947*4882a593Smuzhiyun u8 unused_0; 3948*4882a593Smuzhiyun __le16 led0_state_caps; 3949*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 3950*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 3951*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 3952*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3953*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3954*4882a593Smuzhiyun __le16 led0_color_caps; 3955*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 3956*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3957*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3958*4882a593Smuzhiyun u8 led1_id; 3959*4882a593Smuzhiyun u8 led1_type; 3960*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 3961*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 3962*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 3963*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 3964*4882a593Smuzhiyun u8 led1_group_id; 3965*4882a593Smuzhiyun u8 unused_1; 3966*4882a593Smuzhiyun __le16 led1_state_caps; 3967*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 3968*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 3969*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 3970*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3971*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3972*4882a593Smuzhiyun __le16 led1_color_caps; 3973*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 3974*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3975*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3976*4882a593Smuzhiyun u8 led2_id; 3977*4882a593Smuzhiyun u8 led2_type; 3978*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 3979*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 3980*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 3981*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 3982*4882a593Smuzhiyun u8 led2_group_id; 3983*4882a593Smuzhiyun u8 unused_2; 3984*4882a593Smuzhiyun __le16 led2_state_caps; 3985*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 3986*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 3987*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 3988*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3989*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3990*4882a593Smuzhiyun __le16 led2_color_caps; 3991*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 3992*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3993*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3994*4882a593Smuzhiyun u8 led3_id; 3995*4882a593Smuzhiyun u8 led3_type; 3996*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 3997*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 3998*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 3999*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 4000*4882a593Smuzhiyun u8 led3_group_id; 4001*4882a593Smuzhiyun u8 unused_3; 4002*4882a593Smuzhiyun __le16 led3_state_caps; 4003*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 4004*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 4005*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 4006*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4007*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4008*4882a593Smuzhiyun __le16 led3_color_caps; 4009*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 4010*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4011*4882a593Smuzhiyun #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4012*4882a593Smuzhiyun u8 unused_4[3]; 4013*4882a593Smuzhiyun u8 valid; 4014*4882a593Smuzhiyun }; 4015*4882a593Smuzhiyun 4016*4882a593Smuzhiyun /* hwrm_queue_qportcfg_input (size:192b/24B) */ 4017*4882a593Smuzhiyun struct hwrm_queue_qportcfg_input { 4018*4882a593Smuzhiyun __le16 req_type; 4019*4882a593Smuzhiyun __le16 cmpl_ring; 4020*4882a593Smuzhiyun __le16 seq_id; 4021*4882a593Smuzhiyun __le16 target_id; 4022*4882a593Smuzhiyun __le64 resp_addr; 4023*4882a593Smuzhiyun __le32 flags; 4024*4882a593Smuzhiyun #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 4025*4882a593Smuzhiyun #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 4026*4882a593Smuzhiyun #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 4027*4882a593Smuzhiyun #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 4028*4882a593Smuzhiyun __le16 port_id; 4029*4882a593Smuzhiyun u8 drv_qmap_cap; 4030*4882a593Smuzhiyun #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 4031*4882a593Smuzhiyun #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 4032*4882a593Smuzhiyun #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 4033*4882a593Smuzhiyun u8 unused_0; 4034*4882a593Smuzhiyun }; 4035*4882a593Smuzhiyun 4036*4882a593Smuzhiyun /* hwrm_queue_qportcfg_output (size:1344b/168B) */ 4037*4882a593Smuzhiyun struct hwrm_queue_qportcfg_output { 4038*4882a593Smuzhiyun __le16 error_code; 4039*4882a593Smuzhiyun __le16 req_type; 4040*4882a593Smuzhiyun __le16 seq_id; 4041*4882a593Smuzhiyun __le16 resp_len; 4042*4882a593Smuzhiyun u8 max_configurable_queues; 4043*4882a593Smuzhiyun u8 max_configurable_lossless_queues; 4044*4882a593Smuzhiyun u8 queue_cfg_allowed; 4045*4882a593Smuzhiyun u8 queue_cfg_info; 4046*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 4047*4882a593Smuzhiyun u8 queue_pfcenable_cfg_allowed; 4048*4882a593Smuzhiyun u8 queue_pri2cos_cfg_allowed; 4049*4882a593Smuzhiyun u8 queue_cos2bw_cfg_allowed; 4050*4882a593Smuzhiyun u8 queue_id0; 4051*4882a593Smuzhiyun u8 queue_id0_service_profile; 4052*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 4053*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 4054*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4055*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4056*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4057*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 4058*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 4059*4882a593Smuzhiyun u8 queue_id1; 4060*4882a593Smuzhiyun u8 queue_id1_service_profile; 4061*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 4062*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 4063*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4064*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4065*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4066*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 4067*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 4068*4882a593Smuzhiyun u8 queue_id2; 4069*4882a593Smuzhiyun u8 queue_id2_service_profile; 4070*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 4071*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 4072*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4073*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4074*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4075*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 4076*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 4077*4882a593Smuzhiyun u8 queue_id3; 4078*4882a593Smuzhiyun u8 queue_id3_service_profile; 4079*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 4080*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 4081*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4082*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4083*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4084*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 4085*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 4086*4882a593Smuzhiyun u8 queue_id4; 4087*4882a593Smuzhiyun u8 queue_id4_service_profile; 4088*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 4089*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 4090*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4091*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4092*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4093*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 4094*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 4095*4882a593Smuzhiyun u8 queue_id5; 4096*4882a593Smuzhiyun u8 queue_id5_service_profile; 4097*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 4098*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 4099*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4100*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4101*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4102*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 4103*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 4104*4882a593Smuzhiyun u8 queue_id6; 4105*4882a593Smuzhiyun u8 queue_id6_service_profile; 4106*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 4107*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 4108*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4109*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4110*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4111*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 4112*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 4113*4882a593Smuzhiyun u8 queue_id7; 4114*4882a593Smuzhiyun u8 queue_id7_service_profile; 4115*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 4116*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 4117*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4118*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4119*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4120*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 4121*4882a593Smuzhiyun #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 4122*4882a593Smuzhiyun u8 unused_0; 4123*4882a593Smuzhiyun char qid0_name[16]; 4124*4882a593Smuzhiyun char qid1_name[16]; 4125*4882a593Smuzhiyun char qid2_name[16]; 4126*4882a593Smuzhiyun char qid3_name[16]; 4127*4882a593Smuzhiyun char qid4_name[16]; 4128*4882a593Smuzhiyun char qid5_name[16]; 4129*4882a593Smuzhiyun char qid6_name[16]; 4130*4882a593Smuzhiyun char qid7_name[16]; 4131*4882a593Smuzhiyun u8 unused_1[7]; 4132*4882a593Smuzhiyun u8 valid; 4133*4882a593Smuzhiyun }; 4134*4882a593Smuzhiyun 4135*4882a593Smuzhiyun /* hwrm_queue_qcfg_input (size:192b/24B) */ 4136*4882a593Smuzhiyun struct hwrm_queue_qcfg_input { 4137*4882a593Smuzhiyun __le16 req_type; 4138*4882a593Smuzhiyun __le16 cmpl_ring; 4139*4882a593Smuzhiyun __le16 seq_id; 4140*4882a593Smuzhiyun __le16 target_id; 4141*4882a593Smuzhiyun __le64 resp_addr; 4142*4882a593Smuzhiyun __le32 flags; 4143*4882a593Smuzhiyun #define QUEUE_QCFG_REQ_FLAGS_PATH 0x1UL 4144*4882a593Smuzhiyun #define QUEUE_QCFG_REQ_FLAGS_PATH_TX 0x0UL 4145*4882a593Smuzhiyun #define QUEUE_QCFG_REQ_FLAGS_PATH_RX 0x1UL 4146*4882a593Smuzhiyun #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX 4147*4882a593Smuzhiyun __le32 queue_id; 4148*4882a593Smuzhiyun }; 4149*4882a593Smuzhiyun 4150*4882a593Smuzhiyun /* hwrm_queue_qcfg_output (size:128b/16B) */ 4151*4882a593Smuzhiyun struct hwrm_queue_qcfg_output { 4152*4882a593Smuzhiyun __le16 error_code; 4153*4882a593Smuzhiyun __le16 req_type; 4154*4882a593Smuzhiyun __le16 seq_id; 4155*4882a593Smuzhiyun __le16 resp_len; 4156*4882a593Smuzhiyun __le32 queue_len; 4157*4882a593Smuzhiyun u8 service_profile; 4158*4882a593Smuzhiyun #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY 0x0UL 4159*4882a593Smuzhiyun #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL 4160*4882a593Smuzhiyun #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 0xffUL 4161*4882a593Smuzhiyun #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 4162*4882a593Smuzhiyun u8 queue_cfg_info; 4163*4882a593Smuzhiyun #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 4164*4882a593Smuzhiyun u8 unused_0; 4165*4882a593Smuzhiyun u8 valid; 4166*4882a593Smuzhiyun }; 4167*4882a593Smuzhiyun 4168*4882a593Smuzhiyun /* hwrm_queue_cfg_input (size:320b/40B) */ 4169*4882a593Smuzhiyun struct hwrm_queue_cfg_input { 4170*4882a593Smuzhiyun __le16 req_type; 4171*4882a593Smuzhiyun __le16 cmpl_ring; 4172*4882a593Smuzhiyun __le16 seq_id; 4173*4882a593Smuzhiyun __le16 target_id; 4174*4882a593Smuzhiyun __le64 resp_addr; 4175*4882a593Smuzhiyun __le32 flags; 4176*4882a593Smuzhiyun #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 4177*4882a593Smuzhiyun #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 4178*4882a593Smuzhiyun #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 4179*4882a593Smuzhiyun #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 4180*4882a593Smuzhiyun #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 4181*4882a593Smuzhiyun #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 4182*4882a593Smuzhiyun __le32 enables; 4183*4882a593Smuzhiyun #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 4184*4882a593Smuzhiyun #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 4185*4882a593Smuzhiyun __le32 queue_id; 4186*4882a593Smuzhiyun __le32 dflt_len; 4187*4882a593Smuzhiyun u8 service_profile; 4188*4882a593Smuzhiyun #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 4189*4882a593Smuzhiyun #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 4190*4882a593Smuzhiyun #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 4191*4882a593Smuzhiyun #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 4192*4882a593Smuzhiyun u8 unused_0[7]; 4193*4882a593Smuzhiyun }; 4194*4882a593Smuzhiyun 4195*4882a593Smuzhiyun /* hwrm_queue_cfg_output (size:128b/16B) */ 4196*4882a593Smuzhiyun struct hwrm_queue_cfg_output { 4197*4882a593Smuzhiyun __le16 error_code; 4198*4882a593Smuzhiyun __le16 req_type; 4199*4882a593Smuzhiyun __le16 seq_id; 4200*4882a593Smuzhiyun __le16 resp_len; 4201*4882a593Smuzhiyun u8 unused_0[7]; 4202*4882a593Smuzhiyun u8 valid; 4203*4882a593Smuzhiyun }; 4204*4882a593Smuzhiyun 4205*4882a593Smuzhiyun /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 4206*4882a593Smuzhiyun struct hwrm_queue_pfcenable_qcfg_input { 4207*4882a593Smuzhiyun __le16 req_type; 4208*4882a593Smuzhiyun __le16 cmpl_ring; 4209*4882a593Smuzhiyun __le16 seq_id; 4210*4882a593Smuzhiyun __le16 target_id; 4211*4882a593Smuzhiyun __le64 resp_addr; 4212*4882a593Smuzhiyun __le16 port_id; 4213*4882a593Smuzhiyun u8 unused_0[6]; 4214*4882a593Smuzhiyun }; 4215*4882a593Smuzhiyun 4216*4882a593Smuzhiyun /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 4217*4882a593Smuzhiyun struct hwrm_queue_pfcenable_qcfg_output { 4218*4882a593Smuzhiyun __le16 error_code; 4219*4882a593Smuzhiyun __le16 req_type; 4220*4882a593Smuzhiyun __le16 seq_id; 4221*4882a593Smuzhiyun __le16 resp_len; 4222*4882a593Smuzhiyun __le32 flags; 4223*4882a593Smuzhiyun #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 4224*4882a593Smuzhiyun #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 4225*4882a593Smuzhiyun #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 4226*4882a593Smuzhiyun #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 4227*4882a593Smuzhiyun #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 4228*4882a593Smuzhiyun #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 4229*4882a593Smuzhiyun #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 4230*4882a593Smuzhiyun #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 4231*4882a593Smuzhiyun #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 4232*4882a593Smuzhiyun #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 4233*4882a593Smuzhiyun #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 4234*4882a593Smuzhiyun #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 4235*4882a593Smuzhiyun #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 4236*4882a593Smuzhiyun #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 4237*4882a593Smuzhiyun #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 4238*4882a593Smuzhiyun #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 4239*4882a593Smuzhiyun u8 unused_0[3]; 4240*4882a593Smuzhiyun u8 valid; 4241*4882a593Smuzhiyun }; 4242*4882a593Smuzhiyun 4243*4882a593Smuzhiyun /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 4244*4882a593Smuzhiyun struct hwrm_queue_pfcenable_cfg_input { 4245*4882a593Smuzhiyun __le16 req_type; 4246*4882a593Smuzhiyun __le16 cmpl_ring; 4247*4882a593Smuzhiyun __le16 seq_id; 4248*4882a593Smuzhiyun __le16 target_id; 4249*4882a593Smuzhiyun __le64 resp_addr; 4250*4882a593Smuzhiyun __le32 flags; 4251*4882a593Smuzhiyun #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 4252*4882a593Smuzhiyun #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 4253*4882a593Smuzhiyun #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 4254*4882a593Smuzhiyun #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 4255*4882a593Smuzhiyun #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 4256*4882a593Smuzhiyun #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 4257*4882a593Smuzhiyun #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 4258*4882a593Smuzhiyun #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 4259*4882a593Smuzhiyun #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 4260*4882a593Smuzhiyun #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 4261*4882a593Smuzhiyun #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 4262*4882a593Smuzhiyun #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 4263*4882a593Smuzhiyun #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 4264*4882a593Smuzhiyun #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 4265*4882a593Smuzhiyun #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 4266*4882a593Smuzhiyun #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 4267*4882a593Smuzhiyun __le16 port_id; 4268*4882a593Smuzhiyun u8 unused_0[2]; 4269*4882a593Smuzhiyun }; 4270*4882a593Smuzhiyun 4271*4882a593Smuzhiyun /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 4272*4882a593Smuzhiyun struct hwrm_queue_pfcenable_cfg_output { 4273*4882a593Smuzhiyun __le16 error_code; 4274*4882a593Smuzhiyun __le16 req_type; 4275*4882a593Smuzhiyun __le16 seq_id; 4276*4882a593Smuzhiyun __le16 resp_len; 4277*4882a593Smuzhiyun u8 unused_0[7]; 4278*4882a593Smuzhiyun u8 valid; 4279*4882a593Smuzhiyun }; 4280*4882a593Smuzhiyun 4281*4882a593Smuzhiyun /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 4282*4882a593Smuzhiyun struct hwrm_queue_pri2cos_qcfg_input { 4283*4882a593Smuzhiyun __le16 req_type; 4284*4882a593Smuzhiyun __le16 cmpl_ring; 4285*4882a593Smuzhiyun __le16 seq_id; 4286*4882a593Smuzhiyun __le16 target_id; 4287*4882a593Smuzhiyun __le64 resp_addr; 4288*4882a593Smuzhiyun __le32 flags; 4289*4882a593Smuzhiyun #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 4290*4882a593Smuzhiyun #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 4291*4882a593Smuzhiyun #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 4292*4882a593Smuzhiyun #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 4293*4882a593Smuzhiyun #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 4294*4882a593Smuzhiyun u8 port_id; 4295*4882a593Smuzhiyun u8 unused_0[3]; 4296*4882a593Smuzhiyun }; 4297*4882a593Smuzhiyun 4298*4882a593Smuzhiyun /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 4299*4882a593Smuzhiyun struct hwrm_queue_pri2cos_qcfg_output { 4300*4882a593Smuzhiyun __le16 error_code; 4301*4882a593Smuzhiyun __le16 req_type; 4302*4882a593Smuzhiyun __le16 seq_id; 4303*4882a593Smuzhiyun __le16 resp_len; 4304*4882a593Smuzhiyun u8 pri0_cos_queue_id; 4305*4882a593Smuzhiyun u8 pri1_cos_queue_id; 4306*4882a593Smuzhiyun u8 pri2_cos_queue_id; 4307*4882a593Smuzhiyun u8 pri3_cos_queue_id; 4308*4882a593Smuzhiyun u8 pri4_cos_queue_id; 4309*4882a593Smuzhiyun u8 pri5_cos_queue_id; 4310*4882a593Smuzhiyun u8 pri6_cos_queue_id; 4311*4882a593Smuzhiyun u8 pri7_cos_queue_id; 4312*4882a593Smuzhiyun u8 queue_cfg_info; 4313*4882a593Smuzhiyun #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 4314*4882a593Smuzhiyun u8 unused_0[6]; 4315*4882a593Smuzhiyun u8 valid; 4316*4882a593Smuzhiyun }; 4317*4882a593Smuzhiyun 4318*4882a593Smuzhiyun /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 4319*4882a593Smuzhiyun struct hwrm_queue_pri2cos_cfg_input { 4320*4882a593Smuzhiyun __le16 req_type; 4321*4882a593Smuzhiyun __le16 cmpl_ring; 4322*4882a593Smuzhiyun __le16 seq_id; 4323*4882a593Smuzhiyun __le16 target_id; 4324*4882a593Smuzhiyun __le64 resp_addr; 4325*4882a593Smuzhiyun __le32 flags; 4326*4882a593Smuzhiyun #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 4327*4882a593Smuzhiyun #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 4328*4882a593Smuzhiyun #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 4329*4882a593Smuzhiyun #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 4330*4882a593Smuzhiyun #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 4331*4882a593Smuzhiyun #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 4332*4882a593Smuzhiyun #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 4333*4882a593Smuzhiyun __le32 enables; 4334*4882a593Smuzhiyun #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 4335*4882a593Smuzhiyun #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 4336*4882a593Smuzhiyun #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 4337*4882a593Smuzhiyun #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 4338*4882a593Smuzhiyun #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 4339*4882a593Smuzhiyun #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 4340*4882a593Smuzhiyun #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 4341*4882a593Smuzhiyun #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 4342*4882a593Smuzhiyun u8 port_id; 4343*4882a593Smuzhiyun u8 pri0_cos_queue_id; 4344*4882a593Smuzhiyun u8 pri1_cos_queue_id; 4345*4882a593Smuzhiyun u8 pri2_cos_queue_id; 4346*4882a593Smuzhiyun u8 pri3_cos_queue_id; 4347*4882a593Smuzhiyun u8 pri4_cos_queue_id; 4348*4882a593Smuzhiyun u8 pri5_cos_queue_id; 4349*4882a593Smuzhiyun u8 pri6_cos_queue_id; 4350*4882a593Smuzhiyun u8 pri7_cos_queue_id; 4351*4882a593Smuzhiyun u8 unused_0[7]; 4352*4882a593Smuzhiyun }; 4353*4882a593Smuzhiyun 4354*4882a593Smuzhiyun /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 4355*4882a593Smuzhiyun struct hwrm_queue_pri2cos_cfg_output { 4356*4882a593Smuzhiyun __le16 error_code; 4357*4882a593Smuzhiyun __le16 req_type; 4358*4882a593Smuzhiyun __le16 seq_id; 4359*4882a593Smuzhiyun __le16 resp_len; 4360*4882a593Smuzhiyun u8 unused_0[7]; 4361*4882a593Smuzhiyun u8 valid; 4362*4882a593Smuzhiyun }; 4363*4882a593Smuzhiyun 4364*4882a593Smuzhiyun /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 4365*4882a593Smuzhiyun struct hwrm_queue_cos2bw_qcfg_input { 4366*4882a593Smuzhiyun __le16 req_type; 4367*4882a593Smuzhiyun __le16 cmpl_ring; 4368*4882a593Smuzhiyun __le16 seq_id; 4369*4882a593Smuzhiyun __le16 target_id; 4370*4882a593Smuzhiyun __le64 resp_addr; 4371*4882a593Smuzhiyun __le16 port_id; 4372*4882a593Smuzhiyun u8 unused_0[6]; 4373*4882a593Smuzhiyun }; 4374*4882a593Smuzhiyun 4375*4882a593Smuzhiyun /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 4376*4882a593Smuzhiyun struct hwrm_queue_cos2bw_qcfg_output { 4377*4882a593Smuzhiyun __le16 error_code; 4378*4882a593Smuzhiyun __le16 req_type; 4379*4882a593Smuzhiyun __le16 seq_id; 4380*4882a593Smuzhiyun __le16 resp_len; 4381*4882a593Smuzhiyun u8 queue_id0; 4382*4882a593Smuzhiyun u8 unused_0; 4383*4882a593Smuzhiyun __le16 unused_1; 4384*4882a593Smuzhiyun __le32 queue_id0_min_bw; 4385*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4386*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 4387*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 4388*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 4389*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 4390*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 4391*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4392*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 4393*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4394*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4395*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4396*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4397*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4398*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4399*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 4400*4882a593Smuzhiyun __le32 queue_id0_max_bw; 4401*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4402*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 4403*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 4404*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 4405*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 4406*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 4407*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4408*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 4409*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4410*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4411*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4412*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4413*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4414*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4415*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 4416*4882a593Smuzhiyun u8 queue_id0_tsa_assign; 4417*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 4418*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 4419*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4420*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 4421*4882a593Smuzhiyun u8 queue_id0_pri_lvl; 4422*4882a593Smuzhiyun u8 queue_id0_bw_weight; 4423*4882a593Smuzhiyun u8 queue_id1; 4424*4882a593Smuzhiyun __le32 queue_id1_min_bw; 4425*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4426*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 4427*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 4428*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 4429*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 4430*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 4431*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4432*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 4433*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4434*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4435*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4436*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4437*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4438*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4439*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 4440*4882a593Smuzhiyun __le32 queue_id1_max_bw; 4441*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4442*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 4443*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 4444*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 4445*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 4446*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 4447*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4448*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 4449*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4450*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4451*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4452*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4453*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4454*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4455*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 4456*4882a593Smuzhiyun u8 queue_id1_tsa_assign; 4457*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 4458*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 4459*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4460*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 4461*4882a593Smuzhiyun u8 queue_id1_pri_lvl; 4462*4882a593Smuzhiyun u8 queue_id1_bw_weight; 4463*4882a593Smuzhiyun u8 queue_id2; 4464*4882a593Smuzhiyun __le32 queue_id2_min_bw; 4465*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4466*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 4467*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 4468*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 4469*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 4470*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 4471*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4472*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 4473*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4474*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4475*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4476*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4477*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4478*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4479*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 4480*4882a593Smuzhiyun __le32 queue_id2_max_bw; 4481*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4482*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 4483*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 4484*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 4485*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 4486*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 4487*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4488*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 4489*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4490*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4491*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4492*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4493*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4494*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4495*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 4496*4882a593Smuzhiyun u8 queue_id2_tsa_assign; 4497*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 4498*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 4499*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4500*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 4501*4882a593Smuzhiyun u8 queue_id2_pri_lvl; 4502*4882a593Smuzhiyun u8 queue_id2_bw_weight; 4503*4882a593Smuzhiyun u8 queue_id3; 4504*4882a593Smuzhiyun __le32 queue_id3_min_bw; 4505*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4506*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 4507*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 4508*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 4509*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 4510*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 4511*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4512*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 4513*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4514*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4515*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4516*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4517*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4518*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4519*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 4520*4882a593Smuzhiyun __le32 queue_id3_max_bw; 4521*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4522*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 4523*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 4524*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 4525*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 4526*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 4527*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4528*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 4529*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4530*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4531*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4532*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4533*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4534*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4535*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 4536*4882a593Smuzhiyun u8 queue_id3_tsa_assign; 4537*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 4538*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 4539*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4540*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 4541*4882a593Smuzhiyun u8 queue_id3_pri_lvl; 4542*4882a593Smuzhiyun u8 queue_id3_bw_weight; 4543*4882a593Smuzhiyun u8 queue_id4; 4544*4882a593Smuzhiyun __le32 queue_id4_min_bw; 4545*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4546*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 4547*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 4548*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 4549*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 4550*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 4551*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4552*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 4553*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4554*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4555*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4556*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4557*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4558*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4559*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 4560*4882a593Smuzhiyun __le32 queue_id4_max_bw; 4561*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4562*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 4563*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 4564*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 4565*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 4566*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 4567*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4568*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 4569*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4570*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4571*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4572*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4573*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4574*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4575*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 4576*4882a593Smuzhiyun u8 queue_id4_tsa_assign; 4577*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 4578*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 4579*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4580*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 4581*4882a593Smuzhiyun u8 queue_id4_pri_lvl; 4582*4882a593Smuzhiyun u8 queue_id4_bw_weight; 4583*4882a593Smuzhiyun u8 queue_id5; 4584*4882a593Smuzhiyun __le32 queue_id5_min_bw; 4585*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4586*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 4587*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 4588*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 4589*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 4590*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 4591*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4592*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 4593*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4594*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4595*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4596*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4597*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4598*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4599*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 4600*4882a593Smuzhiyun __le32 queue_id5_max_bw; 4601*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4602*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 4603*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 4604*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 4605*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 4606*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 4607*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4608*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 4609*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4610*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4611*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4612*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4613*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4614*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4615*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 4616*4882a593Smuzhiyun u8 queue_id5_tsa_assign; 4617*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 4618*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 4619*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4620*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 4621*4882a593Smuzhiyun u8 queue_id5_pri_lvl; 4622*4882a593Smuzhiyun u8 queue_id5_bw_weight; 4623*4882a593Smuzhiyun u8 queue_id6; 4624*4882a593Smuzhiyun __le32 queue_id6_min_bw; 4625*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4626*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 4627*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 4628*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 4629*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 4630*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 4631*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4632*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 4633*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4634*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4635*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4636*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4637*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4638*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4639*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 4640*4882a593Smuzhiyun __le32 queue_id6_max_bw; 4641*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4642*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 4643*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 4644*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 4645*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 4646*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 4647*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4648*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 4649*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4650*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4651*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4652*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4653*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4654*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4655*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 4656*4882a593Smuzhiyun u8 queue_id6_tsa_assign; 4657*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 4658*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 4659*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4660*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 4661*4882a593Smuzhiyun u8 queue_id6_pri_lvl; 4662*4882a593Smuzhiyun u8 queue_id6_bw_weight; 4663*4882a593Smuzhiyun u8 queue_id7; 4664*4882a593Smuzhiyun __le32 queue_id7_min_bw; 4665*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4666*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 4667*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 4668*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 4669*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 4670*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 4671*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4672*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 4673*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4674*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4675*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4676*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4677*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4678*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4679*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 4680*4882a593Smuzhiyun __le32 queue_id7_max_bw; 4681*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4682*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 4683*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 4684*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 4685*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 4686*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 4687*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4688*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 4689*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4690*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4691*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4692*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4693*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4694*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4695*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 4696*4882a593Smuzhiyun u8 queue_id7_tsa_assign; 4697*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 4698*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 4699*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4700*4882a593Smuzhiyun #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 4701*4882a593Smuzhiyun u8 queue_id7_pri_lvl; 4702*4882a593Smuzhiyun u8 queue_id7_bw_weight; 4703*4882a593Smuzhiyun u8 unused_2[4]; 4704*4882a593Smuzhiyun u8 valid; 4705*4882a593Smuzhiyun }; 4706*4882a593Smuzhiyun 4707*4882a593Smuzhiyun /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 4708*4882a593Smuzhiyun struct hwrm_queue_cos2bw_cfg_input { 4709*4882a593Smuzhiyun __le16 req_type; 4710*4882a593Smuzhiyun __le16 cmpl_ring; 4711*4882a593Smuzhiyun __le16 seq_id; 4712*4882a593Smuzhiyun __le16 target_id; 4713*4882a593Smuzhiyun __le64 resp_addr; 4714*4882a593Smuzhiyun __le32 flags; 4715*4882a593Smuzhiyun __le32 enables; 4716*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 4717*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 4718*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 4719*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 4720*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 4721*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 4722*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 4723*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 4724*4882a593Smuzhiyun __le16 port_id; 4725*4882a593Smuzhiyun u8 queue_id0; 4726*4882a593Smuzhiyun u8 unused_0; 4727*4882a593Smuzhiyun __le32 queue_id0_min_bw; 4728*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4729*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 4730*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 4731*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 4732*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 4733*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 4734*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4735*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 4736*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4737*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4738*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4739*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4740*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4741*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4742*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 4743*4882a593Smuzhiyun __le32 queue_id0_max_bw; 4744*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4745*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 4746*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 4747*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 4748*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 4749*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 4750*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4751*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 4752*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4753*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4754*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4755*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4756*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4757*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4758*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 4759*4882a593Smuzhiyun u8 queue_id0_tsa_assign; 4760*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 4761*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 4762*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4763*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 4764*4882a593Smuzhiyun u8 queue_id0_pri_lvl; 4765*4882a593Smuzhiyun u8 queue_id0_bw_weight; 4766*4882a593Smuzhiyun u8 queue_id1; 4767*4882a593Smuzhiyun __le32 queue_id1_min_bw; 4768*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4769*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 4770*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 4771*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 4772*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 4773*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 4774*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4775*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 4776*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4777*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4778*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4779*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4780*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4781*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4782*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 4783*4882a593Smuzhiyun __le32 queue_id1_max_bw; 4784*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4785*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 4786*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 4787*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 4788*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 4789*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 4790*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4791*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 4792*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4793*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4794*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4795*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4796*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4797*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4798*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 4799*4882a593Smuzhiyun u8 queue_id1_tsa_assign; 4800*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 4801*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 4802*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4803*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 4804*4882a593Smuzhiyun u8 queue_id1_pri_lvl; 4805*4882a593Smuzhiyun u8 queue_id1_bw_weight; 4806*4882a593Smuzhiyun u8 queue_id2; 4807*4882a593Smuzhiyun __le32 queue_id2_min_bw; 4808*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4809*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 4810*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 4811*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 4812*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 4813*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 4814*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4815*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 4816*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4817*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4818*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4819*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4820*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4821*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4822*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 4823*4882a593Smuzhiyun __le32 queue_id2_max_bw; 4824*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4825*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 4826*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 4827*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 4828*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 4829*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 4830*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4831*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 4832*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4833*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4834*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4835*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4836*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4837*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4838*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 4839*4882a593Smuzhiyun u8 queue_id2_tsa_assign; 4840*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 4841*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 4842*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4843*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 4844*4882a593Smuzhiyun u8 queue_id2_pri_lvl; 4845*4882a593Smuzhiyun u8 queue_id2_bw_weight; 4846*4882a593Smuzhiyun u8 queue_id3; 4847*4882a593Smuzhiyun __le32 queue_id3_min_bw; 4848*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4849*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 4850*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 4851*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 4852*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 4853*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 4854*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4855*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 4856*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4857*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4858*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4859*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4860*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4861*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4862*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 4863*4882a593Smuzhiyun __le32 queue_id3_max_bw; 4864*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4865*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 4866*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 4867*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 4868*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 4869*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 4870*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4871*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 4872*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4873*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4874*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4875*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4876*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4877*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4878*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 4879*4882a593Smuzhiyun u8 queue_id3_tsa_assign; 4880*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 4881*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 4882*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4883*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 4884*4882a593Smuzhiyun u8 queue_id3_pri_lvl; 4885*4882a593Smuzhiyun u8 queue_id3_bw_weight; 4886*4882a593Smuzhiyun u8 queue_id4; 4887*4882a593Smuzhiyun __le32 queue_id4_min_bw; 4888*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4889*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 4890*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 4891*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 4892*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 4893*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 4894*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4895*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 4896*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4897*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4898*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4899*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4900*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4901*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4902*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 4903*4882a593Smuzhiyun __le32 queue_id4_max_bw; 4904*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4905*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 4906*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 4907*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 4908*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 4909*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 4910*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4911*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 4912*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4913*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4914*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4915*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4916*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4917*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4918*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 4919*4882a593Smuzhiyun u8 queue_id4_tsa_assign; 4920*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 4921*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 4922*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4923*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 4924*4882a593Smuzhiyun u8 queue_id4_pri_lvl; 4925*4882a593Smuzhiyun u8 queue_id4_bw_weight; 4926*4882a593Smuzhiyun u8 queue_id5; 4927*4882a593Smuzhiyun __le32 queue_id5_min_bw; 4928*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4929*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 4930*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 4931*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 4932*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 4933*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 4934*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4935*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 4936*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4937*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4938*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4939*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4940*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4941*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4942*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 4943*4882a593Smuzhiyun __le32 queue_id5_max_bw; 4944*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4945*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 4946*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 4947*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 4948*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 4949*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 4950*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4951*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 4952*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4953*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4954*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4955*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4956*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4957*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4958*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 4959*4882a593Smuzhiyun u8 queue_id5_tsa_assign; 4960*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 4961*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 4962*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4963*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 4964*4882a593Smuzhiyun u8 queue_id5_pri_lvl; 4965*4882a593Smuzhiyun u8 queue_id5_bw_weight; 4966*4882a593Smuzhiyun u8 queue_id6; 4967*4882a593Smuzhiyun __le32 queue_id6_min_bw; 4968*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4969*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 4970*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 4971*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 4972*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 4973*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 4974*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4975*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 4976*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4977*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4978*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4979*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4980*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4981*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4982*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 4983*4882a593Smuzhiyun __le32 queue_id6_max_bw; 4984*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4985*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 4986*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 4987*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 4988*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 4989*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 4990*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4991*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 4992*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4993*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4994*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4995*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4996*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4997*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4998*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 4999*4882a593Smuzhiyun u8 queue_id6_tsa_assign; 5000*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 5001*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 5002*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5003*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 5004*4882a593Smuzhiyun u8 queue_id6_pri_lvl; 5005*4882a593Smuzhiyun u8 queue_id6_bw_weight; 5006*4882a593Smuzhiyun u8 queue_id7; 5007*4882a593Smuzhiyun __le32 queue_id7_min_bw; 5008*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5009*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 5010*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 5011*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 5012*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 5013*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 5014*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5015*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 5016*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5017*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5018*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5019*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5020*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5021*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5022*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 5023*4882a593Smuzhiyun __le32 queue_id7_max_bw; 5024*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5025*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 5026*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 5027*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 5028*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 5029*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 5030*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5031*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 5032*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5033*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5034*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5035*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5036*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5037*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5038*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 5039*4882a593Smuzhiyun u8 queue_id7_tsa_assign; 5040*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 5041*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 5042*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5043*4882a593Smuzhiyun #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 5044*4882a593Smuzhiyun u8 queue_id7_pri_lvl; 5045*4882a593Smuzhiyun u8 queue_id7_bw_weight; 5046*4882a593Smuzhiyun u8 unused_1[5]; 5047*4882a593Smuzhiyun }; 5048*4882a593Smuzhiyun 5049*4882a593Smuzhiyun /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 5050*4882a593Smuzhiyun struct hwrm_queue_cos2bw_cfg_output { 5051*4882a593Smuzhiyun __le16 error_code; 5052*4882a593Smuzhiyun __le16 req_type; 5053*4882a593Smuzhiyun __le16 seq_id; 5054*4882a593Smuzhiyun __le16 resp_len; 5055*4882a593Smuzhiyun u8 unused_0[7]; 5056*4882a593Smuzhiyun u8 valid; 5057*4882a593Smuzhiyun }; 5058*4882a593Smuzhiyun 5059*4882a593Smuzhiyun /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 5060*4882a593Smuzhiyun struct hwrm_queue_dscp_qcaps_input { 5061*4882a593Smuzhiyun __le16 req_type; 5062*4882a593Smuzhiyun __le16 cmpl_ring; 5063*4882a593Smuzhiyun __le16 seq_id; 5064*4882a593Smuzhiyun __le16 target_id; 5065*4882a593Smuzhiyun __le64 resp_addr; 5066*4882a593Smuzhiyun u8 port_id; 5067*4882a593Smuzhiyun u8 unused_0[7]; 5068*4882a593Smuzhiyun }; 5069*4882a593Smuzhiyun 5070*4882a593Smuzhiyun /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 5071*4882a593Smuzhiyun struct hwrm_queue_dscp_qcaps_output { 5072*4882a593Smuzhiyun __le16 error_code; 5073*4882a593Smuzhiyun __le16 req_type; 5074*4882a593Smuzhiyun __le16 seq_id; 5075*4882a593Smuzhiyun __le16 resp_len; 5076*4882a593Smuzhiyun u8 num_dscp_bits; 5077*4882a593Smuzhiyun u8 unused_0; 5078*4882a593Smuzhiyun __le16 max_entries; 5079*4882a593Smuzhiyun u8 unused_1[3]; 5080*4882a593Smuzhiyun u8 valid; 5081*4882a593Smuzhiyun }; 5082*4882a593Smuzhiyun 5083*4882a593Smuzhiyun /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 5084*4882a593Smuzhiyun struct hwrm_queue_dscp2pri_qcfg_input { 5085*4882a593Smuzhiyun __le16 req_type; 5086*4882a593Smuzhiyun __le16 cmpl_ring; 5087*4882a593Smuzhiyun __le16 seq_id; 5088*4882a593Smuzhiyun __le16 target_id; 5089*4882a593Smuzhiyun __le64 resp_addr; 5090*4882a593Smuzhiyun __le64 dest_data_addr; 5091*4882a593Smuzhiyun u8 port_id; 5092*4882a593Smuzhiyun u8 unused_0; 5093*4882a593Smuzhiyun __le16 dest_data_buffer_size; 5094*4882a593Smuzhiyun u8 unused_1[4]; 5095*4882a593Smuzhiyun }; 5096*4882a593Smuzhiyun 5097*4882a593Smuzhiyun /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 5098*4882a593Smuzhiyun struct hwrm_queue_dscp2pri_qcfg_output { 5099*4882a593Smuzhiyun __le16 error_code; 5100*4882a593Smuzhiyun __le16 req_type; 5101*4882a593Smuzhiyun __le16 seq_id; 5102*4882a593Smuzhiyun __le16 resp_len; 5103*4882a593Smuzhiyun __le16 entry_cnt; 5104*4882a593Smuzhiyun u8 default_pri; 5105*4882a593Smuzhiyun u8 unused_0[4]; 5106*4882a593Smuzhiyun u8 valid; 5107*4882a593Smuzhiyun }; 5108*4882a593Smuzhiyun 5109*4882a593Smuzhiyun /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 5110*4882a593Smuzhiyun struct hwrm_queue_dscp2pri_cfg_input { 5111*4882a593Smuzhiyun __le16 req_type; 5112*4882a593Smuzhiyun __le16 cmpl_ring; 5113*4882a593Smuzhiyun __le16 seq_id; 5114*4882a593Smuzhiyun __le16 target_id; 5115*4882a593Smuzhiyun __le64 resp_addr; 5116*4882a593Smuzhiyun __le64 src_data_addr; 5117*4882a593Smuzhiyun __le32 flags; 5118*4882a593Smuzhiyun #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 5119*4882a593Smuzhiyun __le32 enables; 5120*4882a593Smuzhiyun #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 5121*4882a593Smuzhiyun u8 port_id; 5122*4882a593Smuzhiyun u8 default_pri; 5123*4882a593Smuzhiyun __le16 entry_cnt; 5124*4882a593Smuzhiyun u8 unused_0[4]; 5125*4882a593Smuzhiyun }; 5126*4882a593Smuzhiyun 5127*4882a593Smuzhiyun /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 5128*4882a593Smuzhiyun struct hwrm_queue_dscp2pri_cfg_output { 5129*4882a593Smuzhiyun __le16 error_code; 5130*4882a593Smuzhiyun __le16 req_type; 5131*4882a593Smuzhiyun __le16 seq_id; 5132*4882a593Smuzhiyun __le16 resp_len; 5133*4882a593Smuzhiyun u8 unused_0[7]; 5134*4882a593Smuzhiyun u8 valid; 5135*4882a593Smuzhiyun }; 5136*4882a593Smuzhiyun 5137*4882a593Smuzhiyun /* hwrm_vnic_alloc_input (size:192b/24B) */ 5138*4882a593Smuzhiyun struct hwrm_vnic_alloc_input { 5139*4882a593Smuzhiyun __le16 req_type; 5140*4882a593Smuzhiyun __le16 cmpl_ring; 5141*4882a593Smuzhiyun __le16 seq_id; 5142*4882a593Smuzhiyun __le16 target_id; 5143*4882a593Smuzhiyun __le64 resp_addr; 5144*4882a593Smuzhiyun __le32 flags; 5145*4882a593Smuzhiyun #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 5146*4882a593Smuzhiyun u8 unused_0[4]; 5147*4882a593Smuzhiyun }; 5148*4882a593Smuzhiyun 5149*4882a593Smuzhiyun /* hwrm_vnic_alloc_output (size:128b/16B) */ 5150*4882a593Smuzhiyun struct hwrm_vnic_alloc_output { 5151*4882a593Smuzhiyun __le16 error_code; 5152*4882a593Smuzhiyun __le16 req_type; 5153*4882a593Smuzhiyun __le16 seq_id; 5154*4882a593Smuzhiyun __le16 resp_len; 5155*4882a593Smuzhiyun __le32 vnic_id; 5156*4882a593Smuzhiyun u8 unused_0[3]; 5157*4882a593Smuzhiyun u8 valid; 5158*4882a593Smuzhiyun }; 5159*4882a593Smuzhiyun 5160*4882a593Smuzhiyun /* hwrm_vnic_free_input (size:192b/24B) */ 5161*4882a593Smuzhiyun struct hwrm_vnic_free_input { 5162*4882a593Smuzhiyun __le16 req_type; 5163*4882a593Smuzhiyun __le16 cmpl_ring; 5164*4882a593Smuzhiyun __le16 seq_id; 5165*4882a593Smuzhiyun __le16 target_id; 5166*4882a593Smuzhiyun __le64 resp_addr; 5167*4882a593Smuzhiyun __le32 vnic_id; 5168*4882a593Smuzhiyun u8 unused_0[4]; 5169*4882a593Smuzhiyun }; 5170*4882a593Smuzhiyun 5171*4882a593Smuzhiyun /* hwrm_vnic_free_output (size:128b/16B) */ 5172*4882a593Smuzhiyun struct hwrm_vnic_free_output { 5173*4882a593Smuzhiyun __le16 error_code; 5174*4882a593Smuzhiyun __le16 req_type; 5175*4882a593Smuzhiyun __le16 seq_id; 5176*4882a593Smuzhiyun __le16 resp_len; 5177*4882a593Smuzhiyun u8 unused_0[7]; 5178*4882a593Smuzhiyun u8 valid; 5179*4882a593Smuzhiyun }; 5180*4882a593Smuzhiyun 5181*4882a593Smuzhiyun /* hwrm_vnic_cfg_input (size:384b/48B) */ 5182*4882a593Smuzhiyun struct hwrm_vnic_cfg_input { 5183*4882a593Smuzhiyun __le16 req_type; 5184*4882a593Smuzhiyun __le16 cmpl_ring; 5185*4882a593Smuzhiyun __le16 seq_id; 5186*4882a593Smuzhiyun __le16 target_id; 5187*4882a593Smuzhiyun __le64 resp_addr; 5188*4882a593Smuzhiyun __le32 flags; 5189*4882a593Smuzhiyun #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 5190*4882a593Smuzhiyun #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 5191*4882a593Smuzhiyun #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 5192*4882a593Smuzhiyun #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 5193*4882a593Smuzhiyun #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 5194*4882a593Smuzhiyun #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 5195*4882a593Smuzhiyun #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 5196*4882a593Smuzhiyun __le32 enables; 5197*4882a593Smuzhiyun #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 5198*4882a593Smuzhiyun #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 5199*4882a593Smuzhiyun #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 5200*4882a593Smuzhiyun #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 5201*4882a593Smuzhiyun #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 5202*4882a593Smuzhiyun #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL 5203*4882a593Smuzhiyun #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL 5204*4882a593Smuzhiyun #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL 5205*4882a593Smuzhiyun #define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL 5206*4882a593Smuzhiyun __le16 vnic_id; 5207*4882a593Smuzhiyun __le16 dflt_ring_grp; 5208*4882a593Smuzhiyun __le16 rss_rule; 5209*4882a593Smuzhiyun __le16 cos_rule; 5210*4882a593Smuzhiyun __le16 lb_rule; 5211*4882a593Smuzhiyun __le16 mru; 5212*4882a593Smuzhiyun __le16 default_rx_ring_id; 5213*4882a593Smuzhiyun __le16 default_cmpl_ring_id; 5214*4882a593Smuzhiyun __le16 queue_id; 5215*4882a593Smuzhiyun u8 rx_csum_v2_mode; 5216*4882a593Smuzhiyun #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL 5217*4882a593Smuzhiyun #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK 0x1UL 5218*4882a593Smuzhiyun #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 0x2UL 5219*4882a593Smuzhiyun #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 5220*4882a593Smuzhiyun u8 unused0[5]; 5221*4882a593Smuzhiyun }; 5222*4882a593Smuzhiyun 5223*4882a593Smuzhiyun /* hwrm_vnic_cfg_output (size:128b/16B) */ 5224*4882a593Smuzhiyun struct hwrm_vnic_cfg_output { 5225*4882a593Smuzhiyun __le16 error_code; 5226*4882a593Smuzhiyun __le16 req_type; 5227*4882a593Smuzhiyun __le16 seq_id; 5228*4882a593Smuzhiyun __le16 resp_len; 5229*4882a593Smuzhiyun u8 unused_0[7]; 5230*4882a593Smuzhiyun u8 valid; 5231*4882a593Smuzhiyun }; 5232*4882a593Smuzhiyun 5233*4882a593Smuzhiyun /* hwrm_vnic_qcaps_input (size:192b/24B) */ 5234*4882a593Smuzhiyun struct hwrm_vnic_qcaps_input { 5235*4882a593Smuzhiyun __le16 req_type; 5236*4882a593Smuzhiyun __le16 cmpl_ring; 5237*4882a593Smuzhiyun __le16 seq_id; 5238*4882a593Smuzhiyun __le16 target_id; 5239*4882a593Smuzhiyun __le64 resp_addr; 5240*4882a593Smuzhiyun __le32 enables; 5241*4882a593Smuzhiyun u8 unused_0[4]; 5242*4882a593Smuzhiyun }; 5243*4882a593Smuzhiyun 5244*4882a593Smuzhiyun /* hwrm_vnic_qcaps_output (size:192b/24B) */ 5245*4882a593Smuzhiyun struct hwrm_vnic_qcaps_output { 5246*4882a593Smuzhiyun __le16 error_code; 5247*4882a593Smuzhiyun __le16 req_type; 5248*4882a593Smuzhiyun __le16 seq_id; 5249*4882a593Smuzhiyun __le16 resp_len; 5250*4882a593Smuzhiyun __le16 mru; 5251*4882a593Smuzhiyun u8 unused_0[2]; 5252*4882a593Smuzhiyun __le32 flags; 5253*4882a593Smuzhiyun #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 5254*4882a593Smuzhiyun #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 5255*4882a593Smuzhiyun #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 5256*4882a593Smuzhiyun #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 5257*4882a593Smuzhiyun #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 5258*4882a593Smuzhiyun #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 5259*4882a593Smuzhiyun #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 5260*4882a593Smuzhiyun #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 5261*4882a593Smuzhiyun #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL 5262*4882a593Smuzhiyun #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP 0x200UL 5263*4882a593Smuzhiyun __le16 max_aggs_supported; 5264*4882a593Smuzhiyun u8 unused_1[5]; 5265*4882a593Smuzhiyun u8 valid; 5266*4882a593Smuzhiyun }; 5267*4882a593Smuzhiyun 5268*4882a593Smuzhiyun /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ 5269*4882a593Smuzhiyun struct hwrm_vnic_tpa_cfg_input { 5270*4882a593Smuzhiyun __le16 req_type; 5271*4882a593Smuzhiyun __le16 cmpl_ring; 5272*4882a593Smuzhiyun __le16 seq_id; 5273*4882a593Smuzhiyun __le16 target_id; 5274*4882a593Smuzhiyun __le64 resp_addr; 5275*4882a593Smuzhiyun __le32 flags; 5276*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 5277*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 5278*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 5279*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 5280*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 5281*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 5282*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 5283*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 5284*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL 5285*4882a593Smuzhiyun __le32 enables; 5286*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 5287*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 5288*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 5289*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 5290*4882a593Smuzhiyun __le16 vnic_id; 5291*4882a593Smuzhiyun __le16 max_agg_segs; 5292*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 5293*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 5294*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 5295*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 5296*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 5297*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 5298*4882a593Smuzhiyun __le16 max_aggs; 5299*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 5300*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 5301*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 5302*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 5303*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 5304*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 5305*4882a593Smuzhiyun #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 5306*4882a593Smuzhiyun u8 unused_0[2]; 5307*4882a593Smuzhiyun __le32 max_agg_timer; 5308*4882a593Smuzhiyun __le32 min_agg_len; 5309*4882a593Smuzhiyun }; 5310*4882a593Smuzhiyun 5311*4882a593Smuzhiyun /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 5312*4882a593Smuzhiyun struct hwrm_vnic_tpa_cfg_output { 5313*4882a593Smuzhiyun __le16 error_code; 5314*4882a593Smuzhiyun __le16 req_type; 5315*4882a593Smuzhiyun __le16 seq_id; 5316*4882a593Smuzhiyun __le16 resp_len; 5317*4882a593Smuzhiyun u8 unused_0[7]; 5318*4882a593Smuzhiyun u8 valid; 5319*4882a593Smuzhiyun }; 5320*4882a593Smuzhiyun 5321*4882a593Smuzhiyun /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 5322*4882a593Smuzhiyun struct hwrm_vnic_tpa_qcfg_input { 5323*4882a593Smuzhiyun __le16 req_type; 5324*4882a593Smuzhiyun __le16 cmpl_ring; 5325*4882a593Smuzhiyun __le16 seq_id; 5326*4882a593Smuzhiyun __le16 target_id; 5327*4882a593Smuzhiyun __le64 resp_addr; 5328*4882a593Smuzhiyun __le16 vnic_id; 5329*4882a593Smuzhiyun u8 unused_0[6]; 5330*4882a593Smuzhiyun }; 5331*4882a593Smuzhiyun 5332*4882a593Smuzhiyun /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 5333*4882a593Smuzhiyun struct hwrm_vnic_tpa_qcfg_output { 5334*4882a593Smuzhiyun __le16 error_code; 5335*4882a593Smuzhiyun __le16 req_type; 5336*4882a593Smuzhiyun __le16 seq_id; 5337*4882a593Smuzhiyun __le16 resp_len; 5338*4882a593Smuzhiyun __le32 flags; 5339*4882a593Smuzhiyun #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 5340*4882a593Smuzhiyun #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 5341*4882a593Smuzhiyun #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 5342*4882a593Smuzhiyun #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 5343*4882a593Smuzhiyun #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 5344*4882a593Smuzhiyun #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 5345*4882a593Smuzhiyun #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 5346*4882a593Smuzhiyun #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 5347*4882a593Smuzhiyun __le16 max_agg_segs; 5348*4882a593Smuzhiyun #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 5349*4882a593Smuzhiyun #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 5350*4882a593Smuzhiyun #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 5351*4882a593Smuzhiyun #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 5352*4882a593Smuzhiyun #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 5353*4882a593Smuzhiyun #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 5354*4882a593Smuzhiyun __le16 max_aggs; 5355*4882a593Smuzhiyun #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 5356*4882a593Smuzhiyun #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 5357*4882a593Smuzhiyun #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 5358*4882a593Smuzhiyun #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 5359*4882a593Smuzhiyun #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 5360*4882a593Smuzhiyun #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 5361*4882a593Smuzhiyun #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 5362*4882a593Smuzhiyun __le32 max_agg_timer; 5363*4882a593Smuzhiyun __le32 min_agg_len; 5364*4882a593Smuzhiyun u8 unused_0[7]; 5365*4882a593Smuzhiyun u8 valid; 5366*4882a593Smuzhiyun }; 5367*4882a593Smuzhiyun 5368*4882a593Smuzhiyun /* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 5369*4882a593Smuzhiyun struct hwrm_vnic_rss_cfg_input { 5370*4882a593Smuzhiyun __le16 req_type; 5371*4882a593Smuzhiyun __le16 cmpl_ring; 5372*4882a593Smuzhiyun __le16 seq_id; 5373*4882a593Smuzhiyun __le16 target_id; 5374*4882a593Smuzhiyun __le64 resp_addr; 5375*4882a593Smuzhiyun __le32 hash_type; 5376*4882a593Smuzhiyun #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 5377*4882a593Smuzhiyun #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 5378*4882a593Smuzhiyun #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 5379*4882a593Smuzhiyun #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 5380*4882a593Smuzhiyun #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 5381*4882a593Smuzhiyun #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 5382*4882a593Smuzhiyun __le16 vnic_id; 5383*4882a593Smuzhiyun u8 ring_table_pair_index; 5384*4882a593Smuzhiyun u8 hash_mode_flags; 5385*4882a593Smuzhiyun #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL 5386*4882a593Smuzhiyun #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 5387*4882a593Smuzhiyun #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 5388*4882a593Smuzhiyun #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 5389*4882a593Smuzhiyun #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 5390*4882a593Smuzhiyun __le64 ring_grp_tbl_addr; 5391*4882a593Smuzhiyun __le64 hash_key_tbl_addr; 5392*4882a593Smuzhiyun __le16 rss_ctx_idx; 5393*4882a593Smuzhiyun u8 unused_1[6]; 5394*4882a593Smuzhiyun }; 5395*4882a593Smuzhiyun 5396*4882a593Smuzhiyun /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 5397*4882a593Smuzhiyun struct hwrm_vnic_rss_cfg_output { 5398*4882a593Smuzhiyun __le16 error_code; 5399*4882a593Smuzhiyun __le16 req_type; 5400*4882a593Smuzhiyun __le16 seq_id; 5401*4882a593Smuzhiyun __le16 resp_len; 5402*4882a593Smuzhiyun u8 unused_0[7]; 5403*4882a593Smuzhiyun u8 valid; 5404*4882a593Smuzhiyun }; 5405*4882a593Smuzhiyun 5406*4882a593Smuzhiyun /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ 5407*4882a593Smuzhiyun struct hwrm_vnic_rss_cfg_cmd_err { 5408*4882a593Smuzhiyun u8 code; 5409*4882a593Smuzhiyun #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 5410*4882a593Smuzhiyun #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL 5411*4882a593Smuzhiyun #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 5412*4882a593Smuzhiyun u8 unused_0[7]; 5413*4882a593Smuzhiyun }; 5414*4882a593Smuzhiyun 5415*4882a593Smuzhiyun /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 5416*4882a593Smuzhiyun struct hwrm_vnic_plcmodes_cfg_input { 5417*4882a593Smuzhiyun __le16 req_type; 5418*4882a593Smuzhiyun __le16 cmpl_ring; 5419*4882a593Smuzhiyun __le16 seq_id; 5420*4882a593Smuzhiyun __le16 target_id; 5421*4882a593Smuzhiyun __le64 resp_addr; 5422*4882a593Smuzhiyun __le32 flags; 5423*4882a593Smuzhiyun #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 5424*4882a593Smuzhiyun #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 5425*4882a593Smuzhiyun #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 5426*4882a593Smuzhiyun #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 5427*4882a593Smuzhiyun #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 5428*4882a593Smuzhiyun #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 5429*4882a593Smuzhiyun #define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT 0x40UL 5430*4882a593Smuzhiyun __le32 enables; 5431*4882a593Smuzhiyun #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 5432*4882a593Smuzhiyun #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 5433*4882a593Smuzhiyun #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 5434*4882a593Smuzhiyun #define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID 0x8UL 5435*4882a593Smuzhiyun __le32 vnic_id; 5436*4882a593Smuzhiyun __le16 jumbo_thresh; 5437*4882a593Smuzhiyun __le16 hds_offset; 5438*4882a593Smuzhiyun __le16 hds_threshold; 5439*4882a593Smuzhiyun __le16 max_bds; 5440*4882a593Smuzhiyun u8 unused_0[4]; 5441*4882a593Smuzhiyun }; 5442*4882a593Smuzhiyun 5443*4882a593Smuzhiyun /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 5444*4882a593Smuzhiyun struct hwrm_vnic_plcmodes_cfg_output { 5445*4882a593Smuzhiyun __le16 error_code; 5446*4882a593Smuzhiyun __le16 req_type; 5447*4882a593Smuzhiyun __le16 seq_id; 5448*4882a593Smuzhiyun __le16 resp_len; 5449*4882a593Smuzhiyun u8 unused_0[7]; 5450*4882a593Smuzhiyun u8 valid; 5451*4882a593Smuzhiyun }; 5452*4882a593Smuzhiyun 5453*4882a593Smuzhiyun /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 5454*4882a593Smuzhiyun struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 5455*4882a593Smuzhiyun __le16 req_type; 5456*4882a593Smuzhiyun __le16 cmpl_ring; 5457*4882a593Smuzhiyun __le16 seq_id; 5458*4882a593Smuzhiyun __le16 target_id; 5459*4882a593Smuzhiyun __le64 resp_addr; 5460*4882a593Smuzhiyun }; 5461*4882a593Smuzhiyun 5462*4882a593Smuzhiyun /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 5463*4882a593Smuzhiyun struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 5464*4882a593Smuzhiyun __le16 error_code; 5465*4882a593Smuzhiyun __le16 req_type; 5466*4882a593Smuzhiyun __le16 seq_id; 5467*4882a593Smuzhiyun __le16 resp_len; 5468*4882a593Smuzhiyun __le16 rss_cos_lb_ctx_id; 5469*4882a593Smuzhiyun u8 unused_0[5]; 5470*4882a593Smuzhiyun u8 valid; 5471*4882a593Smuzhiyun }; 5472*4882a593Smuzhiyun 5473*4882a593Smuzhiyun /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 5474*4882a593Smuzhiyun struct hwrm_vnic_rss_cos_lb_ctx_free_input { 5475*4882a593Smuzhiyun __le16 req_type; 5476*4882a593Smuzhiyun __le16 cmpl_ring; 5477*4882a593Smuzhiyun __le16 seq_id; 5478*4882a593Smuzhiyun __le16 target_id; 5479*4882a593Smuzhiyun __le64 resp_addr; 5480*4882a593Smuzhiyun __le16 rss_cos_lb_ctx_id; 5481*4882a593Smuzhiyun u8 unused_0[6]; 5482*4882a593Smuzhiyun }; 5483*4882a593Smuzhiyun 5484*4882a593Smuzhiyun /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 5485*4882a593Smuzhiyun struct hwrm_vnic_rss_cos_lb_ctx_free_output { 5486*4882a593Smuzhiyun __le16 error_code; 5487*4882a593Smuzhiyun __le16 req_type; 5488*4882a593Smuzhiyun __le16 seq_id; 5489*4882a593Smuzhiyun __le16 resp_len; 5490*4882a593Smuzhiyun u8 unused_0[7]; 5491*4882a593Smuzhiyun u8 valid; 5492*4882a593Smuzhiyun }; 5493*4882a593Smuzhiyun 5494*4882a593Smuzhiyun /* hwrm_ring_alloc_input (size:704b/88B) */ 5495*4882a593Smuzhiyun struct hwrm_ring_alloc_input { 5496*4882a593Smuzhiyun __le16 req_type; 5497*4882a593Smuzhiyun __le16 cmpl_ring; 5498*4882a593Smuzhiyun __le16 seq_id; 5499*4882a593Smuzhiyun __le16 target_id; 5500*4882a593Smuzhiyun __le64 resp_addr; 5501*4882a593Smuzhiyun __le32 enables; 5502*4882a593Smuzhiyun #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 5503*4882a593Smuzhiyun #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 5504*4882a593Smuzhiyun #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 5505*4882a593Smuzhiyun #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL 5506*4882a593Smuzhiyun #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL 5507*4882a593Smuzhiyun #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 5508*4882a593Smuzhiyun #define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL 5509*4882a593Smuzhiyun #define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL 5510*4882a593Smuzhiyun u8 ring_type; 5511*4882a593Smuzhiyun #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 5512*4882a593Smuzhiyun #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 5513*4882a593Smuzhiyun #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 5514*4882a593Smuzhiyun #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5515*4882a593Smuzhiyun #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL 5516*4882a593Smuzhiyun #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL 5517*4882a593Smuzhiyun #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ 5518*4882a593Smuzhiyun u8 unused_0; 5519*4882a593Smuzhiyun __le16 flags; 5520*4882a593Smuzhiyun #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 5521*4882a593Smuzhiyun __le64 page_tbl_addr; 5522*4882a593Smuzhiyun __le32 fbo; 5523*4882a593Smuzhiyun u8 page_size; 5524*4882a593Smuzhiyun u8 page_tbl_depth; 5525*4882a593Smuzhiyun __le16 schq_id; 5526*4882a593Smuzhiyun __le32 length; 5527*4882a593Smuzhiyun __le16 logical_id; 5528*4882a593Smuzhiyun __le16 cmpl_ring_id; 5529*4882a593Smuzhiyun __le16 queue_id; 5530*4882a593Smuzhiyun __le16 rx_buf_size; 5531*4882a593Smuzhiyun __le16 rx_ring_id; 5532*4882a593Smuzhiyun __le16 nq_ring_id; 5533*4882a593Smuzhiyun __le16 ring_arb_cfg; 5534*4882a593Smuzhiyun #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 5535*4882a593Smuzhiyun #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 5536*4882a593Smuzhiyun #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 5537*4882a593Smuzhiyun #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 5538*4882a593Smuzhiyun #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 5539*4882a593Smuzhiyun #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 5540*4882a593Smuzhiyun #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 5541*4882a593Smuzhiyun #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 5542*4882a593Smuzhiyun #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 5543*4882a593Smuzhiyun __le16 unused_3; 5544*4882a593Smuzhiyun __le32 reserved3; 5545*4882a593Smuzhiyun __le32 stat_ctx_id; 5546*4882a593Smuzhiyun __le32 reserved4; 5547*4882a593Smuzhiyun __le32 max_bw; 5548*4882a593Smuzhiyun #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5549*4882a593Smuzhiyun #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 5550*4882a593Smuzhiyun #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 5551*4882a593Smuzhiyun #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 5552*4882a593Smuzhiyun #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 5553*4882a593Smuzhiyun #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 5554*4882a593Smuzhiyun #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5555*4882a593Smuzhiyun #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 5556*4882a593Smuzhiyun #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5557*4882a593Smuzhiyun #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5558*4882a593Smuzhiyun #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5559*4882a593Smuzhiyun #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5560*4882a593Smuzhiyun #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5561*4882a593Smuzhiyun #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5562*4882a593Smuzhiyun #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 5563*4882a593Smuzhiyun u8 int_mode; 5564*4882a593Smuzhiyun #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 5565*4882a593Smuzhiyun #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 5566*4882a593Smuzhiyun #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 5567*4882a593Smuzhiyun #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 5568*4882a593Smuzhiyun #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 5569*4882a593Smuzhiyun u8 mpc_chnls_type; 5570*4882a593Smuzhiyun #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TCE 0x0UL 5571*4882a593Smuzhiyun #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RCE 0x1UL 5572*4882a593Smuzhiyun #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TE_CFA 0x2UL 5573*4882a593Smuzhiyun #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA 0x3UL 5574*4882a593Smuzhiyun #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL 5575*4882a593Smuzhiyun #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 5576*4882a593Smuzhiyun u8 unused_4[2]; 5577*4882a593Smuzhiyun __le64 cq_handle; 5578*4882a593Smuzhiyun }; 5579*4882a593Smuzhiyun 5580*4882a593Smuzhiyun /* hwrm_ring_alloc_output (size:128b/16B) */ 5581*4882a593Smuzhiyun struct hwrm_ring_alloc_output { 5582*4882a593Smuzhiyun __le16 error_code; 5583*4882a593Smuzhiyun __le16 req_type; 5584*4882a593Smuzhiyun __le16 seq_id; 5585*4882a593Smuzhiyun __le16 resp_len; 5586*4882a593Smuzhiyun __le16 ring_id; 5587*4882a593Smuzhiyun __le16 logical_ring_id; 5588*4882a593Smuzhiyun u8 unused_0[3]; 5589*4882a593Smuzhiyun u8 valid; 5590*4882a593Smuzhiyun }; 5591*4882a593Smuzhiyun 5592*4882a593Smuzhiyun /* hwrm_ring_free_input (size:192b/24B) */ 5593*4882a593Smuzhiyun struct hwrm_ring_free_input { 5594*4882a593Smuzhiyun __le16 req_type; 5595*4882a593Smuzhiyun __le16 cmpl_ring; 5596*4882a593Smuzhiyun __le16 seq_id; 5597*4882a593Smuzhiyun __le16 target_id; 5598*4882a593Smuzhiyun __le64 resp_addr; 5599*4882a593Smuzhiyun u8 ring_type; 5600*4882a593Smuzhiyun #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 5601*4882a593Smuzhiyun #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 5602*4882a593Smuzhiyun #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 5603*4882a593Smuzhiyun #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5604*4882a593Smuzhiyun #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL 5605*4882a593Smuzhiyun #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL 5606*4882a593Smuzhiyun #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ 5607*4882a593Smuzhiyun u8 unused_0; 5608*4882a593Smuzhiyun __le16 ring_id; 5609*4882a593Smuzhiyun u8 unused_1[4]; 5610*4882a593Smuzhiyun }; 5611*4882a593Smuzhiyun 5612*4882a593Smuzhiyun /* hwrm_ring_free_output (size:128b/16B) */ 5613*4882a593Smuzhiyun struct hwrm_ring_free_output { 5614*4882a593Smuzhiyun __le16 error_code; 5615*4882a593Smuzhiyun __le16 req_type; 5616*4882a593Smuzhiyun __le16 seq_id; 5617*4882a593Smuzhiyun __le16 resp_len; 5618*4882a593Smuzhiyun u8 unused_0[7]; 5619*4882a593Smuzhiyun u8 valid; 5620*4882a593Smuzhiyun }; 5621*4882a593Smuzhiyun 5622*4882a593Smuzhiyun /* hwrm_ring_reset_input (size:192b/24B) */ 5623*4882a593Smuzhiyun struct hwrm_ring_reset_input { 5624*4882a593Smuzhiyun __le16 req_type; 5625*4882a593Smuzhiyun __le16 cmpl_ring; 5626*4882a593Smuzhiyun __le16 seq_id; 5627*4882a593Smuzhiyun __le16 target_id; 5628*4882a593Smuzhiyun __le64 resp_addr; 5629*4882a593Smuzhiyun u8 ring_type; 5630*4882a593Smuzhiyun #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 5631*4882a593Smuzhiyun #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 5632*4882a593Smuzhiyun #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 5633*4882a593Smuzhiyun #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5634*4882a593Smuzhiyun #define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL 5635*4882a593Smuzhiyun #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_RX_RING_GRP 5636*4882a593Smuzhiyun u8 unused_0; 5637*4882a593Smuzhiyun __le16 ring_id; 5638*4882a593Smuzhiyun u8 unused_1[4]; 5639*4882a593Smuzhiyun }; 5640*4882a593Smuzhiyun 5641*4882a593Smuzhiyun /* hwrm_ring_reset_output (size:128b/16B) */ 5642*4882a593Smuzhiyun struct hwrm_ring_reset_output { 5643*4882a593Smuzhiyun __le16 error_code; 5644*4882a593Smuzhiyun __le16 req_type; 5645*4882a593Smuzhiyun __le16 seq_id; 5646*4882a593Smuzhiyun __le16 resp_len; 5647*4882a593Smuzhiyun u8 unused_0[4]; 5648*4882a593Smuzhiyun u8 consumer_idx[3]; 5649*4882a593Smuzhiyun u8 valid; 5650*4882a593Smuzhiyun }; 5651*4882a593Smuzhiyun 5652*4882a593Smuzhiyun /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ 5653*4882a593Smuzhiyun struct hwrm_ring_aggint_qcaps_input { 5654*4882a593Smuzhiyun __le16 req_type; 5655*4882a593Smuzhiyun __le16 cmpl_ring; 5656*4882a593Smuzhiyun __le16 seq_id; 5657*4882a593Smuzhiyun __le16 target_id; 5658*4882a593Smuzhiyun __le64 resp_addr; 5659*4882a593Smuzhiyun }; 5660*4882a593Smuzhiyun 5661*4882a593Smuzhiyun /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ 5662*4882a593Smuzhiyun struct hwrm_ring_aggint_qcaps_output { 5663*4882a593Smuzhiyun __le16 error_code; 5664*4882a593Smuzhiyun __le16 req_type; 5665*4882a593Smuzhiyun __le16 seq_id; 5666*4882a593Smuzhiyun __le16 resp_len; 5667*4882a593Smuzhiyun __le32 cmpl_params; 5668*4882a593Smuzhiyun #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL 5669*4882a593Smuzhiyun #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL 5670*4882a593Smuzhiyun #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL 5671*4882a593Smuzhiyun #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL 5672*4882a593Smuzhiyun #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL 5673*4882a593Smuzhiyun #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL 5674*4882a593Smuzhiyun #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 5675*4882a593Smuzhiyun #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 5676*4882a593Smuzhiyun #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 5677*4882a593Smuzhiyun __le32 nq_params; 5678*4882a593Smuzhiyun #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 5679*4882a593Smuzhiyun __le16 num_cmpl_dma_aggr_min; 5680*4882a593Smuzhiyun __le16 num_cmpl_dma_aggr_max; 5681*4882a593Smuzhiyun __le16 num_cmpl_dma_aggr_during_int_min; 5682*4882a593Smuzhiyun __le16 num_cmpl_dma_aggr_during_int_max; 5683*4882a593Smuzhiyun __le16 cmpl_aggr_dma_tmr_min; 5684*4882a593Smuzhiyun __le16 cmpl_aggr_dma_tmr_max; 5685*4882a593Smuzhiyun __le16 cmpl_aggr_dma_tmr_during_int_min; 5686*4882a593Smuzhiyun __le16 cmpl_aggr_dma_tmr_during_int_max; 5687*4882a593Smuzhiyun __le16 int_lat_tmr_min_min; 5688*4882a593Smuzhiyun __le16 int_lat_tmr_min_max; 5689*4882a593Smuzhiyun __le16 int_lat_tmr_max_min; 5690*4882a593Smuzhiyun __le16 int_lat_tmr_max_max; 5691*4882a593Smuzhiyun __le16 num_cmpl_aggr_int_min; 5692*4882a593Smuzhiyun __le16 num_cmpl_aggr_int_max; 5693*4882a593Smuzhiyun __le16 timer_units; 5694*4882a593Smuzhiyun u8 unused_0[1]; 5695*4882a593Smuzhiyun u8 valid; 5696*4882a593Smuzhiyun }; 5697*4882a593Smuzhiyun 5698*4882a593Smuzhiyun /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 5699*4882a593Smuzhiyun struct hwrm_ring_cmpl_ring_qaggint_params_input { 5700*4882a593Smuzhiyun __le16 req_type; 5701*4882a593Smuzhiyun __le16 cmpl_ring; 5702*4882a593Smuzhiyun __le16 seq_id; 5703*4882a593Smuzhiyun __le16 target_id; 5704*4882a593Smuzhiyun __le64 resp_addr; 5705*4882a593Smuzhiyun __le16 ring_id; 5706*4882a593Smuzhiyun __le16 flags; 5707*4882a593Smuzhiyun #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL 5708*4882a593Smuzhiyun #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0 5709*4882a593Smuzhiyun #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 5710*4882a593Smuzhiyun u8 unused_0[4]; 5711*4882a593Smuzhiyun }; 5712*4882a593Smuzhiyun 5713*4882a593Smuzhiyun /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 5714*4882a593Smuzhiyun struct hwrm_ring_cmpl_ring_qaggint_params_output { 5715*4882a593Smuzhiyun __le16 error_code; 5716*4882a593Smuzhiyun __le16 req_type; 5717*4882a593Smuzhiyun __le16 seq_id; 5718*4882a593Smuzhiyun __le16 resp_len; 5719*4882a593Smuzhiyun __le16 flags; 5720*4882a593Smuzhiyun #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 5721*4882a593Smuzhiyun #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 5722*4882a593Smuzhiyun __le16 num_cmpl_dma_aggr; 5723*4882a593Smuzhiyun __le16 num_cmpl_dma_aggr_during_int; 5724*4882a593Smuzhiyun __le16 cmpl_aggr_dma_tmr; 5725*4882a593Smuzhiyun __le16 cmpl_aggr_dma_tmr_during_int; 5726*4882a593Smuzhiyun __le16 int_lat_tmr_min; 5727*4882a593Smuzhiyun __le16 int_lat_tmr_max; 5728*4882a593Smuzhiyun __le16 num_cmpl_aggr_int; 5729*4882a593Smuzhiyun u8 unused_0[7]; 5730*4882a593Smuzhiyun u8 valid; 5731*4882a593Smuzhiyun }; 5732*4882a593Smuzhiyun 5733*4882a593Smuzhiyun /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 5734*4882a593Smuzhiyun struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 5735*4882a593Smuzhiyun __le16 req_type; 5736*4882a593Smuzhiyun __le16 cmpl_ring; 5737*4882a593Smuzhiyun __le16 seq_id; 5738*4882a593Smuzhiyun __le16 target_id; 5739*4882a593Smuzhiyun __le64 resp_addr; 5740*4882a593Smuzhiyun __le16 ring_id; 5741*4882a593Smuzhiyun __le16 flags; 5742*4882a593Smuzhiyun #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 5743*4882a593Smuzhiyun #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 5744*4882a593Smuzhiyun #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 5745*4882a593Smuzhiyun __le16 num_cmpl_dma_aggr; 5746*4882a593Smuzhiyun __le16 num_cmpl_dma_aggr_during_int; 5747*4882a593Smuzhiyun __le16 cmpl_aggr_dma_tmr; 5748*4882a593Smuzhiyun __le16 cmpl_aggr_dma_tmr_during_int; 5749*4882a593Smuzhiyun __le16 int_lat_tmr_min; 5750*4882a593Smuzhiyun __le16 int_lat_tmr_max; 5751*4882a593Smuzhiyun __le16 num_cmpl_aggr_int; 5752*4882a593Smuzhiyun __le16 enables; 5753*4882a593Smuzhiyun #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL 5754*4882a593Smuzhiyun #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL 5755*4882a593Smuzhiyun #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL 5756*4882a593Smuzhiyun #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL 5757*4882a593Smuzhiyun #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL 5758*4882a593Smuzhiyun #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL 5759*4882a593Smuzhiyun u8 unused_0[4]; 5760*4882a593Smuzhiyun }; 5761*4882a593Smuzhiyun 5762*4882a593Smuzhiyun /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 5763*4882a593Smuzhiyun struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 5764*4882a593Smuzhiyun __le16 error_code; 5765*4882a593Smuzhiyun __le16 req_type; 5766*4882a593Smuzhiyun __le16 seq_id; 5767*4882a593Smuzhiyun __le16 resp_len; 5768*4882a593Smuzhiyun u8 unused_0[7]; 5769*4882a593Smuzhiyun u8 valid; 5770*4882a593Smuzhiyun }; 5771*4882a593Smuzhiyun 5772*4882a593Smuzhiyun /* hwrm_ring_grp_alloc_input (size:192b/24B) */ 5773*4882a593Smuzhiyun struct hwrm_ring_grp_alloc_input { 5774*4882a593Smuzhiyun __le16 req_type; 5775*4882a593Smuzhiyun __le16 cmpl_ring; 5776*4882a593Smuzhiyun __le16 seq_id; 5777*4882a593Smuzhiyun __le16 target_id; 5778*4882a593Smuzhiyun __le64 resp_addr; 5779*4882a593Smuzhiyun __le16 cr; 5780*4882a593Smuzhiyun __le16 rr; 5781*4882a593Smuzhiyun __le16 ar; 5782*4882a593Smuzhiyun __le16 sc; 5783*4882a593Smuzhiyun }; 5784*4882a593Smuzhiyun 5785*4882a593Smuzhiyun /* hwrm_ring_grp_alloc_output (size:128b/16B) */ 5786*4882a593Smuzhiyun struct hwrm_ring_grp_alloc_output { 5787*4882a593Smuzhiyun __le16 error_code; 5788*4882a593Smuzhiyun __le16 req_type; 5789*4882a593Smuzhiyun __le16 seq_id; 5790*4882a593Smuzhiyun __le16 resp_len; 5791*4882a593Smuzhiyun __le32 ring_group_id; 5792*4882a593Smuzhiyun u8 unused_0[3]; 5793*4882a593Smuzhiyun u8 valid; 5794*4882a593Smuzhiyun }; 5795*4882a593Smuzhiyun 5796*4882a593Smuzhiyun /* hwrm_ring_grp_free_input (size:192b/24B) */ 5797*4882a593Smuzhiyun struct hwrm_ring_grp_free_input { 5798*4882a593Smuzhiyun __le16 req_type; 5799*4882a593Smuzhiyun __le16 cmpl_ring; 5800*4882a593Smuzhiyun __le16 seq_id; 5801*4882a593Smuzhiyun __le16 target_id; 5802*4882a593Smuzhiyun __le64 resp_addr; 5803*4882a593Smuzhiyun __le32 ring_group_id; 5804*4882a593Smuzhiyun u8 unused_0[4]; 5805*4882a593Smuzhiyun }; 5806*4882a593Smuzhiyun 5807*4882a593Smuzhiyun /* hwrm_ring_grp_free_output (size:128b/16B) */ 5808*4882a593Smuzhiyun struct hwrm_ring_grp_free_output { 5809*4882a593Smuzhiyun __le16 error_code; 5810*4882a593Smuzhiyun __le16 req_type; 5811*4882a593Smuzhiyun __le16 seq_id; 5812*4882a593Smuzhiyun __le16 resp_len; 5813*4882a593Smuzhiyun u8 unused_0[7]; 5814*4882a593Smuzhiyun u8 valid; 5815*4882a593Smuzhiyun }; 5816*4882a593Smuzhiyun 5817*4882a593Smuzhiyun #define DEFAULT_FLOW_ID 0xFFFFFFFFUL 5818*4882a593Smuzhiyun #define ROCEV1_FLOW_ID 0xFFFFFFFEUL 5819*4882a593Smuzhiyun #define ROCEV2_FLOW_ID 0xFFFFFFFDUL 5820*4882a593Smuzhiyun #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL 5821*4882a593Smuzhiyun 5822*4882a593Smuzhiyun /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 5823*4882a593Smuzhiyun struct hwrm_cfa_l2_filter_alloc_input { 5824*4882a593Smuzhiyun __le16 req_type; 5825*4882a593Smuzhiyun __le16 cmpl_ring; 5826*4882a593Smuzhiyun __le16 seq_id; 5827*4882a593Smuzhiyun __le16 target_id; 5828*4882a593Smuzhiyun __le64 resp_addr; 5829*4882a593Smuzhiyun __le32 flags; 5830*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 5831*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 5832*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 5833*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 5834*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 5835*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 5836*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 5837*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL 5838*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4 5839*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4) 5840*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4) 5841*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4) 5842*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE 5843*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL 5844*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL 5845*4882a593Smuzhiyun __le32 enables; 5846*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 5847*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 5848*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 5849*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 5850*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 5851*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 5852*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 5853*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 5854*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 5855*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 5856*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 5857*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 5858*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 5859*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 5860*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 5861*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 5862*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 5863*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL 5864*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL 5865*4882a593Smuzhiyun u8 l2_addr[6]; 5866*4882a593Smuzhiyun u8 num_vlans; 5867*4882a593Smuzhiyun u8 t_num_vlans; 5868*4882a593Smuzhiyun u8 l2_addr_mask[6]; 5869*4882a593Smuzhiyun __le16 l2_ovlan; 5870*4882a593Smuzhiyun __le16 l2_ovlan_mask; 5871*4882a593Smuzhiyun __le16 l2_ivlan; 5872*4882a593Smuzhiyun __le16 l2_ivlan_mask; 5873*4882a593Smuzhiyun u8 unused_1[2]; 5874*4882a593Smuzhiyun u8 t_l2_addr[6]; 5875*4882a593Smuzhiyun u8 unused_2[2]; 5876*4882a593Smuzhiyun u8 t_l2_addr_mask[6]; 5877*4882a593Smuzhiyun __le16 t_l2_ovlan; 5878*4882a593Smuzhiyun __le16 t_l2_ovlan_mask; 5879*4882a593Smuzhiyun __le16 t_l2_ivlan; 5880*4882a593Smuzhiyun __le16 t_l2_ivlan_mask; 5881*4882a593Smuzhiyun u8 src_type; 5882*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 5883*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 5884*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 5885*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 5886*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 5887*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 5888*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 5889*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 5890*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 5891*4882a593Smuzhiyun u8 unused_3; 5892*4882a593Smuzhiyun __le32 src_id; 5893*4882a593Smuzhiyun u8 tunnel_type; 5894*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5895*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5896*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5897*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5898*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5899*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5900*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5901*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5902*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5903*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5904*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5905*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5906*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 5907*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5908*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5909*4882a593Smuzhiyun u8 unused_4; 5910*4882a593Smuzhiyun __le16 dst_id; 5911*4882a593Smuzhiyun __le16 mirror_vnic_id; 5912*4882a593Smuzhiyun u8 pri_hint; 5913*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 5914*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 5915*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 5916*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 5917*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 5918*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 5919*4882a593Smuzhiyun u8 unused_5; 5920*4882a593Smuzhiyun __le32 unused_6; 5921*4882a593Smuzhiyun __le64 l2_filter_id_hint; 5922*4882a593Smuzhiyun }; 5923*4882a593Smuzhiyun 5924*4882a593Smuzhiyun /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 5925*4882a593Smuzhiyun struct hwrm_cfa_l2_filter_alloc_output { 5926*4882a593Smuzhiyun __le16 error_code; 5927*4882a593Smuzhiyun __le16 req_type; 5928*4882a593Smuzhiyun __le16 seq_id; 5929*4882a593Smuzhiyun __le16 resp_len; 5930*4882a593Smuzhiyun __le64 l2_filter_id; 5931*4882a593Smuzhiyun __le32 flow_id; 5932*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 5933*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 5934*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 5935*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 5936*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 5937*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 5938*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 5939*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 5940*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 5941*4882a593Smuzhiyun #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 5942*4882a593Smuzhiyun u8 unused_0[3]; 5943*4882a593Smuzhiyun u8 valid; 5944*4882a593Smuzhiyun }; 5945*4882a593Smuzhiyun 5946*4882a593Smuzhiyun /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 5947*4882a593Smuzhiyun struct hwrm_cfa_l2_filter_free_input { 5948*4882a593Smuzhiyun __le16 req_type; 5949*4882a593Smuzhiyun __le16 cmpl_ring; 5950*4882a593Smuzhiyun __le16 seq_id; 5951*4882a593Smuzhiyun __le16 target_id; 5952*4882a593Smuzhiyun __le64 resp_addr; 5953*4882a593Smuzhiyun __le64 l2_filter_id; 5954*4882a593Smuzhiyun }; 5955*4882a593Smuzhiyun 5956*4882a593Smuzhiyun /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 5957*4882a593Smuzhiyun struct hwrm_cfa_l2_filter_free_output { 5958*4882a593Smuzhiyun __le16 error_code; 5959*4882a593Smuzhiyun __le16 req_type; 5960*4882a593Smuzhiyun __le16 seq_id; 5961*4882a593Smuzhiyun __le16 resp_len; 5962*4882a593Smuzhiyun u8 unused_0[7]; 5963*4882a593Smuzhiyun u8 valid; 5964*4882a593Smuzhiyun }; 5965*4882a593Smuzhiyun 5966*4882a593Smuzhiyun /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ 5967*4882a593Smuzhiyun struct hwrm_cfa_l2_filter_cfg_input { 5968*4882a593Smuzhiyun __le16 req_type; 5969*4882a593Smuzhiyun __le16 cmpl_ring; 5970*4882a593Smuzhiyun __le16 seq_id; 5971*4882a593Smuzhiyun __le16 target_id; 5972*4882a593Smuzhiyun __le64 resp_addr; 5973*4882a593Smuzhiyun __le32 flags; 5974*4882a593Smuzhiyun #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 5975*4882a593Smuzhiyun #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 5976*4882a593Smuzhiyun #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 5977*4882a593Smuzhiyun #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 5978*4882a593Smuzhiyun #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 5979*4882a593Smuzhiyun #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 5980*4882a593Smuzhiyun #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 5981*4882a593Smuzhiyun #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 5982*4882a593Smuzhiyun #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 5983*4882a593Smuzhiyun #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 5984*4882a593Smuzhiyun #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 5985*4882a593Smuzhiyun __le32 enables; 5986*4882a593Smuzhiyun #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 5987*4882a593Smuzhiyun #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 5988*4882a593Smuzhiyun __le64 l2_filter_id; 5989*4882a593Smuzhiyun __le32 dst_id; 5990*4882a593Smuzhiyun __le32 new_mirror_vnic_id; 5991*4882a593Smuzhiyun }; 5992*4882a593Smuzhiyun 5993*4882a593Smuzhiyun /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 5994*4882a593Smuzhiyun struct hwrm_cfa_l2_filter_cfg_output { 5995*4882a593Smuzhiyun __le16 error_code; 5996*4882a593Smuzhiyun __le16 req_type; 5997*4882a593Smuzhiyun __le16 seq_id; 5998*4882a593Smuzhiyun __le16 resp_len; 5999*4882a593Smuzhiyun u8 unused_0[7]; 6000*4882a593Smuzhiyun u8 valid; 6001*4882a593Smuzhiyun }; 6002*4882a593Smuzhiyun 6003*4882a593Smuzhiyun /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 6004*4882a593Smuzhiyun struct hwrm_cfa_l2_set_rx_mask_input { 6005*4882a593Smuzhiyun __le16 req_type; 6006*4882a593Smuzhiyun __le16 cmpl_ring; 6007*4882a593Smuzhiyun __le16 seq_id; 6008*4882a593Smuzhiyun __le16 target_id; 6009*4882a593Smuzhiyun __le64 resp_addr; 6010*4882a593Smuzhiyun __le32 vnic_id; 6011*4882a593Smuzhiyun __le32 mask; 6012*4882a593Smuzhiyun #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 6013*4882a593Smuzhiyun #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 6014*4882a593Smuzhiyun #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 6015*4882a593Smuzhiyun #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 6016*4882a593Smuzhiyun #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 6017*4882a593Smuzhiyun #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 6018*4882a593Smuzhiyun #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 6019*4882a593Smuzhiyun #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 6020*4882a593Smuzhiyun __le64 mc_tbl_addr; 6021*4882a593Smuzhiyun __le32 num_mc_entries; 6022*4882a593Smuzhiyun u8 unused_0[4]; 6023*4882a593Smuzhiyun __le64 vlan_tag_tbl_addr; 6024*4882a593Smuzhiyun __le32 num_vlan_tags; 6025*4882a593Smuzhiyun u8 unused_1[4]; 6026*4882a593Smuzhiyun }; 6027*4882a593Smuzhiyun 6028*4882a593Smuzhiyun /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 6029*4882a593Smuzhiyun struct hwrm_cfa_l2_set_rx_mask_output { 6030*4882a593Smuzhiyun __le16 error_code; 6031*4882a593Smuzhiyun __le16 req_type; 6032*4882a593Smuzhiyun __le16 seq_id; 6033*4882a593Smuzhiyun __le16 resp_len; 6034*4882a593Smuzhiyun u8 unused_0[7]; 6035*4882a593Smuzhiyun u8 valid; 6036*4882a593Smuzhiyun }; 6037*4882a593Smuzhiyun 6038*4882a593Smuzhiyun /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 6039*4882a593Smuzhiyun struct hwrm_cfa_l2_set_rx_mask_cmd_err { 6040*4882a593Smuzhiyun u8 code; 6041*4882a593Smuzhiyun #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 6042*4882a593Smuzhiyun #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 6043*4882a593Smuzhiyun #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 6044*4882a593Smuzhiyun u8 unused_0[7]; 6045*4882a593Smuzhiyun }; 6046*4882a593Smuzhiyun 6047*4882a593Smuzhiyun /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 6048*4882a593Smuzhiyun struct hwrm_cfa_tunnel_filter_alloc_input { 6049*4882a593Smuzhiyun __le16 req_type; 6050*4882a593Smuzhiyun __le16 cmpl_ring; 6051*4882a593Smuzhiyun __le16 seq_id; 6052*4882a593Smuzhiyun __le16 target_id; 6053*4882a593Smuzhiyun __le64 resp_addr; 6054*4882a593Smuzhiyun __le32 flags; 6055*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 6056*4882a593Smuzhiyun __le32 enables; 6057*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 6058*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 6059*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 6060*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 6061*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 6062*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 6063*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 6064*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 6065*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 6066*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 6067*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 6068*4882a593Smuzhiyun __le64 l2_filter_id; 6069*4882a593Smuzhiyun u8 l2_addr[6]; 6070*4882a593Smuzhiyun __le16 l2_ivlan; 6071*4882a593Smuzhiyun __le32 l3_addr[4]; 6072*4882a593Smuzhiyun __le32 t_l3_addr[4]; 6073*4882a593Smuzhiyun u8 l3_addr_type; 6074*4882a593Smuzhiyun u8 t_l3_addr_type; 6075*4882a593Smuzhiyun u8 tunnel_type; 6076*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6077*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6078*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6079*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6080*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6081*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6082*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6083*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6084*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6085*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6086*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6087*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6088*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6089*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6090*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6091*4882a593Smuzhiyun u8 tunnel_flags; 6092*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 6093*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 6094*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 6095*4882a593Smuzhiyun __le32 vni; 6096*4882a593Smuzhiyun __le32 dst_vnic_id; 6097*4882a593Smuzhiyun __le32 mirror_vnic_id; 6098*4882a593Smuzhiyun }; 6099*4882a593Smuzhiyun 6100*4882a593Smuzhiyun /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 6101*4882a593Smuzhiyun struct hwrm_cfa_tunnel_filter_alloc_output { 6102*4882a593Smuzhiyun __le16 error_code; 6103*4882a593Smuzhiyun __le16 req_type; 6104*4882a593Smuzhiyun __le16 seq_id; 6105*4882a593Smuzhiyun __le16 resp_len; 6106*4882a593Smuzhiyun __le64 tunnel_filter_id; 6107*4882a593Smuzhiyun __le32 flow_id; 6108*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6109*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6110*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6111*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6112*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6113*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 6114*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 6115*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 6116*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 6117*4882a593Smuzhiyun #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 6118*4882a593Smuzhiyun u8 unused_0[3]; 6119*4882a593Smuzhiyun u8 valid; 6120*4882a593Smuzhiyun }; 6121*4882a593Smuzhiyun 6122*4882a593Smuzhiyun /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 6123*4882a593Smuzhiyun struct hwrm_cfa_tunnel_filter_free_input { 6124*4882a593Smuzhiyun __le16 req_type; 6125*4882a593Smuzhiyun __le16 cmpl_ring; 6126*4882a593Smuzhiyun __le16 seq_id; 6127*4882a593Smuzhiyun __le16 target_id; 6128*4882a593Smuzhiyun __le64 resp_addr; 6129*4882a593Smuzhiyun __le64 tunnel_filter_id; 6130*4882a593Smuzhiyun }; 6131*4882a593Smuzhiyun 6132*4882a593Smuzhiyun /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 6133*4882a593Smuzhiyun struct hwrm_cfa_tunnel_filter_free_output { 6134*4882a593Smuzhiyun __le16 error_code; 6135*4882a593Smuzhiyun __le16 req_type; 6136*4882a593Smuzhiyun __le16 seq_id; 6137*4882a593Smuzhiyun __le16 resp_len; 6138*4882a593Smuzhiyun u8 unused_0[7]; 6139*4882a593Smuzhiyun u8 valid; 6140*4882a593Smuzhiyun }; 6141*4882a593Smuzhiyun 6142*4882a593Smuzhiyun /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 6143*4882a593Smuzhiyun struct hwrm_vxlan_ipv4_hdr { 6144*4882a593Smuzhiyun u8 ver_hlen; 6145*4882a593Smuzhiyun #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 6146*4882a593Smuzhiyun #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 6147*4882a593Smuzhiyun #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 6148*4882a593Smuzhiyun #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 6149*4882a593Smuzhiyun u8 tos; 6150*4882a593Smuzhiyun __be16 ip_id; 6151*4882a593Smuzhiyun __be16 flags_frag_offset; 6152*4882a593Smuzhiyun u8 ttl; 6153*4882a593Smuzhiyun u8 protocol; 6154*4882a593Smuzhiyun __be32 src_ip_addr; 6155*4882a593Smuzhiyun __be32 dest_ip_addr; 6156*4882a593Smuzhiyun }; 6157*4882a593Smuzhiyun 6158*4882a593Smuzhiyun /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 6159*4882a593Smuzhiyun struct hwrm_vxlan_ipv6_hdr { 6160*4882a593Smuzhiyun __be32 ver_tc_flow_label; 6161*4882a593Smuzhiyun #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 6162*4882a593Smuzhiyun #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 6163*4882a593Smuzhiyun #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 6164*4882a593Smuzhiyun #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 6165*4882a593Smuzhiyun #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 6166*4882a593Smuzhiyun #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 6167*4882a593Smuzhiyun #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 6168*4882a593Smuzhiyun __be16 payload_len; 6169*4882a593Smuzhiyun u8 next_hdr; 6170*4882a593Smuzhiyun u8 ttl; 6171*4882a593Smuzhiyun __be32 src_ip_addr[4]; 6172*4882a593Smuzhiyun __be32 dest_ip_addr[4]; 6173*4882a593Smuzhiyun }; 6174*4882a593Smuzhiyun 6175*4882a593Smuzhiyun /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ 6176*4882a593Smuzhiyun struct hwrm_cfa_encap_data_vxlan { 6177*4882a593Smuzhiyun u8 src_mac_addr[6]; 6178*4882a593Smuzhiyun __le16 unused_0; 6179*4882a593Smuzhiyun u8 dst_mac_addr[6]; 6180*4882a593Smuzhiyun u8 num_vlan_tags; 6181*4882a593Smuzhiyun u8 unused_1; 6182*4882a593Smuzhiyun __be16 ovlan_tpid; 6183*4882a593Smuzhiyun __be16 ovlan_tci; 6184*4882a593Smuzhiyun __be16 ivlan_tpid; 6185*4882a593Smuzhiyun __be16 ivlan_tci; 6186*4882a593Smuzhiyun __le32 l3[10]; 6187*4882a593Smuzhiyun #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 6188*4882a593Smuzhiyun #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 6189*4882a593Smuzhiyun #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 6190*4882a593Smuzhiyun #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 6191*4882a593Smuzhiyun __be16 src_port; 6192*4882a593Smuzhiyun __be16 dst_port; 6193*4882a593Smuzhiyun __be32 vni; 6194*4882a593Smuzhiyun u8 hdr_rsvd0[3]; 6195*4882a593Smuzhiyun u8 hdr_rsvd1; 6196*4882a593Smuzhiyun u8 hdr_flags; 6197*4882a593Smuzhiyun u8 unused[3]; 6198*4882a593Smuzhiyun }; 6199*4882a593Smuzhiyun 6200*4882a593Smuzhiyun /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 6201*4882a593Smuzhiyun struct hwrm_cfa_encap_record_alloc_input { 6202*4882a593Smuzhiyun __le16 req_type; 6203*4882a593Smuzhiyun __le16 cmpl_ring; 6204*4882a593Smuzhiyun __le16 seq_id; 6205*4882a593Smuzhiyun __le16 target_id; 6206*4882a593Smuzhiyun __le64 resp_addr; 6207*4882a593Smuzhiyun __le32 flags; 6208*4882a593Smuzhiyun #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 6209*4882a593Smuzhiyun #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL 6210*4882a593Smuzhiyun u8 encap_type; 6211*4882a593Smuzhiyun #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 6212*4882a593Smuzhiyun #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 6213*4882a593Smuzhiyun #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 6214*4882a593Smuzhiyun #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 6215*4882a593Smuzhiyun #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 6216*4882a593Smuzhiyun #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 6217*4882a593Smuzhiyun #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 6218*4882a593Smuzhiyun #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 6219*4882a593Smuzhiyun #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL 6220*4882a593Smuzhiyun #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL 6221*4882a593Smuzhiyun #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL 6222*4882a593Smuzhiyun #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL 6223*4882a593Smuzhiyun #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 6224*4882a593Smuzhiyun u8 unused_0[3]; 6225*4882a593Smuzhiyun __le32 encap_data[20]; 6226*4882a593Smuzhiyun }; 6227*4882a593Smuzhiyun 6228*4882a593Smuzhiyun /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 6229*4882a593Smuzhiyun struct hwrm_cfa_encap_record_alloc_output { 6230*4882a593Smuzhiyun __le16 error_code; 6231*4882a593Smuzhiyun __le16 req_type; 6232*4882a593Smuzhiyun __le16 seq_id; 6233*4882a593Smuzhiyun __le16 resp_len; 6234*4882a593Smuzhiyun __le32 encap_record_id; 6235*4882a593Smuzhiyun u8 unused_0[3]; 6236*4882a593Smuzhiyun u8 valid; 6237*4882a593Smuzhiyun }; 6238*4882a593Smuzhiyun 6239*4882a593Smuzhiyun /* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 6240*4882a593Smuzhiyun struct hwrm_cfa_encap_record_free_input { 6241*4882a593Smuzhiyun __le16 req_type; 6242*4882a593Smuzhiyun __le16 cmpl_ring; 6243*4882a593Smuzhiyun __le16 seq_id; 6244*4882a593Smuzhiyun __le16 target_id; 6245*4882a593Smuzhiyun __le64 resp_addr; 6246*4882a593Smuzhiyun __le32 encap_record_id; 6247*4882a593Smuzhiyun u8 unused_0[4]; 6248*4882a593Smuzhiyun }; 6249*4882a593Smuzhiyun 6250*4882a593Smuzhiyun /* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 6251*4882a593Smuzhiyun struct hwrm_cfa_encap_record_free_output { 6252*4882a593Smuzhiyun __le16 error_code; 6253*4882a593Smuzhiyun __le16 req_type; 6254*4882a593Smuzhiyun __le16 seq_id; 6255*4882a593Smuzhiyun __le16 resp_len; 6256*4882a593Smuzhiyun u8 unused_0[7]; 6257*4882a593Smuzhiyun u8 valid; 6258*4882a593Smuzhiyun }; 6259*4882a593Smuzhiyun 6260*4882a593Smuzhiyun /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ 6261*4882a593Smuzhiyun struct hwrm_cfa_ntuple_filter_alloc_input { 6262*4882a593Smuzhiyun __le16 req_type; 6263*4882a593Smuzhiyun __le16 cmpl_ring; 6264*4882a593Smuzhiyun __le16 seq_id; 6265*4882a593Smuzhiyun __le16 target_id; 6266*4882a593Smuzhiyun __le64 resp_addr; 6267*4882a593Smuzhiyun __le32 flags; 6268*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 6269*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 6270*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 6271*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL 6272*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY 0x10UL 6273*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX 0x20UL 6274*4882a593Smuzhiyun __le32 enables; 6275*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 6276*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 6277*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 6278*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 6279*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 6280*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 6281*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 6282*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 6283*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 6284*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 6285*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 6286*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 6287*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 6288*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 6289*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 6290*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 6291*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 6292*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 6293*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 6294*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL 6295*4882a593Smuzhiyun __le64 l2_filter_id; 6296*4882a593Smuzhiyun u8 src_macaddr[6]; 6297*4882a593Smuzhiyun __be16 ethertype; 6298*4882a593Smuzhiyun u8 ip_addr_type; 6299*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 6300*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 6301*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 6302*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 6303*4882a593Smuzhiyun u8 ip_protocol; 6304*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 6305*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 6306*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 6307*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 6308*4882a593Smuzhiyun __le16 dst_id; 6309*4882a593Smuzhiyun __le16 mirror_vnic_id; 6310*4882a593Smuzhiyun u8 tunnel_type; 6311*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6312*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6313*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6314*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6315*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6316*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6317*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6318*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6319*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6320*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6321*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6322*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6323*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6324*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6325*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6326*4882a593Smuzhiyun u8 pri_hint; 6327*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 6328*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 6329*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 6330*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 6331*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 6332*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 6333*4882a593Smuzhiyun __be32 src_ipaddr[4]; 6334*4882a593Smuzhiyun __be32 src_ipaddr_mask[4]; 6335*4882a593Smuzhiyun __be32 dst_ipaddr[4]; 6336*4882a593Smuzhiyun __be32 dst_ipaddr_mask[4]; 6337*4882a593Smuzhiyun __be16 src_port; 6338*4882a593Smuzhiyun __be16 src_port_mask; 6339*4882a593Smuzhiyun __be16 dst_port; 6340*4882a593Smuzhiyun __be16 dst_port_mask; 6341*4882a593Smuzhiyun __le64 ntuple_filter_id_hint; 6342*4882a593Smuzhiyun }; 6343*4882a593Smuzhiyun 6344*4882a593Smuzhiyun /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 6345*4882a593Smuzhiyun struct hwrm_cfa_ntuple_filter_alloc_output { 6346*4882a593Smuzhiyun __le16 error_code; 6347*4882a593Smuzhiyun __le16 req_type; 6348*4882a593Smuzhiyun __le16 seq_id; 6349*4882a593Smuzhiyun __le16 resp_len; 6350*4882a593Smuzhiyun __le64 ntuple_filter_id; 6351*4882a593Smuzhiyun __le32 flow_id; 6352*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6353*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6354*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6355*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6356*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6357*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 6358*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 6359*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 6360*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 6361*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 6362*4882a593Smuzhiyun u8 unused_0[3]; 6363*4882a593Smuzhiyun u8 valid; 6364*4882a593Smuzhiyun }; 6365*4882a593Smuzhiyun 6366*4882a593Smuzhiyun /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 6367*4882a593Smuzhiyun struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 6368*4882a593Smuzhiyun u8 code; 6369*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 6370*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 6371*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 6372*4882a593Smuzhiyun u8 unused_0[7]; 6373*4882a593Smuzhiyun }; 6374*4882a593Smuzhiyun 6375*4882a593Smuzhiyun /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 6376*4882a593Smuzhiyun struct hwrm_cfa_ntuple_filter_free_input { 6377*4882a593Smuzhiyun __le16 req_type; 6378*4882a593Smuzhiyun __le16 cmpl_ring; 6379*4882a593Smuzhiyun __le16 seq_id; 6380*4882a593Smuzhiyun __le16 target_id; 6381*4882a593Smuzhiyun __le64 resp_addr; 6382*4882a593Smuzhiyun __le64 ntuple_filter_id; 6383*4882a593Smuzhiyun }; 6384*4882a593Smuzhiyun 6385*4882a593Smuzhiyun /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 6386*4882a593Smuzhiyun struct hwrm_cfa_ntuple_filter_free_output { 6387*4882a593Smuzhiyun __le16 error_code; 6388*4882a593Smuzhiyun __le16 req_type; 6389*4882a593Smuzhiyun __le16 seq_id; 6390*4882a593Smuzhiyun __le16 resp_len; 6391*4882a593Smuzhiyun u8 unused_0[7]; 6392*4882a593Smuzhiyun u8 valid; 6393*4882a593Smuzhiyun }; 6394*4882a593Smuzhiyun 6395*4882a593Smuzhiyun /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 6396*4882a593Smuzhiyun struct hwrm_cfa_ntuple_filter_cfg_input { 6397*4882a593Smuzhiyun __le16 req_type; 6398*4882a593Smuzhiyun __le16 cmpl_ring; 6399*4882a593Smuzhiyun __le16 seq_id; 6400*4882a593Smuzhiyun __le16 target_id; 6401*4882a593Smuzhiyun __le64 resp_addr; 6402*4882a593Smuzhiyun __le32 enables; 6403*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 6404*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 6405*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 6406*4882a593Smuzhiyun __le32 flags; 6407*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL 6408*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL 6409*4882a593Smuzhiyun __le64 ntuple_filter_id; 6410*4882a593Smuzhiyun __le32 new_dst_id; 6411*4882a593Smuzhiyun __le32 new_mirror_vnic_id; 6412*4882a593Smuzhiyun __le16 new_meter_instance_id; 6413*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 6414*4882a593Smuzhiyun #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 6415*4882a593Smuzhiyun u8 unused_1[6]; 6416*4882a593Smuzhiyun }; 6417*4882a593Smuzhiyun 6418*4882a593Smuzhiyun /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 6419*4882a593Smuzhiyun struct hwrm_cfa_ntuple_filter_cfg_output { 6420*4882a593Smuzhiyun __le16 error_code; 6421*4882a593Smuzhiyun __le16 req_type; 6422*4882a593Smuzhiyun __le16 seq_id; 6423*4882a593Smuzhiyun __le16 resp_len; 6424*4882a593Smuzhiyun u8 unused_0[7]; 6425*4882a593Smuzhiyun u8 valid; 6426*4882a593Smuzhiyun }; 6427*4882a593Smuzhiyun 6428*4882a593Smuzhiyun /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 6429*4882a593Smuzhiyun struct hwrm_cfa_decap_filter_alloc_input { 6430*4882a593Smuzhiyun __le16 req_type; 6431*4882a593Smuzhiyun __le16 cmpl_ring; 6432*4882a593Smuzhiyun __le16 seq_id; 6433*4882a593Smuzhiyun __le16 target_id; 6434*4882a593Smuzhiyun __le64 resp_addr; 6435*4882a593Smuzhiyun __le32 flags; 6436*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 6437*4882a593Smuzhiyun __le32 enables; 6438*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 6439*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 6440*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 6441*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 6442*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 6443*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 6444*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 6445*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 6446*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 6447*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 6448*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 6449*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 6450*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 6451*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 6452*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 6453*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 6454*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 6455*4882a593Smuzhiyun __be32 tunnel_id; 6456*4882a593Smuzhiyun u8 tunnel_type; 6457*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6458*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6459*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6460*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6461*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6462*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6463*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6464*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6465*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6466*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6467*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6468*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6469*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6470*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6471*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6472*4882a593Smuzhiyun u8 unused_0; 6473*4882a593Smuzhiyun __le16 unused_1; 6474*4882a593Smuzhiyun u8 src_macaddr[6]; 6475*4882a593Smuzhiyun u8 unused_2[2]; 6476*4882a593Smuzhiyun u8 dst_macaddr[6]; 6477*4882a593Smuzhiyun __be16 ovlan_vid; 6478*4882a593Smuzhiyun __be16 ivlan_vid; 6479*4882a593Smuzhiyun __be16 t_ovlan_vid; 6480*4882a593Smuzhiyun __be16 t_ivlan_vid; 6481*4882a593Smuzhiyun __be16 ethertype; 6482*4882a593Smuzhiyun u8 ip_addr_type; 6483*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 6484*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 6485*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 6486*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 6487*4882a593Smuzhiyun u8 ip_protocol; 6488*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 6489*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 6490*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 6491*4882a593Smuzhiyun #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 6492*4882a593Smuzhiyun __le16 unused_3; 6493*4882a593Smuzhiyun __le32 unused_4; 6494*4882a593Smuzhiyun __be32 src_ipaddr[4]; 6495*4882a593Smuzhiyun __be32 dst_ipaddr[4]; 6496*4882a593Smuzhiyun __be16 src_port; 6497*4882a593Smuzhiyun __be16 dst_port; 6498*4882a593Smuzhiyun __le16 dst_id; 6499*4882a593Smuzhiyun __le16 l2_ctxt_ref_id; 6500*4882a593Smuzhiyun }; 6501*4882a593Smuzhiyun 6502*4882a593Smuzhiyun /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 6503*4882a593Smuzhiyun struct hwrm_cfa_decap_filter_alloc_output { 6504*4882a593Smuzhiyun __le16 error_code; 6505*4882a593Smuzhiyun __le16 req_type; 6506*4882a593Smuzhiyun __le16 seq_id; 6507*4882a593Smuzhiyun __le16 resp_len; 6508*4882a593Smuzhiyun __le32 decap_filter_id; 6509*4882a593Smuzhiyun u8 unused_0[3]; 6510*4882a593Smuzhiyun u8 valid; 6511*4882a593Smuzhiyun }; 6512*4882a593Smuzhiyun 6513*4882a593Smuzhiyun /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 6514*4882a593Smuzhiyun struct hwrm_cfa_decap_filter_free_input { 6515*4882a593Smuzhiyun __le16 req_type; 6516*4882a593Smuzhiyun __le16 cmpl_ring; 6517*4882a593Smuzhiyun __le16 seq_id; 6518*4882a593Smuzhiyun __le16 target_id; 6519*4882a593Smuzhiyun __le64 resp_addr; 6520*4882a593Smuzhiyun __le32 decap_filter_id; 6521*4882a593Smuzhiyun u8 unused_0[4]; 6522*4882a593Smuzhiyun }; 6523*4882a593Smuzhiyun 6524*4882a593Smuzhiyun /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 6525*4882a593Smuzhiyun struct hwrm_cfa_decap_filter_free_output { 6526*4882a593Smuzhiyun __le16 error_code; 6527*4882a593Smuzhiyun __le16 req_type; 6528*4882a593Smuzhiyun __le16 seq_id; 6529*4882a593Smuzhiyun __le16 resp_len; 6530*4882a593Smuzhiyun u8 unused_0[7]; 6531*4882a593Smuzhiyun u8 valid; 6532*4882a593Smuzhiyun }; 6533*4882a593Smuzhiyun 6534*4882a593Smuzhiyun /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 6535*4882a593Smuzhiyun struct hwrm_cfa_flow_alloc_input { 6536*4882a593Smuzhiyun __le16 req_type; 6537*4882a593Smuzhiyun __le16 cmpl_ring; 6538*4882a593Smuzhiyun __le16 seq_id; 6539*4882a593Smuzhiyun __le16 target_id; 6540*4882a593Smuzhiyun __le64 resp_addr; 6541*4882a593Smuzhiyun __le16 flags; 6542*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 6543*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 6544*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 6545*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 6546*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 6547*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 6548*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 6549*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 6550*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 6551*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 6552*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 6553*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 6554*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 6555*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 6556*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 6557*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 6558*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL 6559*4882a593Smuzhiyun __le16 src_fid; 6560*4882a593Smuzhiyun __le32 tunnel_handle; 6561*4882a593Smuzhiyun __le16 action_flags; 6562*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 6563*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 6564*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 6565*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 6566*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 6567*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 6568*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 6569*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 6570*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 6571*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 6572*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 6573*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL 6574*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL 6575*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL 6576*4882a593Smuzhiyun __le16 dst_fid; 6577*4882a593Smuzhiyun __be16 l2_rewrite_vlan_tpid; 6578*4882a593Smuzhiyun __be16 l2_rewrite_vlan_tci; 6579*4882a593Smuzhiyun __le16 act_meter_id; 6580*4882a593Smuzhiyun __le16 ref_flow_handle; 6581*4882a593Smuzhiyun __be16 ethertype; 6582*4882a593Smuzhiyun __be16 outer_vlan_tci; 6583*4882a593Smuzhiyun __be16 dmac[3]; 6584*4882a593Smuzhiyun __be16 inner_vlan_tci; 6585*4882a593Smuzhiyun __be16 smac[3]; 6586*4882a593Smuzhiyun u8 ip_dst_mask_len; 6587*4882a593Smuzhiyun u8 ip_src_mask_len; 6588*4882a593Smuzhiyun __be32 ip_dst[4]; 6589*4882a593Smuzhiyun __be32 ip_src[4]; 6590*4882a593Smuzhiyun __be16 l4_src_port; 6591*4882a593Smuzhiyun __be16 l4_src_port_mask; 6592*4882a593Smuzhiyun __be16 l4_dst_port; 6593*4882a593Smuzhiyun __be16 l4_dst_port_mask; 6594*4882a593Smuzhiyun __be32 nat_ip_address[4]; 6595*4882a593Smuzhiyun __be16 l2_rewrite_dmac[3]; 6596*4882a593Smuzhiyun __be16 nat_port; 6597*4882a593Smuzhiyun __be16 l2_rewrite_smac[3]; 6598*4882a593Smuzhiyun u8 ip_proto; 6599*4882a593Smuzhiyun u8 tunnel_type; 6600*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6601*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6602*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6603*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6604*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6605*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6606*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6607*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6608*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6609*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6610*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6611*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6612*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6613*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6614*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6615*4882a593Smuzhiyun }; 6616*4882a593Smuzhiyun 6617*4882a593Smuzhiyun /* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 6618*4882a593Smuzhiyun struct hwrm_cfa_flow_alloc_output { 6619*4882a593Smuzhiyun __le16 error_code; 6620*4882a593Smuzhiyun __le16 req_type; 6621*4882a593Smuzhiyun __le16 seq_id; 6622*4882a593Smuzhiyun __le16 resp_len; 6623*4882a593Smuzhiyun __le16 flow_handle; 6624*4882a593Smuzhiyun u8 unused_0[2]; 6625*4882a593Smuzhiyun __le32 flow_id; 6626*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6627*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6628*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6629*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6630*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6631*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT 6632*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 6633*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 6634*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 6635*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX 6636*4882a593Smuzhiyun __le64 ext_flow_handle; 6637*4882a593Smuzhiyun __le32 flow_counter_id; 6638*4882a593Smuzhiyun u8 unused_1[3]; 6639*4882a593Smuzhiyun u8 valid; 6640*4882a593Smuzhiyun }; 6641*4882a593Smuzhiyun 6642*4882a593Smuzhiyun /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ 6643*4882a593Smuzhiyun struct hwrm_cfa_flow_alloc_cmd_err { 6644*4882a593Smuzhiyun u8 code; 6645*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 6646*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL 6647*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL 6648*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL 6649*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL 6650*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL 6651*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL 6652*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL 6653*4882a593Smuzhiyun #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 6654*4882a593Smuzhiyun u8 unused_0[7]; 6655*4882a593Smuzhiyun }; 6656*4882a593Smuzhiyun 6657*4882a593Smuzhiyun /* hwrm_cfa_flow_free_input (size:256b/32B) */ 6658*4882a593Smuzhiyun struct hwrm_cfa_flow_free_input { 6659*4882a593Smuzhiyun __le16 req_type; 6660*4882a593Smuzhiyun __le16 cmpl_ring; 6661*4882a593Smuzhiyun __le16 seq_id; 6662*4882a593Smuzhiyun __le16 target_id; 6663*4882a593Smuzhiyun __le64 resp_addr; 6664*4882a593Smuzhiyun __le16 flow_handle; 6665*4882a593Smuzhiyun __le16 unused_0; 6666*4882a593Smuzhiyun __le32 flow_counter_id; 6667*4882a593Smuzhiyun __le64 ext_flow_handle; 6668*4882a593Smuzhiyun }; 6669*4882a593Smuzhiyun 6670*4882a593Smuzhiyun /* hwrm_cfa_flow_free_output (size:256b/32B) */ 6671*4882a593Smuzhiyun struct hwrm_cfa_flow_free_output { 6672*4882a593Smuzhiyun __le16 error_code; 6673*4882a593Smuzhiyun __le16 req_type; 6674*4882a593Smuzhiyun __le16 seq_id; 6675*4882a593Smuzhiyun __le16 resp_len; 6676*4882a593Smuzhiyun __le64 packet; 6677*4882a593Smuzhiyun __le64 byte; 6678*4882a593Smuzhiyun u8 unused_0[7]; 6679*4882a593Smuzhiyun u8 valid; 6680*4882a593Smuzhiyun }; 6681*4882a593Smuzhiyun 6682*4882a593Smuzhiyun /* hwrm_cfa_flow_info_input (size:256b/32B) */ 6683*4882a593Smuzhiyun struct hwrm_cfa_flow_info_input { 6684*4882a593Smuzhiyun __le16 req_type; 6685*4882a593Smuzhiyun __le16 cmpl_ring; 6686*4882a593Smuzhiyun __le16 seq_id; 6687*4882a593Smuzhiyun __le16 target_id; 6688*4882a593Smuzhiyun __le64 resp_addr; 6689*4882a593Smuzhiyun __le16 flow_handle; 6690*4882a593Smuzhiyun #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL 6691*4882a593Smuzhiyun #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT 0 6692*4882a593Smuzhiyun #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL 6693*4882a593Smuzhiyun #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL 6694*4882a593Smuzhiyun #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL 6695*4882a593Smuzhiyun #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL 6696*4882a593Smuzhiyun u8 unused_0[6]; 6697*4882a593Smuzhiyun __le64 ext_flow_handle; 6698*4882a593Smuzhiyun }; 6699*4882a593Smuzhiyun 6700*4882a593Smuzhiyun /* hwrm_cfa_flow_info_output (size:5632b/704B) */ 6701*4882a593Smuzhiyun struct hwrm_cfa_flow_info_output { 6702*4882a593Smuzhiyun __le16 error_code; 6703*4882a593Smuzhiyun __le16 req_type; 6704*4882a593Smuzhiyun __le16 seq_id; 6705*4882a593Smuzhiyun __le16 resp_len; 6706*4882a593Smuzhiyun u8 flags; 6707*4882a593Smuzhiyun #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL 6708*4882a593Smuzhiyun #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL 6709*4882a593Smuzhiyun u8 profile; 6710*4882a593Smuzhiyun __le16 src_fid; 6711*4882a593Smuzhiyun __le16 dst_fid; 6712*4882a593Smuzhiyun __le16 l2_ctxt_id; 6713*4882a593Smuzhiyun __le64 em_info; 6714*4882a593Smuzhiyun __le64 tcam_info; 6715*4882a593Smuzhiyun __le64 vfp_tcam_info; 6716*4882a593Smuzhiyun __le16 ar_id; 6717*4882a593Smuzhiyun __le16 flow_handle; 6718*4882a593Smuzhiyun __le32 tunnel_handle; 6719*4882a593Smuzhiyun __le16 flow_timer; 6720*4882a593Smuzhiyun u8 unused_0[6]; 6721*4882a593Smuzhiyun __le32 flow_key_data[130]; 6722*4882a593Smuzhiyun __le32 flow_action_info[30]; 6723*4882a593Smuzhiyun u8 unused_1[7]; 6724*4882a593Smuzhiyun u8 valid; 6725*4882a593Smuzhiyun }; 6726*4882a593Smuzhiyun 6727*4882a593Smuzhiyun /* hwrm_cfa_flow_stats_input (size:640b/80B) */ 6728*4882a593Smuzhiyun struct hwrm_cfa_flow_stats_input { 6729*4882a593Smuzhiyun __le16 req_type; 6730*4882a593Smuzhiyun __le16 cmpl_ring; 6731*4882a593Smuzhiyun __le16 seq_id; 6732*4882a593Smuzhiyun __le16 target_id; 6733*4882a593Smuzhiyun __le64 resp_addr; 6734*4882a593Smuzhiyun __le16 num_flows; 6735*4882a593Smuzhiyun __le16 flow_handle_0; 6736*4882a593Smuzhiyun __le16 flow_handle_1; 6737*4882a593Smuzhiyun __le16 flow_handle_2; 6738*4882a593Smuzhiyun __le16 flow_handle_3; 6739*4882a593Smuzhiyun __le16 flow_handle_4; 6740*4882a593Smuzhiyun __le16 flow_handle_5; 6741*4882a593Smuzhiyun __le16 flow_handle_6; 6742*4882a593Smuzhiyun __le16 flow_handle_7; 6743*4882a593Smuzhiyun __le16 flow_handle_8; 6744*4882a593Smuzhiyun __le16 flow_handle_9; 6745*4882a593Smuzhiyun u8 unused_0[2]; 6746*4882a593Smuzhiyun __le32 flow_id_0; 6747*4882a593Smuzhiyun __le32 flow_id_1; 6748*4882a593Smuzhiyun __le32 flow_id_2; 6749*4882a593Smuzhiyun __le32 flow_id_3; 6750*4882a593Smuzhiyun __le32 flow_id_4; 6751*4882a593Smuzhiyun __le32 flow_id_5; 6752*4882a593Smuzhiyun __le32 flow_id_6; 6753*4882a593Smuzhiyun __le32 flow_id_7; 6754*4882a593Smuzhiyun __le32 flow_id_8; 6755*4882a593Smuzhiyun __le32 flow_id_9; 6756*4882a593Smuzhiyun }; 6757*4882a593Smuzhiyun 6758*4882a593Smuzhiyun /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 6759*4882a593Smuzhiyun struct hwrm_cfa_flow_stats_output { 6760*4882a593Smuzhiyun __le16 error_code; 6761*4882a593Smuzhiyun __le16 req_type; 6762*4882a593Smuzhiyun __le16 seq_id; 6763*4882a593Smuzhiyun __le16 resp_len; 6764*4882a593Smuzhiyun __le64 packet_0; 6765*4882a593Smuzhiyun __le64 packet_1; 6766*4882a593Smuzhiyun __le64 packet_2; 6767*4882a593Smuzhiyun __le64 packet_3; 6768*4882a593Smuzhiyun __le64 packet_4; 6769*4882a593Smuzhiyun __le64 packet_5; 6770*4882a593Smuzhiyun __le64 packet_6; 6771*4882a593Smuzhiyun __le64 packet_7; 6772*4882a593Smuzhiyun __le64 packet_8; 6773*4882a593Smuzhiyun __le64 packet_9; 6774*4882a593Smuzhiyun __le64 byte_0; 6775*4882a593Smuzhiyun __le64 byte_1; 6776*4882a593Smuzhiyun __le64 byte_2; 6777*4882a593Smuzhiyun __le64 byte_3; 6778*4882a593Smuzhiyun __le64 byte_4; 6779*4882a593Smuzhiyun __le64 byte_5; 6780*4882a593Smuzhiyun __le64 byte_6; 6781*4882a593Smuzhiyun __le64 byte_7; 6782*4882a593Smuzhiyun __le64 byte_8; 6783*4882a593Smuzhiyun __le64 byte_9; 6784*4882a593Smuzhiyun u8 unused_0[7]; 6785*4882a593Smuzhiyun u8 valid; 6786*4882a593Smuzhiyun }; 6787*4882a593Smuzhiyun 6788*4882a593Smuzhiyun /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 6789*4882a593Smuzhiyun struct hwrm_cfa_vfr_alloc_input { 6790*4882a593Smuzhiyun __le16 req_type; 6791*4882a593Smuzhiyun __le16 cmpl_ring; 6792*4882a593Smuzhiyun __le16 seq_id; 6793*4882a593Smuzhiyun __le16 target_id; 6794*4882a593Smuzhiyun __le64 resp_addr; 6795*4882a593Smuzhiyun __le16 vf_id; 6796*4882a593Smuzhiyun __le16 reserved; 6797*4882a593Smuzhiyun u8 unused_0[4]; 6798*4882a593Smuzhiyun char vfr_name[32]; 6799*4882a593Smuzhiyun }; 6800*4882a593Smuzhiyun 6801*4882a593Smuzhiyun /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 6802*4882a593Smuzhiyun struct hwrm_cfa_vfr_alloc_output { 6803*4882a593Smuzhiyun __le16 error_code; 6804*4882a593Smuzhiyun __le16 req_type; 6805*4882a593Smuzhiyun __le16 seq_id; 6806*4882a593Smuzhiyun __le16 resp_len; 6807*4882a593Smuzhiyun __le16 rx_cfa_code; 6808*4882a593Smuzhiyun __le16 tx_cfa_action; 6809*4882a593Smuzhiyun u8 unused_0[3]; 6810*4882a593Smuzhiyun u8 valid; 6811*4882a593Smuzhiyun }; 6812*4882a593Smuzhiyun 6813*4882a593Smuzhiyun /* hwrm_cfa_vfr_free_input (size:448b/56B) */ 6814*4882a593Smuzhiyun struct hwrm_cfa_vfr_free_input { 6815*4882a593Smuzhiyun __le16 req_type; 6816*4882a593Smuzhiyun __le16 cmpl_ring; 6817*4882a593Smuzhiyun __le16 seq_id; 6818*4882a593Smuzhiyun __le16 target_id; 6819*4882a593Smuzhiyun __le64 resp_addr; 6820*4882a593Smuzhiyun char vfr_name[32]; 6821*4882a593Smuzhiyun __le16 vf_id; 6822*4882a593Smuzhiyun __le16 reserved; 6823*4882a593Smuzhiyun u8 unused_0[4]; 6824*4882a593Smuzhiyun }; 6825*4882a593Smuzhiyun 6826*4882a593Smuzhiyun /* hwrm_cfa_vfr_free_output (size:128b/16B) */ 6827*4882a593Smuzhiyun struct hwrm_cfa_vfr_free_output { 6828*4882a593Smuzhiyun __le16 error_code; 6829*4882a593Smuzhiyun __le16 req_type; 6830*4882a593Smuzhiyun __le16 seq_id; 6831*4882a593Smuzhiyun __le16 resp_len; 6832*4882a593Smuzhiyun u8 unused_0[7]; 6833*4882a593Smuzhiyun u8 valid; 6834*4882a593Smuzhiyun }; 6835*4882a593Smuzhiyun 6836*4882a593Smuzhiyun /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ 6837*4882a593Smuzhiyun struct hwrm_cfa_eem_qcaps_input { 6838*4882a593Smuzhiyun __le16 req_type; 6839*4882a593Smuzhiyun __le16 cmpl_ring; 6840*4882a593Smuzhiyun __le16 seq_id; 6841*4882a593Smuzhiyun __le16 target_id; 6842*4882a593Smuzhiyun __le64 resp_addr; 6843*4882a593Smuzhiyun __le32 flags; 6844*4882a593Smuzhiyun #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL 6845*4882a593Smuzhiyun #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL 6846*4882a593Smuzhiyun #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 6847*4882a593Smuzhiyun __le32 unused_0; 6848*4882a593Smuzhiyun }; 6849*4882a593Smuzhiyun 6850*4882a593Smuzhiyun /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ 6851*4882a593Smuzhiyun struct hwrm_cfa_eem_qcaps_output { 6852*4882a593Smuzhiyun __le16 error_code; 6853*4882a593Smuzhiyun __le16 req_type; 6854*4882a593Smuzhiyun __le16 seq_id; 6855*4882a593Smuzhiyun __le16 resp_len; 6856*4882a593Smuzhiyun __le32 flags; 6857*4882a593Smuzhiyun #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL 6858*4882a593Smuzhiyun #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL 6859*4882a593Smuzhiyun #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL 6860*4882a593Smuzhiyun #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL 6861*4882a593Smuzhiyun __le32 unused_0; 6862*4882a593Smuzhiyun __le32 supported; 6863*4882a593Smuzhiyun #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL 6864*4882a593Smuzhiyun #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL 6865*4882a593Smuzhiyun #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL 6866*4882a593Smuzhiyun #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL 6867*4882a593Smuzhiyun #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL 6868*4882a593Smuzhiyun __le32 max_entries_supported; 6869*4882a593Smuzhiyun __le16 key_entry_size; 6870*4882a593Smuzhiyun __le16 record_entry_size; 6871*4882a593Smuzhiyun __le16 efc_entry_size; 6872*4882a593Smuzhiyun __le16 fid_entry_size; 6873*4882a593Smuzhiyun u8 unused_1[7]; 6874*4882a593Smuzhiyun u8 valid; 6875*4882a593Smuzhiyun }; 6876*4882a593Smuzhiyun 6877*4882a593Smuzhiyun /* hwrm_cfa_eem_cfg_input (size:384b/48B) */ 6878*4882a593Smuzhiyun struct hwrm_cfa_eem_cfg_input { 6879*4882a593Smuzhiyun __le16 req_type; 6880*4882a593Smuzhiyun __le16 cmpl_ring; 6881*4882a593Smuzhiyun __le16 seq_id; 6882*4882a593Smuzhiyun __le16 target_id; 6883*4882a593Smuzhiyun __le64 resp_addr; 6884*4882a593Smuzhiyun __le32 flags; 6885*4882a593Smuzhiyun #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL 6886*4882a593Smuzhiyun #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL 6887*4882a593Smuzhiyun #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 6888*4882a593Smuzhiyun #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL 6889*4882a593Smuzhiyun __le16 group_id; 6890*4882a593Smuzhiyun __le16 unused_0; 6891*4882a593Smuzhiyun __le32 num_entries; 6892*4882a593Smuzhiyun __le32 unused_1; 6893*4882a593Smuzhiyun __le16 key0_ctx_id; 6894*4882a593Smuzhiyun __le16 key1_ctx_id; 6895*4882a593Smuzhiyun __le16 record_ctx_id; 6896*4882a593Smuzhiyun __le16 efc_ctx_id; 6897*4882a593Smuzhiyun __le16 fid_ctx_id; 6898*4882a593Smuzhiyun __le16 unused_2; 6899*4882a593Smuzhiyun __le32 unused_3; 6900*4882a593Smuzhiyun }; 6901*4882a593Smuzhiyun 6902*4882a593Smuzhiyun /* hwrm_cfa_eem_cfg_output (size:128b/16B) */ 6903*4882a593Smuzhiyun struct hwrm_cfa_eem_cfg_output { 6904*4882a593Smuzhiyun __le16 error_code; 6905*4882a593Smuzhiyun __le16 req_type; 6906*4882a593Smuzhiyun __le16 seq_id; 6907*4882a593Smuzhiyun __le16 resp_len; 6908*4882a593Smuzhiyun u8 unused_0[7]; 6909*4882a593Smuzhiyun u8 valid; 6910*4882a593Smuzhiyun }; 6911*4882a593Smuzhiyun 6912*4882a593Smuzhiyun /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ 6913*4882a593Smuzhiyun struct hwrm_cfa_eem_qcfg_input { 6914*4882a593Smuzhiyun __le16 req_type; 6915*4882a593Smuzhiyun __le16 cmpl_ring; 6916*4882a593Smuzhiyun __le16 seq_id; 6917*4882a593Smuzhiyun __le16 target_id; 6918*4882a593Smuzhiyun __le64 resp_addr; 6919*4882a593Smuzhiyun __le32 flags; 6920*4882a593Smuzhiyun #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL 6921*4882a593Smuzhiyun #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL 6922*4882a593Smuzhiyun __le32 unused_0; 6923*4882a593Smuzhiyun }; 6924*4882a593Smuzhiyun 6925*4882a593Smuzhiyun /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ 6926*4882a593Smuzhiyun struct hwrm_cfa_eem_qcfg_output { 6927*4882a593Smuzhiyun __le16 error_code; 6928*4882a593Smuzhiyun __le16 req_type; 6929*4882a593Smuzhiyun __le16 seq_id; 6930*4882a593Smuzhiyun __le16 resp_len; 6931*4882a593Smuzhiyun __le32 flags; 6932*4882a593Smuzhiyun #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL 6933*4882a593Smuzhiyun #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL 6934*4882a593Smuzhiyun #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL 6935*4882a593Smuzhiyun __le32 num_entries; 6936*4882a593Smuzhiyun __le16 key0_ctx_id; 6937*4882a593Smuzhiyun __le16 key1_ctx_id; 6938*4882a593Smuzhiyun __le16 record_ctx_id; 6939*4882a593Smuzhiyun __le16 efc_ctx_id; 6940*4882a593Smuzhiyun __le16 fid_ctx_id; 6941*4882a593Smuzhiyun u8 unused_2[5]; 6942*4882a593Smuzhiyun u8 valid; 6943*4882a593Smuzhiyun }; 6944*4882a593Smuzhiyun 6945*4882a593Smuzhiyun /* hwrm_cfa_eem_op_input (size:192b/24B) */ 6946*4882a593Smuzhiyun struct hwrm_cfa_eem_op_input { 6947*4882a593Smuzhiyun __le16 req_type; 6948*4882a593Smuzhiyun __le16 cmpl_ring; 6949*4882a593Smuzhiyun __le16 seq_id; 6950*4882a593Smuzhiyun __le16 target_id; 6951*4882a593Smuzhiyun __le64 resp_addr; 6952*4882a593Smuzhiyun __le32 flags; 6953*4882a593Smuzhiyun #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL 6954*4882a593Smuzhiyun #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL 6955*4882a593Smuzhiyun __le16 unused_0; 6956*4882a593Smuzhiyun __le16 op; 6957*4882a593Smuzhiyun #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL 6958*4882a593Smuzhiyun #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL 6959*4882a593Smuzhiyun #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL 6960*4882a593Smuzhiyun #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL 6961*4882a593Smuzhiyun #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP 6962*4882a593Smuzhiyun }; 6963*4882a593Smuzhiyun 6964*4882a593Smuzhiyun /* hwrm_cfa_eem_op_output (size:128b/16B) */ 6965*4882a593Smuzhiyun struct hwrm_cfa_eem_op_output { 6966*4882a593Smuzhiyun __le16 error_code; 6967*4882a593Smuzhiyun __le16 req_type; 6968*4882a593Smuzhiyun __le16 seq_id; 6969*4882a593Smuzhiyun __le16 resp_len; 6970*4882a593Smuzhiyun u8 unused_0[7]; 6971*4882a593Smuzhiyun u8 valid; 6972*4882a593Smuzhiyun }; 6973*4882a593Smuzhiyun 6974*4882a593Smuzhiyun /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ 6975*4882a593Smuzhiyun struct hwrm_cfa_adv_flow_mgnt_qcaps_input { 6976*4882a593Smuzhiyun __le16 req_type; 6977*4882a593Smuzhiyun __le16 cmpl_ring; 6978*4882a593Smuzhiyun __le16 seq_id; 6979*4882a593Smuzhiyun __le16 target_id; 6980*4882a593Smuzhiyun __le64 resp_addr; 6981*4882a593Smuzhiyun __le32 unused_0[4]; 6982*4882a593Smuzhiyun }; 6983*4882a593Smuzhiyun 6984*4882a593Smuzhiyun /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ 6985*4882a593Smuzhiyun struct hwrm_cfa_adv_flow_mgnt_qcaps_output { 6986*4882a593Smuzhiyun __le16 error_code; 6987*4882a593Smuzhiyun __le16 req_type; 6988*4882a593Smuzhiyun __le16 seq_id; 6989*4882a593Smuzhiyun __le16 resp_len; 6990*4882a593Smuzhiyun __le32 flags; 6991*4882a593Smuzhiyun #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL 6992*4882a593Smuzhiyun #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL 6993*4882a593Smuzhiyun #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL 6994*4882a593Smuzhiyun #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL 6995*4882a593Smuzhiyun #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL 6996*4882a593Smuzhiyun #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL 6997*4882a593Smuzhiyun #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL 6998*4882a593Smuzhiyun #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL 6999*4882a593Smuzhiyun #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL 7000*4882a593Smuzhiyun #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL 7001*4882a593Smuzhiyun #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL 7002*4882a593Smuzhiyun #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL 7003*4882a593Smuzhiyun #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL 7004*4882a593Smuzhiyun #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL 7005*4882a593Smuzhiyun #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL 7006*4882a593Smuzhiyun u8 unused_0[3]; 7007*4882a593Smuzhiyun u8 valid; 7008*4882a593Smuzhiyun }; 7009*4882a593Smuzhiyun 7010*4882a593Smuzhiyun /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 7011*4882a593Smuzhiyun struct hwrm_tunnel_dst_port_query_input { 7012*4882a593Smuzhiyun __le16 req_type; 7013*4882a593Smuzhiyun __le16 cmpl_ring; 7014*4882a593Smuzhiyun __le16 seq_id; 7015*4882a593Smuzhiyun __le16 target_id; 7016*4882a593Smuzhiyun __le64 resp_addr; 7017*4882a593Smuzhiyun u8 tunnel_type; 7018*4882a593Smuzhiyun #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7019*4882a593Smuzhiyun #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7020*4882a593Smuzhiyun #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7021*4882a593Smuzhiyun #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7022*4882a593Smuzhiyun #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7023*4882a593Smuzhiyun #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7024*4882a593Smuzhiyun #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7025*4882a593Smuzhiyun u8 unused_0[7]; 7026*4882a593Smuzhiyun }; 7027*4882a593Smuzhiyun 7028*4882a593Smuzhiyun /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 7029*4882a593Smuzhiyun struct hwrm_tunnel_dst_port_query_output { 7030*4882a593Smuzhiyun __le16 error_code; 7031*4882a593Smuzhiyun __le16 req_type; 7032*4882a593Smuzhiyun __le16 seq_id; 7033*4882a593Smuzhiyun __le16 resp_len; 7034*4882a593Smuzhiyun __le16 tunnel_dst_port_id; 7035*4882a593Smuzhiyun __be16 tunnel_dst_port_val; 7036*4882a593Smuzhiyun u8 unused_0[3]; 7037*4882a593Smuzhiyun u8 valid; 7038*4882a593Smuzhiyun }; 7039*4882a593Smuzhiyun 7040*4882a593Smuzhiyun /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 7041*4882a593Smuzhiyun struct hwrm_tunnel_dst_port_alloc_input { 7042*4882a593Smuzhiyun __le16 req_type; 7043*4882a593Smuzhiyun __le16 cmpl_ring; 7044*4882a593Smuzhiyun __le16 seq_id; 7045*4882a593Smuzhiyun __le16 target_id; 7046*4882a593Smuzhiyun __le64 resp_addr; 7047*4882a593Smuzhiyun u8 tunnel_type; 7048*4882a593Smuzhiyun #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7049*4882a593Smuzhiyun #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7050*4882a593Smuzhiyun #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7051*4882a593Smuzhiyun #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7052*4882a593Smuzhiyun #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7053*4882a593Smuzhiyun #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7054*4882a593Smuzhiyun #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7055*4882a593Smuzhiyun u8 unused_0; 7056*4882a593Smuzhiyun __be16 tunnel_dst_port_val; 7057*4882a593Smuzhiyun u8 unused_1[4]; 7058*4882a593Smuzhiyun }; 7059*4882a593Smuzhiyun 7060*4882a593Smuzhiyun /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 7061*4882a593Smuzhiyun struct hwrm_tunnel_dst_port_alloc_output { 7062*4882a593Smuzhiyun __le16 error_code; 7063*4882a593Smuzhiyun __le16 req_type; 7064*4882a593Smuzhiyun __le16 seq_id; 7065*4882a593Smuzhiyun __le16 resp_len; 7066*4882a593Smuzhiyun __le16 tunnel_dst_port_id; 7067*4882a593Smuzhiyun u8 unused_0[5]; 7068*4882a593Smuzhiyun u8 valid; 7069*4882a593Smuzhiyun }; 7070*4882a593Smuzhiyun 7071*4882a593Smuzhiyun /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 7072*4882a593Smuzhiyun struct hwrm_tunnel_dst_port_free_input { 7073*4882a593Smuzhiyun __le16 req_type; 7074*4882a593Smuzhiyun __le16 cmpl_ring; 7075*4882a593Smuzhiyun __le16 seq_id; 7076*4882a593Smuzhiyun __le16 target_id; 7077*4882a593Smuzhiyun __le64 resp_addr; 7078*4882a593Smuzhiyun u8 tunnel_type; 7079*4882a593Smuzhiyun #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7080*4882a593Smuzhiyun #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7081*4882a593Smuzhiyun #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7082*4882a593Smuzhiyun #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7083*4882a593Smuzhiyun #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7084*4882a593Smuzhiyun #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7085*4882a593Smuzhiyun #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7086*4882a593Smuzhiyun u8 unused_0; 7087*4882a593Smuzhiyun __le16 tunnel_dst_port_id; 7088*4882a593Smuzhiyun u8 unused_1[4]; 7089*4882a593Smuzhiyun }; 7090*4882a593Smuzhiyun 7091*4882a593Smuzhiyun /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 7092*4882a593Smuzhiyun struct hwrm_tunnel_dst_port_free_output { 7093*4882a593Smuzhiyun __le16 error_code; 7094*4882a593Smuzhiyun __le16 req_type; 7095*4882a593Smuzhiyun __le16 seq_id; 7096*4882a593Smuzhiyun __le16 resp_len; 7097*4882a593Smuzhiyun u8 unused_1[7]; 7098*4882a593Smuzhiyun u8 valid; 7099*4882a593Smuzhiyun }; 7100*4882a593Smuzhiyun 7101*4882a593Smuzhiyun /* ctx_hw_stats (size:1280b/160B) */ 7102*4882a593Smuzhiyun struct ctx_hw_stats { 7103*4882a593Smuzhiyun __le64 rx_ucast_pkts; 7104*4882a593Smuzhiyun __le64 rx_mcast_pkts; 7105*4882a593Smuzhiyun __le64 rx_bcast_pkts; 7106*4882a593Smuzhiyun __le64 rx_discard_pkts; 7107*4882a593Smuzhiyun __le64 rx_error_pkts; 7108*4882a593Smuzhiyun __le64 rx_ucast_bytes; 7109*4882a593Smuzhiyun __le64 rx_mcast_bytes; 7110*4882a593Smuzhiyun __le64 rx_bcast_bytes; 7111*4882a593Smuzhiyun __le64 tx_ucast_pkts; 7112*4882a593Smuzhiyun __le64 tx_mcast_pkts; 7113*4882a593Smuzhiyun __le64 tx_bcast_pkts; 7114*4882a593Smuzhiyun __le64 tx_error_pkts; 7115*4882a593Smuzhiyun __le64 tx_discard_pkts; 7116*4882a593Smuzhiyun __le64 tx_ucast_bytes; 7117*4882a593Smuzhiyun __le64 tx_mcast_bytes; 7118*4882a593Smuzhiyun __le64 tx_bcast_bytes; 7119*4882a593Smuzhiyun __le64 tpa_pkts; 7120*4882a593Smuzhiyun __le64 tpa_bytes; 7121*4882a593Smuzhiyun __le64 tpa_events; 7122*4882a593Smuzhiyun __le64 tpa_aborts; 7123*4882a593Smuzhiyun }; 7124*4882a593Smuzhiyun 7125*4882a593Smuzhiyun /* ctx_hw_stats_ext (size:1408b/176B) */ 7126*4882a593Smuzhiyun struct ctx_hw_stats_ext { 7127*4882a593Smuzhiyun __le64 rx_ucast_pkts; 7128*4882a593Smuzhiyun __le64 rx_mcast_pkts; 7129*4882a593Smuzhiyun __le64 rx_bcast_pkts; 7130*4882a593Smuzhiyun __le64 rx_discard_pkts; 7131*4882a593Smuzhiyun __le64 rx_error_pkts; 7132*4882a593Smuzhiyun __le64 rx_ucast_bytes; 7133*4882a593Smuzhiyun __le64 rx_mcast_bytes; 7134*4882a593Smuzhiyun __le64 rx_bcast_bytes; 7135*4882a593Smuzhiyun __le64 tx_ucast_pkts; 7136*4882a593Smuzhiyun __le64 tx_mcast_pkts; 7137*4882a593Smuzhiyun __le64 tx_bcast_pkts; 7138*4882a593Smuzhiyun __le64 tx_error_pkts; 7139*4882a593Smuzhiyun __le64 tx_discard_pkts; 7140*4882a593Smuzhiyun __le64 tx_ucast_bytes; 7141*4882a593Smuzhiyun __le64 tx_mcast_bytes; 7142*4882a593Smuzhiyun __le64 tx_bcast_bytes; 7143*4882a593Smuzhiyun __le64 rx_tpa_eligible_pkt; 7144*4882a593Smuzhiyun __le64 rx_tpa_eligible_bytes; 7145*4882a593Smuzhiyun __le64 rx_tpa_pkt; 7146*4882a593Smuzhiyun __le64 rx_tpa_bytes; 7147*4882a593Smuzhiyun __le64 rx_tpa_errors; 7148*4882a593Smuzhiyun __le64 rx_tpa_events; 7149*4882a593Smuzhiyun }; 7150*4882a593Smuzhiyun 7151*4882a593Smuzhiyun /* hwrm_stat_ctx_alloc_input (size:256b/32B) */ 7152*4882a593Smuzhiyun struct hwrm_stat_ctx_alloc_input { 7153*4882a593Smuzhiyun __le16 req_type; 7154*4882a593Smuzhiyun __le16 cmpl_ring; 7155*4882a593Smuzhiyun __le16 seq_id; 7156*4882a593Smuzhiyun __le16 target_id; 7157*4882a593Smuzhiyun __le64 resp_addr; 7158*4882a593Smuzhiyun __le64 stats_dma_addr; 7159*4882a593Smuzhiyun __le32 update_period_ms; 7160*4882a593Smuzhiyun u8 stat_ctx_flags; 7161*4882a593Smuzhiyun #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 7162*4882a593Smuzhiyun u8 unused_0; 7163*4882a593Smuzhiyun __le16 stats_dma_length; 7164*4882a593Smuzhiyun }; 7165*4882a593Smuzhiyun 7166*4882a593Smuzhiyun /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 7167*4882a593Smuzhiyun struct hwrm_stat_ctx_alloc_output { 7168*4882a593Smuzhiyun __le16 error_code; 7169*4882a593Smuzhiyun __le16 req_type; 7170*4882a593Smuzhiyun __le16 seq_id; 7171*4882a593Smuzhiyun __le16 resp_len; 7172*4882a593Smuzhiyun __le32 stat_ctx_id; 7173*4882a593Smuzhiyun u8 unused_0[3]; 7174*4882a593Smuzhiyun u8 valid; 7175*4882a593Smuzhiyun }; 7176*4882a593Smuzhiyun 7177*4882a593Smuzhiyun /* hwrm_stat_ctx_free_input (size:192b/24B) */ 7178*4882a593Smuzhiyun struct hwrm_stat_ctx_free_input { 7179*4882a593Smuzhiyun __le16 req_type; 7180*4882a593Smuzhiyun __le16 cmpl_ring; 7181*4882a593Smuzhiyun __le16 seq_id; 7182*4882a593Smuzhiyun __le16 target_id; 7183*4882a593Smuzhiyun __le64 resp_addr; 7184*4882a593Smuzhiyun __le32 stat_ctx_id; 7185*4882a593Smuzhiyun u8 unused_0[4]; 7186*4882a593Smuzhiyun }; 7187*4882a593Smuzhiyun 7188*4882a593Smuzhiyun /* hwrm_stat_ctx_free_output (size:128b/16B) */ 7189*4882a593Smuzhiyun struct hwrm_stat_ctx_free_output { 7190*4882a593Smuzhiyun __le16 error_code; 7191*4882a593Smuzhiyun __le16 req_type; 7192*4882a593Smuzhiyun __le16 seq_id; 7193*4882a593Smuzhiyun __le16 resp_len; 7194*4882a593Smuzhiyun __le32 stat_ctx_id; 7195*4882a593Smuzhiyun u8 unused_0[3]; 7196*4882a593Smuzhiyun u8 valid; 7197*4882a593Smuzhiyun }; 7198*4882a593Smuzhiyun 7199*4882a593Smuzhiyun /* hwrm_stat_ctx_query_input (size:192b/24B) */ 7200*4882a593Smuzhiyun struct hwrm_stat_ctx_query_input { 7201*4882a593Smuzhiyun __le16 req_type; 7202*4882a593Smuzhiyun __le16 cmpl_ring; 7203*4882a593Smuzhiyun __le16 seq_id; 7204*4882a593Smuzhiyun __le16 target_id; 7205*4882a593Smuzhiyun __le64 resp_addr; 7206*4882a593Smuzhiyun __le32 stat_ctx_id; 7207*4882a593Smuzhiyun u8 flags; 7208*4882a593Smuzhiyun #define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 7209*4882a593Smuzhiyun u8 unused_0[3]; 7210*4882a593Smuzhiyun }; 7211*4882a593Smuzhiyun 7212*4882a593Smuzhiyun /* hwrm_stat_ctx_query_output (size:1408b/176B) */ 7213*4882a593Smuzhiyun struct hwrm_stat_ctx_query_output { 7214*4882a593Smuzhiyun __le16 error_code; 7215*4882a593Smuzhiyun __le16 req_type; 7216*4882a593Smuzhiyun __le16 seq_id; 7217*4882a593Smuzhiyun __le16 resp_len; 7218*4882a593Smuzhiyun __le64 tx_ucast_pkts; 7219*4882a593Smuzhiyun __le64 tx_mcast_pkts; 7220*4882a593Smuzhiyun __le64 tx_bcast_pkts; 7221*4882a593Smuzhiyun __le64 tx_discard_pkts; 7222*4882a593Smuzhiyun __le64 tx_error_pkts; 7223*4882a593Smuzhiyun __le64 tx_ucast_bytes; 7224*4882a593Smuzhiyun __le64 tx_mcast_bytes; 7225*4882a593Smuzhiyun __le64 tx_bcast_bytes; 7226*4882a593Smuzhiyun __le64 rx_ucast_pkts; 7227*4882a593Smuzhiyun __le64 rx_mcast_pkts; 7228*4882a593Smuzhiyun __le64 rx_bcast_pkts; 7229*4882a593Smuzhiyun __le64 rx_discard_pkts; 7230*4882a593Smuzhiyun __le64 rx_error_pkts; 7231*4882a593Smuzhiyun __le64 rx_ucast_bytes; 7232*4882a593Smuzhiyun __le64 rx_mcast_bytes; 7233*4882a593Smuzhiyun __le64 rx_bcast_bytes; 7234*4882a593Smuzhiyun __le64 rx_agg_pkts; 7235*4882a593Smuzhiyun __le64 rx_agg_bytes; 7236*4882a593Smuzhiyun __le64 rx_agg_events; 7237*4882a593Smuzhiyun __le64 rx_agg_aborts; 7238*4882a593Smuzhiyun u8 unused_0[7]; 7239*4882a593Smuzhiyun u8 valid; 7240*4882a593Smuzhiyun }; 7241*4882a593Smuzhiyun 7242*4882a593Smuzhiyun /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */ 7243*4882a593Smuzhiyun struct hwrm_stat_ext_ctx_query_input { 7244*4882a593Smuzhiyun __le16 req_type; 7245*4882a593Smuzhiyun __le16 cmpl_ring; 7246*4882a593Smuzhiyun __le16 seq_id; 7247*4882a593Smuzhiyun __le16 target_id; 7248*4882a593Smuzhiyun __le64 resp_addr; 7249*4882a593Smuzhiyun __le32 stat_ctx_id; 7250*4882a593Smuzhiyun u8 flags; 7251*4882a593Smuzhiyun #define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 7252*4882a593Smuzhiyun u8 unused_0[3]; 7253*4882a593Smuzhiyun }; 7254*4882a593Smuzhiyun 7255*4882a593Smuzhiyun /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */ 7256*4882a593Smuzhiyun struct hwrm_stat_ext_ctx_query_output { 7257*4882a593Smuzhiyun __le16 error_code; 7258*4882a593Smuzhiyun __le16 req_type; 7259*4882a593Smuzhiyun __le16 seq_id; 7260*4882a593Smuzhiyun __le16 resp_len; 7261*4882a593Smuzhiyun __le64 rx_ucast_pkts; 7262*4882a593Smuzhiyun __le64 rx_mcast_pkts; 7263*4882a593Smuzhiyun __le64 rx_bcast_pkts; 7264*4882a593Smuzhiyun __le64 rx_discard_pkts; 7265*4882a593Smuzhiyun __le64 rx_error_pkts; 7266*4882a593Smuzhiyun __le64 rx_ucast_bytes; 7267*4882a593Smuzhiyun __le64 rx_mcast_bytes; 7268*4882a593Smuzhiyun __le64 rx_bcast_bytes; 7269*4882a593Smuzhiyun __le64 tx_ucast_pkts; 7270*4882a593Smuzhiyun __le64 tx_mcast_pkts; 7271*4882a593Smuzhiyun __le64 tx_bcast_pkts; 7272*4882a593Smuzhiyun __le64 tx_error_pkts; 7273*4882a593Smuzhiyun __le64 tx_discard_pkts; 7274*4882a593Smuzhiyun __le64 tx_ucast_bytes; 7275*4882a593Smuzhiyun __le64 tx_mcast_bytes; 7276*4882a593Smuzhiyun __le64 tx_bcast_bytes; 7277*4882a593Smuzhiyun __le64 rx_tpa_eligible_pkt; 7278*4882a593Smuzhiyun __le64 rx_tpa_eligible_bytes; 7279*4882a593Smuzhiyun __le64 rx_tpa_pkt; 7280*4882a593Smuzhiyun __le64 rx_tpa_bytes; 7281*4882a593Smuzhiyun __le64 rx_tpa_errors; 7282*4882a593Smuzhiyun __le64 rx_tpa_events; 7283*4882a593Smuzhiyun u8 unused_0[7]; 7284*4882a593Smuzhiyun u8 valid; 7285*4882a593Smuzhiyun }; 7286*4882a593Smuzhiyun 7287*4882a593Smuzhiyun /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 7288*4882a593Smuzhiyun struct hwrm_stat_ctx_clr_stats_input { 7289*4882a593Smuzhiyun __le16 req_type; 7290*4882a593Smuzhiyun __le16 cmpl_ring; 7291*4882a593Smuzhiyun __le16 seq_id; 7292*4882a593Smuzhiyun __le16 target_id; 7293*4882a593Smuzhiyun __le64 resp_addr; 7294*4882a593Smuzhiyun __le32 stat_ctx_id; 7295*4882a593Smuzhiyun u8 unused_0[4]; 7296*4882a593Smuzhiyun }; 7297*4882a593Smuzhiyun 7298*4882a593Smuzhiyun /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 7299*4882a593Smuzhiyun struct hwrm_stat_ctx_clr_stats_output { 7300*4882a593Smuzhiyun __le16 error_code; 7301*4882a593Smuzhiyun __le16 req_type; 7302*4882a593Smuzhiyun __le16 seq_id; 7303*4882a593Smuzhiyun __le16 resp_len; 7304*4882a593Smuzhiyun u8 unused_0[7]; 7305*4882a593Smuzhiyun u8 valid; 7306*4882a593Smuzhiyun }; 7307*4882a593Smuzhiyun 7308*4882a593Smuzhiyun /* hwrm_pcie_qstats_input (size:256b/32B) */ 7309*4882a593Smuzhiyun struct hwrm_pcie_qstats_input { 7310*4882a593Smuzhiyun __le16 req_type; 7311*4882a593Smuzhiyun __le16 cmpl_ring; 7312*4882a593Smuzhiyun __le16 seq_id; 7313*4882a593Smuzhiyun __le16 target_id; 7314*4882a593Smuzhiyun __le64 resp_addr; 7315*4882a593Smuzhiyun __le16 pcie_stat_size; 7316*4882a593Smuzhiyun u8 unused_0[6]; 7317*4882a593Smuzhiyun __le64 pcie_stat_host_addr; 7318*4882a593Smuzhiyun }; 7319*4882a593Smuzhiyun 7320*4882a593Smuzhiyun /* hwrm_pcie_qstats_output (size:128b/16B) */ 7321*4882a593Smuzhiyun struct hwrm_pcie_qstats_output { 7322*4882a593Smuzhiyun __le16 error_code; 7323*4882a593Smuzhiyun __le16 req_type; 7324*4882a593Smuzhiyun __le16 seq_id; 7325*4882a593Smuzhiyun __le16 resp_len; 7326*4882a593Smuzhiyun __le16 pcie_stat_size; 7327*4882a593Smuzhiyun u8 unused_0[5]; 7328*4882a593Smuzhiyun u8 valid; 7329*4882a593Smuzhiyun }; 7330*4882a593Smuzhiyun 7331*4882a593Smuzhiyun /* pcie_ctx_hw_stats (size:768b/96B) */ 7332*4882a593Smuzhiyun struct pcie_ctx_hw_stats { 7333*4882a593Smuzhiyun __le64 pcie_pl_signal_integrity; 7334*4882a593Smuzhiyun __le64 pcie_dl_signal_integrity; 7335*4882a593Smuzhiyun __le64 pcie_tl_signal_integrity; 7336*4882a593Smuzhiyun __le64 pcie_link_integrity; 7337*4882a593Smuzhiyun __le64 pcie_tx_traffic_rate; 7338*4882a593Smuzhiyun __le64 pcie_rx_traffic_rate; 7339*4882a593Smuzhiyun __le64 pcie_tx_dllp_statistics; 7340*4882a593Smuzhiyun __le64 pcie_rx_dllp_statistics; 7341*4882a593Smuzhiyun __le64 pcie_equalization_time; 7342*4882a593Smuzhiyun __le32 pcie_ltssm_histogram[4]; 7343*4882a593Smuzhiyun __le64 pcie_recovery_histogram; 7344*4882a593Smuzhiyun }; 7345*4882a593Smuzhiyun 7346*4882a593Smuzhiyun /* hwrm_fw_reset_input (size:192b/24B) */ 7347*4882a593Smuzhiyun struct hwrm_fw_reset_input { 7348*4882a593Smuzhiyun __le16 req_type; 7349*4882a593Smuzhiyun __le16 cmpl_ring; 7350*4882a593Smuzhiyun __le16 seq_id; 7351*4882a593Smuzhiyun __le16 target_id; 7352*4882a593Smuzhiyun __le64 resp_addr; 7353*4882a593Smuzhiyun u8 embedded_proc_type; 7354*4882a593Smuzhiyun #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 7355*4882a593Smuzhiyun #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 7356*4882a593Smuzhiyun #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 7357*4882a593Smuzhiyun #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 7358*4882a593Smuzhiyun #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 7359*4882a593Smuzhiyun #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 7360*4882a593Smuzhiyun #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 7361*4882a593Smuzhiyun #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 7362*4882a593Smuzhiyun #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL 7363*4882a593Smuzhiyun #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 7364*4882a593Smuzhiyun u8 selfrst_status; 7365*4882a593Smuzhiyun #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 7366*4882a593Smuzhiyun #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 7367*4882a593Smuzhiyun #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 7368*4882a593Smuzhiyun #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 7369*4882a593Smuzhiyun #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 7370*4882a593Smuzhiyun u8 host_idx; 7371*4882a593Smuzhiyun u8 flags; 7372*4882a593Smuzhiyun #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL 7373*4882a593Smuzhiyun u8 unused_0[4]; 7374*4882a593Smuzhiyun }; 7375*4882a593Smuzhiyun 7376*4882a593Smuzhiyun /* hwrm_fw_reset_output (size:128b/16B) */ 7377*4882a593Smuzhiyun struct hwrm_fw_reset_output { 7378*4882a593Smuzhiyun __le16 error_code; 7379*4882a593Smuzhiyun __le16 req_type; 7380*4882a593Smuzhiyun __le16 seq_id; 7381*4882a593Smuzhiyun __le16 resp_len; 7382*4882a593Smuzhiyun u8 selfrst_status; 7383*4882a593Smuzhiyun #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 7384*4882a593Smuzhiyun #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 7385*4882a593Smuzhiyun #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 7386*4882a593Smuzhiyun #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 7387*4882a593Smuzhiyun #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 7388*4882a593Smuzhiyun u8 unused_0[6]; 7389*4882a593Smuzhiyun u8 valid; 7390*4882a593Smuzhiyun }; 7391*4882a593Smuzhiyun 7392*4882a593Smuzhiyun /* hwrm_fw_qstatus_input (size:192b/24B) */ 7393*4882a593Smuzhiyun struct hwrm_fw_qstatus_input { 7394*4882a593Smuzhiyun __le16 req_type; 7395*4882a593Smuzhiyun __le16 cmpl_ring; 7396*4882a593Smuzhiyun __le16 seq_id; 7397*4882a593Smuzhiyun __le16 target_id; 7398*4882a593Smuzhiyun __le64 resp_addr; 7399*4882a593Smuzhiyun u8 embedded_proc_type; 7400*4882a593Smuzhiyun #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 7401*4882a593Smuzhiyun #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 7402*4882a593Smuzhiyun #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 7403*4882a593Smuzhiyun #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 7404*4882a593Smuzhiyun #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 7405*4882a593Smuzhiyun #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 7406*4882a593Smuzhiyun #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 7407*4882a593Smuzhiyun #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 7408*4882a593Smuzhiyun u8 unused_0[7]; 7409*4882a593Smuzhiyun }; 7410*4882a593Smuzhiyun 7411*4882a593Smuzhiyun /* hwrm_fw_qstatus_output (size:128b/16B) */ 7412*4882a593Smuzhiyun struct hwrm_fw_qstatus_output { 7413*4882a593Smuzhiyun __le16 error_code; 7414*4882a593Smuzhiyun __le16 req_type; 7415*4882a593Smuzhiyun __le16 seq_id; 7416*4882a593Smuzhiyun __le16 resp_len; 7417*4882a593Smuzhiyun u8 selfrst_status; 7418*4882a593Smuzhiyun #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 7419*4882a593Smuzhiyun #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 7420*4882a593Smuzhiyun #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 7421*4882a593Smuzhiyun #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL 7422*4882a593Smuzhiyun #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 7423*4882a593Smuzhiyun u8 unused_0[6]; 7424*4882a593Smuzhiyun u8 valid; 7425*4882a593Smuzhiyun }; 7426*4882a593Smuzhiyun 7427*4882a593Smuzhiyun /* hwrm_fw_set_time_input (size:256b/32B) */ 7428*4882a593Smuzhiyun struct hwrm_fw_set_time_input { 7429*4882a593Smuzhiyun __le16 req_type; 7430*4882a593Smuzhiyun __le16 cmpl_ring; 7431*4882a593Smuzhiyun __le16 seq_id; 7432*4882a593Smuzhiyun __le16 target_id; 7433*4882a593Smuzhiyun __le64 resp_addr; 7434*4882a593Smuzhiyun __le16 year; 7435*4882a593Smuzhiyun #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 7436*4882a593Smuzhiyun #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 7437*4882a593Smuzhiyun u8 month; 7438*4882a593Smuzhiyun u8 day; 7439*4882a593Smuzhiyun u8 hour; 7440*4882a593Smuzhiyun u8 minute; 7441*4882a593Smuzhiyun u8 second; 7442*4882a593Smuzhiyun u8 unused_0; 7443*4882a593Smuzhiyun __le16 millisecond; 7444*4882a593Smuzhiyun __le16 zone; 7445*4882a593Smuzhiyun #define FW_SET_TIME_REQ_ZONE_UTC 0 7446*4882a593Smuzhiyun #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535 7447*4882a593Smuzhiyun #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 7448*4882a593Smuzhiyun u8 unused_1[4]; 7449*4882a593Smuzhiyun }; 7450*4882a593Smuzhiyun 7451*4882a593Smuzhiyun /* hwrm_fw_set_time_output (size:128b/16B) */ 7452*4882a593Smuzhiyun struct hwrm_fw_set_time_output { 7453*4882a593Smuzhiyun __le16 error_code; 7454*4882a593Smuzhiyun __le16 req_type; 7455*4882a593Smuzhiyun __le16 seq_id; 7456*4882a593Smuzhiyun __le16 resp_len; 7457*4882a593Smuzhiyun u8 unused_0[7]; 7458*4882a593Smuzhiyun u8 valid; 7459*4882a593Smuzhiyun }; 7460*4882a593Smuzhiyun 7461*4882a593Smuzhiyun /* hwrm_struct_hdr (size:128b/16B) */ 7462*4882a593Smuzhiyun struct hwrm_struct_hdr { 7463*4882a593Smuzhiyun __le16 struct_id; 7464*4882a593Smuzhiyun #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 7465*4882a593Smuzhiyun #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 7466*4882a593Smuzhiyun #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 7467*4882a593Smuzhiyun #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 7468*4882a593Smuzhiyun #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 7469*4882a593Smuzhiyun #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 7470*4882a593Smuzhiyun #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 7471*4882a593Smuzhiyun #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL 7472*4882a593Smuzhiyun #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 7473*4882a593Smuzhiyun #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 7474*4882a593Smuzhiyun #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 7475*4882a593Smuzhiyun #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_RSS_V2 7476*4882a593Smuzhiyun __le16 len; 7477*4882a593Smuzhiyun u8 version; 7478*4882a593Smuzhiyun u8 count; 7479*4882a593Smuzhiyun __le16 subtype; 7480*4882a593Smuzhiyun __le16 next_offset; 7481*4882a593Smuzhiyun #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 7482*4882a593Smuzhiyun u8 unused_0[6]; 7483*4882a593Smuzhiyun }; 7484*4882a593Smuzhiyun 7485*4882a593Smuzhiyun /* hwrm_struct_data_dcbx_app (size:64b/8B) */ 7486*4882a593Smuzhiyun struct hwrm_struct_data_dcbx_app { 7487*4882a593Smuzhiyun __be16 protocol_id; 7488*4882a593Smuzhiyun u8 protocol_selector; 7489*4882a593Smuzhiyun #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 7490*4882a593Smuzhiyun #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 7491*4882a593Smuzhiyun #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 7492*4882a593Smuzhiyun #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 7493*4882a593Smuzhiyun #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 7494*4882a593Smuzhiyun u8 priority; 7495*4882a593Smuzhiyun u8 valid; 7496*4882a593Smuzhiyun u8 unused_0[3]; 7497*4882a593Smuzhiyun }; 7498*4882a593Smuzhiyun 7499*4882a593Smuzhiyun /* hwrm_fw_set_structured_data_input (size:256b/32B) */ 7500*4882a593Smuzhiyun struct hwrm_fw_set_structured_data_input { 7501*4882a593Smuzhiyun __le16 req_type; 7502*4882a593Smuzhiyun __le16 cmpl_ring; 7503*4882a593Smuzhiyun __le16 seq_id; 7504*4882a593Smuzhiyun __le16 target_id; 7505*4882a593Smuzhiyun __le64 resp_addr; 7506*4882a593Smuzhiyun __le64 src_data_addr; 7507*4882a593Smuzhiyun __le16 data_len; 7508*4882a593Smuzhiyun u8 hdr_cnt; 7509*4882a593Smuzhiyun u8 unused_0[5]; 7510*4882a593Smuzhiyun }; 7511*4882a593Smuzhiyun 7512*4882a593Smuzhiyun /* hwrm_fw_set_structured_data_output (size:128b/16B) */ 7513*4882a593Smuzhiyun struct hwrm_fw_set_structured_data_output { 7514*4882a593Smuzhiyun __le16 error_code; 7515*4882a593Smuzhiyun __le16 req_type; 7516*4882a593Smuzhiyun __le16 seq_id; 7517*4882a593Smuzhiyun __le16 resp_len; 7518*4882a593Smuzhiyun u8 unused_0[7]; 7519*4882a593Smuzhiyun u8 valid; 7520*4882a593Smuzhiyun }; 7521*4882a593Smuzhiyun 7522*4882a593Smuzhiyun /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 7523*4882a593Smuzhiyun struct hwrm_fw_set_structured_data_cmd_err { 7524*4882a593Smuzhiyun u8 code; 7525*4882a593Smuzhiyun #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 7526*4882a593Smuzhiyun #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 7527*4882a593Smuzhiyun #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 7528*4882a593Smuzhiyun #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 7529*4882a593Smuzhiyun #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 7530*4882a593Smuzhiyun u8 unused_0[7]; 7531*4882a593Smuzhiyun }; 7532*4882a593Smuzhiyun 7533*4882a593Smuzhiyun /* hwrm_fw_get_structured_data_input (size:256b/32B) */ 7534*4882a593Smuzhiyun struct hwrm_fw_get_structured_data_input { 7535*4882a593Smuzhiyun __le16 req_type; 7536*4882a593Smuzhiyun __le16 cmpl_ring; 7537*4882a593Smuzhiyun __le16 seq_id; 7538*4882a593Smuzhiyun __le16 target_id; 7539*4882a593Smuzhiyun __le64 resp_addr; 7540*4882a593Smuzhiyun __le64 dest_data_addr; 7541*4882a593Smuzhiyun __le16 data_len; 7542*4882a593Smuzhiyun __le16 structure_id; 7543*4882a593Smuzhiyun __le16 subtype; 7544*4882a593Smuzhiyun #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 7545*4882a593Smuzhiyun #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 7546*4882a593Smuzhiyun #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 7547*4882a593Smuzhiyun #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 7548*4882a593Smuzhiyun #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 7549*4882a593Smuzhiyun #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 7550*4882a593Smuzhiyun #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 7551*4882a593Smuzhiyun #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 7552*4882a593Smuzhiyun #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 7553*4882a593Smuzhiyun #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 7554*4882a593Smuzhiyun u8 count; 7555*4882a593Smuzhiyun u8 unused_0; 7556*4882a593Smuzhiyun }; 7557*4882a593Smuzhiyun 7558*4882a593Smuzhiyun /* hwrm_fw_get_structured_data_output (size:128b/16B) */ 7559*4882a593Smuzhiyun struct hwrm_fw_get_structured_data_output { 7560*4882a593Smuzhiyun __le16 error_code; 7561*4882a593Smuzhiyun __le16 req_type; 7562*4882a593Smuzhiyun __le16 seq_id; 7563*4882a593Smuzhiyun __le16 resp_len; 7564*4882a593Smuzhiyun u8 hdr_cnt; 7565*4882a593Smuzhiyun u8 unused_0[6]; 7566*4882a593Smuzhiyun u8 valid; 7567*4882a593Smuzhiyun }; 7568*4882a593Smuzhiyun 7569*4882a593Smuzhiyun /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 7570*4882a593Smuzhiyun struct hwrm_fw_get_structured_data_cmd_err { 7571*4882a593Smuzhiyun u8 code; 7572*4882a593Smuzhiyun #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 7573*4882a593Smuzhiyun #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 7574*4882a593Smuzhiyun #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 7575*4882a593Smuzhiyun u8 unused_0[7]; 7576*4882a593Smuzhiyun }; 7577*4882a593Smuzhiyun 7578*4882a593Smuzhiyun /* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 7579*4882a593Smuzhiyun struct hwrm_exec_fwd_resp_input { 7580*4882a593Smuzhiyun __le16 req_type; 7581*4882a593Smuzhiyun __le16 cmpl_ring; 7582*4882a593Smuzhiyun __le16 seq_id; 7583*4882a593Smuzhiyun __le16 target_id; 7584*4882a593Smuzhiyun __le64 resp_addr; 7585*4882a593Smuzhiyun __le32 encap_request[26]; 7586*4882a593Smuzhiyun __le16 encap_resp_target_id; 7587*4882a593Smuzhiyun u8 unused_0[6]; 7588*4882a593Smuzhiyun }; 7589*4882a593Smuzhiyun 7590*4882a593Smuzhiyun /* hwrm_exec_fwd_resp_output (size:128b/16B) */ 7591*4882a593Smuzhiyun struct hwrm_exec_fwd_resp_output { 7592*4882a593Smuzhiyun __le16 error_code; 7593*4882a593Smuzhiyun __le16 req_type; 7594*4882a593Smuzhiyun __le16 seq_id; 7595*4882a593Smuzhiyun __le16 resp_len; 7596*4882a593Smuzhiyun u8 unused_0[7]; 7597*4882a593Smuzhiyun u8 valid; 7598*4882a593Smuzhiyun }; 7599*4882a593Smuzhiyun 7600*4882a593Smuzhiyun /* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 7601*4882a593Smuzhiyun struct hwrm_reject_fwd_resp_input { 7602*4882a593Smuzhiyun __le16 req_type; 7603*4882a593Smuzhiyun __le16 cmpl_ring; 7604*4882a593Smuzhiyun __le16 seq_id; 7605*4882a593Smuzhiyun __le16 target_id; 7606*4882a593Smuzhiyun __le64 resp_addr; 7607*4882a593Smuzhiyun __le32 encap_request[26]; 7608*4882a593Smuzhiyun __le16 encap_resp_target_id; 7609*4882a593Smuzhiyun u8 unused_0[6]; 7610*4882a593Smuzhiyun }; 7611*4882a593Smuzhiyun 7612*4882a593Smuzhiyun /* hwrm_reject_fwd_resp_output (size:128b/16B) */ 7613*4882a593Smuzhiyun struct hwrm_reject_fwd_resp_output { 7614*4882a593Smuzhiyun __le16 error_code; 7615*4882a593Smuzhiyun __le16 req_type; 7616*4882a593Smuzhiyun __le16 seq_id; 7617*4882a593Smuzhiyun __le16 resp_len; 7618*4882a593Smuzhiyun u8 unused_0[7]; 7619*4882a593Smuzhiyun u8 valid; 7620*4882a593Smuzhiyun }; 7621*4882a593Smuzhiyun 7622*4882a593Smuzhiyun /* hwrm_fwd_resp_input (size:1024b/128B) */ 7623*4882a593Smuzhiyun struct hwrm_fwd_resp_input { 7624*4882a593Smuzhiyun __le16 req_type; 7625*4882a593Smuzhiyun __le16 cmpl_ring; 7626*4882a593Smuzhiyun __le16 seq_id; 7627*4882a593Smuzhiyun __le16 target_id; 7628*4882a593Smuzhiyun __le64 resp_addr; 7629*4882a593Smuzhiyun __le16 encap_resp_target_id; 7630*4882a593Smuzhiyun __le16 encap_resp_cmpl_ring; 7631*4882a593Smuzhiyun __le16 encap_resp_len; 7632*4882a593Smuzhiyun u8 unused_0; 7633*4882a593Smuzhiyun u8 unused_1; 7634*4882a593Smuzhiyun __le64 encap_resp_addr; 7635*4882a593Smuzhiyun __le32 encap_resp[24]; 7636*4882a593Smuzhiyun }; 7637*4882a593Smuzhiyun 7638*4882a593Smuzhiyun /* hwrm_fwd_resp_output (size:128b/16B) */ 7639*4882a593Smuzhiyun struct hwrm_fwd_resp_output { 7640*4882a593Smuzhiyun __le16 error_code; 7641*4882a593Smuzhiyun __le16 req_type; 7642*4882a593Smuzhiyun __le16 seq_id; 7643*4882a593Smuzhiyun __le16 resp_len; 7644*4882a593Smuzhiyun u8 unused_0[7]; 7645*4882a593Smuzhiyun u8 valid; 7646*4882a593Smuzhiyun }; 7647*4882a593Smuzhiyun 7648*4882a593Smuzhiyun /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 7649*4882a593Smuzhiyun struct hwrm_fwd_async_event_cmpl_input { 7650*4882a593Smuzhiyun __le16 req_type; 7651*4882a593Smuzhiyun __le16 cmpl_ring; 7652*4882a593Smuzhiyun __le16 seq_id; 7653*4882a593Smuzhiyun __le16 target_id; 7654*4882a593Smuzhiyun __le64 resp_addr; 7655*4882a593Smuzhiyun __le16 encap_async_event_target_id; 7656*4882a593Smuzhiyun u8 unused_0[6]; 7657*4882a593Smuzhiyun __le32 encap_async_event_cmpl[4]; 7658*4882a593Smuzhiyun }; 7659*4882a593Smuzhiyun 7660*4882a593Smuzhiyun /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 7661*4882a593Smuzhiyun struct hwrm_fwd_async_event_cmpl_output { 7662*4882a593Smuzhiyun __le16 error_code; 7663*4882a593Smuzhiyun __le16 req_type; 7664*4882a593Smuzhiyun __le16 seq_id; 7665*4882a593Smuzhiyun __le16 resp_len; 7666*4882a593Smuzhiyun u8 unused_0[7]; 7667*4882a593Smuzhiyun u8 valid; 7668*4882a593Smuzhiyun }; 7669*4882a593Smuzhiyun 7670*4882a593Smuzhiyun /* hwrm_temp_monitor_query_input (size:128b/16B) */ 7671*4882a593Smuzhiyun struct hwrm_temp_monitor_query_input { 7672*4882a593Smuzhiyun __le16 req_type; 7673*4882a593Smuzhiyun __le16 cmpl_ring; 7674*4882a593Smuzhiyun __le16 seq_id; 7675*4882a593Smuzhiyun __le16 target_id; 7676*4882a593Smuzhiyun __le64 resp_addr; 7677*4882a593Smuzhiyun }; 7678*4882a593Smuzhiyun 7679*4882a593Smuzhiyun /* hwrm_temp_monitor_query_output (size:128b/16B) */ 7680*4882a593Smuzhiyun struct hwrm_temp_monitor_query_output { 7681*4882a593Smuzhiyun __le16 error_code; 7682*4882a593Smuzhiyun __le16 req_type; 7683*4882a593Smuzhiyun __le16 seq_id; 7684*4882a593Smuzhiyun __le16 resp_len; 7685*4882a593Smuzhiyun u8 temp; 7686*4882a593Smuzhiyun u8 phy_temp; 7687*4882a593Smuzhiyun u8 om_temp; 7688*4882a593Smuzhiyun u8 flags; 7689*4882a593Smuzhiyun #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL 7690*4882a593Smuzhiyun #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL 7691*4882a593Smuzhiyun #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL 7692*4882a593Smuzhiyun #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL 7693*4882a593Smuzhiyun u8 unused_0[3]; 7694*4882a593Smuzhiyun u8 valid; 7695*4882a593Smuzhiyun }; 7696*4882a593Smuzhiyun 7697*4882a593Smuzhiyun /* hwrm_wol_filter_alloc_input (size:512b/64B) */ 7698*4882a593Smuzhiyun struct hwrm_wol_filter_alloc_input { 7699*4882a593Smuzhiyun __le16 req_type; 7700*4882a593Smuzhiyun __le16 cmpl_ring; 7701*4882a593Smuzhiyun __le16 seq_id; 7702*4882a593Smuzhiyun __le16 target_id; 7703*4882a593Smuzhiyun __le64 resp_addr; 7704*4882a593Smuzhiyun __le32 flags; 7705*4882a593Smuzhiyun __le32 enables; 7706*4882a593Smuzhiyun #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 7707*4882a593Smuzhiyun #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 7708*4882a593Smuzhiyun #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 7709*4882a593Smuzhiyun #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 7710*4882a593Smuzhiyun #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 7711*4882a593Smuzhiyun #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 7712*4882a593Smuzhiyun __le16 port_id; 7713*4882a593Smuzhiyun u8 wol_type; 7714*4882a593Smuzhiyun #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 7715*4882a593Smuzhiyun #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 7716*4882a593Smuzhiyun #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 7717*4882a593Smuzhiyun #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 7718*4882a593Smuzhiyun u8 unused_0[5]; 7719*4882a593Smuzhiyun u8 mac_address[6]; 7720*4882a593Smuzhiyun __le16 pattern_offset; 7721*4882a593Smuzhiyun __le16 pattern_buf_size; 7722*4882a593Smuzhiyun __le16 pattern_mask_size; 7723*4882a593Smuzhiyun u8 unused_1[4]; 7724*4882a593Smuzhiyun __le64 pattern_buf_addr; 7725*4882a593Smuzhiyun __le64 pattern_mask_addr; 7726*4882a593Smuzhiyun }; 7727*4882a593Smuzhiyun 7728*4882a593Smuzhiyun /* hwrm_wol_filter_alloc_output (size:128b/16B) */ 7729*4882a593Smuzhiyun struct hwrm_wol_filter_alloc_output { 7730*4882a593Smuzhiyun __le16 error_code; 7731*4882a593Smuzhiyun __le16 req_type; 7732*4882a593Smuzhiyun __le16 seq_id; 7733*4882a593Smuzhiyun __le16 resp_len; 7734*4882a593Smuzhiyun u8 wol_filter_id; 7735*4882a593Smuzhiyun u8 unused_0[6]; 7736*4882a593Smuzhiyun u8 valid; 7737*4882a593Smuzhiyun }; 7738*4882a593Smuzhiyun 7739*4882a593Smuzhiyun /* hwrm_wol_filter_free_input (size:256b/32B) */ 7740*4882a593Smuzhiyun struct hwrm_wol_filter_free_input { 7741*4882a593Smuzhiyun __le16 req_type; 7742*4882a593Smuzhiyun __le16 cmpl_ring; 7743*4882a593Smuzhiyun __le16 seq_id; 7744*4882a593Smuzhiyun __le16 target_id; 7745*4882a593Smuzhiyun __le64 resp_addr; 7746*4882a593Smuzhiyun __le32 flags; 7747*4882a593Smuzhiyun #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 7748*4882a593Smuzhiyun __le32 enables; 7749*4882a593Smuzhiyun #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 7750*4882a593Smuzhiyun __le16 port_id; 7751*4882a593Smuzhiyun u8 wol_filter_id; 7752*4882a593Smuzhiyun u8 unused_0[5]; 7753*4882a593Smuzhiyun }; 7754*4882a593Smuzhiyun 7755*4882a593Smuzhiyun /* hwrm_wol_filter_free_output (size:128b/16B) */ 7756*4882a593Smuzhiyun struct hwrm_wol_filter_free_output { 7757*4882a593Smuzhiyun __le16 error_code; 7758*4882a593Smuzhiyun __le16 req_type; 7759*4882a593Smuzhiyun __le16 seq_id; 7760*4882a593Smuzhiyun __le16 resp_len; 7761*4882a593Smuzhiyun u8 unused_0[7]; 7762*4882a593Smuzhiyun u8 valid; 7763*4882a593Smuzhiyun }; 7764*4882a593Smuzhiyun 7765*4882a593Smuzhiyun /* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 7766*4882a593Smuzhiyun struct hwrm_wol_filter_qcfg_input { 7767*4882a593Smuzhiyun __le16 req_type; 7768*4882a593Smuzhiyun __le16 cmpl_ring; 7769*4882a593Smuzhiyun __le16 seq_id; 7770*4882a593Smuzhiyun __le16 target_id; 7771*4882a593Smuzhiyun __le64 resp_addr; 7772*4882a593Smuzhiyun __le16 port_id; 7773*4882a593Smuzhiyun __le16 handle; 7774*4882a593Smuzhiyun u8 unused_0[4]; 7775*4882a593Smuzhiyun __le64 pattern_buf_addr; 7776*4882a593Smuzhiyun __le16 pattern_buf_size; 7777*4882a593Smuzhiyun u8 unused_1[6]; 7778*4882a593Smuzhiyun __le64 pattern_mask_addr; 7779*4882a593Smuzhiyun __le16 pattern_mask_size; 7780*4882a593Smuzhiyun u8 unused_2[6]; 7781*4882a593Smuzhiyun }; 7782*4882a593Smuzhiyun 7783*4882a593Smuzhiyun /* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 7784*4882a593Smuzhiyun struct hwrm_wol_filter_qcfg_output { 7785*4882a593Smuzhiyun __le16 error_code; 7786*4882a593Smuzhiyun __le16 req_type; 7787*4882a593Smuzhiyun __le16 seq_id; 7788*4882a593Smuzhiyun __le16 resp_len; 7789*4882a593Smuzhiyun __le16 next_handle; 7790*4882a593Smuzhiyun u8 wol_filter_id; 7791*4882a593Smuzhiyun u8 wol_type; 7792*4882a593Smuzhiyun #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 7793*4882a593Smuzhiyun #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 7794*4882a593Smuzhiyun #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 7795*4882a593Smuzhiyun #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 7796*4882a593Smuzhiyun __le32 unused_0; 7797*4882a593Smuzhiyun u8 mac_address[6]; 7798*4882a593Smuzhiyun __le16 pattern_offset; 7799*4882a593Smuzhiyun __le16 pattern_size; 7800*4882a593Smuzhiyun __le16 pattern_mask_size; 7801*4882a593Smuzhiyun u8 unused_1[3]; 7802*4882a593Smuzhiyun u8 valid; 7803*4882a593Smuzhiyun }; 7804*4882a593Smuzhiyun 7805*4882a593Smuzhiyun /* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 7806*4882a593Smuzhiyun struct hwrm_wol_reason_qcfg_input { 7807*4882a593Smuzhiyun __le16 req_type; 7808*4882a593Smuzhiyun __le16 cmpl_ring; 7809*4882a593Smuzhiyun __le16 seq_id; 7810*4882a593Smuzhiyun __le16 target_id; 7811*4882a593Smuzhiyun __le64 resp_addr; 7812*4882a593Smuzhiyun __le16 port_id; 7813*4882a593Smuzhiyun u8 unused_0[6]; 7814*4882a593Smuzhiyun __le64 wol_pkt_buf_addr; 7815*4882a593Smuzhiyun __le16 wol_pkt_buf_size; 7816*4882a593Smuzhiyun u8 unused_1[6]; 7817*4882a593Smuzhiyun }; 7818*4882a593Smuzhiyun 7819*4882a593Smuzhiyun /* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 7820*4882a593Smuzhiyun struct hwrm_wol_reason_qcfg_output { 7821*4882a593Smuzhiyun __le16 error_code; 7822*4882a593Smuzhiyun __le16 req_type; 7823*4882a593Smuzhiyun __le16 seq_id; 7824*4882a593Smuzhiyun __le16 resp_len; 7825*4882a593Smuzhiyun u8 wol_filter_id; 7826*4882a593Smuzhiyun u8 wol_reason; 7827*4882a593Smuzhiyun #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 7828*4882a593Smuzhiyun #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 7829*4882a593Smuzhiyun #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 7830*4882a593Smuzhiyun #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 7831*4882a593Smuzhiyun u8 wol_pkt_len; 7832*4882a593Smuzhiyun u8 unused_0[4]; 7833*4882a593Smuzhiyun u8 valid; 7834*4882a593Smuzhiyun }; 7835*4882a593Smuzhiyun 7836*4882a593Smuzhiyun /* hwrm_dbg_read_direct_input (size:256b/32B) */ 7837*4882a593Smuzhiyun struct hwrm_dbg_read_direct_input { 7838*4882a593Smuzhiyun __le16 req_type; 7839*4882a593Smuzhiyun __le16 cmpl_ring; 7840*4882a593Smuzhiyun __le16 seq_id; 7841*4882a593Smuzhiyun __le16 target_id; 7842*4882a593Smuzhiyun __le64 resp_addr; 7843*4882a593Smuzhiyun __le64 host_dest_addr; 7844*4882a593Smuzhiyun __le32 read_addr; 7845*4882a593Smuzhiyun __le32 read_len32; 7846*4882a593Smuzhiyun }; 7847*4882a593Smuzhiyun 7848*4882a593Smuzhiyun /* hwrm_dbg_read_direct_output (size:128b/16B) */ 7849*4882a593Smuzhiyun struct hwrm_dbg_read_direct_output { 7850*4882a593Smuzhiyun __le16 error_code; 7851*4882a593Smuzhiyun __le16 req_type; 7852*4882a593Smuzhiyun __le16 seq_id; 7853*4882a593Smuzhiyun __le16 resp_len; 7854*4882a593Smuzhiyun __le32 crc32; 7855*4882a593Smuzhiyun u8 unused_0[3]; 7856*4882a593Smuzhiyun u8 valid; 7857*4882a593Smuzhiyun }; 7858*4882a593Smuzhiyun 7859*4882a593Smuzhiyun /* hwrm_dbg_qcaps_input (size:192b/24B) */ 7860*4882a593Smuzhiyun struct hwrm_dbg_qcaps_input { 7861*4882a593Smuzhiyun __le16 req_type; 7862*4882a593Smuzhiyun __le16 cmpl_ring; 7863*4882a593Smuzhiyun __le16 seq_id; 7864*4882a593Smuzhiyun __le16 target_id; 7865*4882a593Smuzhiyun __le64 resp_addr; 7866*4882a593Smuzhiyun __le16 fid; 7867*4882a593Smuzhiyun u8 unused_0[6]; 7868*4882a593Smuzhiyun }; 7869*4882a593Smuzhiyun 7870*4882a593Smuzhiyun /* hwrm_dbg_qcaps_output (size:192b/24B) */ 7871*4882a593Smuzhiyun struct hwrm_dbg_qcaps_output { 7872*4882a593Smuzhiyun __le16 error_code; 7873*4882a593Smuzhiyun __le16 req_type; 7874*4882a593Smuzhiyun __le16 seq_id; 7875*4882a593Smuzhiyun __le16 resp_len; 7876*4882a593Smuzhiyun __le16 fid; 7877*4882a593Smuzhiyun u8 unused_0[2]; 7878*4882a593Smuzhiyun __le32 coredump_component_disable_caps; 7879*4882a593Smuzhiyun #define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM 0x1UL 7880*4882a593Smuzhiyun __le32 flags; 7881*4882a593Smuzhiyun #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL 7882*4882a593Smuzhiyun #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL 7883*4882a593Smuzhiyun #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL 7884*4882a593Smuzhiyun u8 unused_1[3]; 7885*4882a593Smuzhiyun u8 valid; 7886*4882a593Smuzhiyun }; 7887*4882a593Smuzhiyun 7888*4882a593Smuzhiyun /* hwrm_dbg_qcfg_input (size:192b/24B) */ 7889*4882a593Smuzhiyun struct hwrm_dbg_qcfg_input { 7890*4882a593Smuzhiyun __le16 req_type; 7891*4882a593Smuzhiyun __le16 cmpl_ring; 7892*4882a593Smuzhiyun __le16 seq_id; 7893*4882a593Smuzhiyun __le16 target_id; 7894*4882a593Smuzhiyun __le64 resp_addr; 7895*4882a593Smuzhiyun __le16 fid; 7896*4882a593Smuzhiyun __le16 flags; 7897*4882a593Smuzhiyun #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK 0x3UL 7898*4882a593Smuzhiyun #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0 7899*4882a593Smuzhiyun #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM 0x0UL 7900*4882a593Smuzhiyun #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR 0x1UL 7901*4882a593Smuzhiyun #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 0x2UL 7902*4882a593Smuzhiyun #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 7903*4882a593Smuzhiyun __le32 coredump_component_disable_flags; 7904*4882a593Smuzhiyun #define DBG_QCFG_REQ_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM 0x1UL 7905*4882a593Smuzhiyun }; 7906*4882a593Smuzhiyun 7907*4882a593Smuzhiyun /* hwrm_dbg_qcfg_output (size:256b/32B) */ 7908*4882a593Smuzhiyun struct hwrm_dbg_qcfg_output { 7909*4882a593Smuzhiyun __le16 error_code; 7910*4882a593Smuzhiyun __le16 req_type; 7911*4882a593Smuzhiyun __le16 seq_id; 7912*4882a593Smuzhiyun __le16 resp_len; 7913*4882a593Smuzhiyun __le16 fid; 7914*4882a593Smuzhiyun u8 unused_0[2]; 7915*4882a593Smuzhiyun __le32 coredump_size; 7916*4882a593Smuzhiyun __le32 flags; 7917*4882a593Smuzhiyun #define DBG_QCFG_RESP_FLAGS_UART_LOG 0x1UL 7918*4882a593Smuzhiyun #define DBG_QCFG_RESP_FLAGS_UART_LOG_SECONDARY 0x2UL 7919*4882a593Smuzhiyun #define DBG_QCFG_RESP_FLAGS_FW_TRACE 0x4UL 7920*4882a593Smuzhiyun #define DBG_QCFG_RESP_FLAGS_FW_TRACE_SECONDARY 0x8UL 7921*4882a593Smuzhiyun #define DBG_QCFG_RESP_FLAGS_DEBUG_NOTIFY 0x10UL 7922*4882a593Smuzhiyun #define DBG_QCFG_RESP_FLAGS_JTAG_DEBUG 0x20UL 7923*4882a593Smuzhiyun __le16 async_cmpl_ring; 7924*4882a593Smuzhiyun u8 unused_2[2]; 7925*4882a593Smuzhiyun __le32 crashdump_size; 7926*4882a593Smuzhiyun u8 unused_3[3]; 7927*4882a593Smuzhiyun u8 valid; 7928*4882a593Smuzhiyun }; 7929*4882a593Smuzhiyun 7930*4882a593Smuzhiyun /* coredump_segment_record (size:128b/16B) */ 7931*4882a593Smuzhiyun struct coredump_segment_record { 7932*4882a593Smuzhiyun __le16 component_id; 7933*4882a593Smuzhiyun __le16 segment_id; 7934*4882a593Smuzhiyun __le16 max_instances; 7935*4882a593Smuzhiyun u8 version_hi; 7936*4882a593Smuzhiyun u8 version_low; 7937*4882a593Smuzhiyun u8 seg_flags; 7938*4882a593Smuzhiyun u8 compress_flags; 7939*4882a593Smuzhiyun #define SFLAG_COMPRESSED_ZLIB 0x1UL 7940*4882a593Smuzhiyun u8 unused_0[2]; 7941*4882a593Smuzhiyun __le32 segment_len; 7942*4882a593Smuzhiyun }; 7943*4882a593Smuzhiyun 7944*4882a593Smuzhiyun /* hwrm_dbg_coredump_list_input (size:256b/32B) */ 7945*4882a593Smuzhiyun struct hwrm_dbg_coredump_list_input { 7946*4882a593Smuzhiyun __le16 req_type; 7947*4882a593Smuzhiyun __le16 cmpl_ring; 7948*4882a593Smuzhiyun __le16 seq_id; 7949*4882a593Smuzhiyun __le16 target_id; 7950*4882a593Smuzhiyun __le64 resp_addr; 7951*4882a593Smuzhiyun __le64 host_dest_addr; 7952*4882a593Smuzhiyun __le32 host_buf_len; 7953*4882a593Smuzhiyun __le16 seq_no; 7954*4882a593Smuzhiyun u8 flags; 7955*4882a593Smuzhiyun #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL 7956*4882a593Smuzhiyun u8 unused_0[1]; 7957*4882a593Smuzhiyun }; 7958*4882a593Smuzhiyun 7959*4882a593Smuzhiyun /* hwrm_dbg_coredump_list_output (size:128b/16B) */ 7960*4882a593Smuzhiyun struct hwrm_dbg_coredump_list_output { 7961*4882a593Smuzhiyun __le16 error_code; 7962*4882a593Smuzhiyun __le16 req_type; 7963*4882a593Smuzhiyun __le16 seq_id; 7964*4882a593Smuzhiyun __le16 resp_len; 7965*4882a593Smuzhiyun u8 flags; 7966*4882a593Smuzhiyun #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL 7967*4882a593Smuzhiyun u8 unused_0; 7968*4882a593Smuzhiyun __le16 total_segments; 7969*4882a593Smuzhiyun __le16 data_len; 7970*4882a593Smuzhiyun u8 unused_1; 7971*4882a593Smuzhiyun u8 valid; 7972*4882a593Smuzhiyun }; 7973*4882a593Smuzhiyun 7974*4882a593Smuzhiyun /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ 7975*4882a593Smuzhiyun struct hwrm_dbg_coredump_initiate_input { 7976*4882a593Smuzhiyun __le16 req_type; 7977*4882a593Smuzhiyun __le16 cmpl_ring; 7978*4882a593Smuzhiyun __le16 seq_id; 7979*4882a593Smuzhiyun __le16 target_id; 7980*4882a593Smuzhiyun __le64 resp_addr; 7981*4882a593Smuzhiyun __le16 component_id; 7982*4882a593Smuzhiyun __le16 segment_id; 7983*4882a593Smuzhiyun __le16 instance; 7984*4882a593Smuzhiyun __le16 unused_0; 7985*4882a593Smuzhiyun u8 seg_flags; 7986*4882a593Smuzhiyun u8 unused_1[7]; 7987*4882a593Smuzhiyun }; 7988*4882a593Smuzhiyun 7989*4882a593Smuzhiyun /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ 7990*4882a593Smuzhiyun struct hwrm_dbg_coredump_initiate_output { 7991*4882a593Smuzhiyun __le16 error_code; 7992*4882a593Smuzhiyun __le16 req_type; 7993*4882a593Smuzhiyun __le16 seq_id; 7994*4882a593Smuzhiyun __le16 resp_len; 7995*4882a593Smuzhiyun u8 unused_0[7]; 7996*4882a593Smuzhiyun u8 valid; 7997*4882a593Smuzhiyun }; 7998*4882a593Smuzhiyun 7999*4882a593Smuzhiyun /* coredump_data_hdr (size:128b/16B) */ 8000*4882a593Smuzhiyun struct coredump_data_hdr { 8001*4882a593Smuzhiyun __le32 address; 8002*4882a593Smuzhiyun __le32 flags_length; 8003*4882a593Smuzhiyun __le32 instance; 8004*4882a593Smuzhiyun __le32 next_offset; 8005*4882a593Smuzhiyun }; 8006*4882a593Smuzhiyun 8007*4882a593Smuzhiyun /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ 8008*4882a593Smuzhiyun struct hwrm_dbg_coredump_retrieve_input { 8009*4882a593Smuzhiyun __le16 req_type; 8010*4882a593Smuzhiyun __le16 cmpl_ring; 8011*4882a593Smuzhiyun __le16 seq_id; 8012*4882a593Smuzhiyun __le16 target_id; 8013*4882a593Smuzhiyun __le64 resp_addr; 8014*4882a593Smuzhiyun __le64 host_dest_addr; 8015*4882a593Smuzhiyun __le32 host_buf_len; 8016*4882a593Smuzhiyun __le32 unused_0; 8017*4882a593Smuzhiyun __le16 component_id; 8018*4882a593Smuzhiyun __le16 segment_id; 8019*4882a593Smuzhiyun __le16 instance; 8020*4882a593Smuzhiyun __le16 unused_1; 8021*4882a593Smuzhiyun u8 seg_flags; 8022*4882a593Smuzhiyun u8 unused_2; 8023*4882a593Smuzhiyun __le16 unused_3; 8024*4882a593Smuzhiyun __le32 unused_4; 8025*4882a593Smuzhiyun __le32 seq_no; 8026*4882a593Smuzhiyun __le32 unused_5; 8027*4882a593Smuzhiyun }; 8028*4882a593Smuzhiyun 8029*4882a593Smuzhiyun /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ 8030*4882a593Smuzhiyun struct hwrm_dbg_coredump_retrieve_output { 8031*4882a593Smuzhiyun __le16 error_code; 8032*4882a593Smuzhiyun __le16 req_type; 8033*4882a593Smuzhiyun __le16 seq_id; 8034*4882a593Smuzhiyun __le16 resp_len; 8035*4882a593Smuzhiyun u8 flags; 8036*4882a593Smuzhiyun #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL 8037*4882a593Smuzhiyun u8 unused_0; 8038*4882a593Smuzhiyun __le16 data_len; 8039*4882a593Smuzhiyun u8 unused_1[3]; 8040*4882a593Smuzhiyun u8 valid; 8041*4882a593Smuzhiyun }; 8042*4882a593Smuzhiyun 8043*4882a593Smuzhiyun /* hwrm_dbg_ring_info_get_input (size:192b/24B) */ 8044*4882a593Smuzhiyun struct hwrm_dbg_ring_info_get_input { 8045*4882a593Smuzhiyun __le16 req_type; 8046*4882a593Smuzhiyun __le16 cmpl_ring; 8047*4882a593Smuzhiyun __le16 seq_id; 8048*4882a593Smuzhiyun __le16 target_id; 8049*4882a593Smuzhiyun __le64 resp_addr; 8050*4882a593Smuzhiyun u8 ring_type; 8051*4882a593Smuzhiyun #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL 8052*4882a593Smuzhiyun #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL 8053*4882a593Smuzhiyun #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL 8054*4882a593Smuzhiyun #define DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 0x3UL 8055*4882a593Smuzhiyun #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 8056*4882a593Smuzhiyun u8 unused_0[3]; 8057*4882a593Smuzhiyun __le32 fw_ring_id; 8058*4882a593Smuzhiyun }; 8059*4882a593Smuzhiyun 8060*4882a593Smuzhiyun /* hwrm_dbg_ring_info_get_output (size:192b/24B) */ 8061*4882a593Smuzhiyun struct hwrm_dbg_ring_info_get_output { 8062*4882a593Smuzhiyun __le16 error_code; 8063*4882a593Smuzhiyun __le16 req_type; 8064*4882a593Smuzhiyun __le16 seq_id; 8065*4882a593Smuzhiyun __le16 resp_len; 8066*4882a593Smuzhiyun __le32 producer_index; 8067*4882a593Smuzhiyun __le32 consumer_index; 8068*4882a593Smuzhiyun __le32 cag_vector_ctrl; 8069*4882a593Smuzhiyun u8 unused_0[3]; 8070*4882a593Smuzhiyun u8 valid; 8071*4882a593Smuzhiyun }; 8072*4882a593Smuzhiyun 8073*4882a593Smuzhiyun /* hwrm_nvm_read_input (size:320b/40B) */ 8074*4882a593Smuzhiyun struct hwrm_nvm_read_input { 8075*4882a593Smuzhiyun __le16 req_type; 8076*4882a593Smuzhiyun __le16 cmpl_ring; 8077*4882a593Smuzhiyun __le16 seq_id; 8078*4882a593Smuzhiyun __le16 target_id; 8079*4882a593Smuzhiyun __le64 resp_addr; 8080*4882a593Smuzhiyun __le64 host_dest_addr; 8081*4882a593Smuzhiyun __le16 dir_idx; 8082*4882a593Smuzhiyun u8 unused_0[2]; 8083*4882a593Smuzhiyun __le32 offset; 8084*4882a593Smuzhiyun __le32 len; 8085*4882a593Smuzhiyun u8 unused_1[4]; 8086*4882a593Smuzhiyun }; 8087*4882a593Smuzhiyun 8088*4882a593Smuzhiyun /* hwrm_nvm_read_output (size:128b/16B) */ 8089*4882a593Smuzhiyun struct hwrm_nvm_read_output { 8090*4882a593Smuzhiyun __le16 error_code; 8091*4882a593Smuzhiyun __le16 req_type; 8092*4882a593Smuzhiyun __le16 seq_id; 8093*4882a593Smuzhiyun __le16 resp_len; 8094*4882a593Smuzhiyun u8 unused_0[7]; 8095*4882a593Smuzhiyun u8 valid; 8096*4882a593Smuzhiyun }; 8097*4882a593Smuzhiyun 8098*4882a593Smuzhiyun /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 8099*4882a593Smuzhiyun struct hwrm_nvm_get_dir_entries_input { 8100*4882a593Smuzhiyun __le16 req_type; 8101*4882a593Smuzhiyun __le16 cmpl_ring; 8102*4882a593Smuzhiyun __le16 seq_id; 8103*4882a593Smuzhiyun __le16 target_id; 8104*4882a593Smuzhiyun __le64 resp_addr; 8105*4882a593Smuzhiyun __le64 host_dest_addr; 8106*4882a593Smuzhiyun }; 8107*4882a593Smuzhiyun 8108*4882a593Smuzhiyun /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 8109*4882a593Smuzhiyun struct hwrm_nvm_get_dir_entries_output { 8110*4882a593Smuzhiyun __le16 error_code; 8111*4882a593Smuzhiyun __le16 req_type; 8112*4882a593Smuzhiyun __le16 seq_id; 8113*4882a593Smuzhiyun __le16 resp_len; 8114*4882a593Smuzhiyun u8 unused_0[7]; 8115*4882a593Smuzhiyun u8 valid; 8116*4882a593Smuzhiyun }; 8117*4882a593Smuzhiyun 8118*4882a593Smuzhiyun /* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 8119*4882a593Smuzhiyun struct hwrm_nvm_get_dir_info_input { 8120*4882a593Smuzhiyun __le16 req_type; 8121*4882a593Smuzhiyun __le16 cmpl_ring; 8122*4882a593Smuzhiyun __le16 seq_id; 8123*4882a593Smuzhiyun __le16 target_id; 8124*4882a593Smuzhiyun __le64 resp_addr; 8125*4882a593Smuzhiyun }; 8126*4882a593Smuzhiyun 8127*4882a593Smuzhiyun /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 8128*4882a593Smuzhiyun struct hwrm_nvm_get_dir_info_output { 8129*4882a593Smuzhiyun __le16 error_code; 8130*4882a593Smuzhiyun __le16 req_type; 8131*4882a593Smuzhiyun __le16 seq_id; 8132*4882a593Smuzhiyun __le16 resp_len; 8133*4882a593Smuzhiyun __le32 entries; 8134*4882a593Smuzhiyun __le32 entry_length; 8135*4882a593Smuzhiyun u8 unused_0[7]; 8136*4882a593Smuzhiyun u8 valid; 8137*4882a593Smuzhiyun }; 8138*4882a593Smuzhiyun 8139*4882a593Smuzhiyun /* hwrm_nvm_write_input (size:384b/48B) */ 8140*4882a593Smuzhiyun struct hwrm_nvm_write_input { 8141*4882a593Smuzhiyun __le16 req_type; 8142*4882a593Smuzhiyun __le16 cmpl_ring; 8143*4882a593Smuzhiyun __le16 seq_id; 8144*4882a593Smuzhiyun __le16 target_id; 8145*4882a593Smuzhiyun __le64 resp_addr; 8146*4882a593Smuzhiyun __le64 host_src_addr; 8147*4882a593Smuzhiyun __le16 dir_type; 8148*4882a593Smuzhiyun __le16 dir_ordinal; 8149*4882a593Smuzhiyun __le16 dir_ext; 8150*4882a593Smuzhiyun __le16 dir_attr; 8151*4882a593Smuzhiyun __le32 dir_data_length; 8152*4882a593Smuzhiyun __le16 option; 8153*4882a593Smuzhiyun __le16 flags; 8154*4882a593Smuzhiyun #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 8155*4882a593Smuzhiyun __le32 dir_item_length; 8156*4882a593Smuzhiyun __le32 unused_0; 8157*4882a593Smuzhiyun }; 8158*4882a593Smuzhiyun 8159*4882a593Smuzhiyun /* hwrm_nvm_write_output (size:128b/16B) */ 8160*4882a593Smuzhiyun struct hwrm_nvm_write_output { 8161*4882a593Smuzhiyun __le16 error_code; 8162*4882a593Smuzhiyun __le16 req_type; 8163*4882a593Smuzhiyun __le16 seq_id; 8164*4882a593Smuzhiyun __le16 resp_len; 8165*4882a593Smuzhiyun __le32 dir_item_length; 8166*4882a593Smuzhiyun __le16 dir_idx; 8167*4882a593Smuzhiyun u8 unused_0; 8168*4882a593Smuzhiyun u8 valid; 8169*4882a593Smuzhiyun }; 8170*4882a593Smuzhiyun 8171*4882a593Smuzhiyun /* hwrm_nvm_write_cmd_err (size:64b/8B) */ 8172*4882a593Smuzhiyun struct hwrm_nvm_write_cmd_err { 8173*4882a593Smuzhiyun u8 code; 8174*4882a593Smuzhiyun #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 8175*4882a593Smuzhiyun #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 8176*4882a593Smuzhiyun #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 8177*4882a593Smuzhiyun #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 8178*4882a593Smuzhiyun u8 unused_0[7]; 8179*4882a593Smuzhiyun }; 8180*4882a593Smuzhiyun 8181*4882a593Smuzhiyun /* hwrm_nvm_modify_input (size:320b/40B) */ 8182*4882a593Smuzhiyun struct hwrm_nvm_modify_input { 8183*4882a593Smuzhiyun __le16 req_type; 8184*4882a593Smuzhiyun __le16 cmpl_ring; 8185*4882a593Smuzhiyun __le16 seq_id; 8186*4882a593Smuzhiyun __le16 target_id; 8187*4882a593Smuzhiyun __le64 resp_addr; 8188*4882a593Smuzhiyun __le64 host_src_addr; 8189*4882a593Smuzhiyun __le16 dir_idx; 8190*4882a593Smuzhiyun __le16 flags; 8191*4882a593Smuzhiyun #define NVM_MODIFY_REQ_FLAGS_BATCH_MODE 0x1UL 8192*4882a593Smuzhiyun #define NVM_MODIFY_REQ_FLAGS_BATCH_LAST 0x2UL 8193*4882a593Smuzhiyun __le32 offset; 8194*4882a593Smuzhiyun __le32 len; 8195*4882a593Smuzhiyun u8 unused_1[4]; 8196*4882a593Smuzhiyun }; 8197*4882a593Smuzhiyun 8198*4882a593Smuzhiyun /* hwrm_nvm_modify_output (size:128b/16B) */ 8199*4882a593Smuzhiyun struct hwrm_nvm_modify_output { 8200*4882a593Smuzhiyun __le16 error_code; 8201*4882a593Smuzhiyun __le16 req_type; 8202*4882a593Smuzhiyun __le16 seq_id; 8203*4882a593Smuzhiyun __le16 resp_len; 8204*4882a593Smuzhiyun u8 unused_0[7]; 8205*4882a593Smuzhiyun u8 valid; 8206*4882a593Smuzhiyun }; 8207*4882a593Smuzhiyun 8208*4882a593Smuzhiyun /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 8209*4882a593Smuzhiyun struct hwrm_nvm_find_dir_entry_input { 8210*4882a593Smuzhiyun __le16 req_type; 8211*4882a593Smuzhiyun __le16 cmpl_ring; 8212*4882a593Smuzhiyun __le16 seq_id; 8213*4882a593Smuzhiyun __le16 target_id; 8214*4882a593Smuzhiyun __le64 resp_addr; 8215*4882a593Smuzhiyun __le32 enables; 8216*4882a593Smuzhiyun #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 8217*4882a593Smuzhiyun __le16 dir_idx; 8218*4882a593Smuzhiyun __le16 dir_type; 8219*4882a593Smuzhiyun __le16 dir_ordinal; 8220*4882a593Smuzhiyun __le16 dir_ext; 8221*4882a593Smuzhiyun u8 opt_ordinal; 8222*4882a593Smuzhiyun #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 8223*4882a593Smuzhiyun #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 8224*4882a593Smuzhiyun #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 8225*4882a593Smuzhiyun #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 8226*4882a593Smuzhiyun #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 8227*4882a593Smuzhiyun #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 8228*4882a593Smuzhiyun u8 unused_0[3]; 8229*4882a593Smuzhiyun }; 8230*4882a593Smuzhiyun 8231*4882a593Smuzhiyun /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 8232*4882a593Smuzhiyun struct hwrm_nvm_find_dir_entry_output { 8233*4882a593Smuzhiyun __le16 error_code; 8234*4882a593Smuzhiyun __le16 req_type; 8235*4882a593Smuzhiyun __le16 seq_id; 8236*4882a593Smuzhiyun __le16 resp_len; 8237*4882a593Smuzhiyun __le32 dir_item_length; 8238*4882a593Smuzhiyun __le32 dir_data_length; 8239*4882a593Smuzhiyun __le32 fw_ver; 8240*4882a593Smuzhiyun __le16 dir_ordinal; 8241*4882a593Smuzhiyun __le16 dir_idx; 8242*4882a593Smuzhiyun u8 unused_0[7]; 8243*4882a593Smuzhiyun u8 valid; 8244*4882a593Smuzhiyun }; 8245*4882a593Smuzhiyun 8246*4882a593Smuzhiyun /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 8247*4882a593Smuzhiyun struct hwrm_nvm_erase_dir_entry_input { 8248*4882a593Smuzhiyun __le16 req_type; 8249*4882a593Smuzhiyun __le16 cmpl_ring; 8250*4882a593Smuzhiyun __le16 seq_id; 8251*4882a593Smuzhiyun __le16 target_id; 8252*4882a593Smuzhiyun __le64 resp_addr; 8253*4882a593Smuzhiyun __le16 dir_idx; 8254*4882a593Smuzhiyun u8 unused_0[6]; 8255*4882a593Smuzhiyun }; 8256*4882a593Smuzhiyun 8257*4882a593Smuzhiyun /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 8258*4882a593Smuzhiyun struct hwrm_nvm_erase_dir_entry_output { 8259*4882a593Smuzhiyun __le16 error_code; 8260*4882a593Smuzhiyun __le16 req_type; 8261*4882a593Smuzhiyun __le16 seq_id; 8262*4882a593Smuzhiyun __le16 resp_len; 8263*4882a593Smuzhiyun u8 unused_0[7]; 8264*4882a593Smuzhiyun u8 valid; 8265*4882a593Smuzhiyun }; 8266*4882a593Smuzhiyun 8267*4882a593Smuzhiyun /* hwrm_nvm_get_dev_info_input (size:128b/16B) */ 8268*4882a593Smuzhiyun struct hwrm_nvm_get_dev_info_input { 8269*4882a593Smuzhiyun __le16 req_type; 8270*4882a593Smuzhiyun __le16 cmpl_ring; 8271*4882a593Smuzhiyun __le16 seq_id; 8272*4882a593Smuzhiyun __le16 target_id; 8273*4882a593Smuzhiyun __le64 resp_addr; 8274*4882a593Smuzhiyun }; 8275*4882a593Smuzhiyun 8276*4882a593Smuzhiyun /* hwrm_nvm_get_dev_info_output (size:640b/80B) */ 8277*4882a593Smuzhiyun struct hwrm_nvm_get_dev_info_output { 8278*4882a593Smuzhiyun __le16 error_code; 8279*4882a593Smuzhiyun __le16 req_type; 8280*4882a593Smuzhiyun __le16 seq_id; 8281*4882a593Smuzhiyun __le16 resp_len; 8282*4882a593Smuzhiyun __le16 manufacturer_id; 8283*4882a593Smuzhiyun __le16 device_id; 8284*4882a593Smuzhiyun __le32 sector_size; 8285*4882a593Smuzhiyun __le32 nvram_size; 8286*4882a593Smuzhiyun __le32 reserved_size; 8287*4882a593Smuzhiyun __le32 available_size; 8288*4882a593Smuzhiyun u8 nvm_cfg_ver_maj; 8289*4882a593Smuzhiyun u8 nvm_cfg_ver_min; 8290*4882a593Smuzhiyun u8 nvm_cfg_ver_upd; 8291*4882a593Smuzhiyun u8 flags; 8292*4882a593Smuzhiyun #define NVM_GET_DEV_INFO_RESP_FLAGS_FW_VER_VALID 0x1UL 8293*4882a593Smuzhiyun char pkg_name[16]; 8294*4882a593Smuzhiyun __le16 hwrm_fw_major; 8295*4882a593Smuzhiyun __le16 hwrm_fw_minor; 8296*4882a593Smuzhiyun __le16 hwrm_fw_build; 8297*4882a593Smuzhiyun __le16 hwrm_fw_patch; 8298*4882a593Smuzhiyun __le16 mgmt_fw_major; 8299*4882a593Smuzhiyun __le16 mgmt_fw_minor; 8300*4882a593Smuzhiyun __le16 mgmt_fw_build; 8301*4882a593Smuzhiyun __le16 mgmt_fw_patch; 8302*4882a593Smuzhiyun __le16 roce_fw_major; 8303*4882a593Smuzhiyun __le16 roce_fw_minor; 8304*4882a593Smuzhiyun __le16 roce_fw_build; 8305*4882a593Smuzhiyun __le16 roce_fw_patch; 8306*4882a593Smuzhiyun u8 unused_0[7]; 8307*4882a593Smuzhiyun u8 valid; 8308*4882a593Smuzhiyun }; 8309*4882a593Smuzhiyun 8310*4882a593Smuzhiyun /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 8311*4882a593Smuzhiyun struct hwrm_nvm_mod_dir_entry_input { 8312*4882a593Smuzhiyun __le16 req_type; 8313*4882a593Smuzhiyun __le16 cmpl_ring; 8314*4882a593Smuzhiyun __le16 seq_id; 8315*4882a593Smuzhiyun __le16 target_id; 8316*4882a593Smuzhiyun __le64 resp_addr; 8317*4882a593Smuzhiyun __le32 enables; 8318*4882a593Smuzhiyun #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 8319*4882a593Smuzhiyun __le16 dir_idx; 8320*4882a593Smuzhiyun __le16 dir_ordinal; 8321*4882a593Smuzhiyun __le16 dir_ext; 8322*4882a593Smuzhiyun __le16 dir_attr; 8323*4882a593Smuzhiyun __le32 checksum; 8324*4882a593Smuzhiyun }; 8325*4882a593Smuzhiyun 8326*4882a593Smuzhiyun /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 8327*4882a593Smuzhiyun struct hwrm_nvm_mod_dir_entry_output { 8328*4882a593Smuzhiyun __le16 error_code; 8329*4882a593Smuzhiyun __le16 req_type; 8330*4882a593Smuzhiyun __le16 seq_id; 8331*4882a593Smuzhiyun __le16 resp_len; 8332*4882a593Smuzhiyun u8 unused_0[7]; 8333*4882a593Smuzhiyun u8 valid; 8334*4882a593Smuzhiyun }; 8335*4882a593Smuzhiyun 8336*4882a593Smuzhiyun /* hwrm_nvm_verify_update_input (size:192b/24B) */ 8337*4882a593Smuzhiyun struct hwrm_nvm_verify_update_input { 8338*4882a593Smuzhiyun __le16 req_type; 8339*4882a593Smuzhiyun __le16 cmpl_ring; 8340*4882a593Smuzhiyun __le16 seq_id; 8341*4882a593Smuzhiyun __le16 target_id; 8342*4882a593Smuzhiyun __le64 resp_addr; 8343*4882a593Smuzhiyun __le16 dir_type; 8344*4882a593Smuzhiyun __le16 dir_ordinal; 8345*4882a593Smuzhiyun __le16 dir_ext; 8346*4882a593Smuzhiyun u8 unused_0[2]; 8347*4882a593Smuzhiyun }; 8348*4882a593Smuzhiyun 8349*4882a593Smuzhiyun /* hwrm_nvm_verify_update_output (size:128b/16B) */ 8350*4882a593Smuzhiyun struct hwrm_nvm_verify_update_output { 8351*4882a593Smuzhiyun __le16 error_code; 8352*4882a593Smuzhiyun __le16 req_type; 8353*4882a593Smuzhiyun __le16 seq_id; 8354*4882a593Smuzhiyun __le16 resp_len; 8355*4882a593Smuzhiyun u8 unused_0[7]; 8356*4882a593Smuzhiyun u8 valid; 8357*4882a593Smuzhiyun }; 8358*4882a593Smuzhiyun 8359*4882a593Smuzhiyun /* hwrm_nvm_install_update_input (size:192b/24B) */ 8360*4882a593Smuzhiyun struct hwrm_nvm_install_update_input { 8361*4882a593Smuzhiyun __le16 req_type; 8362*4882a593Smuzhiyun __le16 cmpl_ring; 8363*4882a593Smuzhiyun __le16 seq_id; 8364*4882a593Smuzhiyun __le16 target_id; 8365*4882a593Smuzhiyun __le64 resp_addr; 8366*4882a593Smuzhiyun __le32 install_type; 8367*4882a593Smuzhiyun #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 8368*4882a593Smuzhiyun #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 8369*4882a593Smuzhiyun #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 8370*4882a593Smuzhiyun __le16 flags; 8371*4882a593Smuzhiyun #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 8372*4882a593Smuzhiyun #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 8373*4882a593Smuzhiyun #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 8374*4882a593Smuzhiyun #define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY 0x8UL 8375*4882a593Smuzhiyun u8 unused_0[2]; 8376*4882a593Smuzhiyun }; 8377*4882a593Smuzhiyun 8378*4882a593Smuzhiyun /* hwrm_nvm_install_update_output (size:192b/24B) */ 8379*4882a593Smuzhiyun struct hwrm_nvm_install_update_output { 8380*4882a593Smuzhiyun __le16 error_code; 8381*4882a593Smuzhiyun __le16 req_type; 8382*4882a593Smuzhiyun __le16 seq_id; 8383*4882a593Smuzhiyun __le16 resp_len; 8384*4882a593Smuzhiyun __le64 installed_items; 8385*4882a593Smuzhiyun u8 result; 8386*4882a593Smuzhiyun #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 8387*4882a593Smuzhiyun #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 8388*4882a593Smuzhiyun u8 problem_item; 8389*4882a593Smuzhiyun #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 8390*4882a593Smuzhiyun #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 8391*4882a593Smuzhiyun #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 8392*4882a593Smuzhiyun u8 reset_required; 8393*4882a593Smuzhiyun #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 8394*4882a593Smuzhiyun #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 8395*4882a593Smuzhiyun #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 8396*4882a593Smuzhiyun #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 8397*4882a593Smuzhiyun u8 unused_0[4]; 8398*4882a593Smuzhiyun u8 valid; 8399*4882a593Smuzhiyun }; 8400*4882a593Smuzhiyun 8401*4882a593Smuzhiyun /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 8402*4882a593Smuzhiyun struct hwrm_nvm_install_update_cmd_err { 8403*4882a593Smuzhiyun u8 code; 8404*4882a593Smuzhiyun #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 8405*4882a593Smuzhiyun #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 8406*4882a593Smuzhiyun #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 8407*4882a593Smuzhiyun #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 8408*4882a593Smuzhiyun u8 unused_0[7]; 8409*4882a593Smuzhiyun }; 8410*4882a593Smuzhiyun 8411*4882a593Smuzhiyun /* hwrm_nvm_get_variable_input (size:320b/40B) */ 8412*4882a593Smuzhiyun struct hwrm_nvm_get_variable_input { 8413*4882a593Smuzhiyun __le16 req_type; 8414*4882a593Smuzhiyun __le16 cmpl_ring; 8415*4882a593Smuzhiyun __le16 seq_id; 8416*4882a593Smuzhiyun __le16 target_id; 8417*4882a593Smuzhiyun __le64 resp_addr; 8418*4882a593Smuzhiyun __le64 dest_data_addr; 8419*4882a593Smuzhiyun __le16 data_len; 8420*4882a593Smuzhiyun __le16 option_num; 8421*4882a593Smuzhiyun #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 8422*4882a593Smuzhiyun #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 8423*4882a593Smuzhiyun #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 8424*4882a593Smuzhiyun __le16 dimensions; 8425*4882a593Smuzhiyun __le16 index_0; 8426*4882a593Smuzhiyun __le16 index_1; 8427*4882a593Smuzhiyun __le16 index_2; 8428*4882a593Smuzhiyun __le16 index_3; 8429*4882a593Smuzhiyun u8 flags; 8430*4882a593Smuzhiyun #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 8431*4882a593Smuzhiyun u8 unused_0; 8432*4882a593Smuzhiyun }; 8433*4882a593Smuzhiyun 8434*4882a593Smuzhiyun /* hwrm_nvm_get_variable_output (size:128b/16B) */ 8435*4882a593Smuzhiyun struct hwrm_nvm_get_variable_output { 8436*4882a593Smuzhiyun __le16 error_code; 8437*4882a593Smuzhiyun __le16 req_type; 8438*4882a593Smuzhiyun __le16 seq_id; 8439*4882a593Smuzhiyun __le16 resp_len; 8440*4882a593Smuzhiyun __le16 data_len; 8441*4882a593Smuzhiyun __le16 option_num; 8442*4882a593Smuzhiyun #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 8443*4882a593Smuzhiyun #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 8444*4882a593Smuzhiyun #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 8445*4882a593Smuzhiyun u8 unused_0[3]; 8446*4882a593Smuzhiyun u8 valid; 8447*4882a593Smuzhiyun }; 8448*4882a593Smuzhiyun 8449*4882a593Smuzhiyun /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 8450*4882a593Smuzhiyun struct hwrm_nvm_get_variable_cmd_err { 8451*4882a593Smuzhiyun u8 code; 8452*4882a593Smuzhiyun #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 8453*4882a593Smuzhiyun #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 8454*4882a593Smuzhiyun #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 8455*4882a593Smuzhiyun #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 8456*4882a593Smuzhiyun #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 8457*4882a593Smuzhiyun u8 unused_0[7]; 8458*4882a593Smuzhiyun }; 8459*4882a593Smuzhiyun 8460*4882a593Smuzhiyun /* hwrm_nvm_set_variable_input (size:320b/40B) */ 8461*4882a593Smuzhiyun struct hwrm_nvm_set_variable_input { 8462*4882a593Smuzhiyun __le16 req_type; 8463*4882a593Smuzhiyun __le16 cmpl_ring; 8464*4882a593Smuzhiyun __le16 seq_id; 8465*4882a593Smuzhiyun __le16 target_id; 8466*4882a593Smuzhiyun __le64 resp_addr; 8467*4882a593Smuzhiyun __le64 src_data_addr; 8468*4882a593Smuzhiyun __le16 data_len; 8469*4882a593Smuzhiyun __le16 option_num; 8470*4882a593Smuzhiyun #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 8471*4882a593Smuzhiyun #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 8472*4882a593Smuzhiyun #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 8473*4882a593Smuzhiyun __le16 dimensions; 8474*4882a593Smuzhiyun __le16 index_0; 8475*4882a593Smuzhiyun __le16 index_1; 8476*4882a593Smuzhiyun __le16 index_2; 8477*4882a593Smuzhiyun __le16 index_3; 8478*4882a593Smuzhiyun u8 flags; 8479*4882a593Smuzhiyun #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 8480*4882a593Smuzhiyun #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 8481*4882a593Smuzhiyun #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 8482*4882a593Smuzhiyun #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 8483*4882a593Smuzhiyun #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 8484*4882a593Smuzhiyun #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1) 8485*4882a593Smuzhiyun #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1) 8486*4882a593Smuzhiyun #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH 8487*4882a593Smuzhiyun #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL 8488*4882a593Smuzhiyun #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4 8489*4882a593Smuzhiyun #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL 8490*4882a593Smuzhiyun u8 unused_0; 8491*4882a593Smuzhiyun }; 8492*4882a593Smuzhiyun 8493*4882a593Smuzhiyun /* hwrm_nvm_set_variable_output (size:128b/16B) */ 8494*4882a593Smuzhiyun struct hwrm_nvm_set_variable_output { 8495*4882a593Smuzhiyun __le16 error_code; 8496*4882a593Smuzhiyun __le16 req_type; 8497*4882a593Smuzhiyun __le16 seq_id; 8498*4882a593Smuzhiyun __le16 resp_len; 8499*4882a593Smuzhiyun u8 unused_0[7]; 8500*4882a593Smuzhiyun u8 valid; 8501*4882a593Smuzhiyun }; 8502*4882a593Smuzhiyun 8503*4882a593Smuzhiyun /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 8504*4882a593Smuzhiyun struct hwrm_nvm_set_variable_cmd_err { 8505*4882a593Smuzhiyun u8 code; 8506*4882a593Smuzhiyun #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 8507*4882a593Smuzhiyun #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 8508*4882a593Smuzhiyun #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 8509*4882a593Smuzhiyun #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 8510*4882a593Smuzhiyun u8 unused_0[7]; 8511*4882a593Smuzhiyun }; 8512*4882a593Smuzhiyun 8513*4882a593Smuzhiyun /* hwrm_selftest_qlist_input (size:128b/16B) */ 8514*4882a593Smuzhiyun struct hwrm_selftest_qlist_input { 8515*4882a593Smuzhiyun __le16 req_type; 8516*4882a593Smuzhiyun __le16 cmpl_ring; 8517*4882a593Smuzhiyun __le16 seq_id; 8518*4882a593Smuzhiyun __le16 target_id; 8519*4882a593Smuzhiyun __le64 resp_addr; 8520*4882a593Smuzhiyun }; 8521*4882a593Smuzhiyun 8522*4882a593Smuzhiyun /* hwrm_selftest_qlist_output (size:2240b/280B) */ 8523*4882a593Smuzhiyun struct hwrm_selftest_qlist_output { 8524*4882a593Smuzhiyun __le16 error_code; 8525*4882a593Smuzhiyun __le16 req_type; 8526*4882a593Smuzhiyun __le16 seq_id; 8527*4882a593Smuzhiyun __le16 resp_len; 8528*4882a593Smuzhiyun u8 num_tests; 8529*4882a593Smuzhiyun u8 available_tests; 8530*4882a593Smuzhiyun #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 8531*4882a593Smuzhiyun #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 8532*4882a593Smuzhiyun #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 8533*4882a593Smuzhiyun #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 8534*4882a593Smuzhiyun #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 8535*4882a593Smuzhiyun #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 8536*4882a593Smuzhiyun u8 offline_tests; 8537*4882a593Smuzhiyun #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 8538*4882a593Smuzhiyun #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 8539*4882a593Smuzhiyun #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 8540*4882a593Smuzhiyun #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 8541*4882a593Smuzhiyun #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 8542*4882a593Smuzhiyun #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 8543*4882a593Smuzhiyun u8 unused_0; 8544*4882a593Smuzhiyun __le16 test_timeout; 8545*4882a593Smuzhiyun u8 unused_1[2]; 8546*4882a593Smuzhiyun char test0_name[32]; 8547*4882a593Smuzhiyun char test1_name[32]; 8548*4882a593Smuzhiyun char test2_name[32]; 8549*4882a593Smuzhiyun char test3_name[32]; 8550*4882a593Smuzhiyun char test4_name[32]; 8551*4882a593Smuzhiyun char test5_name[32]; 8552*4882a593Smuzhiyun char test6_name[32]; 8553*4882a593Smuzhiyun char test7_name[32]; 8554*4882a593Smuzhiyun u8 eyescope_target_BER_support; 8555*4882a593Smuzhiyun #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED 0x0UL 8556*4882a593Smuzhiyun #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED 0x1UL 8557*4882a593Smuzhiyun #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL 8558*4882a593Smuzhiyun #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL 8559*4882a593Smuzhiyun #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL 8560*4882a593Smuzhiyun #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 8561*4882a593Smuzhiyun u8 unused_2[6]; 8562*4882a593Smuzhiyun u8 valid; 8563*4882a593Smuzhiyun }; 8564*4882a593Smuzhiyun 8565*4882a593Smuzhiyun /* hwrm_selftest_exec_input (size:192b/24B) */ 8566*4882a593Smuzhiyun struct hwrm_selftest_exec_input { 8567*4882a593Smuzhiyun __le16 req_type; 8568*4882a593Smuzhiyun __le16 cmpl_ring; 8569*4882a593Smuzhiyun __le16 seq_id; 8570*4882a593Smuzhiyun __le16 target_id; 8571*4882a593Smuzhiyun __le64 resp_addr; 8572*4882a593Smuzhiyun u8 flags; 8573*4882a593Smuzhiyun #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 8574*4882a593Smuzhiyun #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 8575*4882a593Smuzhiyun #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 8576*4882a593Smuzhiyun #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 8577*4882a593Smuzhiyun #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 8578*4882a593Smuzhiyun #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 8579*4882a593Smuzhiyun u8 unused_0[7]; 8580*4882a593Smuzhiyun }; 8581*4882a593Smuzhiyun 8582*4882a593Smuzhiyun /* hwrm_selftest_exec_output (size:128b/16B) */ 8583*4882a593Smuzhiyun struct hwrm_selftest_exec_output { 8584*4882a593Smuzhiyun __le16 error_code; 8585*4882a593Smuzhiyun __le16 req_type; 8586*4882a593Smuzhiyun __le16 seq_id; 8587*4882a593Smuzhiyun __le16 resp_len; 8588*4882a593Smuzhiyun u8 requested_tests; 8589*4882a593Smuzhiyun #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 8590*4882a593Smuzhiyun #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 8591*4882a593Smuzhiyun #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 8592*4882a593Smuzhiyun #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 8593*4882a593Smuzhiyun #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 8594*4882a593Smuzhiyun #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 8595*4882a593Smuzhiyun u8 test_success; 8596*4882a593Smuzhiyun #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 8597*4882a593Smuzhiyun #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 8598*4882a593Smuzhiyun #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 8599*4882a593Smuzhiyun #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 8600*4882a593Smuzhiyun #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 8601*4882a593Smuzhiyun #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 8602*4882a593Smuzhiyun u8 unused_0[5]; 8603*4882a593Smuzhiyun u8 valid; 8604*4882a593Smuzhiyun }; 8605*4882a593Smuzhiyun 8606*4882a593Smuzhiyun /* hwrm_selftest_irq_input (size:128b/16B) */ 8607*4882a593Smuzhiyun struct hwrm_selftest_irq_input { 8608*4882a593Smuzhiyun __le16 req_type; 8609*4882a593Smuzhiyun __le16 cmpl_ring; 8610*4882a593Smuzhiyun __le16 seq_id; 8611*4882a593Smuzhiyun __le16 target_id; 8612*4882a593Smuzhiyun __le64 resp_addr; 8613*4882a593Smuzhiyun }; 8614*4882a593Smuzhiyun 8615*4882a593Smuzhiyun /* hwrm_selftest_irq_output (size:128b/16B) */ 8616*4882a593Smuzhiyun struct hwrm_selftest_irq_output { 8617*4882a593Smuzhiyun __le16 error_code; 8618*4882a593Smuzhiyun __le16 req_type; 8619*4882a593Smuzhiyun __le16 seq_id; 8620*4882a593Smuzhiyun __le16 resp_len; 8621*4882a593Smuzhiyun u8 unused_0[7]; 8622*4882a593Smuzhiyun u8 valid; 8623*4882a593Smuzhiyun }; 8624*4882a593Smuzhiyun 8625*4882a593Smuzhiyun /* db_push_info (size:64b/8B) */ 8626*4882a593Smuzhiyun struct db_push_info { 8627*4882a593Smuzhiyun u32 push_size_push_index; 8628*4882a593Smuzhiyun #define DB_PUSH_INFO_PUSH_INDEX_MASK 0xffffffUL 8629*4882a593Smuzhiyun #define DB_PUSH_INFO_PUSH_INDEX_SFT 0 8630*4882a593Smuzhiyun #define DB_PUSH_INFO_PUSH_SIZE_MASK 0x1f000000UL 8631*4882a593Smuzhiyun #define DB_PUSH_INFO_PUSH_SIZE_SFT 24 8632*4882a593Smuzhiyun u32 reserved32; 8633*4882a593Smuzhiyun }; 8634*4882a593Smuzhiyun 8635*4882a593Smuzhiyun /* fw_status_reg (size:32b/4B) */ 8636*4882a593Smuzhiyun struct fw_status_reg { 8637*4882a593Smuzhiyun u32 fw_status; 8638*4882a593Smuzhiyun #define FW_STATUS_REG_CODE_MASK 0xffffUL 8639*4882a593Smuzhiyun #define FW_STATUS_REG_CODE_SFT 0 8640*4882a593Smuzhiyun #define FW_STATUS_REG_CODE_READY 0x8000UL 8641*4882a593Smuzhiyun #define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY 8642*4882a593Smuzhiyun #define FW_STATUS_REG_IMAGE_DEGRADED 0x10000UL 8643*4882a593Smuzhiyun #define FW_STATUS_REG_RECOVERABLE 0x20000UL 8644*4882a593Smuzhiyun #define FW_STATUS_REG_CRASHDUMP_ONGOING 0x40000UL 8645*4882a593Smuzhiyun #define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL 8646*4882a593Smuzhiyun #define FW_STATUS_REG_SHUTDOWN 0x100000UL 8647*4882a593Smuzhiyun #define FW_STATUS_REG_CRASHED_NO_MASTER 0x200000UL 8648*4882a593Smuzhiyun }; 8649*4882a593Smuzhiyun 8650*4882a593Smuzhiyun /* hcomm_status (size:64b/8B) */ 8651*4882a593Smuzhiyun struct hcomm_status { 8652*4882a593Smuzhiyun u32 sig_ver; 8653*4882a593Smuzhiyun #define HCOMM_STATUS_VER_MASK 0xffUL 8654*4882a593Smuzhiyun #define HCOMM_STATUS_VER_SFT 0 8655*4882a593Smuzhiyun #define HCOMM_STATUS_VER_LATEST 0x1UL 8656*4882a593Smuzhiyun #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST 8657*4882a593Smuzhiyun #define HCOMM_STATUS_SIGNATURE_MASK 0xffffff00UL 8658*4882a593Smuzhiyun #define HCOMM_STATUS_SIGNATURE_SFT 8 8659*4882a593Smuzhiyun #define HCOMM_STATUS_SIGNATURE_VAL (0x484353UL << 8) 8660*4882a593Smuzhiyun #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL 8661*4882a593Smuzhiyun u32 fw_status_loc; 8662*4882a593Smuzhiyun #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK 0x3UL 8663*4882a593Smuzhiyun #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0 8664*4882a593Smuzhiyun #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG 0x0UL 8665*4882a593Smuzhiyun #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC 0x1UL 8666*4882a593Smuzhiyun #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 0x2UL 8667*4882a593Smuzhiyun #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 0x3UL 8668*4882a593Smuzhiyun #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 8669*4882a593Smuzhiyun #define HCOMM_STATUS_TRUE_OFFSET_MASK 0xfffffffcUL 8670*4882a593Smuzhiyun #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 8671*4882a593Smuzhiyun }; 8672*4882a593Smuzhiyun 8673*4882a593Smuzhiyun #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL 8674*4882a593Smuzhiyun 8675*4882a593Smuzhiyun #endif /* _BNXT_HSI_H_ */ 8676