xref: /OK3568_Linux_fs/kernel/drivers/net/ethernet/broadcom/bcmsysport.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Broadcom BCM7xxx System Port Ethernet MAC driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2014 Broadcom Corporation
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/interrupt.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/netdevice.h>
15*4882a593Smuzhiyun #include <linux/etherdevice.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun #include <linux/of.h>
18*4882a593Smuzhiyun #include <linux/of_net.h>
19*4882a593Smuzhiyun #include <linux/of_mdio.h>
20*4882a593Smuzhiyun #include <linux/phy.h>
21*4882a593Smuzhiyun #include <linux/phy_fixed.h>
22*4882a593Smuzhiyun #include <net/dsa.h>
23*4882a593Smuzhiyun #include <linux/clk.h>
24*4882a593Smuzhiyun #include <net/ip.h>
25*4882a593Smuzhiyun #include <net/ipv6.h>
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #include "bcmsysport.h"
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun /* I/O accessors register helpers */
30*4882a593Smuzhiyun #define BCM_SYSPORT_IO_MACRO(name, offset) \
31*4882a593Smuzhiyun static inline u32 name##_readl(struct bcm_sysport_priv *priv, u32 off)	\
32*4882a593Smuzhiyun {									\
33*4882a593Smuzhiyun 	u32 reg = readl_relaxed(priv->base + offset + off);		\
34*4882a593Smuzhiyun 	return reg;							\
35*4882a593Smuzhiyun }									\
36*4882a593Smuzhiyun static inline void name##_writel(struct bcm_sysport_priv *priv,		\
37*4882a593Smuzhiyun 				  u32 val, u32 off)			\
38*4882a593Smuzhiyun {									\
39*4882a593Smuzhiyun 	writel_relaxed(val, priv->base + offset + off);			\
40*4882a593Smuzhiyun }									\
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun BCM_SYSPORT_IO_MACRO(intrl2_0, SYS_PORT_INTRL2_0_OFFSET);
43*4882a593Smuzhiyun BCM_SYSPORT_IO_MACRO(intrl2_1, SYS_PORT_INTRL2_1_OFFSET);
44*4882a593Smuzhiyun BCM_SYSPORT_IO_MACRO(umac, SYS_PORT_UMAC_OFFSET);
45*4882a593Smuzhiyun BCM_SYSPORT_IO_MACRO(gib, SYS_PORT_GIB_OFFSET);
46*4882a593Smuzhiyun BCM_SYSPORT_IO_MACRO(tdma, SYS_PORT_TDMA_OFFSET);
47*4882a593Smuzhiyun BCM_SYSPORT_IO_MACRO(rxchk, SYS_PORT_RXCHK_OFFSET);
48*4882a593Smuzhiyun BCM_SYSPORT_IO_MACRO(txchk, SYS_PORT_TXCHK_OFFSET);
49*4882a593Smuzhiyun BCM_SYSPORT_IO_MACRO(rbuf, SYS_PORT_RBUF_OFFSET);
50*4882a593Smuzhiyun BCM_SYSPORT_IO_MACRO(tbuf, SYS_PORT_TBUF_OFFSET);
51*4882a593Smuzhiyun BCM_SYSPORT_IO_MACRO(topctrl, SYS_PORT_TOPCTRL_OFFSET);
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun /* On SYSTEMPORT Lite, any register after RDMA_STATUS has the exact
54*4882a593Smuzhiyun  * same layout, except it has been moved by 4 bytes up, *sigh*
55*4882a593Smuzhiyun  */
rdma_readl(struct bcm_sysport_priv * priv,u32 off)56*4882a593Smuzhiyun static inline u32 rdma_readl(struct bcm_sysport_priv *priv, u32 off)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun 	if (priv->is_lite && off >= RDMA_STATUS)
59*4882a593Smuzhiyun 		off += 4;
60*4882a593Smuzhiyun 	return readl_relaxed(priv->base + SYS_PORT_RDMA_OFFSET + off);
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun 
rdma_writel(struct bcm_sysport_priv * priv,u32 val,u32 off)63*4882a593Smuzhiyun static inline void rdma_writel(struct bcm_sysport_priv *priv, u32 val, u32 off)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun 	if (priv->is_lite && off >= RDMA_STATUS)
66*4882a593Smuzhiyun 		off += 4;
67*4882a593Smuzhiyun 	writel_relaxed(val, priv->base + SYS_PORT_RDMA_OFFSET + off);
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun 
tdma_control_bit(struct bcm_sysport_priv * priv,u32 bit)70*4882a593Smuzhiyun static inline u32 tdma_control_bit(struct bcm_sysport_priv *priv, u32 bit)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun 	if (!priv->is_lite) {
73*4882a593Smuzhiyun 		return BIT(bit);
74*4882a593Smuzhiyun 	} else {
75*4882a593Smuzhiyun 		if (bit >= ACB_ALGO)
76*4882a593Smuzhiyun 			return BIT(bit + 1);
77*4882a593Smuzhiyun 		else
78*4882a593Smuzhiyun 			return BIT(bit);
79*4882a593Smuzhiyun 	}
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun /* L2-interrupt masking/unmasking helpers, does automatic saving of the applied
83*4882a593Smuzhiyun  * mask in a software copy to avoid CPU_MASK_STATUS reads in hot-paths.
84*4882a593Smuzhiyun   */
85*4882a593Smuzhiyun #define BCM_SYSPORT_INTR_L2(which)	\
86*4882a593Smuzhiyun static inline void intrl2_##which##_mask_clear(struct bcm_sysport_priv *priv, \
87*4882a593Smuzhiyun 						u32 mask)		\
88*4882a593Smuzhiyun {									\
89*4882a593Smuzhiyun 	priv->irq##which##_mask &= ~(mask);				\
90*4882a593Smuzhiyun 	intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR);	\
91*4882a593Smuzhiyun }									\
92*4882a593Smuzhiyun static inline void intrl2_##which##_mask_set(struct bcm_sysport_priv *priv, \
93*4882a593Smuzhiyun 						u32 mask)		\
94*4882a593Smuzhiyun {									\
95*4882a593Smuzhiyun 	intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET);	\
96*4882a593Smuzhiyun 	priv->irq##which##_mask |= (mask);				\
97*4882a593Smuzhiyun }									\
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun BCM_SYSPORT_INTR_L2(0)
100*4882a593Smuzhiyun BCM_SYSPORT_INTR_L2(1)
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun /* Register accesses to GISB/RBUS registers are expensive (few hundred
103*4882a593Smuzhiyun  * nanoseconds), so keep the check for 64-bits explicit here to save
104*4882a593Smuzhiyun  * one register write per-packet on 32-bits platforms.
105*4882a593Smuzhiyun  */
dma_desc_set_addr(struct bcm_sysport_priv * priv,void __iomem * d,dma_addr_t addr)106*4882a593Smuzhiyun static inline void dma_desc_set_addr(struct bcm_sysport_priv *priv,
107*4882a593Smuzhiyun 				     void __iomem *d,
108*4882a593Smuzhiyun 				     dma_addr_t addr)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun #ifdef CONFIG_PHYS_ADDR_T_64BIT
111*4882a593Smuzhiyun 	writel_relaxed(upper_32_bits(addr) & DESC_ADDR_HI_MASK,
112*4882a593Smuzhiyun 		     d + DESC_ADDR_HI_STATUS_LEN);
113*4882a593Smuzhiyun #endif
114*4882a593Smuzhiyun 	writel_relaxed(lower_32_bits(addr), d + DESC_ADDR_LO);
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun /* Ethtool operations */
bcm_sysport_set_rx_csum(struct net_device * dev,netdev_features_t wanted)118*4882a593Smuzhiyun static void bcm_sysport_set_rx_csum(struct net_device *dev,
119*4882a593Smuzhiyun 				    netdev_features_t wanted)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
122*4882a593Smuzhiyun 	u32 reg;
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	priv->rx_chk_en = !!(wanted & NETIF_F_RXCSUM);
125*4882a593Smuzhiyun 	reg = rxchk_readl(priv, RXCHK_CONTROL);
126*4882a593Smuzhiyun 	/* Clear L2 header checks, which would prevent BPDUs
127*4882a593Smuzhiyun 	 * from being received.
128*4882a593Smuzhiyun 	 */
129*4882a593Smuzhiyun 	reg &= ~RXCHK_L2_HDR_DIS;
130*4882a593Smuzhiyun 	if (priv->rx_chk_en)
131*4882a593Smuzhiyun 		reg |= RXCHK_EN;
132*4882a593Smuzhiyun 	else
133*4882a593Smuzhiyun 		reg &= ~RXCHK_EN;
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	/* If UniMAC forwards CRC, we need to skip over it to get
136*4882a593Smuzhiyun 	 * a valid CHK bit to be set in the per-packet status word
137*4882a593Smuzhiyun 	 */
138*4882a593Smuzhiyun 	if (priv->rx_chk_en && priv->crc_fwd)
139*4882a593Smuzhiyun 		reg |= RXCHK_SKIP_FCS;
140*4882a593Smuzhiyun 	else
141*4882a593Smuzhiyun 		reg &= ~RXCHK_SKIP_FCS;
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	/* If Broadcom tags are enabled (e.g: using a switch), make
144*4882a593Smuzhiyun 	 * sure we tell the RXCHK hardware to expect a 4-bytes Broadcom
145*4882a593Smuzhiyun 	 * tag after the Ethernet MAC Source Address.
146*4882a593Smuzhiyun 	 */
147*4882a593Smuzhiyun 	if (netdev_uses_dsa(dev))
148*4882a593Smuzhiyun 		reg |= RXCHK_BRCM_TAG_EN;
149*4882a593Smuzhiyun 	else
150*4882a593Smuzhiyun 		reg &= ~RXCHK_BRCM_TAG_EN;
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	rxchk_writel(priv, reg, RXCHK_CONTROL);
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun 
bcm_sysport_set_tx_csum(struct net_device * dev,netdev_features_t wanted)155*4882a593Smuzhiyun static void bcm_sysport_set_tx_csum(struct net_device *dev,
156*4882a593Smuzhiyun 				    netdev_features_t wanted)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
159*4882a593Smuzhiyun 	u32 reg;
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	/* Hardware transmit checksum requires us to enable the Transmit status
162*4882a593Smuzhiyun 	 * block prepended to the packet contents
163*4882a593Smuzhiyun 	 */
164*4882a593Smuzhiyun 	priv->tsb_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
165*4882a593Smuzhiyun 				    NETIF_F_HW_VLAN_CTAG_TX));
166*4882a593Smuzhiyun 	reg = tdma_readl(priv, TDMA_CONTROL);
167*4882a593Smuzhiyun 	if (priv->tsb_en)
168*4882a593Smuzhiyun 		reg |= tdma_control_bit(priv, TSB_EN);
169*4882a593Smuzhiyun 	else
170*4882a593Smuzhiyun 		reg &= ~tdma_control_bit(priv, TSB_EN);
171*4882a593Smuzhiyun 	/* Indicating that software inserts Broadcom tags is needed for the TX
172*4882a593Smuzhiyun 	 * checksum to be computed correctly when using VLAN HW acceleration,
173*4882a593Smuzhiyun 	 * else it has no effect, so it can always be turned on.
174*4882a593Smuzhiyun 	 */
175*4882a593Smuzhiyun 	if (netdev_uses_dsa(dev))
176*4882a593Smuzhiyun 		reg |= tdma_control_bit(priv, SW_BRCM_TAG);
177*4882a593Smuzhiyun 	else
178*4882a593Smuzhiyun 		reg &= ~tdma_control_bit(priv, SW_BRCM_TAG);
179*4882a593Smuzhiyun 	tdma_writel(priv, reg, TDMA_CONTROL);
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	/* Default TPID is ETH_P_8021AD, change to ETH_P_8021Q */
182*4882a593Smuzhiyun 	if (wanted & NETIF_F_HW_VLAN_CTAG_TX)
183*4882a593Smuzhiyun 		tdma_writel(priv, ETH_P_8021Q, TDMA_TPID);
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun 
bcm_sysport_set_features(struct net_device * dev,netdev_features_t features)186*4882a593Smuzhiyun static int bcm_sysport_set_features(struct net_device *dev,
187*4882a593Smuzhiyun 				    netdev_features_t features)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
190*4882a593Smuzhiyun 	int ret;
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	ret = clk_prepare_enable(priv->clk);
193*4882a593Smuzhiyun 	if (ret)
194*4882a593Smuzhiyun 		return ret;
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	/* Read CRC forward */
197*4882a593Smuzhiyun 	if (!priv->is_lite)
198*4882a593Smuzhiyun 		priv->crc_fwd = !!(umac_readl(priv, UMAC_CMD) & CMD_CRC_FWD);
199*4882a593Smuzhiyun 	else
200*4882a593Smuzhiyun 		priv->crc_fwd = !((gib_readl(priv, GIB_CONTROL) &
201*4882a593Smuzhiyun 				  GIB_FCS_STRIP) >> GIB_FCS_STRIP_SHIFT);
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	bcm_sysport_set_rx_csum(dev, features);
204*4882a593Smuzhiyun 	bcm_sysport_set_tx_csum(dev, features);
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 	clk_disable_unprepare(priv->clk);
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	return 0;
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun /* Hardware counters must be kept in sync because the order/offset
212*4882a593Smuzhiyun  * is important here (order in structure declaration = order in hardware)
213*4882a593Smuzhiyun  */
214*4882a593Smuzhiyun static const struct bcm_sysport_stats bcm_sysport_gstrings_stats[] = {
215*4882a593Smuzhiyun 	/* general stats */
216*4882a593Smuzhiyun 	STAT_NETDEV64(rx_packets),
217*4882a593Smuzhiyun 	STAT_NETDEV64(tx_packets),
218*4882a593Smuzhiyun 	STAT_NETDEV64(rx_bytes),
219*4882a593Smuzhiyun 	STAT_NETDEV64(tx_bytes),
220*4882a593Smuzhiyun 	STAT_NETDEV(rx_errors),
221*4882a593Smuzhiyun 	STAT_NETDEV(tx_errors),
222*4882a593Smuzhiyun 	STAT_NETDEV(rx_dropped),
223*4882a593Smuzhiyun 	STAT_NETDEV(tx_dropped),
224*4882a593Smuzhiyun 	STAT_NETDEV(multicast),
225*4882a593Smuzhiyun 	/* UniMAC RSV counters */
226*4882a593Smuzhiyun 	STAT_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
227*4882a593Smuzhiyun 	STAT_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
228*4882a593Smuzhiyun 	STAT_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
229*4882a593Smuzhiyun 	STAT_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
230*4882a593Smuzhiyun 	STAT_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
231*4882a593Smuzhiyun 	STAT_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
232*4882a593Smuzhiyun 	STAT_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
233*4882a593Smuzhiyun 	STAT_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
234*4882a593Smuzhiyun 	STAT_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
235*4882a593Smuzhiyun 	STAT_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
236*4882a593Smuzhiyun 	STAT_MIB_RX("rx_pkts", mib.rx.pkt),
237*4882a593Smuzhiyun 	STAT_MIB_RX("rx_bytes", mib.rx.bytes),
238*4882a593Smuzhiyun 	STAT_MIB_RX("rx_multicast", mib.rx.mca),
239*4882a593Smuzhiyun 	STAT_MIB_RX("rx_broadcast", mib.rx.bca),
240*4882a593Smuzhiyun 	STAT_MIB_RX("rx_fcs", mib.rx.fcs),
241*4882a593Smuzhiyun 	STAT_MIB_RX("rx_control", mib.rx.cf),
242*4882a593Smuzhiyun 	STAT_MIB_RX("rx_pause", mib.rx.pf),
243*4882a593Smuzhiyun 	STAT_MIB_RX("rx_unknown", mib.rx.uo),
244*4882a593Smuzhiyun 	STAT_MIB_RX("rx_align", mib.rx.aln),
245*4882a593Smuzhiyun 	STAT_MIB_RX("rx_outrange", mib.rx.flr),
246*4882a593Smuzhiyun 	STAT_MIB_RX("rx_code", mib.rx.cde),
247*4882a593Smuzhiyun 	STAT_MIB_RX("rx_carrier", mib.rx.fcr),
248*4882a593Smuzhiyun 	STAT_MIB_RX("rx_oversize", mib.rx.ovr),
249*4882a593Smuzhiyun 	STAT_MIB_RX("rx_jabber", mib.rx.jbr),
250*4882a593Smuzhiyun 	STAT_MIB_RX("rx_mtu_err", mib.rx.mtue),
251*4882a593Smuzhiyun 	STAT_MIB_RX("rx_good_pkts", mib.rx.pok),
252*4882a593Smuzhiyun 	STAT_MIB_RX("rx_unicast", mib.rx.uc),
253*4882a593Smuzhiyun 	STAT_MIB_RX("rx_ppp", mib.rx.ppp),
254*4882a593Smuzhiyun 	STAT_MIB_RX("rx_crc", mib.rx.rcrc),
255*4882a593Smuzhiyun 	/* UniMAC TSV counters */
256*4882a593Smuzhiyun 	STAT_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
257*4882a593Smuzhiyun 	STAT_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
258*4882a593Smuzhiyun 	STAT_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
259*4882a593Smuzhiyun 	STAT_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
260*4882a593Smuzhiyun 	STAT_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
261*4882a593Smuzhiyun 	STAT_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
262*4882a593Smuzhiyun 	STAT_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
263*4882a593Smuzhiyun 	STAT_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
264*4882a593Smuzhiyun 	STAT_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
265*4882a593Smuzhiyun 	STAT_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
266*4882a593Smuzhiyun 	STAT_MIB_TX("tx_pkts", mib.tx.pkts),
267*4882a593Smuzhiyun 	STAT_MIB_TX("tx_multicast", mib.tx.mca),
268*4882a593Smuzhiyun 	STAT_MIB_TX("tx_broadcast", mib.tx.bca),
269*4882a593Smuzhiyun 	STAT_MIB_TX("tx_pause", mib.tx.pf),
270*4882a593Smuzhiyun 	STAT_MIB_TX("tx_control", mib.tx.cf),
271*4882a593Smuzhiyun 	STAT_MIB_TX("tx_fcs_err", mib.tx.fcs),
272*4882a593Smuzhiyun 	STAT_MIB_TX("tx_oversize", mib.tx.ovr),
273*4882a593Smuzhiyun 	STAT_MIB_TX("tx_defer", mib.tx.drf),
274*4882a593Smuzhiyun 	STAT_MIB_TX("tx_excess_defer", mib.tx.edf),
275*4882a593Smuzhiyun 	STAT_MIB_TX("tx_single_col", mib.tx.scl),
276*4882a593Smuzhiyun 	STAT_MIB_TX("tx_multi_col", mib.tx.mcl),
277*4882a593Smuzhiyun 	STAT_MIB_TX("tx_late_col", mib.tx.lcl),
278*4882a593Smuzhiyun 	STAT_MIB_TX("tx_excess_col", mib.tx.ecl),
279*4882a593Smuzhiyun 	STAT_MIB_TX("tx_frags", mib.tx.frg),
280*4882a593Smuzhiyun 	STAT_MIB_TX("tx_total_col", mib.tx.ncl),
281*4882a593Smuzhiyun 	STAT_MIB_TX("tx_jabber", mib.tx.jbr),
282*4882a593Smuzhiyun 	STAT_MIB_TX("tx_bytes", mib.tx.bytes),
283*4882a593Smuzhiyun 	STAT_MIB_TX("tx_good_pkts", mib.tx.pok),
284*4882a593Smuzhiyun 	STAT_MIB_TX("tx_unicast", mib.tx.uc),
285*4882a593Smuzhiyun 	/* UniMAC RUNT counters */
286*4882a593Smuzhiyun 	STAT_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
287*4882a593Smuzhiyun 	STAT_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
288*4882a593Smuzhiyun 	STAT_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
289*4882a593Smuzhiyun 	STAT_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
290*4882a593Smuzhiyun 	/* RXCHK misc statistics */
291*4882a593Smuzhiyun 	STAT_RXCHK("rxchk_bad_csum", mib.rxchk_bad_csum, RXCHK_BAD_CSUM_CNTR),
292*4882a593Smuzhiyun 	STAT_RXCHK("rxchk_other_pkt_disc", mib.rxchk_other_pkt_disc,
293*4882a593Smuzhiyun 		   RXCHK_OTHER_DISC_CNTR),
294*4882a593Smuzhiyun 	/* RBUF misc statistics */
295*4882a593Smuzhiyun 	STAT_RBUF("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, RBUF_OVFL_DISC_CNTR),
296*4882a593Smuzhiyun 	STAT_RBUF("rbuf_err_cnt", mib.rbuf_err_cnt, RBUF_ERR_PKT_CNTR),
297*4882a593Smuzhiyun 	STAT_MIB_SOFT("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
298*4882a593Smuzhiyun 	STAT_MIB_SOFT("rx_dma_failed", mib.rx_dma_failed),
299*4882a593Smuzhiyun 	STAT_MIB_SOFT("tx_dma_failed", mib.tx_dma_failed),
300*4882a593Smuzhiyun 	STAT_MIB_SOFT("tx_realloc_tsb", mib.tx_realloc_tsb),
301*4882a593Smuzhiyun 	STAT_MIB_SOFT("tx_realloc_tsb_failed", mib.tx_realloc_tsb_failed),
302*4882a593Smuzhiyun 	/* Per TX-queue statistics are dynamically appended */
303*4882a593Smuzhiyun };
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun #define BCM_SYSPORT_STATS_LEN	ARRAY_SIZE(bcm_sysport_gstrings_stats)
306*4882a593Smuzhiyun 
bcm_sysport_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)307*4882a593Smuzhiyun static void bcm_sysport_get_drvinfo(struct net_device *dev,
308*4882a593Smuzhiyun 				    struct ethtool_drvinfo *info)
309*4882a593Smuzhiyun {
310*4882a593Smuzhiyun 	strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
311*4882a593Smuzhiyun 	strlcpy(info->bus_info, "platform", sizeof(info->bus_info));
312*4882a593Smuzhiyun }
313*4882a593Smuzhiyun 
bcm_sysport_get_msglvl(struct net_device * dev)314*4882a593Smuzhiyun static u32 bcm_sysport_get_msglvl(struct net_device *dev)
315*4882a593Smuzhiyun {
316*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 	return priv->msg_enable;
319*4882a593Smuzhiyun }
320*4882a593Smuzhiyun 
bcm_sysport_set_msglvl(struct net_device * dev,u32 enable)321*4882a593Smuzhiyun static void bcm_sysport_set_msglvl(struct net_device *dev, u32 enable)
322*4882a593Smuzhiyun {
323*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 	priv->msg_enable = enable;
326*4882a593Smuzhiyun }
327*4882a593Smuzhiyun 
bcm_sysport_lite_stat_valid(enum bcm_sysport_stat_type type)328*4882a593Smuzhiyun static inline bool bcm_sysport_lite_stat_valid(enum bcm_sysport_stat_type type)
329*4882a593Smuzhiyun {
330*4882a593Smuzhiyun 	switch (type) {
331*4882a593Smuzhiyun 	case BCM_SYSPORT_STAT_NETDEV:
332*4882a593Smuzhiyun 	case BCM_SYSPORT_STAT_NETDEV64:
333*4882a593Smuzhiyun 	case BCM_SYSPORT_STAT_RXCHK:
334*4882a593Smuzhiyun 	case BCM_SYSPORT_STAT_RBUF:
335*4882a593Smuzhiyun 	case BCM_SYSPORT_STAT_SOFT:
336*4882a593Smuzhiyun 		return true;
337*4882a593Smuzhiyun 	default:
338*4882a593Smuzhiyun 		return false;
339*4882a593Smuzhiyun 	}
340*4882a593Smuzhiyun }
341*4882a593Smuzhiyun 
bcm_sysport_get_sset_count(struct net_device * dev,int string_set)342*4882a593Smuzhiyun static int bcm_sysport_get_sset_count(struct net_device *dev, int string_set)
343*4882a593Smuzhiyun {
344*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
345*4882a593Smuzhiyun 	const struct bcm_sysport_stats *s;
346*4882a593Smuzhiyun 	unsigned int i, j;
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun 	switch (string_set) {
349*4882a593Smuzhiyun 	case ETH_SS_STATS:
350*4882a593Smuzhiyun 		for (i = 0, j = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
351*4882a593Smuzhiyun 			s = &bcm_sysport_gstrings_stats[i];
352*4882a593Smuzhiyun 			if (priv->is_lite &&
353*4882a593Smuzhiyun 			    !bcm_sysport_lite_stat_valid(s->type))
354*4882a593Smuzhiyun 				continue;
355*4882a593Smuzhiyun 			j++;
356*4882a593Smuzhiyun 		}
357*4882a593Smuzhiyun 		/* Include per-queue statistics */
358*4882a593Smuzhiyun 		return j + dev->num_tx_queues * NUM_SYSPORT_TXQ_STAT;
359*4882a593Smuzhiyun 	default:
360*4882a593Smuzhiyun 		return -EOPNOTSUPP;
361*4882a593Smuzhiyun 	}
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun 
bcm_sysport_get_strings(struct net_device * dev,u32 stringset,u8 * data)364*4882a593Smuzhiyun static void bcm_sysport_get_strings(struct net_device *dev,
365*4882a593Smuzhiyun 				    u32 stringset, u8 *data)
366*4882a593Smuzhiyun {
367*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
368*4882a593Smuzhiyun 	const struct bcm_sysport_stats *s;
369*4882a593Smuzhiyun 	char buf[128];
370*4882a593Smuzhiyun 	int i, j;
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun 	switch (stringset) {
373*4882a593Smuzhiyun 	case ETH_SS_STATS:
374*4882a593Smuzhiyun 		for (i = 0, j = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
375*4882a593Smuzhiyun 			s = &bcm_sysport_gstrings_stats[i];
376*4882a593Smuzhiyun 			if (priv->is_lite &&
377*4882a593Smuzhiyun 			    !bcm_sysport_lite_stat_valid(s->type))
378*4882a593Smuzhiyun 				continue;
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun 			memcpy(data + j * ETH_GSTRING_LEN, s->stat_string,
381*4882a593Smuzhiyun 			       ETH_GSTRING_LEN);
382*4882a593Smuzhiyun 			j++;
383*4882a593Smuzhiyun 		}
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun 		for (i = 0; i < dev->num_tx_queues; i++) {
386*4882a593Smuzhiyun 			snprintf(buf, sizeof(buf), "txq%d_packets", i);
387*4882a593Smuzhiyun 			memcpy(data + j * ETH_GSTRING_LEN, buf,
388*4882a593Smuzhiyun 			       ETH_GSTRING_LEN);
389*4882a593Smuzhiyun 			j++;
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun 			snprintf(buf, sizeof(buf), "txq%d_bytes", i);
392*4882a593Smuzhiyun 			memcpy(data + j * ETH_GSTRING_LEN, buf,
393*4882a593Smuzhiyun 			       ETH_GSTRING_LEN);
394*4882a593Smuzhiyun 			j++;
395*4882a593Smuzhiyun 		}
396*4882a593Smuzhiyun 		break;
397*4882a593Smuzhiyun 	default:
398*4882a593Smuzhiyun 		break;
399*4882a593Smuzhiyun 	}
400*4882a593Smuzhiyun }
401*4882a593Smuzhiyun 
bcm_sysport_update_mib_counters(struct bcm_sysport_priv * priv)402*4882a593Smuzhiyun static void bcm_sysport_update_mib_counters(struct bcm_sysport_priv *priv)
403*4882a593Smuzhiyun {
404*4882a593Smuzhiyun 	int i, j = 0;
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun 	for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
407*4882a593Smuzhiyun 		const struct bcm_sysport_stats *s;
408*4882a593Smuzhiyun 		u8 offset = 0;
409*4882a593Smuzhiyun 		u32 val = 0;
410*4882a593Smuzhiyun 		char *p;
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun 		s = &bcm_sysport_gstrings_stats[i];
413*4882a593Smuzhiyun 		switch (s->type) {
414*4882a593Smuzhiyun 		case BCM_SYSPORT_STAT_NETDEV:
415*4882a593Smuzhiyun 		case BCM_SYSPORT_STAT_NETDEV64:
416*4882a593Smuzhiyun 		case BCM_SYSPORT_STAT_SOFT:
417*4882a593Smuzhiyun 			continue;
418*4882a593Smuzhiyun 		case BCM_SYSPORT_STAT_MIB_RX:
419*4882a593Smuzhiyun 		case BCM_SYSPORT_STAT_MIB_TX:
420*4882a593Smuzhiyun 		case BCM_SYSPORT_STAT_RUNT:
421*4882a593Smuzhiyun 			if (priv->is_lite)
422*4882a593Smuzhiyun 				continue;
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun 			if (s->type != BCM_SYSPORT_STAT_MIB_RX)
425*4882a593Smuzhiyun 				offset = UMAC_MIB_STAT_OFFSET;
426*4882a593Smuzhiyun 			val = umac_readl(priv, UMAC_MIB_START + j + offset);
427*4882a593Smuzhiyun 			break;
428*4882a593Smuzhiyun 		case BCM_SYSPORT_STAT_RXCHK:
429*4882a593Smuzhiyun 			val = rxchk_readl(priv, s->reg_offset);
430*4882a593Smuzhiyun 			if (val == ~0)
431*4882a593Smuzhiyun 				rxchk_writel(priv, 0, s->reg_offset);
432*4882a593Smuzhiyun 			break;
433*4882a593Smuzhiyun 		case BCM_SYSPORT_STAT_RBUF:
434*4882a593Smuzhiyun 			val = rbuf_readl(priv, s->reg_offset);
435*4882a593Smuzhiyun 			if (val == ~0)
436*4882a593Smuzhiyun 				rbuf_writel(priv, 0, s->reg_offset);
437*4882a593Smuzhiyun 			break;
438*4882a593Smuzhiyun 		}
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun 		j += s->stat_sizeof;
441*4882a593Smuzhiyun 		p = (char *)priv + s->stat_offset;
442*4882a593Smuzhiyun 		*(u32 *)p = val;
443*4882a593Smuzhiyun 	}
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun 	netif_dbg(priv, hw, priv->netdev, "updated MIB counters\n");
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun 
bcm_sysport_update_tx_stats(struct bcm_sysport_priv * priv,u64 * tx_bytes,u64 * tx_packets)448*4882a593Smuzhiyun static void bcm_sysport_update_tx_stats(struct bcm_sysport_priv *priv,
449*4882a593Smuzhiyun 					u64 *tx_bytes, u64 *tx_packets)
450*4882a593Smuzhiyun {
451*4882a593Smuzhiyun 	struct bcm_sysport_tx_ring *ring;
452*4882a593Smuzhiyun 	u64 bytes = 0, packets = 0;
453*4882a593Smuzhiyun 	unsigned int start;
454*4882a593Smuzhiyun 	unsigned int q;
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun 	for (q = 0; q < priv->netdev->num_tx_queues; q++) {
457*4882a593Smuzhiyun 		ring = &priv->tx_rings[q];
458*4882a593Smuzhiyun 		do {
459*4882a593Smuzhiyun 			start = u64_stats_fetch_begin_irq(&priv->syncp);
460*4882a593Smuzhiyun 			bytes = ring->bytes;
461*4882a593Smuzhiyun 			packets = ring->packets;
462*4882a593Smuzhiyun 		} while (u64_stats_fetch_retry_irq(&priv->syncp, start));
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun 		*tx_bytes += bytes;
465*4882a593Smuzhiyun 		*tx_packets += packets;
466*4882a593Smuzhiyun 	}
467*4882a593Smuzhiyun }
468*4882a593Smuzhiyun 
bcm_sysport_get_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)469*4882a593Smuzhiyun static void bcm_sysport_get_stats(struct net_device *dev,
470*4882a593Smuzhiyun 				  struct ethtool_stats *stats, u64 *data)
471*4882a593Smuzhiyun {
472*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
473*4882a593Smuzhiyun 	struct bcm_sysport_stats64 *stats64 = &priv->stats64;
474*4882a593Smuzhiyun 	struct u64_stats_sync *syncp = &priv->syncp;
475*4882a593Smuzhiyun 	struct bcm_sysport_tx_ring *ring;
476*4882a593Smuzhiyun 	u64 tx_bytes = 0, tx_packets = 0;
477*4882a593Smuzhiyun 	unsigned int start;
478*4882a593Smuzhiyun 	int i, j;
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun 	if (netif_running(dev)) {
481*4882a593Smuzhiyun 		bcm_sysport_update_mib_counters(priv);
482*4882a593Smuzhiyun 		bcm_sysport_update_tx_stats(priv, &tx_bytes, &tx_packets);
483*4882a593Smuzhiyun 		stats64->tx_bytes = tx_bytes;
484*4882a593Smuzhiyun 		stats64->tx_packets = tx_packets;
485*4882a593Smuzhiyun 	}
486*4882a593Smuzhiyun 
487*4882a593Smuzhiyun 	for (i =  0, j = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
488*4882a593Smuzhiyun 		const struct bcm_sysport_stats *s;
489*4882a593Smuzhiyun 		char *p;
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun 		s = &bcm_sysport_gstrings_stats[i];
492*4882a593Smuzhiyun 		if (s->type == BCM_SYSPORT_STAT_NETDEV)
493*4882a593Smuzhiyun 			p = (char *)&dev->stats;
494*4882a593Smuzhiyun 		else if (s->type == BCM_SYSPORT_STAT_NETDEV64)
495*4882a593Smuzhiyun 			p = (char *)stats64;
496*4882a593Smuzhiyun 		else
497*4882a593Smuzhiyun 			p = (char *)priv;
498*4882a593Smuzhiyun 
499*4882a593Smuzhiyun 		if (priv->is_lite && !bcm_sysport_lite_stat_valid(s->type))
500*4882a593Smuzhiyun 			continue;
501*4882a593Smuzhiyun 		p += s->stat_offset;
502*4882a593Smuzhiyun 
503*4882a593Smuzhiyun 		if (s->stat_sizeof == sizeof(u64) &&
504*4882a593Smuzhiyun 		    s->type == BCM_SYSPORT_STAT_NETDEV64) {
505*4882a593Smuzhiyun 			do {
506*4882a593Smuzhiyun 				start = u64_stats_fetch_begin_irq(syncp);
507*4882a593Smuzhiyun 				data[i] = *(u64 *)p;
508*4882a593Smuzhiyun 			} while (u64_stats_fetch_retry_irq(syncp, start));
509*4882a593Smuzhiyun 		} else
510*4882a593Smuzhiyun 			data[i] = *(u32 *)p;
511*4882a593Smuzhiyun 		j++;
512*4882a593Smuzhiyun 	}
513*4882a593Smuzhiyun 
514*4882a593Smuzhiyun 	/* For SYSTEMPORT Lite since we have holes in our statistics, j would
515*4882a593Smuzhiyun 	 * be equal to BCM_SYSPORT_STATS_LEN at the end of the loop, but it
516*4882a593Smuzhiyun 	 * needs to point to how many total statistics we have minus the
517*4882a593Smuzhiyun 	 * number of per TX queue statistics
518*4882a593Smuzhiyun 	 */
519*4882a593Smuzhiyun 	j = bcm_sysport_get_sset_count(dev, ETH_SS_STATS) -
520*4882a593Smuzhiyun 	    dev->num_tx_queues * NUM_SYSPORT_TXQ_STAT;
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun 	for (i = 0; i < dev->num_tx_queues; i++) {
523*4882a593Smuzhiyun 		ring = &priv->tx_rings[i];
524*4882a593Smuzhiyun 		data[j] = ring->packets;
525*4882a593Smuzhiyun 		j++;
526*4882a593Smuzhiyun 		data[j] = ring->bytes;
527*4882a593Smuzhiyun 		j++;
528*4882a593Smuzhiyun 	}
529*4882a593Smuzhiyun }
530*4882a593Smuzhiyun 
bcm_sysport_get_wol(struct net_device * dev,struct ethtool_wolinfo * wol)531*4882a593Smuzhiyun static void bcm_sysport_get_wol(struct net_device *dev,
532*4882a593Smuzhiyun 				struct ethtool_wolinfo *wol)
533*4882a593Smuzhiyun {
534*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
535*4882a593Smuzhiyun 
536*4882a593Smuzhiyun 	wol->supported = WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_FILTER;
537*4882a593Smuzhiyun 	wol->wolopts = priv->wolopts;
538*4882a593Smuzhiyun 
539*4882a593Smuzhiyun 	if (!(priv->wolopts & WAKE_MAGICSECURE))
540*4882a593Smuzhiyun 		return;
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun 	memcpy(wol->sopass, priv->sopass, sizeof(priv->sopass));
543*4882a593Smuzhiyun }
544*4882a593Smuzhiyun 
bcm_sysport_set_wol(struct net_device * dev,struct ethtool_wolinfo * wol)545*4882a593Smuzhiyun static int bcm_sysport_set_wol(struct net_device *dev,
546*4882a593Smuzhiyun 			       struct ethtool_wolinfo *wol)
547*4882a593Smuzhiyun {
548*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
549*4882a593Smuzhiyun 	struct device *kdev = &priv->pdev->dev;
550*4882a593Smuzhiyun 	u32 supported = WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_FILTER;
551*4882a593Smuzhiyun 
552*4882a593Smuzhiyun 	if (!device_can_wakeup(kdev))
553*4882a593Smuzhiyun 		return -ENOTSUPP;
554*4882a593Smuzhiyun 
555*4882a593Smuzhiyun 	if (wol->wolopts & ~supported)
556*4882a593Smuzhiyun 		return -EINVAL;
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun 	if (wol->wolopts & WAKE_MAGICSECURE)
559*4882a593Smuzhiyun 		memcpy(priv->sopass, wol->sopass, sizeof(priv->sopass));
560*4882a593Smuzhiyun 
561*4882a593Smuzhiyun 	/* Flag the device and relevant IRQ as wakeup capable */
562*4882a593Smuzhiyun 	if (wol->wolopts) {
563*4882a593Smuzhiyun 		device_set_wakeup_enable(kdev, 1);
564*4882a593Smuzhiyun 		if (priv->wol_irq_disabled)
565*4882a593Smuzhiyun 			enable_irq_wake(priv->wol_irq);
566*4882a593Smuzhiyun 		priv->wol_irq_disabled = 0;
567*4882a593Smuzhiyun 	} else {
568*4882a593Smuzhiyun 		device_set_wakeup_enable(kdev, 0);
569*4882a593Smuzhiyun 		/* Avoid unbalanced disable_irq_wake calls */
570*4882a593Smuzhiyun 		if (!priv->wol_irq_disabled)
571*4882a593Smuzhiyun 			disable_irq_wake(priv->wol_irq);
572*4882a593Smuzhiyun 		priv->wol_irq_disabled = 1;
573*4882a593Smuzhiyun 	}
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun 	priv->wolopts = wol->wolopts;
576*4882a593Smuzhiyun 
577*4882a593Smuzhiyun 	return 0;
578*4882a593Smuzhiyun }
579*4882a593Smuzhiyun 
bcm_sysport_set_rx_coalesce(struct bcm_sysport_priv * priv,u32 usecs,u32 pkts)580*4882a593Smuzhiyun static void bcm_sysport_set_rx_coalesce(struct bcm_sysport_priv *priv,
581*4882a593Smuzhiyun 					u32 usecs, u32 pkts)
582*4882a593Smuzhiyun {
583*4882a593Smuzhiyun 	u32 reg;
584*4882a593Smuzhiyun 
585*4882a593Smuzhiyun 	reg = rdma_readl(priv, RDMA_MBDONE_INTR);
586*4882a593Smuzhiyun 	reg &= ~(RDMA_INTR_THRESH_MASK |
587*4882a593Smuzhiyun 		 RDMA_TIMEOUT_MASK << RDMA_TIMEOUT_SHIFT);
588*4882a593Smuzhiyun 	reg |= pkts;
589*4882a593Smuzhiyun 	reg |= DIV_ROUND_UP(usecs * 1000, 8192) << RDMA_TIMEOUT_SHIFT;
590*4882a593Smuzhiyun 	rdma_writel(priv, reg, RDMA_MBDONE_INTR);
591*4882a593Smuzhiyun }
592*4882a593Smuzhiyun 
bcm_sysport_set_tx_coalesce(struct bcm_sysport_tx_ring * ring,struct ethtool_coalesce * ec)593*4882a593Smuzhiyun static void bcm_sysport_set_tx_coalesce(struct bcm_sysport_tx_ring *ring,
594*4882a593Smuzhiyun 					struct ethtool_coalesce *ec)
595*4882a593Smuzhiyun {
596*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = ring->priv;
597*4882a593Smuzhiyun 	u32 reg;
598*4882a593Smuzhiyun 
599*4882a593Smuzhiyun 	reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(ring->index));
600*4882a593Smuzhiyun 	reg &= ~(RING_INTR_THRESH_MASK |
601*4882a593Smuzhiyun 		 RING_TIMEOUT_MASK << RING_TIMEOUT_SHIFT);
602*4882a593Smuzhiyun 	reg |= ec->tx_max_coalesced_frames;
603*4882a593Smuzhiyun 	reg |= DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000, 8192) <<
604*4882a593Smuzhiyun 			    RING_TIMEOUT_SHIFT;
605*4882a593Smuzhiyun 	tdma_writel(priv, reg, TDMA_DESC_RING_INTR_CONTROL(ring->index));
606*4882a593Smuzhiyun }
607*4882a593Smuzhiyun 
bcm_sysport_get_coalesce(struct net_device * dev,struct ethtool_coalesce * ec)608*4882a593Smuzhiyun static int bcm_sysport_get_coalesce(struct net_device *dev,
609*4882a593Smuzhiyun 				    struct ethtool_coalesce *ec)
610*4882a593Smuzhiyun {
611*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
612*4882a593Smuzhiyun 	u32 reg;
613*4882a593Smuzhiyun 
614*4882a593Smuzhiyun 	reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(0));
615*4882a593Smuzhiyun 
616*4882a593Smuzhiyun 	ec->tx_coalesce_usecs = (reg >> RING_TIMEOUT_SHIFT) * 8192 / 1000;
617*4882a593Smuzhiyun 	ec->tx_max_coalesced_frames = reg & RING_INTR_THRESH_MASK;
618*4882a593Smuzhiyun 
619*4882a593Smuzhiyun 	reg = rdma_readl(priv, RDMA_MBDONE_INTR);
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun 	ec->rx_coalesce_usecs = (reg >> RDMA_TIMEOUT_SHIFT) * 8192 / 1000;
622*4882a593Smuzhiyun 	ec->rx_max_coalesced_frames = reg & RDMA_INTR_THRESH_MASK;
623*4882a593Smuzhiyun 	ec->use_adaptive_rx_coalesce = priv->dim.use_dim;
624*4882a593Smuzhiyun 
625*4882a593Smuzhiyun 	return 0;
626*4882a593Smuzhiyun }
627*4882a593Smuzhiyun 
bcm_sysport_set_coalesce(struct net_device * dev,struct ethtool_coalesce * ec)628*4882a593Smuzhiyun static int bcm_sysport_set_coalesce(struct net_device *dev,
629*4882a593Smuzhiyun 				    struct ethtool_coalesce *ec)
630*4882a593Smuzhiyun {
631*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
632*4882a593Smuzhiyun 	struct dim_cq_moder moder;
633*4882a593Smuzhiyun 	u32 usecs, pkts;
634*4882a593Smuzhiyun 	unsigned int i;
635*4882a593Smuzhiyun 
636*4882a593Smuzhiyun 	/* Base system clock is 125Mhz, DMA timeout is this reference clock
637*4882a593Smuzhiyun 	 * divided by 1024, which yield roughly 8.192 us, our maximum value has
638*4882a593Smuzhiyun 	 * to fit in the RING_TIMEOUT_MASK (16 bits).
639*4882a593Smuzhiyun 	 */
640*4882a593Smuzhiyun 	if (ec->tx_max_coalesced_frames > RING_INTR_THRESH_MASK ||
641*4882a593Smuzhiyun 	    ec->tx_coalesce_usecs > (RING_TIMEOUT_MASK * 8) + 1 ||
642*4882a593Smuzhiyun 	    ec->rx_max_coalesced_frames > RDMA_INTR_THRESH_MASK ||
643*4882a593Smuzhiyun 	    ec->rx_coalesce_usecs > (RDMA_TIMEOUT_MASK * 8) + 1)
644*4882a593Smuzhiyun 		return -EINVAL;
645*4882a593Smuzhiyun 
646*4882a593Smuzhiyun 	if ((ec->tx_coalesce_usecs == 0 && ec->tx_max_coalesced_frames == 0) ||
647*4882a593Smuzhiyun 	    (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0))
648*4882a593Smuzhiyun 		return -EINVAL;
649*4882a593Smuzhiyun 
650*4882a593Smuzhiyun 	for (i = 0; i < dev->num_tx_queues; i++)
651*4882a593Smuzhiyun 		bcm_sysport_set_tx_coalesce(&priv->tx_rings[i], ec);
652*4882a593Smuzhiyun 
653*4882a593Smuzhiyun 	priv->rx_coalesce_usecs = ec->rx_coalesce_usecs;
654*4882a593Smuzhiyun 	priv->rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
655*4882a593Smuzhiyun 	usecs = priv->rx_coalesce_usecs;
656*4882a593Smuzhiyun 	pkts = priv->rx_max_coalesced_frames;
657*4882a593Smuzhiyun 
658*4882a593Smuzhiyun 	if (ec->use_adaptive_rx_coalesce && !priv->dim.use_dim) {
659*4882a593Smuzhiyun 		moder = net_dim_get_def_rx_moderation(priv->dim.dim.mode);
660*4882a593Smuzhiyun 		usecs = moder.usec;
661*4882a593Smuzhiyun 		pkts = moder.pkts;
662*4882a593Smuzhiyun 	}
663*4882a593Smuzhiyun 
664*4882a593Smuzhiyun 	priv->dim.use_dim = ec->use_adaptive_rx_coalesce;
665*4882a593Smuzhiyun 
666*4882a593Smuzhiyun 	/* Apply desired coalescing parameters */
667*4882a593Smuzhiyun 	bcm_sysport_set_rx_coalesce(priv, usecs, pkts);
668*4882a593Smuzhiyun 
669*4882a593Smuzhiyun 	return 0;
670*4882a593Smuzhiyun }
671*4882a593Smuzhiyun 
bcm_sysport_free_cb(struct bcm_sysport_cb * cb)672*4882a593Smuzhiyun static void bcm_sysport_free_cb(struct bcm_sysport_cb *cb)
673*4882a593Smuzhiyun {
674*4882a593Smuzhiyun 	dev_consume_skb_any(cb->skb);
675*4882a593Smuzhiyun 	cb->skb = NULL;
676*4882a593Smuzhiyun 	dma_unmap_addr_set(cb, dma_addr, 0);
677*4882a593Smuzhiyun }
678*4882a593Smuzhiyun 
bcm_sysport_rx_refill(struct bcm_sysport_priv * priv,struct bcm_sysport_cb * cb)679*4882a593Smuzhiyun static struct sk_buff *bcm_sysport_rx_refill(struct bcm_sysport_priv *priv,
680*4882a593Smuzhiyun 					     struct bcm_sysport_cb *cb)
681*4882a593Smuzhiyun {
682*4882a593Smuzhiyun 	struct device *kdev = &priv->pdev->dev;
683*4882a593Smuzhiyun 	struct net_device *ndev = priv->netdev;
684*4882a593Smuzhiyun 	struct sk_buff *skb, *rx_skb;
685*4882a593Smuzhiyun 	dma_addr_t mapping;
686*4882a593Smuzhiyun 
687*4882a593Smuzhiyun 	/* Allocate a new SKB for a new packet */
688*4882a593Smuzhiyun 	skb = __netdev_alloc_skb(priv->netdev, RX_BUF_LENGTH,
689*4882a593Smuzhiyun 				 GFP_ATOMIC | __GFP_NOWARN);
690*4882a593Smuzhiyun 	if (!skb) {
691*4882a593Smuzhiyun 		priv->mib.alloc_rx_buff_failed++;
692*4882a593Smuzhiyun 		netif_err(priv, rx_err, ndev, "SKB alloc failed\n");
693*4882a593Smuzhiyun 		return NULL;
694*4882a593Smuzhiyun 	}
695*4882a593Smuzhiyun 
696*4882a593Smuzhiyun 	mapping = dma_map_single(kdev, skb->data,
697*4882a593Smuzhiyun 				 RX_BUF_LENGTH, DMA_FROM_DEVICE);
698*4882a593Smuzhiyun 	if (dma_mapping_error(kdev, mapping)) {
699*4882a593Smuzhiyun 		priv->mib.rx_dma_failed++;
700*4882a593Smuzhiyun 		dev_kfree_skb_any(skb);
701*4882a593Smuzhiyun 		netif_err(priv, rx_err, ndev, "DMA mapping failure\n");
702*4882a593Smuzhiyun 		return NULL;
703*4882a593Smuzhiyun 	}
704*4882a593Smuzhiyun 
705*4882a593Smuzhiyun 	/* Grab the current SKB on the ring */
706*4882a593Smuzhiyun 	rx_skb = cb->skb;
707*4882a593Smuzhiyun 	if (likely(rx_skb))
708*4882a593Smuzhiyun 		dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
709*4882a593Smuzhiyun 				 RX_BUF_LENGTH, DMA_FROM_DEVICE);
710*4882a593Smuzhiyun 
711*4882a593Smuzhiyun 	/* Put the new SKB on the ring */
712*4882a593Smuzhiyun 	cb->skb = skb;
713*4882a593Smuzhiyun 	dma_unmap_addr_set(cb, dma_addr, mapping);
714*4882a593Smuzhiyun 	dma_desc_set_addr(priv, cb->bd_addr, mapping);
715*4882a593Smuzhiyun 
716*4882a593Smuzhiyun 	netif_dbg(priv, rx_status, ndev, "RX refill\n");
717*4882a593Smuzhiyun 
718*4882a593Smuzhiyun 	/* Return the current SKB to the caller */
719*4882a593Smuzhiyun 	return rx_skb;
720*4882a593Smuzhiyun }
721*4882a593Smuzhiyun 
bcm_sysport_alloc_rx_bufs(struct bcm_sysport_priv * priv)722*4882a593Smuzhiyun static int bcm_sysport_alloc_rx_bufs(struct bcm_sysport_priv *priv)
723*4882a593Smuzhiyun {
724*4882a593Smuzhiyun 	struct bcm_sysport_cb *cb;
725*4882a593Smuzhiyun 	struct sk_buff *skb;
726*4882a593Smuzhiyun 	unsigned int i;
727*4882a593Smuzhiyun 
728*4882a593Smuzhiyun 	for (i = 0; i < priv->num_rx_bds; i++) {
729*4882a593Smuzhiyun 		cb = &priv->rx_cbs[i];
730*4882a593Smuzhiyun 		skb = bcm_sysport_rx_refill(priv, cb);
731*4882a593Smuzhiyun 		dev_kfree_skb(skb);
732*4882a593Smuzhiyun 		if (!cb->skb)
733*4882a593Smuzhiyun 			return -ENOMEM;
734*4882a593Smuzhiyun 	}
735*4882a593Smuzhiyun 
736*4882a593Smuzhiyun 	return 0;
737*4882a593Smuzhiyun }
738*4882a593Smuzhiyun 
739*4882a593Smuzhiyun /* Poll the hardware for up to budget packets to process */
bcm_sysport_desc_rx(struct bcm_sysport_priv * priv,unsigned int budget)740*4882a593Smuzhiyun static unsigned int bcm_sysport_desc_rx(struct bcm_sysport_priv *priv,
741*4882a593Smuzhiyun 					unsigned int budget)
742*4882a593Smuzhiyun {
743*4882a593Smuzhiyun 	struct bcm_sysport_stats64 *stats64 = &priv->stats64;
744*4882a593Smuzhiyun 	struct net_device *ndev = priv->netdev;
745*4882a593Smuzhiyun 	unsigned int processed = 0, to_process;
746*4882a593Smuzhiyun 	unsigned int processed_bytes = 0;
747*4882a593Smuzhiyun 	struct bcm_sysport_cb *cb;
748*4882a593Smuzhiyun 	struct sk_buff *skb;
749*4882a593Smuzhiyun 	unsigned int p_index;
750*4882a593Smuzhiyun 	u16 len, status;
751*4882a593Smuzhiyun 	struct bcm_rsb *rsb;
752*4882a593Smuzhiyun 
753*4882a593Smuzhiyun 	/* Clear status before servicing to reduce spurious interrupts */
754*4882a593Smuzhiyun 	intrl2_0_writel(priv, INTRL2_0_RDMA_MBDONE, INTRL2_CPU_CLEAR);
755*4882a593Smuzhiyun 
756*4882a593Smuzhiyun 	/* Determine how much we should process since last call, SYSTEMPORT Lite
757*4882a593Smuzhiyun 	 * groups the producer and consumer indexes into the same 32-bit
758*4882a593Smuzhiyun 	 * which we access using RDMA_CONS_INDEX
759*4882a593Smuzhiyun 	 */
760*4882a593Smuzhiyun 	if (!priv->is_lite)
761*4882a593Smuzhiyun 		p_index = rdma_readl(priv, RDMA_PROD_INDEX);
762*4882a593Smuzhiyun 	else
763*4882a593Smuzhiyun 		p_index = rdma_readl(priv, RDMA_CONS_INDEX);
764*4882a593Smuzhiyun 	p_index &= RDMA_PROD_INDEX_MASK;
765*4882a593Smuzhiyun 
766*4882a593Smuzhiyun 	to_process = (p_index - priv->rx_c_index) & RDMA_CONS_INDEX_MASK;
767*4882a593Smuzhiyun 
768*4882a593Smuzhiyun 	netif_dbg(priv, rx_status, ndev,
769*4882a593Smuzhiyun 		  "p_index=%d rx_c_index=%d to_process=%d\n",
770*4882a593Smuzhiyun 		  p_index, priv->rx_c_index, to_process);
771*4882a593Smuzhiyun 
772*4882a593Smuzhiyun 	while ((processed < to_process) && (processed < budget)) {
773*4882a593Smuzhiyun 		cb = &priv->rx_cbs[priv->rx_read_ptr];
774*4882a593Smuzhiyun 		skb = bcm_sysport_rx_refill(priv, cb);
775*4882a593Smuzhiyun 
776*4882a593Smuzhiyun 
777*4882a593Smuzhiyun 		/* We do not have a backing SKB, so we do not a corresponding
778*4882a593Smuzhiyun 		 * DMA mapping for this incoming packet since
779*4882a593Smuzhiyun 		 * bcm_sysport_rx_refill always either has both skb and mapping
780*4882a593Smuzhiyun 		 * or none.
781*4882a593Smuzhiyun 		 */
782*4882a593Smuzhiyun 		if (unlikely(!skb)) {
783*4882a593Smuzhiyun 			netif_err(priv, rx_err, ndev, "out of memory!\n");
784*4882a593Smuzhiyun 			ndev->stats.rx_dropped++;
785*4882a593Smuzhiyun 			ndev->stats.rx_errors++;
786*4882a593Smuzhiyun 			goto next;
787*4882a593Smuzhiyun 		}
788*4882a593Smuzhiyun 
789*4882a593Smuzhiyun 		/* Extract the Receive Status Block prepended */
790*4882a593Smuzhiyun 		rsb = (struct bcm_rsb *)skb->data;
791*4882a593Smuzhiyun 		len = (rsb->rx_status_len >> DESC_LEN_SHIFT) & DESC_LEN_MASK;
792*4882a593Smuzhiyun 		status = (rsb->rx_status_len >> DESC_STATUS_SHIFT) &
793*4882a593Smuzhiyun 			  DESC_STATUS_MASK;
794*4882a593Smuzhiyun 
795*4882a593Smuzhiyun 		netif_dbg(priv, rx_status, ndev,
796*4882a593Smuzhiyun 			  "p=%d, c=%d, rd_ptr=%d, len=%d, flag=0x%04x\n",
797*4882a593Smuzhiyun 			  p_index, priv->rx_c_index, priv->rx_read_ptr,
798*4882a593Smuzhiyun 			  len, status);
799*4882a593Smuzhiyun 
800*4882a593Smuzhiyun 		if (unlikely(len > RX_BUF_LENGTH)) {
801*4882a593Smuzhiyun 			netif_err(priv, rx_status, ndev, "oversized packet\n");
802*4882a593Smuzhiyun 			ndev->stats.rx_length_errors++;
803*4882a593Smuzhiyun 			ndev->stats.rx_errors++;
804*4882a593Smuzhiyun 			dev_kfree_skb_any(skb);
805*4882a593Smuzhiyun 			goto next;
806*4882a593Smuzhiyun 		}
807*4882a593Smuzhiyun 
808*4882a593Smuzhiyun 		if (unlikely(!(status & DESC_EOP) || !(status & DESC_SOP))) {
809*4882a593Smuzhiyun 			netif_err(priv, rx_status, ndev, "fragmented packet!\n");
810*4882a593Smuzhiyun 			ndev->stats.rx_dropped++;
811*4882a593Smuzhiyun 			ndev->stats.rx_errors++;
812*4882a593Smuzhiyun 			dev_kfree_skb_any(skb);
813*4882a593Smuzhiyun 			goto next;
814*4882a593Smuzhiyun 		}
815*4882a593Smuzhiyun 
816*4882a593Smuzhiyun 		if (unlikely(status & (RX_STATUS_ERR | RX_STATUS_OVFLOW))) {
817*4882a593Smuzhiyun 			netif_err(priv, rx_err, ndev, "error packet\n");
818*4882a593Smuzhiyun 			if (status & RX_STATUS_OVFLOW)
819*4882a593Smuzhiyun 				ndev->stats.rx_over_errors++;
820*4882a593Smuzhiyun 			ndev->stats.rx_dropped++;
821*4882a593Smuzhiyun 			ndev->stats.rx_errors++;
822*4882a593Smuzhiyun 			dev_kfree_skb_any(skb);
823*4882a593Smuzhiyun 			goto next;
824*4882a593Smuzhiyun 		}
825*4882a593Smuzhiyun 
826*4882a593Smuzhiyun 		skb_put(skb, len);
827*4882a593Smuzhiyun 
828*4882a593Smuzhiyun 		/* Hardware validated our checksum */
829*4882a593Smuzhiyun 		if (likely(status & DESC_L4_CSUM))
830*4882a593Smuzhiyun 			skb->ip_summed = CHECKSUM_UNNECESSARY;
831*4882a593Smuzhiyun 
832*4882a593Smuzhiyun 		/* Hardware pre-pends packets with 2bytes before Ethernet
833*4882a593Smuzhiyun 		 * header plus we have the Receive Status Block, strip off all
834*4882a593Smuzhiyun 		 * of this from the SKB.
835*4882a593Smuzhiyun 		 */
836*4882a593Smuzhiyun 		skb_pull(skb, sizeof(*rsb) + 2);
837*4882a593Smuzhiyun 		len -= (sizeof(*rsb) + 2);
838*4882a593Smuzhiyun 		processed_bytes += len;
839*4882a593Smuzhiyun 
840*4882a593Smuzhiyun 		/* UniMAC may forward CRC */
841*4882a593Smuzhiyun 		if (priv->crc_fwd) {
842*4882a593Smuzhiyun 			skb_trim(skb, len - ETH_FCS_LEN);
843*4882a593Smuzhiyun 			len -= ETH_FCS_LEN;
844*4882a593Smuzhiyun 		}
845*4882a593Smuzhiyun 
846*4882a593Smuzhiyun 		skb->protocol = eth_type_trans(skb, ndev);
847*4882a593Smuzhiyun 		ndev->stats.rx_packets++;
848*4882a593Smuzhiyun 		ndev->stats.rx_bytes += len;
849*4882a593Smuzhiyun 		u64_stats_update_begin(&priv->syncp);
850*4882a593Smuzhiyun 		stats64->rx_packets++;
851*4882a593Smuzhiyun 		stats64->rx_bytes += len;
852*4882a593Smuzhiyun 		u64_stats_update_end(&priv->syncp);
853*4882a593Smuzhiyun 
854*4882a593Smuzhiyun 		napi_gro_receive(&priv->napi, skb);
855*4882a593Smuzhiyun next:
856*4882a593Smuzhiyun 		processed++;
857*4882a593Smuzhiyun 		priv->rx_read_ptr++;
858*4882a593Smuzhiyun 
859*4882a593Smuzhiyun 		if (priv->rx_read_ptr == priv->num_rx_bds)
860*4882a593Smuzhiyun 			priv->rx_read_ptr = 0;
861*4882a593Smuzhiyun 	}
862*4882a593Smuzhiyun 
863*4882a593Smuzhiyun 	priv->dim.packets = processed;
864*4882a593Smuzhiyun 	priv->dim.bytes = processed_bytes;
865*4882a593Smuzhiyun 
866*4882a593Smuzhiyun 	return processed;
867*4882a593Smuzhiyun }
868*4882a593Smuzhiyun 
bcm_sysport_tx_reclaim_one(struct bcm_sysport_tx_ring * ring,struct bcm_sysport_cb * cb,unsigned int * bytes_compl,unsigned int * pkts_compl)869*4882a593Smuzhiyun static void bcm_sysport_tx_reclaim_one(struct bcm_sysport_tx_ring *ring,
870*4882a593Smuzhiyun 				       struct bcm_sysport_cb *cb,
871*4882a593Smuzhiyun 				       unsigned int *bytes_compl,
872*4882a593Smuzhiyun 				       unsigned int *pkts_compl)
873*4882a593Smuzhiyun {
874*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = ring->priv;
875*4882a593Smuzhiyun 	struct device *kdev = &priv->pdev->dev;
876*4882a593Smuzhiyun 
877*4882a593Smuzhiyun 	if (cb->skb) {
878*4882a593Smuzhiyun 		*bytes_compl += cb->skb->len;
879*4882a593Smuzhiyun 		dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
880*4882a593Smuzhiyun 				 dma_unmap_len(cb, dma_len),
881*4882a593Smuzhiyun 				 DMA_TO_DEVICE);
882*4882a593Smuzhiyun 		(*pkts_compl)++;
883*4882a593Smuzhiyun 		bcm_sysport_free_cb(cb);
884*4882a593Smuzhiyun 	/* SKB fragment */
885*4882a593Smuzhiyun 	} else if (dma_unmap_addr(cb, dma_addr)) {
886*4882a593Smuzhiyun 		*bytes_compl += dma_unmap_len(cb, dma_len);
887*4882a593Smuzhiyun 		dma_unmap_page(kdev, dma_unmap_addr(cb, dma_addr),
888*4882a593Smuzhiyun 			       dma_unmap_len(cb, dma_len), DMA_TO_DEVICE);
889*4882a593Smuzhiyun 		dma_unmap_addr_set(cb, dma_addr, 0);
890*4882a593Smuzhiyun 	}
891*4882a593Smuzhiyun }
892*4882a593Smuzhiyun 
893*4882a593Smuzhiyun /* Reclaim queued SKBs for transmission completion, lockless version */
__bcm_sysport_tx_reclaim(struct bcm_sysport_priv * priv,struct bcm_sysport_tx_ring * ring)894*4882a593Smuzhiyun static unsigned int __bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv,
895*4882a593Smuzhiyun 					     struct bcm_sysport_tx_ring *ring)
896*4882a593Smuzhiyun {
897*4882a593Smuzhiyun 	unsigned int pkts_compl = 0, bytes_compl = 0;
898*4882a593Smuzhiyun 	struct net_device *ndev = priv->netdev;
899*4882a593Smuzhiyun 	unsigned int txbds_processed = 0;
900*4882a593Smuzhiyun 	struct bcm_sysport_cb *cb;
901*4882a593Smuzhiyun 	unsigned int txbds_ready;
902*4882a593Smuzhiyun 	unsigned int c_index;
903*4882a593Smuzhiyun 	u32 hw_ind;
904*4882a593Smuzhiyun 
905*4882a593Smuzhiyun 	/* Clear status before servicing to reduce spurious interrupts */
906*4882a593Smuzhiyun 	if (!ring->priv->is_lite)
907*4882a593Smuzhiyun 		intrl2_1_writel(ring->priv, BIT(ring->index), INTRL2_CPU_CLEAR);
908*4882a593Smuzhiyun 	else
909*4882a593Smuzhiyun 		intrl2_0_writel(ring->priv, BIT(ring->index +
910*4882a593Smuzhiyun 				INTRL2_0_TDMA_MBDONE_SHIFT), INTRL2_CPU_CLEAR);
911*4882a593Smuzhiyun 
912*4882a593Smuzhiyun 	/* Compute how many descriptors have been processed since last call */
913*4882a593Smuzhiyun 	hw_ind = tdma_readl(priv, TDMA_DESC_RING_PROD_CONS_INDEX(ring->index));
914*4882a593Smuzhiyun 	c_index = (hw_ind >> RING_CONS_INDEX_SHIFT) & RING_CONS_INDEX_MASK;
915*4882a593Smuzhiyun 	txbds_ready = (c_index - ring->c_index) & RING_CONS_INDEX_MASK;
916*4882a593Smuzhiyun 
917*4882a593Smuzhiyun 	netif_dbg(priv, tx_done, ndev,
918*4882a593Smuzhiyun 		  "ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
919*4882a593Smuzhiyun 		  ring->index, ring->c_index, c_index, txbds_ready);
920*4882a593Smuzhiyun 
921*4882a593Smuzhiyun 	while (txbds_processed < txbds_ready) {
922*4882a593Smuzhiyun 		cb = &ring->cbs[ring->clean_index];
923*4882a593Smuzhiyun 		bcm_sysport_tx_reclaim_one(ring, cb, &bytes_compl, &pkts_compl);
924*4882a593Smuzhiyun 
925*4882a593Smuzhiyun 		ring->desc_count++;
926*4882a593Smuzhiyun 		txbds_processed++;
927*4882a593Smuzhiyun 
928*4882a593Smuzhiyun 		if (likely(ring->clean_index < ring->size - 1))
929*4882a593Smuzhiyun 			ring->clean_index++;
930*4882a593Smuzhiyun 		else
931*4882a593Smuzhiyun 			ring->clean_index = 0;
932*4882a593Smuzhiyun 	}
933*4882a593Smuzhiyun 
934*4882a593Smuzhiyun 	u64_stats_update_begin(&priv->syncp);
935*4882a593Smuzhiyun 	ring->packets += pkts_compl;
936*4882a593Smuzhiyun 	ring->bytes += bytes_compl;
937*4882a593Smuzhiyun 	u64_stats_update_end(&priv->syncp);
938*4882a593Smuzhiyun 
939*4882a593Smuzhiyun 	ring->c_index = c_index;
940*4882a593Smuzhiyun 
941*4882a593Smuzhiyun 	netif_dbg(priv, tx_done, ndev,
942*4882a593Smuzhiyun 		  "ring=%d c_index=%d pkts_compl=%d, bytes_compl=%d\n",
943*4882a593Smuzhiyun 		  ring->index, ring->c_index, pkts_compl, bytes_compl);
944*4882a593Smuzhiyun 
945*4882a593Smuzhiyun 	return pkts_compl;
946*4882a593Smuzhiyun }
947*4882a593Smuzhiyun 
948*4882a593Smuzhiyun /* Locked version of the per-ring TX reclaim routine */
bcm_sysport_tx_reclaim(struct bcm_sysport_priv * priv,struct bcm_sysport_tx_ring * ring)949*4882a593Smuzhiyun static unsigned int bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv,
950*4882a593Smuzhiyun 					   struct bcm_sysport_tx_ring *ring)
951*4882a593Smuzhiyun {
952*4882a593Smuzhiyun 	struct netdev_queue *txq;
953*4882a593Smuzhiyun 	unsigned int released;
954*4882a593Smuzhiyun 	unsigned long flags;
955*4882a593Smuzhiyun 
956*4882a593Smuzhiyun 	txq = netdev_get_tx_queue(priv->netdev, ring->index);
957*4882a593Smuzhiyun 
958*4882a593Smuzhiyun 	spin_lock_irqsave(&ring->lock, flags);
959*4882a593Smuzhiyun 	released = __bcm_sysport_tx_reclaim(priv, ring);
960*4882a593Smuzhiyun 	if (released)
961*4882a593Smuzhiyun 		netif_tx_wake_queue(txq);
962*4882a593Smuzhiyun 
963*4882a593Smuzhiyun 	spin_unlock_irqrestore(&ring->lock, flags);
964*4882a593Smuzhiyun 
965*4882a593Smuzhiyun 	return released;
966*4882a593Smuzhiyun }
967*4882a593Smuzhiyun 
968*4882a593Smuzhiyun /* Locked version of the per-ring TX reclaim, but does not wake the queue */
bcm_sysport_tx_clean(struct bcm_sysport_priv * priv,struct bcm_sysport_tx_ring * ring)969*4882a593Smuzhiyun static void bcm_sysport_tx_clean(struct bcm_sysport_priv *priv,
970*4882a593Smuzhiyun 				 struct bcm_sysport_tx_ring *ring)
971*4882a593Smuzhiyun {
972*4882a593Smuzhiyun 	unsigned long flags;
973*4882a593Smuzhiyun 
974*4882a593Smuzhiyun 	spin_lock_irqsave(&ring->lock, flags);
975*4882a593Smuzhiyun 	__bcm_sysport_tx_reclaim(priv, ring);
976*4882a593Smuzhiyun 	spin_unlock_irqrestore(&ring->lock, flags);
977*4882a593Smuzhiyun }
978*4882a593Smuzhiyun 
bcm_sysport_tx_poll(struct napi_struct * napi,int budget)979*4882a593Smuzhiyun static int bcm_sysport_tx_poll(struct napi_struct *napi, int budget)
980*4882a593Smuzhiyun {
981*4882a593Smuzhiyun 	struct bcm_sysport_tx_ring *ring =
982*4882a593Smuzhiyun 		container_of(napi, struct bcm_sysport_tx_ring, napi);
983*4882a593Smuzhiyun 	unsigned int work_done = 0;
984*4882a593Smuzhiyun 
985*4882a593Smuzhiyun 	work_done = bcm_sysport_tx_reclaim(ring->priv, ring);
986*4882a593Smuzhiyun 
987*4882a593Smuzhiyun 	if (work_done == 0) {
988*4882a593Smuzhiyun 		napi_complete(napi);
989*4882a593Smuzhiyun 		/* re-enable TX interrupt */
990*4882a593Smuzhiyun 		if (!ring->priv->is_lite)
991*4882a593Smuzhiyun 			intrl2_1_mask_clear(ring->priv, BIT(ring->index));
992*4882a593Smuzhiyun 		else
993*4882a593Smuzhiyun 			intrl2_0_mask_clear(ring->priv, BIT(ring->index +
994*4882a593Smuzhiyun 					    INTRL2_0_TDMA_MBDONE_SHIFT));
995*4882a593Smuzhiyun 
996*4882a593Smuzhiyun 		return 0;
997*4882a593Smuzhiyun 	}
998*4882a593Smuzhiyun 
999*4882a593Smuzhiyun 	return budget;
1000*4882a593Smuzhiyun }
1001*4882a593Smuzhiyun 
bcm_sysport_tx_reclaim_all(struct bcm_sysport_priv * priv)1002*4882a593Smuzhiyun static void bcm_sysport_tx_reclaim_all(struct bcm_sysport_priv *priv)
1003*4882a593Smuzhiyun {
1004*4882a593Smuzhiyun 	unsigned int q;
1005*4882a593Smuzhiyun 
1006*4882a593Smuzhiyun 	for (q = 0; q < priv->netdev->num_tx_queues; q++)
1007*4882a593Smuzhiyun 		bcm_sysport_tx_reclaim(priv, &priv->tx_rings[q]);
1008*4882a593Smuzhiyun }
1009*4882a593Smuzhiyun 
bcm_sysport_poll(struct napi_struct * napi,int budget)1010*4882a593Smuzhiyun static int bcm_sysport_poll(struct napi_struct *napi, int budget)
1011*4882a593Smuzhiyun {
1012*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv =
1013*4882a593Smuzhiyun 		container_of(napi, struct bcm_sysport_priv, napi);
1014*4882a593Smuzhiyun 	struct dim_sample dim_sample = {};
1015*4882a593Smuzhiyun 	unsigned int work_done = 0;
1016*4882a593Smuzhiyun 
1017*4882a593Smuzhiyun 	work_done = bcm_sysport_desc_rx(priv, budget);
1018*4882a593Smuzhiyun 
1019*4882a593Smuzhiyun 	priv->rx_c_index += work_done;
1020*4882a593Smuzhiyun 	priv->rx_c_index &= RDMA_CONS_INDEX_MASK;
1021*4882a593Smuzhiyun 
1022*4882a593Smuzhiyun 	/* SYSTEMPORT Lite groups the producer/consumer index, producer is
1023*4882a593Smuzhiyun 	 * maintained by HW, but writes to it will be ignore while RDMA
1024*4882a593Smuzhiyun 	 * is active
1025*4882a593Smuzhiyun 	 */
1026*4882a593Smuzhiyun 	if (!priv->is_lite)
1027*4882a593Smuzhiyun 		rdma_writel(priv, priv->rx_c_index, RDMA_CONS_INDEX);
1028*4882a593Smuzhiyun 	else
1029*4882a593Smuzhiyun 		rdma_writel(priv, priv->rx_c_index << 16, RDMA_CONS_INDEX);
1030*4882a593Smuzhiyun 
1031*4882a593Smuzhiyun 	if (work_done < budget) {
1032*4882a593Smuzhiyun 		napi_complete_done(napi, work_done);
1033*4882a593Smuzhiyun 		/* re-enable RX interrupts */
1034*4882a593Smuzhiyun 		intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE);
1035*4882a593Smuzhiyun 	}
1036*4882a593Smuzhiyun 
1037*4882a593Smuzhiyun 	if (priv->dim.use_dim) {
1038*4882a593Smuzhiyun 		dim_update_sample(priv->dim.event_ctr, priv->dim.packets,
1039*4882a593Smuzhiyun 				  priv->dim.bytes, &dim_sample);
1040*4882a593Smuzhiyun 		net_dim(&priv->dim.dim, dim_sample);
1041*4882a593Smuzhiyun 	}
1042*4882a593Smuzhiyun 
1043*4882a593Smuzhiyun 	return work_done;
1044*4882a593Smuzhiyun }
1045*4882a593Smuzhiyun 
mpd_enable_set(struct bcm_sysport_priv * priv,bool enable)1046*4882a593Smuzhiyun static void mpd_enable_set(struct bcm_sysport_priv *priv, bool enable)
1047*4882a593Smuzhiyun {
1048*4882a593Smuzhiyun 	u32 reg, bit;
1049*4882a593Smuzhiyun 
1050*4882a593Smuzhiyun 	reg = umac_readl(priv, UMAC_MPD_CTRL);
1051*4882a593Smuzhiyun 	if (enable)
1052*4882a593Smuzhiyun 		reg |= MPD_EN;
1053*4882a593Smuzhiyun 	else
1054*4882a593Smuzhiyun 		reg &= ~MPD_EN;
1055*4882a593Smuzhiyun 	umac_writel(priv, reg, UMAC_MPD_CTRL);
1056*4882a593Smuzhiyun 
1057*4882a593Smuzhiyun 	if (priv->is_lite)
1058*4882a593Smuzhiyun 		bit = RBUF_ACPI_EN_LITE;
1059*4882a593Smuzhiyun 	else
1060*4882a593Smuzhiyun 		bit = RBUF_ACPI_EN;
1061*4882a593Smuzhiyun 
1062*4882a593Smuzhiyun 	reg = rbuf_readl(priv, RBUF_CONTROL);
1063*4882a593Smuzhiyun 	if (enable)
1064*4882a593Smuzhiyun 		reg |= bit;
1065*4882a593Smuzhiyun 	else
1066*4882a593Smuzhiyun 		reg &= ~bit;
1067*4882a593Smuzhiyun 	rbuf_writel(priv, reg, RBUF_CONTROL);
1068*4882a593Smuzhiyun }
1069*4882a593Smuzhiyun 
bcm_sysport_resume_from_wol(struct bcm_sysport_priv * priv)1070*4882a593Smuzhiyun static void bcm_sysport_resume_from_wol(struct bcm_sysport_priv *priv)
1071*4882a593Smuzhiyun {
1072*4882a593Smuzhiyun 	unsigned int index;
1073*4882a593Smuzhiyun 	u32 reg;
1074*4882a593Smuzhiyun 
1075*4882a593Smuzhiyun 	/* Disable RXCHK, active filters and Broadcom tag matching */
1076*4882a593Smuzhiyun 	reg = rxchk_readl(priv, RXCHK_CONTROL);
1077*4882a593Smuzhiyun 	reg &= ~(RXCHK_BRCM_TAG_MATCH_MASK <<
1078*4882a593Smuzhiyun 		 RXCHK_BRCM_TAG_MATCH_SHIFT | RXCHK_EN | RXCHK_BRCM_TAG_EN);
1079*4882a593Smuzhiyun 	rxchk_writel(priv, reg, RXCHK_CONTROL);
1080*4882a593Smuzhiyun 
1081*4882a593Smuzhiyun 	/* Make sure we restore correct CID index in case HW lost
1082*4882a593Smuzhiyun 	 * its context during deep idle state
1083*4882a593Smuzhiyun 	 */
1084*4882a593Smuzhiyun 	for_each_set_bit(index, priv->filters, RXCHK_BRCM_TAG_MAX) {
1085*4882a593Smuzhiyun 		rxchk_writel(priv, priv->filters_loc[index] <<
1086*4882a593Smuzhiyun 			     RXCHK_BRCM_TAG_CID_SHIFT, RXCHK_BRCM_TAG(index));
1087*4882a593Smuzhiyun 		rxchk_writel(priv, 0xff00ffff, RXCHK_BRCM_TAG_MASK(index));
1088*4882a593Smuzhiyun 	}
1089*4882a593Smuzhiyun 
1090*4882a593Smuzhiyun 	/* Clear the MagicPacket detection logic */
1091*4882a593Smuzhiyun 	mpd_enable_set(priv, false);
1092*4882a593Smuzhiyun 
1093*4882a593Smuzhiyun 	reg = intrl2_0_readl(priv, INTRL2_CPU_STATUS);
1094*4882a593Smuzhiyun 	if (reg & INTRL2_0_MPD)
1095*4882a593Smuzhiyun 		netdev_info(priv->netdev, "Wake-on-LAN (MPD) interrupt!\n");
1096*4882a593Smuzhiyun 
1097*4882a593Smuzhiyun 	if (reg & INTRL2_0_BRCM_MATCH_TAG) {
1098*4882a593Smuzhiyun 		reg = rxchk_readl(priv, RXCHK_BRCM_TAG_MATCH_STATUS) &
1099*4882a593Smuzhiyun 				  RXCHK_BRCM_TAG_MATCH_MASK;
1100*4882a593Smuzhiyun 		netdev_info(priv->netdev,
1101*4882a593Smuzhiyun 			    "Wake-on-LAN (filters 0x%02x) interrupt!\n", reg);
1102*4882a593Smuzhiyun 	}
1103*4882a593Smuzhiyun 
1104*4882a593Smuzhiyun 	netif_dbg(priv, wol, priv->netdev, "resumed from WOL\n");
1105*4882a593Smuzhiyun }
1106*4882a593Smuzhiyun 
bcm_sysport_dim_work(struct work_struct * work)1107*4882a593Smuzhiyun static void bcm_sysport_dim_work(struct work_struct *work)
1108*4882a593Smuzhiyun {
1109*4882a593Smuzhiyun 	struct dim *dim = container_of(work, struct dim, work);
1110*4882a593Smuzhiyun 	struct bcm_sysport_net_dim *ndim =
1111*4882a593Smuzhiyun 			container_of(dim, struct bcm_sysport_net_dim, dim);
1112*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv =
1113*4882a593Smuzhiyun 			container_of(ndim, struct bcm_sysport_priv, dim);
1114*4882a593Smuzhiyun 	struct dim_cq_moder cur_profile = net_dim_get_rx_moderation(dim->mode,
1115*4882a593Smuzhiyun 								    dim->profile_ix);
1116*4882a593Smuzhiyun 
1117*4882a593Smuzhiyun 	bcm_sysport_set_rx_coalesce(priv, cur_profile.usec, cur_profile.pkts);
1118*4882a593Smuzhiyun 	dim->state = DIM_START_MEASURE;
1119*4882a593Smuzhiyun }
1120*4882a593Smuzhiyun 
1121*4882a593Smuzhiyun /* RX and misc interrupt routine */
bcm_sysport_rx_isr(int irq,void * dev_id)1122*4882a593Smuzhiyun static irqreturn_t bcm_sysport_rx_isr(int irq, void *dev_id)
1123*4882a593Smuzhiyun {
1124*4882a593Smuzhiyun 	struct net_device *dev = dev_id;
1125*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
1126*4882a593Smuzhiyun 	struct bcm_sysport_tx_ring *txr;
1127*4882a593Smuzhiyun 	unsigned int ring, ring_bit;
1128*4882a593Smuzhiyun 
1129*4882a593Smuzhiyun 	priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
1130*4882a593Smuzhiyun 			  ~intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
1131*4882a593Smuzhiyun 	intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
1132*4882a593Smuzhiyun 
1133*4882a593Smuzhiyun 	if (unlikely(priv->irq0_stat == 0)) {
1134*4882a593Smuzhiyun 		netdev_warn(priv->netdev, "spurious RX interrupt\n");
1135*4882a593Smuzhiyun 		return IRQ_NONE;
1136*4882a593Smuzhiyun 	}
1137*4882a593Smuzhiyun 
1138*4882a593Smuzhiyun 	if (priv->irq0_stat & INTRL2_0_RDMA_MBDONE) {
1139*4882a593Smuzhiyun 		priv->dim.event_ctr++;
1140*4882a593Smuzhiyun 		if (likely(napi_schedule_prep(&priv->napi))) {
1141*4882a593Smuzhiyun 			/* disable RX interrupts */
1142*4882a593Smuzhiyun 			intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE);
1143*4882a593Smuzhiyun 			__napi_schedule_irqoff(&priv->napi);
1144*4882a593Smuzhiyun 		}
1145*4882a593Smuzhiyun 	}
1146*4882a593Smuzhiyun 
1147*4882a593Smuzhiyun 	/* TX ring is full, perform a full reclaim since we do not know
1148*4882a593Smuzhiyun 	 * which one would trigger this interrupt
1149*4882a593Smuzhiyun 	 */
1150*4882a593Smuzhiyun 	if (priv->irq0_stat & INTRL2_0_TX_RING_FULL)
1151*4882a593Smuzhiyun 		bcm_sysport_tx_reclaim_all(priv);
1152*4882a593Smuzhiyun 
1153*4882a593Smuzhiyun 	if (!priv->is_lite)
1154*4882a593Smuzhiyun 		goto out;
1155*4882a593Smuzhiyun 
1156*4882a593Smuzhiyun 	for (ring = 0; ring < dev->num_tx_queues; ring++) {
1157*4882a593Smuzhiyun 		ring_bit = BIT(ring + INTRL2_0_TDMA_MBDONE_SHIFT);
1158*4882a593Smuzhiyun 		if (!(priv->irq0_stat & ring_bit))
1159*4882a593Smuzhiyun 			continue;
1160*4882a593Smuzhiyun 
1161*4882a593Smuzhiyun 		txr = &priv->tx_rings[ring];
1162*4882a593Smuzhiyun 
1163*4882a593Smuzhiyun 		if (likely(napi_schedule_prep(&txr->napi))) {
1164*4882a593Smuzhiyun 			intrl2_0_mask_set(priv, ring_bit);
1165*4882a593Smuzhiyun 			__napi_schedule(&txr->napi);
1166*4882a593Smuzhiyun 		}
1167*4882a593Smuzhiyun 	}
1168*4882a593Smuzhiyun out:
1169*4882a593Smuzhiyun 	return IRQ_HANDLED;
1170*4882a593Smuzhiyun }
1171*4882a593Smuzhiyun 
1172*4882a593Smuzhiyun /* TX interrupt service routine */
bcm_sysport_tx_isr(int irq,void * dev_id)1173*4882a593Smuzhiyun static irqreturn_t bcm_sysport_tx_isr(int irq, void *dev_id)
1174*4882a593Smuzhiyun {
1175*4882a593Smuzhiyun 	struct net_device *dev = dev_id;
1176*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
1177*4882a593Smuzhiyun 	struct bcm_sysport_tx_ring *txr;
1178*4882a593Smuzhiyun 	unsigned int ring;
1179*4882a593Smuzhiyun 
1180*4882a593Smuzhiyun 	priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
1181*4882a593Smuzhiyun 				~intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
1182*4882a593Smuzhiyun 	intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1183*4882a593Smuzhiyun 
1184*4882a593Smuzhiyun 	if (unlikely(priv->irq1_stat == 0)) {
1185*4882a593Smuzhiyun 		netdev_warn(priv->netdev, "spurious TX interrupt\n");
1186*4882a593Smuzhiyun 		return IRQ_NONE;
1187*4882a593Smuzhiyun 	}
1188*4882a593Smuzhiyun 
1189*4882a593Smuzhiyun 	for (ring = 0; ring < dev->num_tx_queues; ring++) {
1190*4882a593Smuzhiyun 		if (!(priv->irq1_stat & BIT(ring)))
1191*4882a593Smuzhiyun 			continue;
1192*4882a593Smuzhiyun 
1193*4882a593Smuzhiyun 		txr = &priv->tx_rings[ring];
1194*4882a593Smuzhiyun 
1195*4882a593Smuzhiyun 		if (likely(napi_schedule_prep(&txr->napi))) {
1196*4882a593Smuzhiyun 			intrl2_1_mask_set(priv, BIT(ring));
1197*4882a593Smuzhiyun 			__napi_schedule_irqoff(&txr->napi);
1198*4882a593Smuzhiyun 		}
1199*4882a593Smuzhiyun 	}
1200*4882a593Smuzhiyun 
1201*4882a593Smuzhiyun 	return IRQ_HANDLED;
1202*4882a593Smuzhiyun }
1203*4882a593Smuzhiyun 
bcm_sysport_wol_isr(int irq,void * dev_id)1204*4882a593Smuzhiyun static irqreturn_t bcm_sysport_wol_isr(int irq, void *dev_id)
1205*4882a593Smuzhiyun {
1206*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = dev_id;
1207*4882a593Smuzhiyun 
1208*4882a593Smuzhiyun 	pm_wakeup_event(&priv->pdev->dev, 0);
1209*4882a593Smuzhiyun 
1210*4882a593Smuzhiyun 	return IRQ_HANDLED;
1211*4882a593Smuzhiyun }
1212*4882a593Smuzhiyun 
1213*4882a593Smuzhiyun #ifdef CONFIG_NET_POLL_CONTROLLER
bcm_sysport_poll_controller(struct net_device * dev)1214*4882a593Smuzhiyun static void bcm_sysport_poll_controller(struct net_device *dev)
1215*4882a593Smuzhiyun {
1216*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
1217*4882a593Smuzhiyun 
1218*4882a593Smuzhiyun 	disable_irq(priv->irq0);
1219*4882a593Smuzhiyun 	bcm_sysport_rx_isr(priv->irq0, priv);
1220*4882a593Smuzhiyun 	enable_irq(priv->irq0);
1221*4882a593Smuzhiyun 
1222*4882a593Smuzhiyun 	if (!priv->is_lite) {
1223*4882a593Smuzhiyun 		disable_irq(priv->irq1);
1224*4882a593Smuzhiyun 		bcm_sysport_tx_isr(priv->irq1, priv);
1225*4882a593Smuzhiyun 		enable_irq(priv->irq1);
1226*4882a593Smuzhiyun 	}
1227*4882a593Smuzhiyun }
1228*4882a593Smuzhiyun #endif
1229*4882a593Smuzhiyun 
bcm_sysport_insert_tsb(struct sk_buff * skb,struct net_device * dev)1230*4882a593Smuzhiyun static struct sk_buff *bcm_sysport_insert_tsb(struct sk_buff *skb,
1231*4882a593Smuzhiyun 					      struct net_device *dev)
1232*4882a593Smuzhiyun {
1233*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
1234*4882a593Smuzhiyun 	struct sk_buff *nskb;
1235*4882a593Smuzhiyun 	struct bcm_tsb *tsb;
1236*4882a593Smuzhiyun 	u32 csum_info;
1237*4882a593Smuzhiyun 	u8 ip_proto;
1238*4882a593Smuzhiyun 	u16 csum_start;
1239*4882a593Smuzhiyun 	__be16 ip_ver;
1240*4882a593Smuzhiyun 
1241*4882a593Smuzhiyun 	/* Re-allocate SKB if needed */
1242*4882a593Smuzhiyun 	if (unlikely(skb_headroom(skb) < sizeof(*tsb))) {
1243*4882a593Smuzhiyun 		nskb = skb_realloc_headroom(skb, sizeof(*tsb));
1244*4882a593Smuzhiyun 		if (!nskb) {
1245*4882a593Smuzhiyun 			dev_kfree_skb_any(skb);
1246*4882a593Smuzhiyun 			priv->mib.tx_realloc_tsb_failed++;
1247*4882a593Smuzhiyun 			dev->stats.tx_errors++;
1248*4882a593Smuzhiyun 			dev->stats.tx_dropped++;
1249*4882a593Smuzhiyun 			return NULL;
1250*4882a593Smuzhiyun 		}
1251*4882a593Smuzhiyun 		dev_consume_skb_any(skb);
1252*4882a593Smuzhiyun 		skb = nskb;
1253*4882a593Smuzhiyun 		priv->mib.tx_realloc_tsb++;
1254*4882a593Smuzhiyun 	}
1255*4882a593Smuzhiyun 
1256*4882a593Smuzhiyun 	tsb = skb_push(skb, sizeof(*tsb));
1257*4882a593Smuzhiyun 	/* Zero-out TSB by default */
1258*4882a593Smuzhiyun 	memset(tsb, 0, sizeof(*tsb));
1259*4882a593Smuzhiyun 
1260*4882a593Smuzhiyun 	if (skb_vlan_tag_present(skb)) {
1261*4882a593Smuzhiyun 		tsb->pcp_dei_vid = skb_vlan_tag_get_prio(skb) & PCP_DEI_MASK;
1262*4882a593Smuzhiyun 		tsb->pcp_dei_vid |= (u32)skb_vlan_tag_get_id(skb) << VID_SHIFT;
1263*4882a593Smuzhiyun 	}
1264*4882a593Smuzhiyun 
1265*4882a593Smuzhiyun 	if (skb->ip_summed == CHECKSUM_PARTIAL) {
1266*4882a593Smuzhiyun 		ip_ver = skb->protocol;
1267*4882a593Smuzhiyun 		switch (ip_ver) {
1268*4882a593Smuzhiyun 		case htons(ETH_P_IP):
1269*4882a593Smuzhiyun 			ip_proto = ip_hdr(skb)->protocol;
1270*4882a593Smuzhiyun 			break;
1271*4882a593Smuzhiyun 		case htons(ETH_P_IPV6):
1272*4882a593Smuzhiyun 			ip_proto = ipv6_hdr(skb)->nexthdr;
1273*4882a593Smuzhiyun 			break;
1274*4882a593Smuzhiyun 		default:
1275*4882a593Smuzhiyun 			return skb;
1276*4882a593Smuzhiyun 		}
1277*4882a593Smuzhiyun 
1278*4882a593Smuzhiyun 		/* Get the checksum offset and the L4 (transport) offset */
1279*4882a593Smuzhiyun 		csum_start = skb_checksum_start_offset(skb) - sizeof(*tsb);
1280*4882a593Smuzhiyun 		/* Account for the HW inserted VLAN tag */
1281*4882a593Smuzhiyun 		if (skb_vlan_tag_present(skb))
1282*4882a593Smuzhiyun 			csum_start += VLAN_HLEN;
1283*4882a593Smuzhiyun 		csum_info = (csum_start + skb->csum_offset) & L4_CSUM_PTR_MASK;
1284*4882a593Smuzhiyun 		csum_info |= (csum_start << L4_PTR_SHIFT);
1285*4882a593Smuzhiyun 
1286*4882a593Smuzhiyun 		if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1287*4882a593Smuzhiyun 			csum_info |= L4_LENGTH_VALID;
1288*4882a593Smuzhiyun 			if (ip_proto == IPPROTO_UDP &&
1289*4882a593Smuzhiyun 			    ip_ver == htons(ETH_P_IP))
1290*4882a593Smuzhiyun 				csum_info |= L4_UDP;
1291*4882a593Smuzhiyun 		} else {
1292*4882a593Smuzhiyun 			csum_info = 0;
1293*4882a593Smuzhiyun 		}
1294*4882a593Smuzhiyun 
1295*4882a593Smuzhiyun 		tsb->l4_ptr_dest_map = csum_info;
1296*4882a593Smuzhiyun 	}
1297*4882a593Smuzhiyun 
1298*4882a593Smuzhiyun 	return skb;
1299*4882a593Smuzhiyun }
1300*4882a593Smuzhiyun 
bcm_sysport_xmit(struct sk_buff * skb,struct net_device * dev)1301*4882a593Smuzhiyun static netdev_tx_t bcm_sysport_xmit(struct sk_buff *skb,
1302*4882a593Smuzhiyun 				    struct net_device *dev)
1303*4882a593Smuzhiyun {
1304*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
1305*4882a593Smuzhiyun 	struct device *kdev = &priv->pdev->dev;
1306*4882a593Smuzhiyun 	struct bcm_sysport_tx_ring *ring;
1307*4882a593Smuzhiyun 	unsigned long flags, desc_flags;
1308*4882a593Smuzhiyun 	struct bcm_sysport_cb *cb;
1309*4882a593Smuzhiyun 	struct netdev_queue *txq;
1310*4882a593Smuzhiyun 	u32 len_status, addr_lo;
1311*4882a593Smuzhiyun 	unsigned int skb_len;
1312*4882a593Smuzhiyun 	dma_addr_t mapping;
1313*4882a593Smuzhiyun 	u16 queue;
1314*4882a593Smuzhiyun 	int ret;
1315*4882a593Smuzhiyun 
1316*4882a593Smuzhiyun 	queue = skb_get_queue_mapping(skb);
1317*4882a593Smuzhiyun 	txq = netdev_get_tx_queue(dev, queue);
1318*4882a593Smuzhiyun 	ring = &priv->tx_rings[queue];
1319*4882a593Smuzhiyun 
1320*4882a593Smuzhiyun 	/* lock against tx reclaim in BH context and TX ring full interrupt */
1321*4882a593Smuzhiyun 	spin_lock_irqsave(&ring->lock, flags);
1322*4882a593Smuzhiyun 	if (unlikely(ring->desc_count == 0)) {
1323*4882a593Smuzhiyun 		netif_tx_stop_queue(txq);
1324*4882a593Smuzhiyun 		netdev_err(dev, "queue %d awake and ring full!\n", queue);
1325*4882a593Smuzhiyun 		ret = NETDEV_TX_BUSY;
1326*4882a593Smuzhiyun 		goto out;
1327*4882a593Smuzhiyun 	}
1328*4882a593Smuzhiyun 
1329*4882a593Smuzhiyun 	/* Insert TSB and checksum infos */
1330*4882a593Smuzhiyun 	if (priv->tsb_en) {
1331*4882a593Smuzhiyun 		skb = bcm_sysport_insert_tsb(skb, dev);
1332*4882a593Smuzhiyun 		if (!skb) {
1333*4882a593Smuzhiyun 			ret = NETDEV_TX_OK;
1334*4882a593Smuzhiyun 			goto out;
1335*4882a593Smuzhiyun 		}
1336*4882a593Smuzhiyun 	}
1337*4882a593Smuzhiyun 
1338*4882a593Smuzhiyun 	skb_len = skb->len;
1339*4882a593Smuzhiyun 
1340*4882a593Smuzhiyun 	mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1341*4882a593Smuzhiyun 	if (dma_mapping_error(kdev, mapping)) {
1342*4882a593Smuzhiyun 		priv->mib.tx_dma_failed++;
1343*4882a593Smuzhiyun 		netif_err(priv, tx_err, dev, "DMA map failed at %p (len=%d)\n",
1344*4882a593Smuzhiyun 			  skb->data, skb_len);
1345*4882a593Smuzhiyun 		ret = NETDEV_TX_OK;
1346*4882a593Smuzhiyun 		goto out;
1347*4882a593Smuzhiyun 	}
1348*4882a593Smuzhiyun 
1349*4882a593Smuzhiyun 	/* Remember the SKB for future freeing */
1350*4882a593Smuzhiyun 	cb = &ring->cbs[ring->curr_desc];
1351*4882a593Smuzhiyun 	cb->skb = skb;
1352*4882a593Smuzhiyun 	dma_unmap_addr_set(cb, dma_addr, mapping);
1353*4882a593Smuzhiyun 	dma_unmap_len_set(cb, dma_len, skb_len);
1354*4882a593Smuzhiyun 
1355*4882a593Smuzhiyun 	addr_lo = lower_32_bits(mapping);
1356*4882a593Smuzhiyun 	len_status = upper_32_bits(mapping) & DESC_ADDR_HI_MASK;
1357*4882a593Smuzhiyun 	len_status |= (skb_len << DESC_LEN_SHIFT);
1358*4882a593Smuzhiyun 	len_status |= (DESC_SOP | DESC_EOP | TX_STATUS_APP_CRC) <<
1359*4882a593Smuzhiyun 		       DESC_STATUS_SHIFT;
1360*4882a593Smuzhiyun 	if (skb->ip_summed == CHECKSUM_PARTIAL)
1361*4882a593Smuzhiyun 		len_status |= (DESC_L4_CSUM << DESC_STATUS_SHIFT);
1362*4882a593Smuzhiyun 	if (skb_vlan_tag_present(skb))
1363*4882a593Smuzhiyun 		len_status |= (TX_STATUS_VLAN_VID_TSB << DESC_STATUS_SHIFT);
1364*4882a593Smuzhiyun 
1365*4882a593Smuzhiyun 	ring->curr_desc++;
1366*4882a593Smuzhiyun 	if (ring->curr_desc == ring->size)
1367*4882a593Smuzhiyun 		ring->curr_desc = 0;
1368*4882a593Smuzhiyun 	ring->desc_count--;
1369*4882a593Smuzhiyun 
1370*4882a593Smuzhiyun 	/* Ports are latched, so write upper address first */
1371*4882a593Smuzhiyun 	spin_lock_irqsave(&priv->desc_lock, desc_flags);
1372*4882a593Smuzhiyun 	tdma_writel(priv, len_status, TDMA_WRITE_PORT_HI(ring->index));
1373*4882a593Smuzhiyun 	tdma_writel(priv, addr_lo, TDMA_WRITE_PORT_LO(ring->index));
1374*4882a593Smuzhiyun 	spin_unlock_irqrestore(&priv->desc_lock, desc_flags);
1375*4882a593Smuzhiyun 
1376*4882a593Smuzhiyun 	/* Check ring space and update SW control flow */
1377*4882a593Smuzhiyun 	if (ring->desc_count == 0)
1378*4882a593Smuzhiyun 		netif_tx_stop_queue(txq);
1379*4882a593Smuzhiyun 
1380*4882a593Smuzhiyun 	netif_dbg(priv, tx_queued, dev, "ring=%d desc_count=%d, curr_desc=%d\n",
1381*4882a593Smuzhiyun 		  ring->index, ring->desc_count, ring->curr_desc);
1382*4882a593Smuzhiyun 
1383*4882a593Smuzhiyun 	ret = NETDEV_TX_OK;
1384*4882a593Smuzhiyun out:
1385*4882a593Smuzhiyun 	spin_unlock_irqrestore(&ring->lock, flags);
1386*4882a593Smuzhiyun 	return ret;
1387*4882a593Smuzhiyun }
1388*4882a593Smuzhiyun 
bcm_sysport_tx_timeout(struct net_device * dev,unsigned int txqueue)1389*4882a593Smuzhiyun static void bcm_sysport_tx_timeout(struct net_device *dev, unsigned int txqueue)
1390*4882a593Smuzhiyun {
1391*4882a593Smuzhiyun 	netdev_warn(dev, "transmit timeout!\n");
1392*4882a593Smuzhiyun 
1393*4882a593Smuzhiyun 	netif_trans_update(dev);
1394*4882a593Smuzhiyun 	dev->stats.tx_errors++;
1395*4882a593Smuzhiyun 
1396*4882a593Smuzhiyun 	netif_tx_wake_all_queues(dev);
1397*4882a593Smuzhiyun }
1398*4882a593Smuzhiyun 
1399*4882a593Smuzhiyun /* phylib adjust link callback */
bcm_sysport_adj_link(struct net_device * dev)1400*4882a593Smuzhiyun static void bcm_sysport_adj_link(struct net_device *dev)
1401*4882a593Smuzhiyun {
1402*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
1403*4882a593Smuzhiyun 	struct phy_device *phydev = dev->phydev;
1404*4882a593Smuzhiyun 	unsigned int changed = 0;
1405*4882a593Smuzhiyun 	u32 cmd_bits = 0, reg;
1406*4882a593Smuzhiyun 
1407*4882a593Smuzhiyun 	if (priv->old_link != phydev->link) {
1408*4882a593Smuzhiyun 		changed = 1;
1409*4882a593Smuzhiyun 		priv->old_link = phydev->link;
1410*4882a593Smuzhiyun 	}
1411*4882a593Smuzhiyun 
1412*4882a593Smuzhiyun 	if (priv->old_duplex != phydev->duplex) {
1413*4882a593Smuzhiyun 		changed = 1;
1414*4882a593Smuzhiyun 		priv->old_duplex = phydev->duplex;
1415*4882a593Smuzhiyun 	}
1416*4882a593Smuzhiyun 
1417*4882a593Smuzhiyun 	if (priv->is_lite)
1418*4882a593Smuzhiyun 		goto out;
1419*4882a593Smuzhiyun 
1420*4882a593Smuzhiyun 	switch (phydev->speed) {
1421*4882a593Smuzhiyun 	case SPEED_2500:
1422*4882a593Smuzhiyun 		cmd_bits = CMD_SPEED_2500;
1423*4882a593Smuzhiyun 		break;
1424*4882a593Smuzhiyun 	case SPEED_1000:
1425*4882a593Smuzhiyun 		cmd_bits = CMD_SPEED_1000;
1426*4882a593Smuzhiyun 		break;
1427*4882a593Smuzhiyun 	case SPEED_100:
1428*4882a593Smuzhiyun 		cmd_bits = CMD_SPEED_100;
1429*4882a593Smuzhiyun 		break;
1430*4882a593Smuzhiyun 	case SPEED_10:
1431*4882a593Smuzhiyun 		cmd_bits = CMD_SPEED_10;
1432*4882a593Smuzhiyun 		break;
1433*4882a593Smuzhiyun 	default:
1434*4882a593Smuzhiyun 		break;
1435*4882a593Smuzhiyun 	}
1436*4882a593Smuzhiyun 	cmd_bits <<= CMD_SPEED_SHIFT;
1437*4882a593Smuzhiyun 
1438*4882a593Smuzhiyun 	if (phydev->duplex == DUPLEX_HALF)
1439*4882a593Smuzhiyun 		cmd_bits |= CMD_HD_EN;
1440*4882a593Smuzhiyun 
1441*4882a593Smuzhiyun 	if (priv->old_pause != phydev->pause) {
1442*4882a593Smuzhiyun 		changed = 1;
1443*4882a593Smuzhiyun 		priv->old_pause = phydev->pause;
1444*4882a593Smuzhiyun 	}
1445*4882a593Smuzhiyun 
1446*4882a593Smuzhiyun 	if (!phydev->pause)
1447*4882a593Smuzhiyun 		cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
1448*4882a593Smuzhiyun 
1449*4882a593Smuzhiyun 	if (!changed)
1450*4882a593Smuzhiyun 		return;
1451*4882a593Smuzhiyun 
1452*4882a593Smuzhiyun 	if (phydev->link) {
1453*4882a593Smuzhiyun 		reg = umac_readl(priv, UMAC_CMD);
1454*4882a593Smuzhiyun 		reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
1455*4882a593Smuzhiyun 			CMD_HD_EN | CMD_RX_PAUSE_IGNORE |
1456*4882a593Smuzhiyun 			CMD_TX_PAUSE_IGNORE);
1457*4882a593Smuzhiyun 		reg |= cmd_bits;
1458*4882a593Smuzhiyun 		umac_writel(priv, reg, UMAC_CMD);
1459*4882a593Smuzhiyun 	}
1460*4882a593Smuzhiyun out:
1461*4882a593Smuzhiyun 	if (changed)
1462*4882a593Smuzhiyun 		phy_print_status(phydev);
1463*4882a593Smuzhiyun }
1464*4882a593Smuzhiyun 
bcm_sysport_init_dim(struct bcm_sysport_priv * priv,void (* cb)(struct work_struct * work))1465*4882a593Smuzhiyun static void bcm_sysport_init_dim(struct bcm_sysport_priv *priv,
1466*4882a593Smuzhiyun 				 void (*cb)(struct work_struct *work))
1467*4882a593Smuzhiyun {
1468*4882a593Smuzhiyun 	struct bcm_sysport_net_dim *dim = &priv->dim;
1469*4882a593Smuzhiyun 
1470*4882a593Smuzhiyun 	INIT_WORK(&dim->dim.work, cb);
1471*4882a593Smuzhiyun 	dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1472*4882a593Smuzhiyun 	dim->event_ctr = 0;
1473*4882a593Smuzhiyun 	dim->packets = 0;
1474*4882a593Smuzhiyun 	dim->bytes = 0;
1475*4882a593Smuzhiyun }
1476*4882a593Smuzhiyun 
bcm_sysport_init_rx_coalesce(struct bcm_sysport_priv * priv)1477*4882a593Smuzhiyun static void bcm_sysport_init_rx_coalesce(struct bcm_sysport_priv *priv)
1478*4882a593Smuzhiyun {
1479*4882a593Smuzhiyun 	struct bcm_sysport_net_dim *dim = &priv->dim;
1480*4882a593Smuzhiyun 	struct dim_cq_moder moder;
1481*4882a593Smuzhiyun 	u32 usecs, pkts;
1482*4882a593Smuzhiyun 
1483*4882a593Smuzhiyun 	usecs = priv->rx_coalesce_usecs;
1484*4882a593Smuzhiyun 	pkts = priv->rx_max_coalesced_frames;
1485*4882a593Smuzhiyun 
1486*4882a593Smuzhiyun 	/* If DIM was enabled, re-apply default parameters */
1487*4882a593Smuzhiyun 	if (dim->use_dim) {
1488*4882a593Smuzhiyun 		moder = net_dim_get_def_rx_moderation(dim->dim.mode);
1489*4882a593Smuzhiyun 		usecs = moder.usec;
1490*4882a593Smuzhiyun 		pkts = moder.pkts;
1491*4882a593Smuzhiyun 	}
1492*4882a593Smuzhiyun 
1493*4882a593Smuzhiyun 	bcm_sysport_set_rx_coalesce(priv, usecs, pkts);
1494*4882a593Smuzhiyun }
1495*4882a593Smuzhiyun 
bcm_sysport_init_tx_ring(struct bcm_sysport_priv * priv,unsigned int index)1496*4882a593Smuzhiyun static int bcm_sysport_init_tx_ring(struct bcm_sysport_priv *priv,
1497*4882a593Smuzhiyun 				    unsigned int index)
1498*4882a593Smuzhiyun {
1499*4882a593Smuzhiyun 	struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index];
1500*4882a593Smuzhiyun 	size_t size;
1501*4882a593Smuzhiyun 	u32 reg;
1502*4882a593Smuzhiyun 
1503*4882a593Smuzhiyun 	/* Simple descriptors partitioning for now */
1504*4882a593Smuzhiyun 	size = 256;
1505*4882a593Smuzhiyun 
1506*4882a593Smuzhiyun 	ring->cbs = kcalloc(size, sizeof(struct bcm_sysport_cb), GFP_KERNEL);
1507*4882a593Smuzhiyun 	if (!ring->cbs) {
1508*4882a593Smuzhiyun 		netif_err(priv, hw, priv->netdev, "CB allocation failed\n");
1509*4882a593Smuzhiyun 		return -ENOMEM;
1510*4882a593Smuzhiyun 	}
1511*4882a593Smuzhiyun 
1512*4882a593Smuzhiyun 	/* Initialize SW view of the ring */
1513*4882a593Smuzhiyun 	spin_lock_init(&ring->lock);
1514*4882a593Smuzhiyun 	ring->priv = priv;
1515*4882a593Smuzhiyun 	netif_tx_napi_add(priv->netdev, &ring->napi, bcm_sysport_tx_poll, 64);
1516*4882a593Smuzhiyun 	ring->index = index;
1517*4882a593Smuzhiyun 	ring->size = size;
1518*4882a593Smuzhiyun 	ring->clean_index = 0;
1519*4882a593Smuzhiyun 	ring->alloc_size = ring->size;
1520*4882a593Smuzhiyun 	ring->desc_count = ring->size;
1521*4882a593Smuzhiyun 	ring->curr_desc = 0;
1522*4882a593Smuzhiyun 
1523*4882a593Smuzhiyun 	/* Initialize HW ring */
1524*4882a593Smuzhiyun 	tdma_writel(priv, RING_EN, TDMA_DESC_RING_HEAD_TAIL_PTR(index));
1525*4882a593Smuzhiyun 	tdma_writel(priv, 0, TDMA_DESC_RING_COUNT(index));
1526*4882a593Smuzhiyun 	tdma_writel(priv, 1, TDMA_DESC_RING_INTR_CONTROL(index));
1527*4882a593Smuzhiyun 	tdma_writel(priv, 0, TDMA_DESC_RING_PROD_CONS_INDEX(index));
1528*4882a593Smuzhiyun 
1529*4882a593Smuzhiyun 	/* Configure QID and port mapping */
1530*4882a593Smuzhiyun 	reg = tdma_readl(priv, TDMA_DESC_RING_MAPPING(index));
1531*4882a593Smuzhiyun 	reg &= ~(RING_QID_MASK | RING_PORT_ID_MASK << RING_PORT_ID_SHIFT);
1532*4882a593Smuzhiyun 	if (ring->inspect) {
1533*4882a593Smuzhiyun 		reg |= ring->switch_queue & RING_QID_MASK;
1534*4882a593Smuzhiyun 		reg |= ring->switch_port << RING_PORT_ID_SHIFT;
1535*4882a593Smuzhiyun 	} else {
1536*4882a593Smuzhiyun 		reg |= RING_IGNORE_STATUS;
1537*4882a593Smuzhiyun 	}
1538*4882a593Smuzhiyun 	tdma_writel(priv, reg, TDMA_DESC_RING_MAPPING(index));
1539*4882a593Smuzhiyun 	reg = 0;
1540*4882a593Smuzhiyun 	/* Adjust the packet size calculations if SYSTEMPORT is responsible
1541*4882a593Smuzhiyun 	 * for HW insertion of VLAN tags
1542*4882a593Smuzhiyun 	 */
1543*4882a593Smuzhiyun 	if (priv->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)
1544*4882a593Smuzhiyun 		reg = VLAN_HLEN << RING_PKT_SIZE_ADJ_SHIFT;
1545*4882a593Smuzhiyun 	tdma_writel(priv, reg, TDMA_DESC_RING_PCP_DEI_VID(index));
1546*4882a593Smuzhiyun 
1547*4882a593Smuzhiyun 	/* Enable ACB algorithm 2 */
1548*4882a593Smuzhiyun 	reg = tdma_readl(priv, TDMA_CONTROL);
1549*4882a593Smuzhiyun 	reg |= tdma_control_bit(priv, ACB_ALGO);
1550*4882a593Smuzhiyun 	tdma_writel(priv, reg, TDMA_CONTROL);
1551*4882a593Smuzhiyun 
1552*4882a593Smuzhiyun 	/* Do not use tdma_control_bit() here because TSB_SWAP1 collides
1553*4882a593Smuzhiyun 	 * with the original definition of ACB_ALGO
1554*4882a593Smuzhiyun 	 */
1555*4882a593Smuzhiyun 	reg = tdma_readl(priv, TDMA_CONTROL);
1556*4882a593Smuzhiyun 	if (priv->is_lite)
1557*4882a593Smuzhiyun 		reg &= ~BIT(TSB_SWAP1);
1558*4882a593Smuzhiyun 	/* Set a correct TSB format based on host endian */
1559*4882a593Smuzhiyun 	if (!IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
1560*4882a593Smuzhiyun 		reg |= tdma_control_bit(priv, TSB_SWAP0);
1561*4882a593Smuzhiyun 	else
1562*4882a593Smuzhiyun 		reg &= ~tdma_control_bit(priv, TSB_SWAP0);
1563*4882a593Smuzhiyun 	tdma_writel(priv, reg, TDMA_CONTROL);
1564*4882a593Smuzhiyun 
1565*4882a593Smuzhiyun 	/* Program the number of descriptors as MAX_THRESHOLD and half of
1566*4882a593Smuzhiyun 	 * its size for the hysteresis trigger
1567*4882a593Smuzhiyun 	 */
1568*4882a593Smuzhiyun 	tdma_writel(priv, ring->size |
1569*4882a593Smuzhiyun 			1 << RING_HYST_THRESH_SHIFT,
1570*4882a593Smuzhiyun 			TDMA_DESC_RING_MAX_HYST(index));
1571*4882a593Smuzhiyun 
1572*4882a593Smuzhiyun 	/* Enable the ring queue in the arbiter */
1573*4882a593Smuzhiyun 	reg = tdma_readl(priv, TDMA_TIER1_ARB_0_QUEUE_EN);
1574*4882a593Smuzhiyun 	reg |= (1 << index);
1575*4882a593Smuzhiyun 	tdma_writel(priv, reg, TDMA_TIER1_ARB_0_QUEUE_EN);
1576*4882a593Smuzhiyun 
1577*4882a593Smuzhiyun 	napi_enable(&ring->napi);
1578*4882a593Smuzhiyun 
1579*4882a593Smuzhiyun 	netif_dbg(priv, hw, priv->netdev,
1580*4882a593Smuzhiyun 		  "TDMA cfg, size=%d, switch q=%d,port=%d\n",
1581*4882a593Smuzhiyun 		  ring->size, ring->switch_queue,
1582*4882a593Smuzhiyun 		  ring->switch_port);
1583*4882a593Smuzhiyun 
1584*4882a593Smuzhiyun 	return 0;
1585*4882a593Smuzhiyun }
1586*4882a593Smuzhiyun 
bcm_sysport_fini_tx_ring(struct bcm_sysport_priv * priv,unsigned int index)1587*4882a593Smuzhiyun static void bcm_sysport_fini_tx_ring(struct bcm_sysport_priv *priv,
1588*4882a593Smuzhiyun 				     unsigned int index)
1589*4882a593Smuzhiyun {
1590*4882a593Smuzhiyun 	struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index];
1591*4882a593Smuzhiyun 	u32 reg;
1592*4882a593Smuzhiyun 
1593*4882a593Smuzhiyun 	/* Caller should stop the TDMA engine */
1594*4882a593Smuzhiyun 	reg = tdma_readl(priv, TDMA_STATUS);
1595*4882a593Smuzhiyun 	if (!(reg & TDMA_DISABLED))
1596*4882a593Smuzhiyun 		netdev_warn(priv->netdev, "TDMA not stopped!\n");
1597*4882a593Smuzhiyun 
1598*4882a593Smuzhiyun 	/* ring->cbs is the last part in bcm_sysport_init_tx_ring which could
1599*4882a593Smuzhiyun 	 * fail, so by checking this pointer we know whether the TX ring was
1600*4882a593Smuzhiyun 	 * fully initialized or not.
1601*4882a593Smuzhiyun 	 */
1602*4882a593Smuzhiyun 	if (!ring->cbs)
1603*4882a593Smuzhiyun 		return;
1604*4882a593Smuzhiyun 
1605*4882a593Smuzhiyun 	napi_disable(&ring->napi);
1606*4882a593Smuzhiyun 	netif_napi_del(&ring->napi);
1607*4882a593Smuzhiyun 
1608*4882a593Smuzhiyun 	bcm_sysport_tx_clean(priv, ring);
1609*4882a593Smuzhiyun 
1610*4882a593Smuzhiyun 	kfree(ring->cbs);
1611*4882a593Smuzhiyun 	ring->cbs = NULL;
1612*4882a593Smuzhiyun 	ring->size = 0;
1613*4882a593Smuzhiyun 	ring->alloc_size = 0;
1614*4882a593Smuzhiyun 
1615*4882a593Smuzhiyun 	netif_dbg(priv, hw, priv->netdev, "TDMA fini done\n");
1616*4882a593Smuzhiyun }
1617*4882a593Smuzhiyun 
1618*4882a593Smuzhiyun /* RDMA helper */
rdma_enable_set(struct bcm_sysport_priv * priv,unsigned int enable)1619*4882a593Smuzhiyun static inline int rdma_enable_set(struct bcm_sysport_priv *priv,
1620*4882a593Smuzhiyun 				  unsigned int enable)
1621*4882a593Smuzhiyun {
1622*4882a593Smuzhiyun 	unsigned int timeout = 1000;
1623*4882a593Smuzhiyun 	u32 reg;
1624*4882a593Smuzhiyun 
1625*4882a593Smuzhiyun 	reg = rdma_readl(priv, RDMA_CONTROL);
1626*4882a593Smuzhiyun 	if (enable)
1627*4882a593Smuzhiyun 		reg |= RDMA_EN;
1628*4882a593Smuzhiyun 	else
1629*4882a593Smuzhiyun 		reg &= ~RDMA_EN;
1630*4882a593Smuzhiyun 	rdma_writel(priv, reg, RDMA_CONTROL);
1631*4882a593Smuzhiyun 
1632*4882a593Smuzhiyun 	/* Poll for RMDA disabling completion */
1633*4882a593Smuzhiyun 	do {
1634*4882a593Smuzhiyun 		reg = rdma_readl(priv, RDMA_STATUS);
1635*4882a593Smuzhiyun 		if (!!(reg & RDMA_DISABLED) == !enable)
1636*4882a593Smuzhiyun 			return 0;
1637*4882a593Smuzhiyun 		usleep_range(1000, 2000);
1638*4882a593Smuzhiyun 	} while (timeout-- > 0);
1639*4882a593Smuzhiyun 
1640*4882a593Smuzhiyun 	netdev_err(priv->netdev, "timeout waiting for RDMA to finish\n");
1641*4882a593Smuzhiyun 
1642*4882a593Smuzhiyun 	return -ETIMEDOUT;
1643*4882a593Smuzhiyun }
1644*4882a593Smuzhiyun 
1645*4882a593Smuzhiyun /* TDMA helper */
tdma_enable_set(struct bcm_sysport_priv * priv,unsigned int enable)1646*4882a593Smuzhiyun static inline int tdma_enable_set(struct bcm_sysport_priv *priv,
1647*4882a593Smuzhiyun 				  unsigned int enable)
1648*4882a593Smuzhiyun {
1649*4882a593Smuzhiyun 	unsigned int timeout = 1000;
1650*4882a593Smuzhiyun 	u32 reg;
1651*4882a593Smuzhiyun 
1652*4882a593Smuzhiyun 	reg = tdma_readl(priv, TDMA_CONTROL);
1653*4882a593Smuzhiyun 	if (enable)
1654*4882a593Smuzhiyun 		reg |= tdma_control_bit(priv, TDMA_EN);
1655*4882a593Smuzhiyun 	else
1656*4882a593Smuzhiyun 		reg &= ~tdma_control_bit(priv, TDMA_EN);
1657*4882a593Smuzhiyun 	tdma_writel(priv, reg, TDMA_CONTROL);
1658*4882a593Smuzhiyun 
1659*4882a593Smuzhiyun 	/* Poll for TMDA disabling completion */
1660*4882a593Smuzhiyun 	do {
1661*4882a593Smuzhiyun 		reg = tdma_readl(priv, TDMA_STATUS);
1662*4882a593Smuzhiyun 		if (!!(reg & TDMA_DISABLED) == !enable)
1663*4882a593Smuzhiyun 			return 0;
1664*4882a593Smuzhiyun 
1665*4882a593Smuzhiyun 		usleep_range(1000, 2000);
1666*4882a593Smuzhiyun 	} while (timeout-- > 0);
1667*4882a593Smuzhiyun 
1668*4882a593Smuzhiyun 	netdev_err(priv->netdev, "timeout waiting for TDMA to finish\n");
1669*4882a593Smuzhiyun 
1670*4882a593Smuzhiyun 	return -ETIMEDOUT;
1671*4882a593Smuzhiyun }
1672*4882a593Smuzhiyun 
bcm_sysport_init_rx_ring(struct bcm_sysport_priv * priv)1673*4882a593Smuzhiyun static int bcm_sysport_init_rx_ring(struct bcm_sysport_priv *priv)
1674*4882a593Smuzhiyun {
1675*4882a593Smuzhiyun 	struct bcm_sysport_cb *cb;
1676*4882a593Smuzhiyun 	u32 reg;
1677*4882a593Smuzhiyun 	int ret;
1678*4882a593Smuzhiyun 	int i;
1679*4882a593Smuzhiyun 
1680*4882a593Smuzhiyun 	/* Initialize SW view of the RX ring */
1681*4882a593Smuzhiyun 	priv->num_rx_bds = priv->num_rx_desc_words / WORDS_PER_DESC;
1682*4882a593Smuzhiyun 	priv->rx_bds = priv->base + SYS_PORT_RDMA_OFFSET;
1683*4882a593Smuzhiyun 	priv->rx_c_index = 0;
1684*4882a593Smuzhiyun 	priv->rx_read_ptr = 0;
1685*4882a593Smuzhiyun 	priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct bcm_sysport_cb),
1686*4882a593Smuzhiyun 				GFP_KERNEL);
1687*4882a593Smuzhiyun 	if (!priv->rx_cbs) {
1688*4882a593Smuzhiyun 		netif_err(priv, hw, priv->netdev, "CB allocation failed\n");
1689*4882a593Smuzhiyun 		return -ENOMEM;
1690*4882a593Smuzhiyun 	}
1691*4882a593Smuzhiyun 
1692*4882a593Smuzhiyun 	for (i = 0; i < priv->num_rx_bds; i++) {
1693*4882a593Smuzhiyun 		cb = priv->rx_cbs + i;
1694*4882a593Smuzhiyun 		cb->bd_addr = priv->rx_bds + i * DESC_SIZE;
1695*4882a593Smuzhiyun 	}
1696*4882a593Smuzhiyun 
1697*4882a593Smuzhiyun 	ret = bcm_sysport_alloc_rx_bufs(priv);
1698*4882a593Smuzhiyun 	if (ret) {
1699*4882a593Smuzhiyun 		netif_err(priv, hw, priv->netdev, "SKB allocation failed\n");
1700*4882a593Smuzhiyun 		return ret;
1701*4882a593Smuzhiyun 	}
1702*4882a593Smuzhiyun 
1703*4882a593Smuzhiyun 	/* Initialize HW, ensure RDMA is disabled */
1704*4882a593Smuzhiyun 	reg = rdma_readl(priv, RDMA_STATUS);
1705*4882a593Smuzhiyun 	if (!(reg & RDMA_DISABLED))
1706*4882a593Smuzhiyun 		rdma_enable_set(priv, 0);
1707*4882a593Smuzhiyun 
1708*4882a593Smuzhiyun 	rdma_writel(priv, 0, RDMA_WRITE_PTR_LO);
1709*4882a593Smuzhiyun 	rdma_writel(priv, 0, RDMA_WRITE_PTR_HI);
1710*4882a593Smuzhiyun 	rdma_writel(priv, 0, RDMA_PROD_INDEX);
1711*4882a593Smuzhiyun 	rdma_writel(priv, 0, RDMA_CONS_INDEX);
1712*4882a593Smuzhiyun 	rdma_writel(priv, priv->num_rx_bds << RDMA_RING_SIZE_SHIFT |
1713*4882a593Smuzhiyun 			  RX_BUF_LENGTH, RDMA_RING_BUF_SIZE);
1714*4882a593Smuzhiyun 	/* Operate the queue in ring mode */
1715*4882a593Smuzhiyun 	rdma_writel(priv, 0, RDMA_START_ADDR_HI);
1716*4882a593Smuzhiyun 	rdma_writel(priv, 0, RDMA_START_ADDR_LO);
1717*4882a593Smuzhiyun 	rdma_writel(priv, 0, RDMA_END_ADDR_HI);
1718*4882a593Smuzhiyun 	rdma_writel(priv, priv->num_rx_desc_words - 1, RDMA_END_ADDR_LO);
1719*4882a593Smuzhiyun 
1720*4882a593Smuzhiyun 	netif_dbg(priv, hw, priv->netdev,
1721*4882a593Smuzhiyun 		  "RDMA cfg, num_rx_bds=%d, rx_bds=%p\n",
1722*4882a593Smuzhiyun 		  priv->num_rx_bds, priv->rx_bds);
1723*4882a593Smuzhiyun 
1724*4882a593Smuzhiyun 	return 0;
1725*4882a593Smuzhiyun }
1726*4882a593Smuzhiyun 
bcm_sysport_fini_rx_ring(struct bcm_sysport_priv * priv)1727*4882a593Smuzhiyun static void bcm_sysport_fini_rx_ring(struct bcm_sysport_priv *priv)
1728*4882a593Smuzhiyun {
1729*4882a593Smuzhiyun 	struct bcm_sysport_cb *cb;
1730*4882a593Smuzhiyun 	unsigned int i;
1731*4882a593Smuzhiyun 	u32 reg;
1732*4882a593Smuzhiyun 
1733*4882a593Smuzhiyun 	/* Caller should ensure RDMA is disabled */
1734*4882a593Smuzhiyun 	reg = rdma_readl(priv, RDMA_STATUS);
1735*4882a593Smuzhiyun 	if (!(reg & RDMA_DISABLED))
1736*4882a593Smuzhiyun 		netdev_warn(priv->netdev, "RDMA not stopped!\n");
1737*4882a593Smuzhiyun 
1738*4882a593Smuzhiyun 	for (i = 0; i < priv->num_rx_bds; i++) {
1739*4882a593Smuzhiyun 		cb = &priv->rx_cbs[i];
1740*4882a593Smuzhiyun 		if (dma_unmap_addr(cb, dma_addr))
1741*4882a593Smuzhiyun 			dma_unmap_single(&priv->pdev->dev,
1742*4882a593Smuzhiyun 					 dma_unmap_addr(cb, dma_addr),
1743*4882a593Smuzhiyun 					 RX_BUF_LENGTH, DMA_FROM_DEVICE);
1744*4882a593Smuzhiyun 		bcm_sysport_free_cb(cb);
1745*4882a593Smuzhiyun 	}
1746*4882a593Smuzhiyun 
1747*4882a593Smuzhiyun 	kfree(priv->rx_cbs);
1748*4882a593Smuzhiyun 	priv->rx_cbs = NULL;
1749*4882a593Smuzhiyun 
1750*4882a593Smuzhiyun 	netif_dbg(priv, hw, priv->netdev, "RDMA fini done\n");
1751*4882a593Smuzhiyun }
1752*4882a593Smuzhiyun 
bcm_sysport_set_rx_mode(struct net_device * dev)1753*4882a593Smuzhiyun static void bcm_sysport_set_rx_mode(struct net_device *dev)
1754*4882a593Smuzhiyun {
1755*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
1756*4882a593Smuzhiyun 	u32 reg;
1757*4882a593Smuzhiyun 
1758*4882a593Smuzhiyun 	if (priv->is_lite)
1759*4882a593Smuzhiyun 		return;
1760*4882a593Smuzhiyun 
1761*4882a593Smuzhiyun 	reg = umac_readl(priv, UMAC_CMD);
1762*4882a593Smuzhiyun 	if (dev->flags & IFF_PROMISC)
1763*4882a593Smuzhiyun 		reg |= CMD_PROMISC;
1764*4882a593Smuzhiyun 	else
1765*4882a593Smuzhiyun 		reg &= ~CMD_PROMISC;
1766*4882a593Smuzhiyun 	umac_writel(priv, reg, UMAC_CMD);
1767*4882a593Smuzhiyun 
1768*4882a593Smuzhiyun 	/* No support for ALLMULTI */
1769*4882a593Smuzhiyun 	if (dev->flags & IFF_ALLMULTI)
1770*4882a593Smuzhiyun 		return;
1771*4882a593Smuzhiyun }
1772*4882a593Smuzhiyun 
umac_enable_set(struct bcm_sysport_priv * priv,u32 mask,unsigned int enable)1773*4882a593Smuzhiyun static inline void umac_enable_set(struct bcm_sysport_priv *priv,
1774*4882a593Smuzhiyun 				   u32 mask, unsigned int enable)
1775*4882a593Smuzhiyun {
1776*4882a593Smuzhiyun 	u32 reg;
1777*4882a593Smuzhiyun 
1778*4882a593Smuzhiyun 	if (!priv->is_lite) {
1779*4882a593Smuzhiyun 		reg = umac_readl(priv, UMAC_CMD);
1780*4882a593Smuzhiyun 		if (enable)
1781*4882a593Smuzhiyun 			reg |= mask;
1782*4882a593Smuzhiyun 		else
1783*4882a593Smuzhiyun 			reg &= ~mask;
1784*4882a593Smuzhiyun 		umac_writel(priv, reg, UMAC_CMD);
1785*4882a593Smuzhiyun 	} else {
1786*4882a593Smuzhiyun 		reg = gib_readl(priv, GIB_CONTROL);
1787*4882a593Smuzhiyun 		if (enable)
1788*4882a593Smuzhiyun 			reg |= mask;
1789*4882a593Smuzhiyun 		else
1790*4882a593Smuzhiyun 			reg &= ~mask;
1791*4882a593Smuzhiyun 		gib_writel(priv, reg, GIB_CONTROL);
1792*4882a593Smuzhiyun 	}
1793*4882a593Smuzhiyun 
1794*4882a593Smuzhiyun 	/* UniMAC stops on a packet boundary, wait for a full-sized packet
1795*4882a593Smuzhiyun 	 * to be processed (1 msec).
1796*4882a593Smuzhiyun 	 */
1797*4882a593Smuzhiyun 	if (enable == 0)
1798*4882a593Smuzhiyun 		usleep_range(1000, 2000);
1799*4882a593Smuzhiyun }
1800*4882a593Smuzhiyun 
umac_reset(struct bcm_sysport_priv * priv)1801*4882a593Smuzhiyun static inline void umac_reset(struct bcm_sysport_priv *priv)
1802*4882a593Smuzhiyun {
1803*4882a593Smuzhiyun 	u32 reg;
1804*4882a593Smuzhiyun 
1805*4882a593Smuzhiyun 	if (priv->is_lite)
1806*4882a593Smuzhiyun 		return;
1807*4882a593Smuzhiyun 
1808*4882a593Smuzhiyun 	reg = umac_readl(priv, UMAC_CMD);
1809*4882a593Smuzhiyun 	reg |= CMD_SW_RESET;
1810*4882a593Smuzhiyun 	umac_writel(priv, reg, UMAC_CMD);
1811*4882a593Smuzhiyun 	udelay(10);
1812*4882a593Smuzhiyun 	reg = umac_readl(priv, UMAC_CMD);
1813*4882a593Smuzhiyun 	reg &= ~CMD_SW_RESET;
1814*4882a593Smuzhiyun 	umac_writel(priv, reg, UMAC_CMD);
1815*4882a593Smuzhiyun }
1816*4882a593Smuzhiyun 
umac_set_hw_addr(struct bcm_sysport_priv * priv,unsigned char * addr)1817*4882a593Smuzhiyun static void umac_set_hw_addr(struct bcm_sysport_priv *priv,
1818*4882a593Smuzhiyun 			     unsigned char *addr)
1819*4882a593Smuzhiyun {
1820*4882a593Smuzhiyun 	u32 mac0 = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) |
1821*4882a593Smuzhiyun 		    addr[3];
1822*4882a593Smuzhiyun 	u32 mac1 = (addr[4] << 8) | addr[5];
1823*4882a593Smuzhiyun 
1824*4882a593Smuzhiyun 	if (!priv->is_lite) {
1825*4882a593Smuzhiyun 		umac_writel(priv, mac0, UMAC_MAC0);
1826*4882a593Smuzhiyun 		umac_writel(priv, mac1, UMAC_MAC1);
1827*4882a593Smuzhiyun 	} else {
1828*4882a593Smuzhiyun 		gib_writel(priv, mac0, GIB_MAC0);
1829*4882a593Smuzhiyun 		gib_writel(priv, mac1, GIB_MAC1);
1830*4882a593Smuzhiyun 	}
1831*4882a593Smuzhiyun }
1832*4882a593Smuzhiyun 
topctrl_flush(struct bcm_sysport_priv * priv)1833*4882a593Smuzhiyun static void topctrl_flush(struct bcm_sysport_priv *priv)
1834*4882a593Smuzhiyun {
1835*4882a593Smuzhiyun 	topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL);
1836*4882a593Smuzhiyun 	topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL);
1837*4882a593Smuzhiyun 	mdelay(1);
1838*4882a593Smuzhiyun 	topctrl_writel(priv, 0, RX_FLUSH_CNTL);
1839*4882a593Smuzhiyun 	topctrl_writel(priv, 0, TX_FLUSH_CNTL);
1840*4882a593Smuzhiyun }
1841*4882a593Smuzhiyun 
bcm_sysport_change_mac(struct net_device * dev,void * p)1842*4882a593Smuzhiyun static int bcm_sysport_change_mac(struct net_device *dev, void *p)
1843*4882a593Smuzhiyun {
1844*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
1845*4882a593Smuzhiyun 	struct sockaddr *addr = p;
1846*4882a593Smuzhiyun 
1847*4882a593Smuzhiyun 	if (!is_valid_ether_addr(addr->sa_data))
1848*4882a593Smuzhiyun 		return -EINVAL;
1849*4882a593Smuzhiyun 
1850*4882a593Smuzhiyun 	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1851*4882a593Smuzhiyun 
1852*4882a593Smuzhiyun 	/* interface is disabled, changes to MAC will be reflected on next
1853*4882a593Smuzhiyun 	 * open call
1854*4882a593Smuzhiyun 	 */
1855*4882a593Smuzhiyun 	if (!netif_running(dev))
1856*4882a593Smuzhiyun 		return 0;
1857*4882a593Smuzhiyun 
1858*4882a593Smuzhiyun 	umac_set_hw_addr(priv, dev->dev_addr);
1859*4882a593Smuzhiyun 
1860*4882a593Smuzhiyun 	return 0;
1861*4882a593Smuzhiyun }
1862*4882a593Smuzhiyun 
bcm_sysport_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * stats)1863*4882a593Smuzhiyun static void bcm_sysport_get_stats64(struct net_device *dev,
1864*4882a593Smuzhiyun 				    struct rtnl_link_stats64 *stats)
1865*4882a593Smuzhiyun {
1866*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
1867*4882a593Smuzhiyun 	struct bcm_sysport_stats64 *stats64 = &priv->stats64;
1868*4882a593Smuzhiyun 	unsigned int start;
1869*4882a593Smuzhiyun 
1870*4882a593Smuzhiyun 	netdev_stats_to_stats64(stats, &dev->stats);
1871*4882a593Smuzhiyun 
1872*4882a593Smuzhiyun 	bcm_sysport_update_tx_stats(priv, &stats->tx_bytes,
1873*4882a593Smuzhiyun 				    &stats->tx_packets);
1874*4882a593Smuzhiyun 
1875*4882a593Smuzhiyun 	do {
1876*4882a593Smuzhiyun 		start = u64_stats_fetch_begin_irq(&priv->syncp);
1877*4882a593Smuzhiyun 		stats->rx_packets = stats64->rx_packets;
1878*4882a593Smuzhiyun 		stats->rx_bytes = stats64->rx_bytes;
1879*4882a593Smuzhiyun 	} while (u64_stats_fetch_retry_irq(&priv->syncp, start));
1880*4882a593Smuzhiyun }
1881*4882a593Smuzhiyun 
bcm_sysport_netif_start(struct net_device * dev)1882*4882a593Smuzhiyun static void bcm_sysport_netif_start(struct net_device *dev)
1883*4882a593Smuzhiyun {
1884*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
1885*4882a593Smuzhiyun 
1886*4882a593Smuzhiyun 	/* Enable NAPI */
1887*4882a593Smuzhiyun 	bcm_sysport_init_dim(priv, bcm_sysport_dim_work);
1888*4882a593Smuzhiyun 	bcm_sysport_init_rx_coalesce(priv);
1889*4882a593Smuzhiyun 	napi_enable(&priv->napi);
1890*4882a593Smuzhiyun 
1891*4882a593Smuzhiyun 	/* Enable RX interrupt and TX ring full interrupt */
1892*4882a593Smuzhiyun 	intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL);
1893*4882a593Smuzhiyun 
1894*4882a593Smuzhiyun 	phy_start(dev->phydev);
1895*4882a593Smuzhiyun 
1896*4882a593Smuzhiyun 	/* Enable TX interrupts for the TXQs */
1897*4882a593Smuzhiyun 	if (!priv->is_lite)
1898*4882a593Smuzhiyun 		intrl2_1_mask_clear(priv, 0xffffffff);
1899*4882a593Smuzhiyun 	else
1900*4882a593Smuzhiyun 		intrl2_0_mask_clear(priv, INTRL2_0_TDMA_MBDONE_MASK);
1901*4882a593Smuzhiyun }
1902*4882a593Smuzhiyun 
rbuf_init(struct bcm_sysport_priv * priv)1903*4882a593Smuzhiyun static void rbuf_init(struct bcm_sysport_priv *priv)
1904*4882a593Smuzhiyun {
1905*4882a593Smuzhiyun 	u32 reg;
1906*4882a593Smuzhiyun 
1907*4882a593Smuzhiyun 	reg = rbuf_readl(priv, RBUF_CONTROL);
1908*4882a593Smuzhiyun 	reg |= RBUF_4B_ALGN | RBUF_RSB_EN;
1909*4882a593Smuzhiyun 	/* Set a correct RSB format on SYSTEMPORT Lite */
1910*4882a593Smuzhiyun 	if (priv->is_lite)
1911*4882a593Smuzhiyun 		reg &= ~RBUF_RSB_SWAP1;
1912*4882a593Smuzhiyun 
1913*4882a593Smuzhiyun 	/* Set a correct RSB format based on host endian */
1914*4882a593Smuzhiyun 	if (!IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
1915*4882a593Smuzhiyun 		reg |= RBUF_RSB_SWAP0;
1916*4882a593Smuzhiyun 	else
1917*4882a593Smuzhiyun 		reg &= ~RBUF_RSB_SWAP0;
1918*4882a593Smuzhiyun 	rbuf_writel(priv, reg, RBUF_CONTROL);
1919*4882a593Smuzhiyun }
1920*4882a593Smuzhiyun 
bcm_sysport_mask_all_intrs(struct bcm_sysport_priv * priv)1921*4882a593Smuzhiyun static inline void bcm_sysport_mask_all_intrs(struct bcm_sysport_priv *priv)
1922*4882a593Smuzhiyun {
1923*4882a593Smuzhiyun 	intrl2_0_mask_set(priv, 0xffffffff);
1924*4882a593Smuzhiyun 	intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1925*4882a593Smuzhiyun 	if (!priv->is_lite) {
1926*4882a593Smuzhiyun 		intrl2_1_mask_set(priv, 0xffffffff);
1927*4882a593Smuzhiyun 		intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1928*4882a593Smuzhiyun 	}
1929*4882a593Smuzhiyun }
1930*4882a593Smuzhiyun 
gib_set_pad_extension(struct bcm_sysport_priv * priv)1931*4882a593Smuzhiyun static inline void gib_set_pad_extension(struct bcm_sysport_priv *priv)
1932*4882a593Smuzhiyun {
1933*4882a593Smuzhiyun 	u32 reg;
1934*4882a593Smuzhiyun 
1935*4882a593Smuzhiyun 	reg = gib_readl(priv, GIB_CONTROL);
1936*4882a593Smuzhiyun 	/* Include Broadcom tag in pad extension and fix up IPG_LENGTH */
1937*4882a593Smuzhiyun 	if (netdev_uses_dsa(priv->netdev)) {
1938*4882a593Smuzhiyun 		reg &= ~(GIB_PAD_EXTENSION_MASK << GIB_PAD_EXTENSION_SHIFT);
1939*4882a593Smuzhiyun 		reg |= ENET_BRCM_TAG_LEN << GIB_PAD_EXTENSION_SHIFT;
1940*4882a593Smuzhiyun 	}
1941*4882a593Smuzhiyun 	reg &= ~(GIB_IPG_LEN_MASK << GIB_IPG_LEN_SHIFT);
1942*4882a593Smuzhiyun 	reg |= 12 << GIB_IPG_LEN_SHIFT;
1943*4882a593Smuzhiyun 	gib_writel(priv, reg, GIB_CONTROL);
1944*4882a593Smuzhiyun }
1945*4882a593Smuzhiyun 
bcm_sysport_open(struct net_device * dev)1946*4882a593Smuzhiyun static int bcm_sysport_open(struct net_device *dev)
1947*4882a593Smuzhiyun {
1948*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
1949*4882a593Smuzhiyun 	struct phy_device *phydev;
1950*4882a593Smuzhiyun 	unsigned int i;
1951*4882a593Smuzhiyun 	int ret;
1952*4882a593Smuzhiyun 
1953*4882a593Smuzhiyun 	clk_prepare_enable(priv->clk);
1954*4882a593Smuzhiyun 
1955*4882a593Smuzhiyun 	/* Reset UniMAC */
1956*4882a593Smuzhiyun 	umac_reset(priv);
1957*4882a593Smuzhiyun 
1958*4882a593Smuzhiyun 	/* Flush TX and RX FIFOs at TOPCTRL level */
1959*4882a593Smuzhiyun 	topctrl_flush(priv);
1960*4882a593Smuzhiyun 
1961*4882a593Smuzhiyun 	/* Disable the UniMAC RX/TX */
1962*4882a593Smuzhiyun 	umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 0);
1963*4882a593Smuzhiyun 
1964*4882a593Smuzhiyun 	/* Enable RBUF 2bytes alignment and Receive Status Block */
1965*4882a593Smuzhiyun 	rbuf_init(priv);
1966*4882a593Smuzhiyun 
1967*4882a593Smuzhiyun 	/* Set maximum frame length */
1968*4882a593Smuzhiyun 	if (!priv->is_lite)
1969*4882a593Smuzhiyun 		umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1970*4882a593Smuzhiyun 	else
1971*4882a593Smuzhiyun 		gib_set_pad_extension(priv);
1972*4882a593Smuzhiyun 
1973*4882a593Smuzhiyun 	/* Apply features again in case we changed them while interface was
1974*4882a593Smuzhiyun 	 * down
1975*4882a593Smuzhiyun 	 */
1976*4882a593Smuzhiyun 	bcm_sysport_set_features(dev, dev->features);
1977*4882a593Smuzhiyun 
1978*4882a593Smuzhiyun 	/* Set MAC address */
1979*4882a593Smuzhiyun 	umac_set_hw_addr(priv, dev->dev_addr);
1980*4882a593Smuzhiyun 
1981*4882a593Smuzhiyun 	phydev = of_phy_connect(dev, priv->phy_dn, bcm_sysport_adj_link,
1982*4882a593Smuzhiyun 				0, priv->phy_interface);
1983*4882a593Smuzhiyun 	if (!phydev) {
1984*4882a593Smuzhiyun 		netdev_err(dev, "could not attach to PHY\n");
1985*4882a593Smuzhiyun 		ret = -ENODEV;
1986*4882a593Smuzhiyun 		goto out_clk_disable;
1987*4882a593Smuzhiyun 	}
1988*4882a593Smuzhiyun 
1989*4882a593Smuzhiyun 	/* Reset house keeping link status */
1990*4882a593Smuzhiyun 	priv->old_duplex = -1;
1991*4882a593Smuzhiyun 	priv->old_link = -1;
1992*4882a593Smuzhiyun 	priv->old_pause = -1;
1993*4882a593Smuzhiyun 
1994*4882a593Smuzhiyun 	/* mask all interrupts and request them */
1995*4882a593Smuzhiyun 	bcm_sysport_mask_all_intrs(priv);
1996*4882a593Smuzhiyun 
1997*4882a593Smuzhiyun 	ret = request_irq(priv->irq0, bcm_sysport_rx_isr, 0, dev->name, dev);
1998*4882a593Smuzhiyun 	if (ret) {
1999*4882a593Smuzhiyun 		netdev_err(dev, "failed to request RX interrupt\n");
2000*4882a593Smuzhiyun 		goto out_phy_disconnect;
2001*4882a593Smuzhiyun 	}
2002*4882a593Smuzhiyun 
2003*4882a593Smuzhiyun 	if (!priv->is_lite) {
2004*4882a593Smuzhiyun 		ret = request_irq(priv->irq1, bcm_sysport_tx_isr, 0,
2005*4882a593Smuzhiyun 				  dev->name, dev);
2006*4882a593Smuzhiyun 		if (ret) {
2007*4882a593Smuzhiyun 			netdev_err(dev, "failed to request TX interrupt\n");
2008*4882a593Smuzhiyun 			goto out_free_irq0;
2009*4882a593Smuzhiyun 		}
2010*4882a593Smuzhiyun 	}
2011*4882a593Smuzhiyun 
2012*4882a593Smuzhiyun 	/* Initialize both hardware and software ring */
2013*4882a593Smuzhiyun 	spin_lock_init(&priv->desc_lock);
2014*4882a593Smuzhiyun 	for (i = 0; i < dev->num_tx_queues; i++) {
2015*4882a593Smuzhiyun 		ret = bcm_sysport_init_tx_ring(priv, i);
2016*4882a593Smuzhiyun 		if (ret) {
2017*4882a593Smuzhiyun 			netdev_err(dev, "failed to initialize TX ring %d\n",
2018*4882a593Smuzhiyun 				   i);
2019*4882a593Smuzhiyun 			goto out_free_tx_ring;
2020*4882a593Smuzhiyun 		}
2021*4882a593Smuzhiyun 	}
2022*4882a593Smuzhiyun 
2023*4882a593Smuzhiyun 	/* Initialize linked-list */
2024*4882a593Smuzhiyun 	tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS);
2025*4882a593Smuzhiyun 
2026*4882a593Smuzhiyun 	/* Initialize RX ring */
2027*4882a593Smuzhiyun 	ret = bcm_sysport_init_rx_ring(priv);
2028*4882a593Smuzhiyun 	if (ret) {
2029*4882a593Smuzhiyun 		netdev_err(dev, "failed to initialize RX ring\n");
2030*4882a593Smuzhiyun 		goto out_free_rx_ring;
2031*4882a593Smuzhiyun 	}
2032*4882a593Smuzhiyun 
2033*4882a593Smuzhiyun 	/* Turn on RDMA */
2034*4882a593Smuzhiyun 	ret = rdma_enable_set(priv, 1);
2035*4882a593Smuzhiyun 	if (ret)
2036*4882a593Smuzhiyun 		goto out_free_rx_ring;
2037*4882a593Smuzhiyun 
2038*4882a593Smuzhiyun 	/* Turn on TDMA */
2039*4882a593Smuzhiyun 	ret = tdma_enable_set(priv, 1);
2040*4882a593Smuzhiyun 	if (ret)
2041*4882a593Smuzhiyun 		goto out_clear_rx_int;
2042*4882a593Smuzhiyun 
2043*4882a593Smuzhiyun 	/* Turn on UniMAC TX/RX */
2044*4882a593Smuzhiyun 	umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 1);
2045*4882a593Smuzhiyun 
2046*4882a593Smuzhiyun 	bcm_sysport_netif_start(dev);
2047*4882a593Smuzhiyun 
2048*4882a593Smuzhiyun 	netif_tx_start_all_queues(dev);
2049*4882a593Smuzhiyun 
2050*4882a593Smuzhiyun 	return 0;
2051*4882a593Smuzhiyun 
2052*4882a593Smuzhiyun out_clear_rx_int:
2053*4882a593Smuzhiyun 	intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL);
2054*4882a593Smuzhiyun out_free_rx_ring:
2055*4882a593Smuzhiyun 	bcm_sysport_fini_rx_ring(priv);
2056*4882a593Smuzhiyun out_free_tx_ring:
2057*4882a593Smuzhiyun 	for (i = 0; i < dev->num_tx_queues; i++)
2058*4882a593Smuzhiyun 		bcm_sysport_fini_tx_ring(priv, i);
2059*4882a593Smuzhiyun 	if (!priv->is_lite)
2060*4882a593Smuzhiyun 		free_irq(priv->irq1, dev);
2061*4882a593Smuzhiyun out_free_irq0:
2062*4882a593Smuzhiyun 	free_irq(priv->irq0, dev);
2063*4882a593Smuzhiyun out_phy_disconnect:
2064*4882a593Smuzhiyun 	phy_disconnect(phydev);
2065*4882a593Smuzhiyun out_clk_disable:
2066*4882a593Smuzhiyun 	clk_disable_unprepare(priv->clk);
2067*4882a593Smuzhiyun 	return ret;
2068*4882a593Smuzhiyun }
2069*4882a593Smuzhiyun 
bcm_sysport_netif_stop(struct net_device * dev)2070*4882a593Smuzhiyun static void bcm_sysport_netif_stop(struct net_device *dev)
2071*4882a593Smuzhiyun {
2072*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
2073*4882a593Smuzhiyun 
2074*4882a593Smuzhiyun 	/* stop all software from updating hardware */
2075*4882a593Smuzhiyun 	netif_tx_disable(dev);
2076*4882a593Smuzhiyun 	napi_disable(&priv->napi);
2077*4882a593Smuzhiyun 	cancel_work_sync(&priv->dim.dim.work);
2078*4882a593Smuzhiyun 	phy_stop(dev->phydev);
2079*4882a593Smuzhiyun 
2080*4882a593Smuzhiyun 	/* mask all interrupts */
2081*4882a593Smuzhiyun 	bcm_sysport_mask_all_intrs(priv);
2082*4882a593Smuzhiyun }
2083*4882a593Smuzhiyun 
bcm_sysport_stop(struct net_device * dev)2084*4882a593Smuzhiyun static int bcm_sysport_stop(struct net_device *dev)
2085*4882a593Smuzhiyun {
2086*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
2087*4882a593Smuzhiyun 	unsigned int i;
2088*4882a593Smuzhiyun 	int ret;
2089*4882a593Smuzhiyun 
2090*4882a593Smuzhiyun 	bcm_sysport_netif_stop(dev);
2091*4882a593Smuzhiyun 
2092*4882a593Smuzhiyun 	/* Disable UniMAC RX */
2093*4882a593Smuzhiyun 	umac_enable_set(priv, CMD_RX_EN, 0);
2094*4882a593Smuzhiyun 
2095*4882a593Smuzhiyun 	ret = tdma_enable_set(priv, 0);
2096*4882a593Smuzhiyun 	if (ret) {
2097*4882a593Smuzhiyun 		netdev_err(dev, "timeout disabling RDMA\n");
2098*4882a593Smuzhiyun 		return ret;
2099*4882a593Smuzhiyun 	}
2100*4882a593Smuzhiyun 
2101*4882a593Smuzhiyun 	/* Wait for a maximum packet size to be drained */
2102*4882a593Smuzhiyun 	usleep_range(2000, 3000);
2103*4882a593Smuzhiyun 
2104*4882a593Smuzhiyun 	ret = rdma_enable_set(priv, 0);
2105*4882a593Smuzhiyun 	if (ret) {
2106*4882a593Smuzhiyun 		netdev_err(dev, "timeout disabling TDMA\n");
2107*4882a593Smuzhiyun 		return ret;
2108*4882a593Smuzhiyun 	}
2109*4882a593Smuzhiyun 
2110*4882a593Smuzhiyun 	/* Disable UniMAC TX */
2111*4882a593Smuzhiyun 	umac_enable_set(priv, CMD_TX_EN, 0);
2112*4882a593Smuzhiyun 
2113*4882a593Smuzhiyun 	/* Free RX/TX rings SW structures */
2114*4882a593Smuzhiyun 	for (i = 0; i < dev->num_tx_queues; i++)
2115*4882a593Smuzhiyun 		bcm_sysport_fini_tx_ring(priv, i);
2116*4882a593Smuzhiyun 	bcm_sysport_fini_rx_ring(priv);
2117*4882a593Smuzhiyun 
2118*4882a593Smuzhiyun 	free_irq(priv->irq0, dev);
2119*4882a593Smuzhiyun 	if (!priv->is_lite)
2120*4882a593Smuzhiyun 		free_irq(priv->irq1, dev);
2121*4882a593Smuzhiyun 
2122*4882a593Smuzhiyun 	/* Disconnect from PHY */
2123*4882a593Smuzhiyun 	phy_disconnect(dev->phydev);
2124*4882a593Smuzhiyun 
2125*4882a593Smuzhiyun 	clk_disable_unprepare(priv->clk);
2126*4882a593Smuzhiyun 
2127*4882a593Smuzhiyun 	return 0;
2128*4882a593Smuzhiyun }
2129*4882a593Smuzhiyun 
bcm_sysport_rule_find(struct bcm_sysport_priv * priv,u64 location)2130*4882a593Smuzhiyun static int bcm_sysport_rule_find(struct bcm_sysport_priv *priv,
2131*4882a593Smuzhiyun 				 u64 location)
2132*4882a593Smuzhiyun {
2133*4882a593Smuzhiyun 	unsigned int index;
2134*4882a593Smuzhiyun 	u32 reg;
2135*4882a593Smuzhiyun 
2136*4882a593Smuzhiyun 	for_each_set_bit(index, priv->filters, RXCHK_BRCM_TAG_MAX) {
2137*4882a593Smuzhiyun 		reg = rxchk_readl(priv, RXCHK_BRCM_TAG(index));
2138*4882a593Smuzhiyun 		reg >>= RXCHK_BRCM_TAG_CID_SHIFT;
2139*4882a593Smuzhiyun 		reg &= RXCHK_BRCM_TAG_CID_MASK;
2140*4882a593Smuzhiyun 		if (reg == location)
2141*4882a593Smuzhiyun 			return index;
2142*4882a593Smuzhiyun 	}
2143*4882a593Smuzhiyun 
2144*4882a593Smuzhiyun 	return -EINVAL;
2145*4882a593Smuzhiyun }
2146*4882a593Smuzhiyun 
bcm_sysport_rule_get(struct bcm_sysport_priv * priv,struct ethtool_rxnfc * nfc)2147*4882a593Smuzhiyun static int bcm_sysport_rule_get(struct bcm_sysport_priv *priv,
2148*4882a593Smuzhiyun 				struct ethtool_rxnfc *nfc)
2149*4882a593Smuzhiyun {
2150*4882a593Smuzhiyun 	int index;
2151*4882a593Smuzhiyun 
2152*4882a593Smuzhiyun 	/* This is not a rule that we know about */
2153*4882a593Smuzhiyun 	index = bcm_sysport_rule_find(priv, nfc->fs.location);
2154*4882a593Smuzhiyun 	if (index < 0)
2155*4882a593Smuzhiyun 		return -EOPNOTSUPP;
2156*4882a593Smuzhiyun 
2157*4882a593Smuzhiyun 	nfc->fs.ring_cookie = RX_CLS_FLOW_WAKE;
2158*4882a593Smuzhiyun 
2159*4882a593Smuzhiyun 	return 0;
2160*4882a593Smuzhiyun }
2161*4882a593Smuzhiyun 
bcm_sysport_rule_set(struct bcm_sysport_priv * priv,struct ethtool_rxnfc * nfc)2162*4882a593Smuzhiyun static int bcm_sysport_rule_set(struct bcm_sysport_priv *priv,
2163*4882a593Smuzhiyun 				struct ethtool_rxnfc *nfc)
2164*4882a593Smuzhiyun {
2165*4882a593Smuzhiyun 	unsigned int index;
2166*4882a593Smuzhiyun 	u32 reg;
2167*4882a593Smuzhiyun 
2168*4882a593Smuzhiyun 	/* We cannot match locations greater than what the classification ID
2169*4882a593Smuzhiyun 	 * permits (256 entries)
2170*4882a593Smuzhiyun 	 */
2171*4882a593Smuzhiyun 	if (nfc->fs.location > RXCHK_BRCM_TAG_CID_MASK)
2172*4882a593Smuzhiyun 		return -E2BIG;
2173*4882a593Smuzhiyun 
2174*4882a593Smuzhiyun 	/* We cannot support flows that are not destined for a wake-up */
2175*4882a593Smuzhiyun 	if (nfc->fs.ring_cookie != RX_CLS_FLOW_WAKE)
2176*4882a593Smuzhiyun 		return -EOPNOTSUPP;
2177*4882a593Smuzhiyun 
2178*4882a593Smuzhiyun 	/* All filters are already in use, we cannot match more rules */
2179*4882a593Smuzhiyun 	if (bitmap_weight(priv->filters, RXCHK_BRCM_TAG_MAX) ==
2180*4882a593Smuzhiyun 	    RXCHK_BRCM_TAG_MAX)
2181*4882a593Smuzhiyun 		return -ENOSPC;
2182*4882a593Smuzhiyun 
2183*4882a593Smuzhiyun 	index = find_first_zero_bit(priv->filters, RXCHK_BRCM_TAG_MAX);
2184*4882a593Smuzhiyun 	if (index >= RXCHK_BRCM_TAG_MAX)
2185*4882a593Smuzhiyun 		return -ENOSPC;
2186*4882a593Smuzhiyun 
2187*4882a593Smuzhiyun 	/* Location is the classification ID, and index is the position
2188*4882a593Smuzhiyun 	 * within one of our 8 possible filters to be programmed
2189*4882a593Smuzhiyun 	 */
2190*4882a593Smuzhiyun 	reg = rxchk_readl(priv, RXCHK_BRCM_TAG(index));
2191*4882a593Smuzhiyun 	reg &= ~(RXCHK_BRCM_TAG_CID_MASK << RXCHK_BRCM_TAG_CID_SHIFT);
2192*4882a593Smuzhiyun 	reg |= nfc->fs.location << RXCHK_BRCM_TAG_CID_SHIFT;
2193*4882a593Smuzhiyun 	rxchk_writel(priv, reg, RXCHK_BRCM_TAG(index));
2194*4882a593Smuzhiyun 	rxchk_writel(priv, 0xff00ffff, RXCHK_BRCM_TAG_MASK(index));
2195*4882a593Smuzhiyun 
2196*4882a593Smuzhiyun 	priv->filters_loc[index] = nfc->fs.location;
2197*4882a593Smuzhiyun 	set_bit(index, priv->filters);
2198*4882a593Smuzhiyun 
2199*4882a593Smuzhiyun 	return 0;
2200*4882a593Smuzhiyun }
2201*4882a593Smuzhiyun 
bcm_sysport_rule_del(struct bcm_sysport_priv * priv,u64 location)2202*4882a593Smuzhiyun static int bcm_sysport_rule_del(struct bcm_sysport_priv *priv,
2203*4882a593Smuzhiyun 				u64 location)
2204*4882a593Smuzhiyun {
2205*4882a593Smuzhiyun 	int index;
2206*4882a593Smuzhiyun 
2207*4882a593Smuzhiyun 	/* This is not a rule that we know about */
2208*4882a593Smuzhiyun 	index = bcm_sysport_rule_find(priv, location);
2209*4882a593Smuzhiyun 	if (index < 0)
2210*4882a593Smuzhiyun 		return -EOPNOTSUPP;
2211*4882a593Smuzhiyun 
2212*4882a593Smuzhiyun 	/* No need to disable this filter if it was enabled, this will
2213*4882a593Smuzhiyun 	 * be taken care of during suspend time by bcm_sysport_suspend_to_wol
2214*4882a593Smuzhiyun 	 */
2215*4882a593Smuzhiyun 	clear_bit(index, priv->filters);
2216*4882a593Smuzhiyun 	priv->filters_loc[index] = 0;
2217*4882a593Smuzhiyun 
2218*4882a593Smuzhiyun 	return 0;
2219*4882a593Smuzhiyun }
2220*4882a593Smuzhiyun 
bcm_sysport_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * nfc,u32 * rule_locs)2221*4882a593Smuzhiyun static int bcm_sysport_get_rxnfc(struct net_device *dev,
2222*4882a593Smuzhiyun 				 struct ethtool_rxnfc *nfc, u32 *rule_locs)
2223*4882a593Smuzhiyun {
2224*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
2225*4882a593Smuzhiyun 	int ret = -EOPNOTSUPP;
2226*4882a593Smuzhiyun 
2227*4882a593Smuzhiyun 	switch (nfc->cmd) {
2228*4882a593Smuzhiyun 	case ETHTOOL_GRXCLSRULE:
2229*4882a593Smuzhiyun 		ret = bcm_sysport_rule_get(priv, nfc);
2230*4882a593Smuzhiyun 		break;
2231*4882a593Smuzhiyun 	default:
2232*4882a593Smuzhiyun 		break;
2233*4882a593Smuzhiyun 	}
2234*4882a593Smuzhiyun 
2235*4882a593Smuzhiyun 	return ret;
2236*4882a593Smuzhiyun }
2237*4882a593Smuzhiyun 
bcm_sysport_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * nfc)2238*4882a593Smuzhiyun static int bcm_sysport_set_rxnfc(struct net_device *dev,
2239*4882a593Smuzhiyun 				 struct ethtool_rxnfc *nfc)
2240*4882a593Smuzhiyun {
2241*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
2242*4882a593Smuzhiyun 	int ret = -EOPNOTSUPP;
2243*4882a593Smuzhiyun 
2244*4882a593Smuzhiyun 	switch (nfc->cmd) {
2245*4882a593Smuzhiyun 	case ETHTOOL_SRXCLSRLINS:
2246*4882a593Smuzhiyun 		ret = bcm_sysport_rule_set(priv, nfc);
2247*4882a593Smuzhiyun 		break;
2248*4882a593Smuzhiyun 	case ETHTOOL_SRXCLSRLDEL:
2249*4882a593Smuzhiyun 		ret = bcm_sysport_rule_del(priv, nfc->fs.location);
2250*4882a593Smuzhiyun 		break;
2251*4882a593Smuzhiyun 	default:
2252*4882a593Smuzhiyun 		break;
2253*4882a593Smuzhiyun 	}
2254*4882a593Smuzhiyun 
2255*4882a593Smuzhiyun 	return ret;
2256*4882a593Smuzhiyun }
2257*4882a593Smuzhiyun 
2258*4882a593Smuzhiyun static const struct ethtool_ops bcm_sysport_ethtool_ops = {
2259*4882a593Smuzhiyun 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2260*4882a593Smuzhiyun 				     ETHTOOL_COALESCE_MAX_FRAMES |
2261*4882a593Smuzhiyun 				     ETHTOOL_COALESCE_USE_ADAPTIVE_RX,
2262*4882a593Smuzhiyun 	.get_drvinfo		= bcm_sysport_get_drvinfo,
2263*4882a593Smuzhiyun 	.get_msglevel		= bcm_sysport_get_msglvl,
2264*4882a593Smuzhiyun 	.set_msglevel		= bcm_sysport_set_msglvl,
2265*4882a593Smuzhiyun 	.get_link		= ethtool_op_get_link,
2266*4882a593Smuzhiyun 	.get_strings		= bcm_sysport_get_strings,
2267*4882a593Smuzhiyun 	.get_ethtool_stats	= bcm_sysport_get_stats,
2268*4882a593Smuzhiyun 	.get_sset_count		= bcm_sysport_get_sset_count,
2269*4882a593Smuzhiyun 	.get_wol		= bcm_sysport_get_wol,
2270*4882a593Smuzhiyun 	.set_wol		= bcm_sysport_set_wol,
2271*4882a593Smuzhiyun 	.get_coalesce		= bcm_sysport_get_coalesce,
2272*4882a593Smuzhiyun 	.set_coalesce		= bcm_sysport_set_coalesce,
2273*4882a593Smuzhiyun 	.get_link_ksettings     = phy_ethtool_get_link_ksettings,
2274*4882a593Smuzhiyun 	.set_link_ksettings     = phy_ethtool_set_link_ksettings,
2275*4882a593Smuzhiyun 	.get_rxnfc		= bcm_sysport_get_rxnfc,
2276*4882a593Smuzhiyun 	.set_rxnfc		= bcm_sysport_set_rxnfc,
2277*4882a593Smuzhiyun };
2278*4882a593Smuzhiyun 
bcm_sysport_select_queue(struct net_device * dev,struct sk_buff * skb,struct net_device * sb_dev)2279*4882a593Smuzhiyun static u16 bcm_sysport_select_queue(struct net_device *dev, struct sk_buff *skb,
2280*4882a593Smuzhiyun 				    struct net_device *sb_dev)
2281*4882a593Smuzhiyun {
2282*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
2283*4882a593Smuzhiyun 	u16 queue = skb_get_queue_mapping(skb);
2284*4882a593Smuzhiyun 	struct bcm_sysport_tx_ring *tx_ring;
2285*4882a593Smuzhiyun 	unsigned int q, port;
2286*4882a593Smuzhiyun 
2287*4882a593Smuzhiyun 	if (!netdev_uses_dsa(dev))
2288*4882a593Smuzhiyun 		return netdev_pick_tx(dev, skb, NULL);
2289*4882a593Smuzhiyun 
2290*4882a593Smuzhiyun 	/* DSA tagging layer will have configured the correct queue */
2291*4882a593Smuzhiyun 	q = BRCM_TAG_GET_QUEUE(queue);
2292*4882a593Smuzhiyun 	port = BRCM_TAG_GET_PORT(queue);
2293*4882a593Smuzhiyun 	tx_ring = priv->ring_map[q + port * priv->per_port_num_tx_queues];
2294*4882a593Smuzhiyun 
2295*4882a593Smuzhiyun 	if (unlikely(!tx_ring))
2296*4882a593Smuzhiyun 		return netdev_pick_tx(dev, skb, NULL);
2297*4882a593Smuzhiyun 
2298*4882a593Smuzhiyun 	return tx_ring->index;
2299*4882a593Smuzhiyun }
2300*4882a593Smuzhiyun 
2301*4882a593Smuzhiyun static const struct net_device_ops bcm_sysport_netdev_ops = {
2302*4882a593Smuzhiyun 	.ndo_start_xmit		= bcm_sysport_xmit,
2303*4882a593Smuzhiyun 	.ndo_tx_timeout		= bcm_sysport_tx_timeout,
2304*4882a593Smuzhiyun 	.ndo_open		= bcm_sysport_open,
2305*4882a593Smuzhiyun 	.ndo_stop		= bcm_sysport_stop,
2306*4882a593Smuzhiyun 	.ndo_set_features	= bcm_sysport_set_features,
2307*4882a593Smuzhiyun 	.ndo_set_rx_mode	= bcm_sysport_set_rx_mode,
2308*4882a593Smuzhiyun 	.ndo_set_mac_address	= bcm_sysport_change_mac,
2309*4882a593Smuzhiyun #ifdef CONFIG_NET_POLL_CONTROLLER
2310*4882a593Smuzhiyun 	.ndo_poll_controller	= bcm_sysport_poll_controller,
2311*4882a593Smuzhiyun #endif
2312*4882a593Smuzhiyun 	.ndo_get_stats64	= bcm_sysport_get_stats64,
2313*4882a593Smuzhiyun 	.ndo_select_queue	= bcm_sysport_select_queue,
2314*4882a593Smuzhiyun };
2315*4882a593Smuzhiyun 
bcm_sysport_map_queues(struct notifier_block * nb,struct dsa_notifier_register_info * info)2316*4882a593Smuzhiyun static int bcm_sysport_map_queues(struct notifier_block *nb,
2317*4882a593Smuzhiyun 				  struct dsa_notifier_register_info *info)
2318*4882a593Smuzhiyun {
2319*4882a593Smuzhiyun 	struct bcm_sysport_tx_ring *ring;
2320*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv;
2321*4882a593Smuzhiyun 	struct net_device *slave_dev;
2322*4882a593Smuzhiyun 	unsigned int num_tx_queues;
2323*4882a593Smuzhiyun 	unsigned int q, qp, port;
2324*4882a593Smuzhiyun 	struct net_device *dev;
2325*4882a593Smuzhiyun 
2326*4882a593Smuzhiyun 	priv = container_of(nb, struct bcm_sysport_priv, dsa_notifier);
2327*4882a593Smuzhiyun 	if (priv->netdev != info->master)
2328*4882a593Smuzhiyun 		return 0;
2329*4882a593Smuzhiyun 
2330*4882a593Smuzhiyun 	dev = info->master;
2331*4882a593Smuzhiyun 
2332*4882a593Smuzhiyun 	/* We can't be setting up queue inspection for non directly attached
2333*4882a593Smuzhiyun 	 * switches
2334*4882a593Smuzhiyun 	 */
2335*4882a593Smuzhiyun 	if (info->switch_number)
2336*4882a593Smuzhiyun 		return 0;
2337*4882a593Smuzhiyun 
2338*4882a593Smuzhiyun 	if (dev->netdev_ops != &bcm_sysport_netdev_ops)
2339*4882a593Smuzhiyun 		return 0;
2340*4882a593Smuzhiyun 
2341*4882a593Smuzhiyun 	port = info->port_number;
2342*4882a593Smuzhiyun 	slave_dev = info->info.dev;
2343*4882a593Smuzhiyun 
2344*4882a593Smuzhiyun 	/* On SYSTEMPORT Lite we have twice as less queues, so we cannot do a
2345*4882a593Smuzhiyun 	 * 1:1 mapping, we can only do a 2:1 mapping. By reducing the number of
2346*4882a593Smuzhiyun 	 * per-port (slave_dev) network devices queue, we achieve just that.
2347*4882a593Smuzhiyun 	 * This need to happen now before any slave network device is used such
2348*4882a593Smuzhiyun 	 * it accurately reflects the number of real TX queues.
2349*4882a593Smuzhiyun 	 */
2350*4882a593Smuzhiyun 	if (priv->is_lite)
2351*4882a593Smuzhiyun 		netif_set_real_num_tx_queues(slave_dev,
2352*4882a593Smuzhiyun 					     slave_dev->num_tx_queues / 2);
2353*4882a593Smuzhiyun 
2354*4882a593Smuzhiyun 	num_tx_queues = slave_dev->real_num_tx_queues;
2355*4882a593Smuzhiyun 
2356*4882a593Smuzhiyun 	if (priv->per_port_num_tx_queues &&
2357*4882a593Smuzhiyun 	    priv->per_port_num_tx_queues != num_tx_queues)
2358*4882a593Smuzhiyun 		netdev_warn(slave_dev, "asymmetric number of per-port queues\n");
2359*4882a593Smuzhiyun 
2360*4882a593Smuzhiyun 	priv->per_port_num_tx_queues = num_tx_queues;
2361*4882a593Smuzhiyun 
2362*4882a593Smuzhiyun 	for (q = 0, qp = 0; q < dev->num_tx_queues && qp < num_tx_queues;
2363*4882a593Smuzhiyun 	     q++) {
2364*4882a593Smuzhiyun 		ring = &priv->tx_rings[q];
2365*4882a593Smuzhiyun 
2366*4882a593Smuzhiyun 		if (ring->inspect)
2367*4882a593Smuzhiyun 			continue;
2368*4882a593Smuzhiyun 
2369*4882a593Smuzhiyun 		/* Just remember the mapping actual programming done
2370*4882a593Smuzhiyun 		 * during bcm_sysport_init_tx_ring
2371*4882a593Smuzhiyun 		 */
2372*4882a593Smuzhiyun 		ring->switch_queue = qp;
2373*4882a593Smuzhiyun 		ring->switch_port = port;
2374*4882a593Smuzhiyun 		ring->inspect = true;
2375*4882a593Smuzhiyun 		priv->ring_map[qp + port * num_tx_queues] = ring;
2376*4882a593Smuzhiyun 		qp++;
2377*4882a593Smuzhiyun 	}
2378*4882a593Smuzhiyun 
2379*4882a593Smuzhiyun 	return 0;
2380*4882a593Smuzhiyun }
2381*4882a593Smuzhiyun 
bcm_sysport_unmap_queues(struct notifier_block * nb,struct dsa_notifier_register_info * info)2382*4882a593Smuzhiyun static int bcm_sysport_unmap_queues(struct notifier_block *nb,
2383*4882a593Smuzhiyun 				    struct dsa_notifier_register_info *info)
2384*4882a593Smuzhiyun {
2385*4882a593Smuzhiyun 	struct bcm_sysport_tx_ring *ring;
2386*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv;
2387*4882a593Smuzhiyun 	struct net_device *slave_dev;
2388*4882a593Smuzhiyun 	unsigned int num_tx_queues;
2389*4882a593Smuzhiyun 	struct net_device *dev;
2390*4882a593Smuzhiyun 	unsigned int q, qp, port;
2391*4882a593Smuzhiyun 
2392*4882a593Smuzhiyun 	priv = container_of(nb, struct bcm_sysport_priv, dsa_notifier);
2393*4882a593Smuzhiyun 	if (priv->netdev != info->master)
2394*4882a593Smuzhiyun 		return 0;
2395*4882a593Smuzhiyun 
2396*4882a593Smuzhiyun 	dev = info->master;
2397*4882a593Smuzhiyun 
2398*4882a593Smuzhiyun 	if (dev->netdev_ops != &bcm_sysport_netdev_ops)
2399*4882a593Smuzhiyun 		return 0;
2400*4882a593Smuzhiyun 
2401*4882a593Smuzhiyun 	port = info->port_number;
2402*4882a593Smuzhiyun 	slave_dev = info->info.dev;
2403*4882a593Smuzhiyun 
2404*4882a593Smuzhiyun 	num_tx_queues = slave_dev->real_num_tx_queues;
2405*4882a593Smuzhiyun 
2406*4882a593Smuzhiyun 	for (q = 0; q < dev->num_tx_queues; q++) {
2407*4882a593Smuzhiyun 		ring = &priv->tx_rings[q];
2408*4882a593Smuzhiyun 
2409*4882a593Smuzhiyun 		if (ring->switch_port != port)
2410*4882a593Smuzhiyun 			continue;
2411*4882a593Smuzhiyun 
2412*4882a593Smuzhiyun 		if (!ring->inspect)
2413*4882a593Smuzhiyun 			continue;
2414*4882a593Smuzhiyun 
2415*4882a593Smuzhiyun 		ring->inspect = false;
2416*4882a593Smuzhiyun 		qp = ring->switch_queue;
2417*4882a593Smuzhiyun 		priv->ring_map[qp + port * num_tx_queues] = NULL;
2418*4882a593Smuzhiyun 	}
2419*4882a593Smuzhiyun 
2420*4882a593Smuzhiyun 	return 0;
2421*4882a593Smuzhiyun }
2422*4882a593Smuzhiyun 
bcm_sysport_dsa_notifier(struct notifier_block * nb,unsigned long event,void * ptr)2423*4882a593Smuzhiyun static int bcm_sysport_dsa_notifier(struct notifier_block *nb,
2424*4882a593Smuzhiyun 				    unsigned long event, void *ptr)
2425*4882a593Smuzhiyun {
2426*4882a593Smuzhiyun 	int ret = NOTIFY_DONE;
2427*4882a593Smuzhiyun 
2428*4882a593Smuzhiyun 	switch (event) {
2429*4882a593Smuzhiyun 	case DSA_PORT_REGISTER:
2430*4882a593Smuzhiyun 		ret = bcm_sysport_map_queues(nb, ptr);
2431*4882a593Smuzhiyun 		break;
2432*4882a593Smuzhiyun 	case DSA_PORT_UNREGISTER:
2433*4882a593Smuzhiyun 		ret = bcm_sysport_unmap_queues(nb, ptr);
2434*4882a593Smuzhiyun 		break;
2435*4882a593Smuzhiyun 	}
2436*4882a593Smuzhiyun 
2437*4882a593Smuzhiyun 	return notifier_from_errno(ret);
2438*4882a593Smuzhiyun }
2439*4882a593Smuzhiyun 
2440*4882a593Smuzhiyun #define REV_FMT	"v%2x.%02x"
2441*4882a593Smuzhiyun 
2442*4882a593Smuzhiyun static const struct bcm_sysport_hw_params bcm_sysport_params[] = {
2443*4882a593Smuzhiyun 	[SYSTEMPORT] = {
2444*4882a593Smuzhiyun 		.is_lite = false,
2445*4882a593Smuzhiyun 		.num_rx_desc_words = SP_NUM_HW_RX_DESC_WORDS,
2446*4882a593Smuzhiyun 	},
2447*4882a593Smuzhiyun 	[SYSTEMPORT_LITE] = {
2448*4882a593Smuzhiyun 		.is_lite = true,
2449*4882a593Smuzhiyun 		.num_rx_desc_words = SP_LT_NUM_HW_RX_DESC_WORDS,
2450*4882a593Smuzhiyun 	},
2451*4882a593Smuzhiyun };
2452*4882a593Smuzhiyun 
2453*4882a593Smuzhiyun static const struct of_device_id bcm_sysport_of_match[] = {
2454*4882a593Smuzhiyun 	{ .compatible = "brcm,systemportlite-v1.00",
2455*4882a593Smuzhiyun 	  .data = &bcm_sysport_params[SYSTEMPORT_LITE] },
2456*4882a593Smuzhiyun 	{ .compatible = "brcm,systemport-v1.00",
2457*4882a593Smuzhiyun 	  .data = &bcm_sysport_params[SYSTEMPORT] },
2458*4882a593Smuzhiyun 	{ .compatible = "brcm,systemport",
2459*4882a593Smuzhiyun 	  .data = &bcm_sysport_params[SYSTEMPORT] },
2460*4882a593Smuzhiyun 	{ /* sentinel */ }
2461*4882a593Smuzhiyun };
2462*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, bcm_sysport_of_match);
2463*4882a593Smuzhiyun 
bcm_sysport_probe(struct platform_device * pdev)2464*4882a593Smuzhiyun static int bcm_sysport_probe(struct platform_device *pdev)
2465*4882a593Smuzhiyun {
2466*4882a593Smuzhiyun 	const struct bcm_sysport_hw_params *params;
2467*4882a593Smuzhiyun 	const struct of_device_id *of_id = NULL;
2468*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv;
2469*4882a593Smuzhiyun 	struct device_node *dn;
2470*4882a593Smuzhiyun 	struct net_device *dev;
2471*4882a593Smuzhiyun 	const void *macaddr;
2472*4882a593Smuzhiyun 	u32 txq, rxq;
2473*4882a593Smuzhiyun 	int ret;
2474*4882a593Smuzhiyun 
2475*4882a593Smuzhiyun 	dn = pdev->dev.of_node;
2476*4882a593Smuzhiyun 	of_id = of_match_node(bcm_sysport_of_match, dn);
2477*4882a593Smuzhiyun 	if (!of_id || !of_id->data)
2478*4882a593Smuzhiyun 		return -EINVAL;
2479*4882a593Smuzhiyun 
2480*4882a593Smuzhiyun 	ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
2481*4882a593Smuzhiyun 	if (ret)
2482*4882a593Smuzhiyun 		ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
2483*4882a593Smuzhiyun 	if (ret) {
2484*4882a593Smuzhiyun 		dev_err(&pdev->dev, "unable to set DMA mask: %d\n", ret);
2485*4882a593Smuzhiyun 		return ret;
2486*4882a593Smuzhiyun 	}
2487*4882a593Smuzhiyun 
2488*4882a593Smuzhiyun 	/* Fairly quickly we need to know the type of adapter we have */
2489*4882a593Smuzhiyun 	params = of_id->data;
2490*4882a593Smuzhiyun 
2491*4882a593Smuzhiyun 	/* Read the Transmit/Receive Queue properties */
2492*4882a593Smuzhiyun 	if (of_property_read_u32(dn, "systemport,num-txq", &txq))
2493*4882a593Smuzhiyun 		txq = TDMA_NUM_RINGS;
2494*4882a593Smuzhiyun 	if (of_property_read_u32(dn, "systemport,num-rxq", &rxq))
2495*4882a593Smuzhiyun 		rxq = 1;
2496*4882a593Smuzhiyun 
2497*4882a593Smuzhiyun 	/* Sanity check the number of transmit queues */
2498*4882a593Smuzhiyun 	if (!txq || txq > TDMA_NUM_RINGS)
2499*4882a593Smuzhiyun 		return -EINVAL;
2500*4882a593Smuzhiyun 
2501*4882a593Smuzhiyun 	dev = alloc_etherdev_mqs(sizeof(*priv), txq, rxq);
2502*4882a593Smuzhiyun 	if (!dev)
2503*4882a593Smuzhiyun 		return -ENOMEM;
2504*4882a593Smuzhiyun 
2505*4882a593Smuzhiyun 	/* Initialize private members */
2506*4882a593Smuzhiyun 	priv = netdev_priv(dev);
2507*4882a593Smuzhiyun 
2508*4882a593Smuzhiyun 	priv->clk = devm_clk_get_optional(&pdev->dev, "sw_sysport");
2509*4882a593Smuzhiyun 	if (IS_ERR(priv->clk)) {
2510*4882a593Smuzhiyun 		ret = PTR_ERR(priv->clk);
2511*4882a593Smuzhiyun 		goto err_free_netdev;
2512*4882a593Smuzhiyun 	}
2513*4882a593Smuzhiyun 
2514*4882a593Smuzhiyun 	/* Allocate number of TX rings */
2515*4882a593Smuzhiyun 	priv->tx_rings = devm_kcalloc(&pdev->dev, txq,
2516*4882a593Smuzhiyun 				      sizeof(struct bcm_sysport_tx_ring),
2517*4882a593Smuzhiyun 				      GFP_KERNEL);
2518*4882a593Smuzhiyun 	if (!priv->tx_rings) {
2519*4882a593Smuzhiyun 		ret = -ENOMEM;
2520*4882a593Smuzhiyun 		goto err_free_netdev;
2521*4882a593Smuzhiyun 	}
2522*4882a593Smuzhiyun 
2523*4882a593Smuzhiyun 	priv->is_lite = params->is_lite;
2524*4882a593Smuzhiyun 	priv->num_rx_desc_words = params->num_rx_desc_words;
2525*4882a593Smuzhiyun 
2526*4882a593Smuzhiyun 	priv->irq0 = platform_get_irq(pdev, 0);
2527*4882a593Smuzhiyun 	if (!priv->is_lite) {
2528*4882a593Smuzhiyun 		priv->irq1 = platform_get_irq(pdev, 1);
2529*4882a593Smuzhiyun 		priv->wol_irq = platform_get_irq(pdev, 2);
2530*4882a593Smuzhiyun 	} else {
2531*4882a593Smuzhiyun 		priv->wol_irq = platform_get_irq(pdev, 1);
2532*4882a593Smuzhiyun 	}
2533*4882a593Smuzhiyun 	if (priv->irq0 <= 0 || (priv->irq1 <= 0 && !priv->is_lite)) {
2534*4882a593Smuzhiyun 		ret = -EINVAL;
2535*4882a593Smuzhiyun 		goto err_free_netdev;
2536*4882a593Smuzhiyun 	}
2537*4882a593Smuzhiyun 
2538*4882a593Smuzhiyun 	priv->base = devm_platform_ioremap_resource(pdev, 0);
2539*4882a593Smuzhiyun 	if (IS_ERR(priv->base)) {
2540*4882a593Smuzhiyun 		ret = PTR_ERR(priv->base);
2541*4882a593Smuzhiyun 		goto err_free_netdev;
2542*4882a593Smuzhiyun 	}
2543*4882a593Smuzhiyun 
2544*4882a593Smuzhiyun 	priv->netdev = dev;
2545*4882a593Smuzhiyun 	priv->pdev = pdev;
2546*4882a593Smuzhiyun 
2547*4882a593Smuzhiyun 	ret = of_get_phy_mode(dn, &priv->phy_interface);
2548*4882a593Smuzhiyun 	/* Default to GMII interface mode */
2549*4882a593Smuzhiyun 	if (ret)
2550*4882a593Smuzhiyun 		priv->phy_interface = PHY_INTERFACE_MODE_GMII;
2551*4882a593Smuzhiyun 
2552*4882a593Smuzhiyun 	/* In the case of a fixed PHY, the DT node associated
2553*4882a593Smuzhiyun 	 * to the PHY is the Ethernet MAC DT node.
2554*4882a593Smuzhiyun 	 */
2555*4882a593Smuzhiyun 	if (of_phy_is_fixed_link(dn)) {
2556*4882a593Smuzhiyun 		ret = of_phy_register_fixed_link(dn);
2557*4882a593Smuzhiyun 		if (ret) {
2558*4882a593Smuzhiyun 			dev_err(&pdev->dev, "failed to register fixed PHY\n");
2559*4882a593Smuzhiyun 			goto err_free_netdev;
2560*4882a593Smuzhiyun 		}
2561*4882a593Smuzhiyun 
2562*4882a593Smuzhiyun 		priv->phy_dn = dn;
2563*4882a593Smuzhiyun 	}
2564*4882a593Smuzhiyun 
2565*4882a593Smuzhiyun 	/* Initialize netdevice members */
2566*4882a593Smuzhiyun 	macaddr = of_get_mac_address(dn);
2567*4882a593Smuzhiyun 	if (IS_ERR(macaddr)) {
2568*4882a593Smuzhiyun 		dev_warn(&pdev->dev, "using random Ethernet MAC\n");
2569*4882a593Smuzhiyun 		eth_hw_addr_random(dev);
2570*4882a593Smuzhiyun 	} else {
2571*4882a593Smuzhiyun 		ether_addr_copy(dev->dev_addr, macaddr);
2572*4882a593Smuzhiyun 	}
2573*4882a593Smuzhiyun 
2574*4882a593Smuzhiyun 	SET_NETDEV_DEV(dev, &pdev->dev);
2575*4882a593Smuzhiyun 	dev_set_drvdata(&pdev->dev, dev);
2576*4882a593Smuzhiyun 	dev->ethtool_ops = &bcm_sysport_ethtool_ops;
2577*4882a593Smuzhiyun 	dev->netdev_ops = &bcm_sysport_netdev_ops;
2578*4882a593Smuzhiyun 	netif_napi_add(dev, &priv->napi, bcm_sysport_poll, 64);
2579*4882a593Smuzhiyun 
2580*4882a593Smuzhiyun 	dev->features |= NETIF_F_RXCSUM | NETIF_F_HIGHDMA |
2581*4882a593Smuzhiyun 			 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2582*4882a593Smuzhiyun 			 NETIF_F_HW_VLAN_CTAG_TX;
2583*4882a593Smuzhiyun 	dev->hw_features |= dev->features;
2584*4882a593Smuzhiyun 	dev->vlan_features |= dev->features;
2585*4882a593Smuzhiyun 	dev->max_mtu = UMAC_MAX_MTU_SIZE;
2586*4882a593Smuzhiyun 
2587*4882a593Smuzhiyun 	/* Request the WOL interrupt and advertise suspend if available */
2588*4882a593Smuzhiyun 	priv->wol_irq_disabled = 1;
2589*4882a593Smuzhiyun 	ret = devm_request_irq(&pdev->dev, priv->wol_irq,
2590*4882a593Smuzhiyun 			       bcm_sysport_wol_isr, 0, dev->name, priv);
2591*4882a593Smuzhiyun 	if (!ret)
2592*4882a593Smuzhiyun 		device_set_wakeup_capable(&pdev->dev, 1);
2593*4882a593Smuzhiyun 
2594*4882a593Smuzhiyun 	priv->wol_clk = devm_clk_get_optional(&pdev->dev, "sw_sysportwol");
2595*4882a593Smuzhiyun 	if (IS_ERR(priv->wol_clk)) {
2596*4882a593Smuzhiyun 		ret = PTR_ERR(priv->wol_clk);
2597*4882a593Smuzhiyun 		goto err_deregister_fixed_link;
2598*4882a593Smuzhiyun 	}
2599*4882a593Smuzhiyun 
2600*4882a593Smuzhiyun 	/* Set the needed headroom once and for all */
2601*4882a593Smuzhiyun 	BUILD_BUG_ON(sizeof(struct bcm_tsb) != 8);
2602*4882a593Smuzhiyun 	dev->needed_headroom += sizeof(struct bcm_tsb);
2603*4882a593Smuzhiyun 
2604*4882a593Smuzhiyun 	/* libphy will adjust the link state accordingly */
2605*4882a593Smuzhiyun 	netif_carrier_off(dev);
2606*4882a593Smuzhiyun 
2607*4882a593Smuzhiyun 	priv->rx_max_coalesced_frames = 1;
2608*4882a593Smuzhiyun 	u64_stats_init(&priv->syncp);
2609*4882a593Smuzhiyun 
2610*4882a593Smuzhiyun 	priv->dsa_notifier.notifier_call = bcm_sysport_dsa_notifier;
2611*4882a593Smuzhiyun 
2612*4882a593Smuzhiyun 	ret = register_dsa_notifier(&priv->dsa_notifier);
2613*4882a593Smuzhiyun 	if (ret) {
2614*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to register DSA notifier\n");
2615*4882a593Smuzhiyun 		goto err_deregister_fixed_link;
2616*4882a593Smuzhiyun 	}
2617*4882a593Smuzhiyun 
2618*4882a593Smuzhiyun 	ret = register_netdev(dev);
2619*4882a593Smuzhiyun 	if (ret) {
2620*4882a593Smuzhiyun 		dev_err(&pdev->dev, "failed to register net_device\n");
2621*4882a593Smuzhiyun 		goto err_deregister_notifier;
2622*4882a593Smuzhiyun 	}
2623*4882a593Smuzhiyun 
2624*4882a593Smuzhiyun 	clk_prepare_enable(priv->clk);
2625*4882a593Smuzhiyun 
2626*4882a593Smuzhiyun 	priv->rev = topctrl_readl(priv, REV_CNTL) & REV_MASK;
2627*4882a593Smuzhiyun 	dev_info(&pdev->dev,
2628*4882a593Smuzhiyun 		 "Broadcom SYSTEMPORT%s " REV_FMT
2629*4882a593Smuzhiyun 		 " (irqs: %d, %d, TXQs: %d, RXQs: %d)\n",
2630*4882a593Smuzhiyun 		 priv->is_lite ? " Lite" : "",
2631*4882a593Smuzhiyun 		 (priv->rev >> 8) & 0xff, priv->rev & 0xff,
2632*4882a593Smuzhiyun 		 priv->irq0, priv->irq1, txq, rxq);
2633*4882a593Smuzhiyun 
2634*4882a593Smuzhiyun 	clk_disable_unprepare(priv->clk);
2635*4882a593Smuzhiyun 
2636*4882a593Smuzhiyun 	return 0;
2637*4882a593Smuzhiyun 
2638*4882a593Smuzhiyun err_deregister_notifier:
2639*4882a593Smuzhiyun 	unregister_dsa_notifier(&priv->dsa_notifier);
2640*4882a593Smuzhiyun err_deregister_fixed_link:
2641*4882a593Smuzhiyun 	if (of_phy_is_fixed_link(dn))
2642*4882a593Smuzhiyun 		of_phy_deregister_fixed_link(dn);
2643*4882a593Smuzhiyun err_free_netdev:
2644*4882a593Smuzhiyun 	free_netdev(dev);
2645*4882a593Smuzhiyun 	return ret;
2646*4882a593Smuzhiyun }
2647*4882a593Smuzhiyun 
bcm_sysport_remove(struct platform_device * pdev)2648*4882a593Smuzhiyun static int bcm_sysport_remove(struct platform_device *pdev)
2649*4882a593Smuzhiyun {
2650*4882a593Smuzhiyun 	struct net_device *dev = dev_get_drvdata(&pdev->dev);
2651*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
2652*4882a593Smuzhiyun 	struct device_node *dn = pdev->dev.of_node;
2653*4882a593Smuzhiyun 
2654*4882a593Smuzhiyun 	/* Not much to do, ndo_close has been called
2655*4882a593Smuzhiyun 	 * and we use managed allocations
2656*4882a593Smuzhiyun 	 */
2657*4882a593Smuzhiyun 	unregister_dsa_notifier(&priv->dsa_notifier);
2658*4882a593Smuzhiyun 	unregister_netdev(dev);
2659*4882a593Smuzhiyun 	if (of_phy_is_fixed_link(dn))
2660*4882a593Smuzhiyun 		of_phy_deregister_fixed_link(dn);
2661*4882a593Smuzhiyun 	free_netdev(dev);
2662*4882a593Smuzhiyun 	dev_set_drvdata(&pdev->dev, NULL);
2663*4882a593Smuzhiyun 
2664*4882a593Smuzhiyun 	return 0;
2665*4882a593Smuzhiyun }
2666*4882a593Smuzhiyun 
bcm_sysport_suspend_to_wol(struct bcm_sysport_priv * priv)2667*4882a593Smuzhiyun static int bcm_sysport_suspend_to_wol(struct bcm_sysport_priv *priv)
2668*4882a593Smuzhiyun {
2669*4882a593Smuzhiyun 	struct net_device *ndev = priv->netdev;
2670*4882a593Smuzhiyun 	unsigned int timeout = 1000;
2671*4882a593Smuzhiyun 	unsigned int index, i = 0;
2672*4882a593Smuzhiyun 	u32 reg;
2673*4882a593Smuzhiyun 
2674*4882a593Smuzhiyun 	reg = umac_readl(priv, UMAC_MPD_CTRL);
2675*4882a593Smuzhiyun 	if (priv->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE))
2676*4882a593Smuzhiyun 		reg |= MPD_EN;
2677*4882a593Smuzhiyun 	reg &= ~PSW_EN;
2678*4882a593Smuzhiyun 	if (priv->wolopts & WAKE_MAGICSECURE) {
2679*4882a593Smuzhiyun 		/* Program the SecureOn password */
2680*4882a593Smuzhiyun 		umac_writel(priv, get_unaligned_be16(&priv->sopass[0]),
2681*4882a593Smuzhiyun 			    UMAC_PSW_MS);
2682*4882a593Smuzhiyun 		umac_writel(priv, get_unaligned_be32(&priv->sopass[2]),
2683*4882a593Smuzhiyun 			    UMAC_PSW_LS);
2684*4882a593Smuzhiyun 		reg |= PSW_EN;
2685*4882a593Smuzhiyun 	}
2686*4882a593Smuzhiyun 	umac_writel(priv, reg, UMAC_MPD_CTRL);
2687*4882a593Smuzhiyun 
2688*4882a593Smuzhiyun 	if (priv->wolopts & WAKE_FILTER) {
2689*4882a593Smuzhiyun 		/* Turn on ACPI matching to steal packets from RBUF */
2690*4882a593Smuzhiyun 		reg = rbuf_readl(priv, RBUF_CONTROL);
2691*4882a593Smuzhiyun 		if (priv->is_lite)
2692*4882a593Smuzhiyun 			reg |= RBUF_ACPI_EN_LITE;
2693*4882a593Smuzhiyun 		else
2694*4882a593Smuzhiyun 			reg |= RBUF_ACPI_EN;
2695*4882a593Smuzhiyun 		rbuf_writel(priv, reg, RBUF_CONTROL);
2696*4882a593Smuzhiyun 
2697*4882a593Smuzhiyun 		/* Enable RXCHK, active filters and Broadcom tag matching */
2698*4882a593Smuzhiyun 		reg = rxchk_readl(priv, RXCHK_CONTROL);
2699*4882a593Smuzhiyun 		reg &= ~(RXCHK_BRCM_TAG_MATCH_MASK <<
2700*4882a593Smuzhiyun 			 RXCHK_BRCM_TAG_MATCH_SHIFT);
2701*4882a593Smuzhiyun 		for_each_set_bit(index, priv->filters, RXCHK_BRCM_TAG_MAX) {
2702*4882a593Smuzhiyun 			reg |= BIT(RXCHK_BRCM_TAG_MATCH_SHIFT + i);
2703*4882a593Smuzhiyun 			i++;
2704*4882a593Smuzhiyun 		}
2705*4882a593Smuzhiyun 		reg |= RXCHK_EN | RXCHK_BRCM_TAG_EN;
2706*4882a593Smuzhiyun 		rxchk_writel(priv, reg, RXCHK_CONTROL);
2707*4882a593Smuzhiyun 	}
2708*4882a593Smuzhiyun 
2709*4882a593Smuzhiyun 	/* Make sure RBUF entered WoL mode as result */
2710*4882a593Smuzhiyun 	do {
2711*4882a593Smuzhiyun 		reg = rbuf_readl(priv, RBUF_STATUS);
2712*4882a593Smuzhiyun 		if (reg & RBUF_WOL_MODE)
2713*4882a593Smuzhiyun 			break;
2714*4882a593Smuzhiyun 
2715*4882a593Smuzhiyun 		udelay(10);
2716*4882a593Smuzhiyun 	} while (timeout-- > 0);
2717*4882a593Smuzhiyun 
2718*4882a593Smuzhiyun 	/* Do not leave the UniMAC RBUF matching only MPD packets */
2719*4882a593Smuzhiyun 	if (!timeout) {
2720*4882a593Smuzhiyun 		mpd_enable_set(priv, false);
2721*4882a593Smuzhiyun 		netif_err(priv, wol, ndev, "failed to enter WOL mode\n");
2722*4882a593Smuzhiyun 		return -ETIMEDOUT;
2723*4882a593Smuzhiyun 	}
2724*4882a593Smuzhiyun 
2725*4882a593Smuzhiyun 	/* UniMAC receive needs to be turned on */
2726*4882a593Smuzhiyun 	umac_enable_set(priv, CMD_RX_EN, 1);
2727*4882a593Smuzhiyun 
2728*4882a593Smuzhiyun 	netif_dbg(priv, wol, ndev, "entered WOL mode\n");
2729*4882a593Smuzhiyun 
2730*4882a593Smuzhiyun 	return 0;
2731*4882a593Smuzhiyun }
2732*4882a593Smuzhiyun 
bcm_sysport_suspend(struct device * d)2733*4882a593Smuzhiyun static int __maybe_unused bcm_sysport_suspend(struct device *d)
2734*4882a593Smuzhiyun {
2735*4882a593Smuzhiyun 	struct net_device *dev = dev_get_drvdata(d);
2736*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
2737*4882a593Smuzhiyun 	unsigned int i;
2738*4882a593Smuzhiyun 	int ret = 0;
2739*4882a593Smuzhiyun 	u32 reg;
2740*4882a593Smuzhiyun 
2741*4882a593Smuzhiyun 	if (!netif_running(dev))
2742*4882a593Smuzhiyun 		return 0;
2743*4882a593Smuzhiyun 
2744*4882a593Smuzhiyun 	netif_device_detach(dev);
2745*4882a593Smuzhiyun 
2746*4882a593Smuzhiyun 	bcm_sysport_netif_stop(dev);
2747*4882a593Smuzhiyun 
2748*4882a593Smuzhiyun 	phy_suspend(dev->phydev);
2749*4882a593Smuzhiyun 
2750*4882a593Smuzhiyun 	/* Disable UniMAC RX */
2751*4882a593Smuzhiyun 	umac_enable_set(priv, CMD_RX_EN, 0);
2752*4882a593Smuzhiyun 
2753*4882a593Smuzhiyun 	ret = rdma_enable_set(priv, 0);
2754*4882a593Smuzhiyun 	if (ret) {
2755*4882a593Smuzhiyun 		netdev_err(dev, "RDMA timeout!\n");
2756*4882a593Smuzhiyun 		return ret;
2757*4882a593Smuzhiyun 	}
2758*4882a593Smuzhiyun 
2759*4882a593Smuzhiyun 	/* Disable RXCHK if enabled */
2760*4882a593Smuzhiyun 	if (priv->rx_chk_en) {
2761*4882a593Smuzhiyun 		reg = rxchk_readl(priv, RXCHK_CONTROL);
2762*4882a593Smuzhiyun 		reg &= ~RXCHK_EN;
2763*4882a593Smuzhiyun 		rxchk_writel(priv, reg, RXCHK_CONTROL);
2764*4882a593Smuzhiyun 	}
2765*4882a593Smuzhiyun 
2766*4882a593Smuzhiyun 	/* Flush RX pipe */
2767*4882a593Smuzhiyun 	if (!priv->wolopts)
2768*4882a593Smuzhiyun 		topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL);
2769*4882a593Smuzhiyun 
2770*4882a593Smuzhiyun 	ret = tdma_enable_set(priv, 0);
2771*4882a593Smuzhiyun 	if (ret) {
2772*4882a593Smuzhiyun 		netdev_err(dev, "TDMA timeout!\n");
2773*4882a593Smuzhiyun 		return ret;
2774*4882a593Smuzhiyun 	}
2775*4882a593Smuzhiyun 
2776*4882a593Smuzhiyun 	/* Wait for a packet boundary */
2777*4882a593Smuzhiyun 	usleep_range(2000, 3000);
2778*4882a593Smuzhiyun 
2779*4882a593Smuzhiyun 	umac_enable_set(priv, CMD_TX_EN, 0);
2780*4882a593Smuzhiyun 
2781*4882a593Smuzhiyun 	topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL);
2782*4882a593Smuzhiyun 
2783*4882a593Smuzhiyun 	/* Free RX/TX rings SW structures */
2784*4882a593Smuzhiyun 	for (i = 0; i < dev->num_tx_queues; i++)
2785*4882a593Smuzhiyun 		bcm_sysport_fini_tx_ring(priv, i);
2786*4882a593Smuzhiyun 	bcm_sysport_fini_rx_ring(priv);
2787*4882a593Smuzhiyun 
2788*4882a593Smuzhiyun 	/* Get prepared for Wake-on-LAN */
2789*4882a593Smuzhiyun 	if (device_may_wakeup(d) && priv->wolopts) {
2790*4882a593Smuzhiyun 		clk_prepare_enable(priv->wol_clk);
2791*4882a593Smuzhiyun 		ret = bcm_sysport_suspend_to_wol(priv);
2792*4882a593Smuzhiyun 	}
2793*4882a593Smuzhiyun 
2794*4882a593Smuzhiyun 	clk_disable_unprepare(priv->clk);
2795*4882a593Smuzhiyun 
2796*4882a593Smuzhiyun 	return ret;
2797*4882a593Smuzhiyun }
2798*4882a593Smuzhiyun 
bcm_sysport_resume(struct device * d)2799*4882a593Smuzhiyun static int __maybe_unused bcm_sysport_resume(struct device *d)
2800*4882a593Smuzhiyun {
2801*4882a593Smuzhiyun 	struct net_device *dev = dev_get_drvdata(d);
2802*4882a593Smuzhiyun 	struct bcm_sysport_priv *priv = netdev_priv(dev);
2803*4882a593Smuzhiyun 	unsigned int i;
2804*4882a593Smuzhiyun 	int ret;
2805*4882a593Smuzhiyun 
2806*4882a593Smuzhiyun 	if (!netif_running(dev))
2807*4882a593Smuzhiyun 		return 0;
2808*4882a593Smuzhiyun 
2809*4882a593Smuzhiyun 	clk_prepare_enable(priv->clk);
2810*4882a593Smuzhiyun 	if (priv->wolopts)
2811*4882a593Smuzhiyun 		clk_disable_unprepare(priv->wol_clk);
2812*4882a593Smuzhiyun 
2813*4882a593Smuzhiyun 	umac_reset(priv);
2814*4882a593Smuzhiyun 
2815*4882a593Smuzhiyun 	/* Disable the UniMAC RX/TX */
2816*4882a593Smuzhiyun 	umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 0);
2817*4882a593Smuzhiyun 
2818*4882a593Smuzhiyun 	/* We may have been suspended and never received a WOL event that
2819*4882a593Smuzhiyun 	 * would turn off MPD detection, take care of that now
2820*4882a593Smuzhiyun 	 */
2821*4882a593Smuzhiyun 	bcm_sysport_resume_from_wol(priv);
2822*4882a593Smuzhiyun 
2823*4882a593Smuzhiyun 	/* Initialize both hardware and software ring */
2824*4882a593Smuzhiyun 	for (i = 0; i < dev->num_tx_queues; i++) {
2825*4882a593Smuzhiyun 		ret = bcm_sysport_init_tx_ring(priv, i);
2826*4882a593Smuzhiyun 		if (ret) {
2827*4882a593Smuzhiyun 			netdev_err(dev, "failed to initialize TX ring %d\n",
2828*4882a593Smuzhiyun 				   i);
2829*4882a593Smuzhiyun 			goto out_free_tx_rings;
2830*4882a593Smuzhiyun 		}
2831*4882a593Smuzhiyun 	}
2832*4882a593Smuzhiyun 
2833*4882a593Smuzhiyun 	/* Initialize linked-list */
2834*4882a593Smuzhiyun 	tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS);
2835*4882a593Smuzhiyun 
2836*4882a593Smuzhiyun 	/* Initialize RX ring */
2837*4882a593Smuzhiyun 	ret = bcm_sysport_init_rx_ring(priv);
2838*4882a593Smuzhiyun 	if (ret) {
2839*4882a593Smuzhiyun 		netdev_err(dev, "failed to initialize RX ring\n");
2840*4882a593Smuzhiyun 		goto out_free_rx_ring;
2841*4882a593Smuzhiyun 	}
2842*4882a593Smuzhiyun 
2843*4882a593Smuzhiyun 	/* RX pipe enable */
2844*4882a593Smuzhiyun 	topctrl_writel(priv, 0, RX_FLUSH_CNTL);
2845*4882a593Smuzhiyun 
2846*4882a593Smuzhiyun 	ret = rdma_enable_set(priv, 1);
2847*4882a593Smuzhiyun 	if (ret) {
2848*4882a593Smuzhiyun 		netdev_err(dev, "failed to enable RDMA\n");
2849*4882a593Smuzhiyun 		goto out_free_rx_ring;
2850*4882a593Smuzhiyun 	}
2851*4882a593Smuzhiyun 
2852*4882a593Smuzhiyun 	/* Restore enabled features */
2853*4882a593Smuzhiyun 	bcm_sysport_set_features(dev, dev->features);
2854*4882a593Smuzhiyun 
2855*4882a593Smuzhiyun 	rbuf_init(priv);
2856*4882a593Smuzhiyun 
2857*4882a593Smuzhiyun 	/* Set maximum frame length */
2858*4882a593Smuzhiyun 	if (!priv->is_lite)
2859*4882a593Smuzhiyun 		umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2860*4882a593Smuzhiyun 	else
2861*4882a593Smuzhiyun 		gib_set_pad_extension(priv);
2862*4882a593Smuzhiyun 
2863*4882a593Smuzhiyun 	/* Set MAC address */
2864*4882a593Smuzhiyun 	umac_set_hw_addr(priv, dev->dev_addr);
2865*4882a593Smuzhiyun 
2866*4882a593Smuzhiyun 	umac_enable_set(priv, CMD_RX_EN, 1);
2867*4882a593Smuzhiyun 
2868*4882a593Smuzhiyun 	/* TX pipe enable */
2869*4882a593Smuzhiyun 	topctrl_writel(priv, 0, TX_FLUSH_CNTL);
2870*4882a593Smuzhiyun 
2871*4882a593Smuzhiyun 	umac_enable_set(priv, CMD_TX_EN, 1);
2872*4882a593Smuzhiyun 
2873*4882a593Smuzhiyun 	ret = tdma_enable_set(priv, 1);
2874*4882a593Smuzhiyun 	if (ret) {
2875*4882a593Smuzhiyun 		netdev_err(dev, "TDMA timeout!\n");
2876*4882a593Smuzhiyun 		goto out_free_rx_ring;
2877*4882a593Smuzhiyun 	}
2878*4882a593Smuzhiyun 
2879*4882a593Smuzhiyun 	phy_resume(dev->phydev);
2880*4882a593Smuzhiyun 
2881*4882a593Smuzhiyun 	bcm_sysport_netif_start(dev);
2882*4882a593Smuzhiyun 
2883*4882a593Smuzhiyun 	netif_device_attach(dev);
2884*4882a593Smuzhiyun 
2885*4882a593Smuzhiyun 	return 0;
2886*4882a593Smuzhiyun 
2887*4882a593Smuzhiyun out_free_rx_ring:
2888*4882a593Smuzhiyun 	bcm_sysport_fini_rx_ring(priv);
2889*4882a593Smuzhiyun out_free_tx_rings:
2890*4882a593Smuzhiyun 	for (i = 0; i < dev->num_tx_queues; i++)
2891*4882a593Smuzhiyun 		bcm_sysport_fini_tx_ring(priv, i);
2892*4882a593Smuzhiyun 	clk_disable_unprepare(priv->clk);
2893*4882a593Smuzhiyun 	return ret;
2894*4882a593Smuzhiyun }
2895*4882a593Smuzhiyun 
2896*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(bcm_sysport_pm_ops,
2897*4882a593Smuzhiyun 		bcm_sysport_suspend, bcm_sysport_resume);
2898*4882a593Smuzhiyun 
2899*4882a593Smuzhiyun static struct platform_driver bcm_sysport_driver = {
2900*4882a593Smuzhiyun 	.probe	= bcm_sysport_probe,
2901*4882a593Smuzhiyun 	.remove	= bcm_sysport_remove,
2902*4882a593Smuzhiyun 	.driver =  {
2903*4882a593Smuzhiyun 		.name = "brcm-systemport",
2904*4882a593Smuzhiyun 		.of_match_table = bcm_sysport_of_match,
2905*4882a593Smuzhiyun 		.pm = &bcm_sysport_pm_ops,
2906*4882a593Smuzhiyun 	},
2907*4882a593Smuzhiyun };
2908*4882a593Smuzhiyun module_platform_driver(bcm_sysport_driver);
2909*4882a593Smuzhiyun 
2910*4882a593Smuzhiyun MODULE_AUTHOR("Broadcom Corporation");
2911*4882a593Smuzhiyun MODULE_DESCRIPTION("Broadcom System Port Ethernet MAC driver");
2912*4882a593Smuzhiyun MODULE_ALIAS("platform:brcm-systemport");
2913*4882a593Smuzhiyun MODULE_LICENSE("GPL");
2914