xref: /OK3568_Linux_fs/kernel/drivers/net/ethernet/arc/emac_rockchip.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /**
3*4882a593Smuzhiyun  * emac-rockchip.c - Rockchip EMAC specific glue layer
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2014 Romain Perier <romain.perier@gmail.com>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/etherdevice.h>
9*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/of_net.h>
12*4882a593Smuzhiyun #include <linux/platform_device.h>
13*4882a593Smuzhiyun #include <linux/regmap.h>
14*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #include "emac.h"
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define DRV_NAME        "rockchip_emac"
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun struct emac_rockchip_soc_data {
21*4882a593Smuzhiyun 	unsigned int grf_offset;
22*4882a593Smuzhiyun 	unsigned int grf_mode_offset;
23*4882a593Smuzhiyun 	unsigned int grf_speed_offset;
24*4882a593Smuzhiyun 	bool need_div_macclk;
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun struct rockchip_priv_data {
28*4882a593Smuzhiyun 	struct arc_emac_priv emac;
29*4882a593Smuzhiyun 	struct regmap *grf;
30*4882a593Smuzhiyun 	const struct emac_rockchip_soc_data *soc_data;
31*4882a593Smuzhiyun 	struct regulator *regulator;
32*4882a593Smuzhiyun 	struct clk *refclk;
33*4882a593Smuzhiyun 	struct clk *macclk;
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun 
emac_rockchip_set_mac_speed(void * priv,unsigned int speed)36*4882a593Smuzhiyun static void emac_rockchip_set_mac_speed(void *priv, unsigned int speed)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun 	struct rockchip_priv_data *emac = priv;
39*4882a593Smuzhiyun 	u32 speed_offset = emac->soc_data->grf_speed_offset;
40*4882a593Smuzhiyun 	u32 data;
41*4882a593Smuzhiyun 	int err = 0;
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun 	switch (speed) {
44*4882a593Smuzhiyun 	case 10:
45*4882a593Smuzhiyun 		data = (1 << (speed_offset + 16)) | (0 << speed_offset);
46*4882a593Smuzhiyun 		break;
47*4882a593Smuzhiyun 	case 100:
48*4882a593Smuzhiyun 		data = (1 << (speed_offset + 16)) | (1 << speed_offset);
49*4882a593Smuzhiyun 		break;
50*4882a593Smuzhiyun 	default:
51*4882a593Smuzhiyun 		pr_err("speed %u not supported\n", speed);
52*4882a593Smuzhiyun 		return;
53*4882a593Smuzhiyun 	}
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	err = regmap_write(emac->grf, emac->soc_data->grf_offset, data);
56*4882a593Smuzhiyun 	if (err)
57*4882a593Smuzhiyun 		pr_err("unable to apply speed %u to grf (%d)\n", speed, err);
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun static const struct emac_rockchip_soc_data emac_rk3036_emac_data = {
61*4882a593Smuzhiyun 	.grf_offset = 0x140,   .grf_mode_offset = 8,
62*4882a593Smuzhiyun 	.grf_speed_offset = 9, .need_div_macclk = 1,
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun static const struct emac_rockchip_soc_data emac_rk3066_emac_data = {
66*4882a593Smuzhiyun 	.grf_offset = 0x154,   .grf_mode_offset = 0,
67*4882a593Smuzhiyun 	.grf_speed_offset = 1, .need_div_macclk = 0,
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun static const struct emac_rockchip_soc_data emac_rk3188_emac_data = {
71*4882a593Smuzhiyun 	.grf_offset = 0x0a4,   .grf_mode_offset = 0,
72*4882a593Smuzhiyun 	.grf_speed_offset = 1, .need_div_macclk = 0,
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun static const struct of_device_id emac_rockchip_dt_ids[] = {
76*4882a593Smuzhiyun 	{
77*4882a593Smuzhiyun 		.compatible = "rockchip,rk3036-emac",
78*4882a593Smuzhiyun 		.data = &emac_rk3036_emac_data,
79*4882a593Smuzhiyun 	},
80*4882a593Smuzhiyun 	{
81*4882a593Smuzhiyun 		.compatible = "rockchip,rk3066-emac",
82*4882a593Smuzhiyun 		.data = &emac_rk3066_emac_data,
83*4882a593Smuzhiyun 	},
84*4882a593Smuzhiyun 	{
85*4882a593Smuzhiyun 		.compatible = "rockchip,rk3188-emac",
86*4882a593Smuzhiyun 		.data = &emac_rk3188_emac_data,
87*4882a593Smuzhiyun 	},
88*4882a593Smuzhiyun 	{ /* Sentinel */ }
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, emac_rockchip_dt_ids);
92*4882a593Smuzhiyun 
emac_rockchip_probe(struct platform_device * pdev)93*4882a593Smuzhiyun static int emac_rockchip_probe(struct platform_device *pdev)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
96*4882a593Smuzhiyun 	struct net_device *ndev;
97*4882a593Smuzhiyun 	struct rockchip_priv_data *priv;
98*4882a593Smuzhiyun 	const struct of_device_id *match;
99*4882a593Smuzhiyun 	phy_interface_t interface;
100*4882a593Smuzhiyun 	u32 data;
101*4882a593Smuzhiyun 	int err;
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	if (!pdev->dev.of_node)
104*4882a593Smuzhiyun 		return -ENODEV;
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	ndev = alloc_etherdev(sizeof(struct rockchip_priv_data));
107*4882a593Smuzhiyun 	if (!ndev)
108*4882a593Smuzhiyun 		return -ENOMEM;
109*4882a593Smuzhiyun 	platform_set_drvdata(pdev, ndev);
110*4882a593Smuzhiyun 	SET_NETDEV_DEV(ndev, dev);
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	priv = netdev_priv(ndev);
113*4882a593Smuzhiyun 	priv->emac.drv_name = DRV_NAME;
114*4882a593Smuzhiyun 	priv->emac.set_mac_speed = emac_rockchip_set_mac_speed;
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	err = of_get_phy_mode(dev->of_node, &interface);
117*4882a593Smuzhiyun 	if (err)
118*4882a593Smuzhiyun 		goto out_netdev;
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	/* RK3036/RK3066/RK3188 SoCs only support RMII */
121*4882a593Smuzhiyun 	if (interface != PHY_INTERFACE_MODE_RMII) {
122*4882a593Smuzhiyun 		dev_err(dev, "unsupported phy interface mode %d\n", interface);
123*4882a593Smuzhiyun 		err = -ENOTSUPP;
124*4882a593Smuzhiyun 		goto out_netdev;
125*4882a593Smuzhiyun 	}
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 	priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
128*4882a593Smuzhiyun 						    "rockchip,grf");
129*4882a593Smuzhiyun 	if (IS_ERR(priv->grf)) {
130*4882a593Smuzhiyun 		dev_err(dev, "failed to retrieve global register file (%ld)\n",
131*4882a593Smuzhiyun 			PTR_ERR(priv->grf));
132*4882a593Smuzhiyun 		err = PTR_ERR(priv->grf);
133*4882a593Smuzhiyun 		goto out_netdev;
134*4882a593Smuzhiyun 	}
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	match = of_match_node(emac_rockchip_dt_ids, dev->of_node);
137*4882a593Smuzhiyun 	priv->soc_data = match->data;
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	priv->emac.clk = devm_clk_get(dev, "hclk");
140*4882a593Smuzhiyun 	if (IS_ERR(priv->emac.clk)) {
141*4882a593Smuzhiyun 		dev_err(dev, "failed to retrieve host clock (%ld)\n",
142*4882a593Smuzhiyun 			PTR_ERR(priv->emac.clk));
143*4882a593Smuzhiyun 		err = PTR_ERR(priv->emac.clk);
144*4882a593Smuzhiyun 		goto out_netdev;
145*4882a593Smuzhiyun 	}
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	priv->refclk = devm_clk_get(dev, "macref");
148*4882a593Smuzhiyun 	if (IS_ERR(priv->refclk)) {
149*4882a593Smuzhiyun 		dev_err(dev, "failed to retrieve reference clock (%ld)\n",
150*4882a593Smuzhiyun 			PTR_ERR(priv->refclk));
151*4882a593Smuzhiyun 		err = PTR_ERR(priv->refclk);
152*4882a593Smuzhiyun 		goto out_netdev;
153*4882a593Smuzhiyun 	}
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	err = clk_prepare_enable(priv->refclk);
156*4882a593Smuzhiyun 	if (err) {
157*4882a593Smuzhiyun 		dev_err(dev, "failed to enable reference clock (%d)\n", err);
158*4882a593Smuzhiyun 		goto out_netdev;
159*4882a593Smuzhiyun 	}
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	/* Optional regulator for PHY */
162*4882a593Smuzhiyun 	priv->regulator = devm_regulator_get_optional(dev, "phy");
163*4882a593Smuzhiyun 	if (IS_ERR(priv->regulator)) {
164*4882a593Smuzhiyun 		if (PTR_ERR(priv->regulator) == -EPROBE_DEFER) {
165*4882a593Smuzhiyun 			err = -EPROBE_DEFER;
166*4882a593Smuzhiyun 			goto out_clk_disable;
167*4882a593Smuzhiyun 		}
168*4882a593Smuzhiyun 		dev_err(dev, "no regulator found\n");
169*4882a593Smuzhiyun 		priv->regulator = NULL;
170*4882a593Smuzhiyun 	}
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	if (priv->regulator) {
173*4882a593Smuzhiyun 		err = regulator_enable(priv->regulator);
174*4882a593Smuzhiyun 		if (err) {
175*4882a593Smuzhiyun 			dev_err(dev, "failed to enable phy-supply (%d)\n", err);
176*4882a593Smuzhiyun 			goto out_clk_disable;
177*4882a593Smuzhiyun 		}
178*4882a593Smuzhiyun 	}
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	/* Set speed 100M */
181*4882a593Smuzhiyun 	data = (1 << (priv->soc_data->grf_speed_offset + 16)) |
182*4882a593Smuzhiyun 	       (1 << priv->soc_data->grf_speed_offset);
183*4882a593Smuzhiyun 	/* Set RMII mode */
184*4882a593Smuzhiyun 	data |= (1 << (priv->soc_data->grf_mode_offset + 16)) |
185*4882a593Smuzhiyun 		(0 << priv->soc_data->grf_mode_offset);
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 	err = regmap_write(priv->grf, priv->soc_data->grf_offset, data);
188*4882a593Smuzhiyun 	if (err) {
189*4882a593Smuzhiyun 		dev_err(dev, "unable to apply initial settings to grf (%d)\n",
190*4882a593Smuzhiyun 			err);
191*4882a593Smuzhiyun 		goto out_regulator_disable;
192*4882a593Smuzhiyun 	}
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	/* RMII interface needs always a rate of 50MHz */
195*4882a593Smuzhiyun 	err = clk_set_rate(priv->refclk, 50000000);
196*4882a593Smuzhiyun 	if (err) {
197*4882a593Smuzhiyun 		dev_err(dev,
198*4882a593Smuzhiyun 			"failed to change reference clock rate (%d)\n", err);
199*4882a593Smuzhiyun 		goto out_regulator_disable;
200*4882a593Smuzhiyun 	}
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	if (priv->soc_data->need_div_macclk) {
203*4882a593Smuzhiyun 		priv->macclk = devm_clk_get(dev, "macclk");
204*4882a593Smuzhiyun 		if (IS_ERR(priv->macclk)) {
205*4882a593Smuzhiyun 			dev_err(dev, "failed to retrieve mac clock (%ld)\n",
206*4882a593Smuzhiyun 				PTR_ERR(priv->macclk));
207*4882a593Smuzhiyun 			err = PTR_ERR(priv->macclk);
208*4882a593Smuzhiyun 			goto out_regulator_disable;
209*4882a593Smuzhiyun 		}
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 		err = clk_prepare_enable(priv->macclk);
212*4882a593Smuzhiyun 		if (err) {
213*4882a593Smuzhiyun 			dev_err(dev, "failed to enable mac clock (%d)\n", err);
214*4882a593Smuzhiyun 			goto out_regulator_disable;
215*4882a593Smuzhiyun 		}
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 		/* RMII TX/RX needs always a rate of 25MHz */
218*4882a593Smuzhiyun 		err = clk_set_rate(priv->macclk, 25000000);
219*4882a593Smuzhiyun 		if (err) {
220*4882a593Smuzhiyun 			dev_err(dev,
221*4882a593Smuzhiyun 				"failed to change mac clock rate (%d)\n", err);
222*4882a593Smuzhiyun 			goto out_clk_disable_macclk;
223*4882a593Smuzhiyun 		}
224*4882a593Smuzhiyun 	}
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	err = arc_emac_probe(ndev, interface);
227*4882a593Smuzhiyun 	if (err) {
228*4882a593Smuzhiyun 		dev_err(dev, "failed to probe arc emac (%d)\n", err);
229*4882a593Smuzhiyun 		goto out_clk_disable_macclk;
230*4882a593Smuzhiyun 	}
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	return 0;
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun out_clk_disable_macclk:
235*4882a593Smuzhiyun 	if (priv->soc_data->need_div_macclk)
236*4882a593Smuzhiyun 		clk_disable_unprepare(priv->macclk);
237*4882a593Smuzhiyun out_regulator_disable:
238*4882a593Smuzhiyun 	if (priv->regulator)
239*4882a593Smuzhiyun 		regulator_disable(priv->regulator);
240*4882a593Smuzhiyun out_clk_disable:
241*4882a593Smuzhiyun 	clk_disable_unprepare(priv->refclk);
242*4882a593Smuzhiyun out_netdev:
243*4882a593Smuzhiyun 	free_netdev(ndev);
244*4882a593Smuzhiyun 	return err;
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun 
emac_rockchip_remove(struct platform_device * pdev)247*4882a593Smuzhiyun static int emac_rockchip_remove(struct platform_device *pdev)
248*4882a593Smuzhiyun {
249*4882a593Smuzhiyun 	struct net_device *ndev = platform_get_drvdata(pdev);
250*4882a593Smuzhiyun 	struct rockchip_priv_data *priv = netdev_priv(ndev);
251*4882a593Smuzhiyun 	int err;
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun 	err = arc_emac_remove(ndev);
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	clk_disable_unprepare(priv->refclk);
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	if (priv->regulator)
258*4882a593Smuzhiyun 		regulator_disable(priv->regulator);
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun 	if (priv->soc_data->need_div_macclk)
261*4882a593Smuzhiyun 		clk_disable_unprepare(priv->macclk);
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	free_netdev(ndev);
264*4882a593Smuzhiyun 	return err;
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun static struct platform_driver emac_rockchip_driver = {
268*4882a593Smuzhiyun 	.probe = emac_rockchip_probe,
269*4882a593Smuzhiyun 	.remove = emac_rockchip_remove,
270*4882a593Smuzhiyun 	.driver = {
271*4882a593Smuzhiyun 		.name = DRV_NAME,
272*4882a593Smuzhiyun 		.of_match_table  = emac_rockchip_dt_ids,
273*4882a593Smuzhiyun 	},
274*4882a593Smuzhiyun };
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun module_platform_driver(emac_rockchip_driver);
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun MODULE_AUTHOR("Romain Perier <romain.perier@gmail.com>");
279*4882a593Smuzhiyun MODULE_DESCRIPTION("Rockchip EMAC platform driver");
280*4882a593Smuzhiyun MODULE_LICENSE("GPL");
281